blob: ddb802bce0a3252e0ed447f927187cdf0feacd09 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00002/*
3 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02004 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00005 */
6
Mikko Perttunenad926012016-12-14 13:16:11 +02007#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +02008#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01009#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020010#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011
Thierry Reding1503ca42014-11-24 17:41:23 +010012#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010013#include <drm/drm_atomic_helper.h>
14
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +030015#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
16#include <asm/dma-iommu.h>
17#endif
18
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000019#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020020#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000021
22#define DRIVER_NAME "tegra"
23#define DRIVER_DESC "NVIDIA Tegra graphics"
24#define DRIVER_DATE "20120330"
25#define DRIVER_MAJOR 0
26#define DRIVER_MINOR 0
27#define DRIVER_PATCHLEVEL 0
28
Mikko Perttunenad926012016-12-14 13:16:11 +020029#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030030#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020031
Thierry Reding08943e62013-09-26 16:08:18 +020032struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010033 struct idr contexts;
34 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020035};
36
Thierry Redingab7d3f52017-12-14 13:46:20 +010037static int tegra_atomic_check(struct drm_device *drm,
38 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010039{
Thierry Reding1503ca42014-11-24 17:41:23 +010040 int err;
41
Peter Ujfalusia18301b2018-03-21 12:20:26 +020042 err = drm_atomic_helper_check(drm, state);
Thierry Redingab7d3f52017-12-14 13:46:20 +010043 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010044 return err;
45
Peter Ujfalusia18301b2018-03-21 12:20:26 +020046 return tegra_display_hub_atomic_check(drm, state);
Thierry Reding1503ca42014-11-24 17:41:23 +010047}
48
Thierry Reding31b02ca2017-10-12 17:40:46 +020049static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010050 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053051#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010052 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010053#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010054 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020055 .atomic_commit = drm_atomic_helper_commit,
56};
57
Thierry Redingc4755fb2017-11-13 11:08:13 +010058static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
59{
60 struct drm_device *drm = old_state->dev;
61 struct tegra_drm *tegra = drm->dev_private;
62
63 if (tegra->hub) {
64 drm_atomic_helper_commit_modeset_disables(drm, old_state);
65 tegra_display_hub_atomic_commit(drm, old_state);
66 drm_atomic_helper_commit_planes(drm, old_state, 0);
67 drm_atomic_helper_commit_modeset_enables(drm, old_state);
68 drm_atomic_helper_commit_hw_done(old_state);
69 drm_atomic_helper_wait_for_vblanks(drm, old_state);
70 drm_atomic_helper_cleanup_planes(drm, old_state);
71 } else {
72 drm_atomic_helper_commit_tail_rpm(old_state);
73 }
74}
75
Thierry Reding31b02ca2017-10-12 17:40:46 +020076static const struct drm_mode_config_helper_funcs
77tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010078 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010079};
80
Thierry Reding776dc382013-10-14 14:43:22 +020081static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000082{
Thierry Reding776dc382013-10-14 14:43:22 +020083 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020084 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000085 int err;
86
Thierry Reding776dc382013-10-14 14:43:22 +020087 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +020088 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +020089 return -ENOMEM;
90
Thierry Redingdf06b752014-06-26 21:41:53 +020091 if (iommu_present(&platform_bus_type)) {
92 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +030093 if (!tegra->domain) {
94 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +020095 goto free;
96 }
97
Thierry Reding24cfdc12018-04-23 08:57:45 +020098 err = iova_cache_get();
99 if (err < 0)
100 goto domain;
Thierry Redingdf06b752014-06-26 21:41:53 +0200101 }
102
Thierry Reding386a2a72013-09-24 13:22:17 +0200103 mutex_init(&tegra->clients_lock);
104 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100105
Thierry Reding386a2a72013-09-24 13:22:17 +0200106 drm->dev_private = tegra;
107 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000108
109 drm_mode_config_init(drm);
110
Thierry Redingf9914212014-11-26 13:03:57 +0100111 drm->mode_config.min_width = 0;
112 drm->mode_config.min_height = 0;
113
114 drm->mode_config.max_width = 4096;
115 drm->mode_config.max_height = 4096;
116
Alexandre Courbot5e911442016-11-08 16:50:42 +0900117 drm->mode_config.allow_fb_modifiers = true;
118
Peter Ujfalusia18301b2018-03-21 12:20:26 +0200119 drm->mode_config.normalize_zpos = true;
120
Thierry Reding31b02ca2017-10-12 17:40:46 +0200121 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
122 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100123
Thierry Redinge2215322014-06-27 17:19:25 +0200124 err = tegra_drm_fb_prepare(drm);
125 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100126 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200127
128 drm_kms_helper_poll_init(drm);
129
Thierry Reding776dc382013-10-14 14:43:22 +0200130 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000131 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100132 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000133
Thierry Redingb9f8b092019-02-01 14:28:33 +0100134 if (tegra->domain) {
135 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding02be8e42019-02-01 14:28:34 +0100136 u64 dma_mask = dma_get_mask(&device->dev);
Thierry Redingb9f8b092019-02-01 14:28:33 +0100137 dma_addr_t start, end;
138 unsigned long order;
139
Thierry Reding02be8e42019-02-01 14:28:34 +0100140 start = tegra->domain->geometry.aperture_start & dma_mask;
141 end = tegra->domain->geometry.aperture_end & dma_mask;
Thierry Redingb9f8b092019-02-01 14:28:33 +0100142
143 gem_start = start;
144 gem_end = end - CARVEOUT_SZ;
145 carveout_start = gem_end + 1;
146 carveout_end = end;
147
148 order = __ffs(tegra->domain->pgsize_bitmap);
149 init_iova_domain(&tegra->carveout.domain, 1UL << order,
150 carveout_start >> order);
151
152 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
153 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
154
155 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
156 mutex_init(&tegra->mm_lock);
157
158 DRM_DEBUG("IOMMU apertures:\n");
159 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
160 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
161 carveout_end);
162 }
163
Thierry Redingc4755fb2017-11-13 11:08:13 +0100164 if (tegra->hub) {
165 err = tegra_display_hub_prepare(tegra->hub);
166 if (err < 0)
167 goto device;
168 }
169
Thierry Reding603f0cc2013-04-22 21:22:14 +0200170 /*
171 * We don't use the drm_irq_install() helpers provided by the DRM
172 * core, so we need to set this manually in order to allow the
173 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
174 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300175 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200176
Thierry Reding42e9ce02015-01-28 14:43:05 +0100177 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100178 drm->max_vblank_count = 0xffffffff;
179
Thierry Reding6e5ff992012-11-28 11:45:47 +0100180 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
181 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100182 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100183
Thierry Reding31930d42015-07-02 17:04:06 +0200184 drm_mode_config_reset(drm);
185
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000186 err = tegra_drm_fb_init(drm);
187 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100188 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000189
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000190 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100191
Thierry Redingc4755fb2017-11-13 11:08:13 +0100192hub:
193 if (tegra->hub)
194 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100195device:
196 host1x_device_exit(device);
197fbdev:
198 drm_kms_helper_poll_fini(drm);
199 tegra_drm_fb_free(drm);
200config:
201 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200202
203 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100204 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200205 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200206 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200207 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200208 }
Thierry Reding24cfdc12018-04-23 08:57:45 +0200209domain:
210 if (tegra->domain)
211 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200212free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100213 kfree(tegra);
214 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000215}
216
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200217static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000218{
Thierry Reding776dc382013-10-14 14:43:22 +0200219 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200220 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200221 int err;
222
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000223 drm_kms_helper_poll_fini(drm);
224 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100225 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200226 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000227
Thierry Reding776dc382013-10-14 14:43:22 +0200228 err = host1x_device_exit(device);
229 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200230 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200231
Thierry Redingdf06b752014-06-26 21:41:53 +0200232 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100233 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200234 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200235 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200236 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200237 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200238 }
239
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100240 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000241}
242
243static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
244{
Thierry Reding08943e62013-09-26 16:08:18 +0200245 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200246
247 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
248 if (!fpriv)
249 return -ENOMEM;
250
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100251 idr_init(&fpriv->contexts);
252 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200253 filp->driver_priv = fpriv;
254
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000255 return 0;
256}
257
Thierry Redingc88c3632013-09-26 16:08:22 +0200258static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200259{
260 context->client->ops->close_channel(context);
261 kfree(context);
262}
263
Thierry Redingc40f0f12013-10-10 11:00:33 +0200264static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100265host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200266{
267 struct drm_gem_object *gem;
268 struct tegra_bo *bo;
269
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100270 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200271 if (!gem)
272 return NULL;
273
Thierry Redingc40f0f12013-10-10 11:00:33 +0200274 bo = to_tegra_bo(gem);
275 return &bo->base;
276}
277
Thierry Reding961e3be2014-06-10 10:25:00 +0200278static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
279 struct drm_tegra_reloc __user *src,
280 struct drm_device *drm,
281 struct drm_file *file)
282{
283 u32 cmdbuf, target;
284 int err;
285
286 err = get_user(cmdbuf, &src->cmdbuf.handle);
287 if (err < 0)
288 return err;
289
290 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
291 if (err < 0)
292 return err;
293
294 err = get_user(target, &src->target.handle);
295 if (err < 0)
296 return err;
297
David Ung31f40f82015-01-20 18:37:35 -0800298 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200299 if (err < 0)
300 return err;
301
302 err = get_user(dest->shift, &src->shift);
303 if (err < 0)
304 return err;
305
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100306 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200307 if (!dest->cmdbuf.bo)
308 return -ENOENT;
309
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100310 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200311 if (!dest->target.bo)
312 return -ENOENT;
313
314 return 0;
315}
316
Thierry Redingc40f0f12013-10-10 11:00:33 +0200317int tegra_drm_submit(struct tegra_drm_context *context,
318 struct drm_tegra_submit *args, struct drm_device *drm,
319 struct drm_file *file)
320{
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200321 struct host1x_client *client = &context->client->base;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200322 unsigned int num_cmdbufs = args->num_cmdbufs;
323 unsigned int num_relocs = args->num_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300324 struct drm_tegra_cmdbuf __user *user_cmdbufs;
325 struct drm_tegra_reloc __user *user_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300326 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200327 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300328 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200329 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300330 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200331 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200332 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200333 int err;
334
Mikko Perttunena176c672017-09-28 15:50:44 +0300335 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
336 user_relocs = u64_to_user_ptr(args->relocs);
Mikko Perttunena176c672017-09-28 15:50:44 +0300337 user_syncpt = u64_to_user_ptr(args->syncpts);
338
Thierry Redingc40f0f12013-10-10 11:00:33 +0200339 /* We don't yet support other than one syncpt_incr struct per submit */
340 if (args->num_syncpts != 1)
341 return -EINVAL;
342
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300343 /* We don't yet support waitchks */
344 if (args->num_waitchks != 0)
345 return -EINVAL;
346
Thierry Redingc40f0f12013-10-10 11:00:33 +0200347 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
Thierry Reding24c94e12018-05-05 08:45:47 +0200348 args->num_relocs);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200349 if (!job)
350 return -ENOMEM;
351
352 job->num_relocs = args->num_relocs;
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200353 job->client = client;
354 job->class = client->class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200355 job->serialize = true;
356
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200357 /*
358 * Track referenced BOs so that they can be unreferenced after the
359 * submission is complete.
360 */
Thierry Reding24c94e12018-05-05 08:45:47 +0200361 num_refs = num_cmdbufs + num_relocs * 2;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200362
363 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
364 if (!refs) {
365 err = -ENOMEM;
366 goto put;
367 }
368
369 /* reuse as an iterator later */
370 num_refs = 0;
371
Thierry Redingc40f0f12013-10-10 11:00:33 +0200372 while (num_cmdbufs) {
373 struct drm_tegra_cmdbuf cmdbuf;
374 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300375 struct tegra_bo *obj;
376 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200377
Mikko Perttunena176c672017-09-28 15:50:44 +0300378 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300379 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200380 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300381 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200382
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300383 /*
384 * The maximum number of CDMA gather fetches is 16383, a higher
385 * value means the words count is malformed.
386 */
387 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
388 err = -EINVAL;
389 goto fail;
390 }
391
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100392 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200393 if (!bo) {
394 err = -ENOENT;
395 goto fail;
396 }
397
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300398 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
399 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200400 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300401
402 /*
403 * Gather buffer base address must be 4-bytes aligned,
404 * unaligned offset is malformed and cause commands stream
405 * corruption on the buffer address relocation.
406 */
Mikko Perttunen5265f032018-06-20 16:03:58 +0300407 if (offset & 3 || offset > obj->gem.size) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300408 err = -EINVAL;
409 goto fail;
410 }
411
Thierry Redingc40f0f12013-10-10 11:00:33 +0200412 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
413 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300414 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200415 }
416
Thierry Reding961e3be2014-06-10 10:25:00 +0200417 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200418 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300419 struct host1x_reloc *reloc;
420 struct tegra_bo *obj;
421
Thierry Reding06490bb2018-05-16 16:58:44 +0200422 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300423 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200424 file);
425 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200426 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300427
Thierry Reding06490bb2018-05-16 16:58:44 +0200428 reloc = &job->relocs[num_relocs];
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300429 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200430 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300431
432 /*
433 * The unaligned cmdbuf offset will cause an unaligned write
434 * during of the relocations patching, corrupting the commands
435 * stream.
436 */
437 if (reloc->cmdbuf.offset & 3 ||
438 reloc->cmdbuf.offset >= obj->gem.size) {
439 err = -EINVAL;
440 goto fail;
441 }
442
443 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200444 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300445
446 if (reloc->target.offset >= obj->gem.size) {
447 err = -EINVAL;
448 goto fail;
449 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200450 }
451
Mikko Perttunena176c672017-09-28 15:50:44 +0300452 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300453 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200454 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300455 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200456
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300457 /* check whether syncpoint ID is valid */
458 sp = host1x_syncpt_get(host1x, syncpt.id);
459 if (!sp) {
460 err = -ENOENT;
461 goto fail;
462 }
463
Thierry Redingc40f0f12013-10-10 11:00:33 +0200464 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300465 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200466 job->syncpt_incrs = syncpt.incrs;
467 job->syncpt_id = syncpt.id;
468 job->timeout = 10000;
469
470 if (args->timeout && args->timeout < 10000)
471 job->timeout = args->timeout;
472
473 err = host1x_job_pin(job, context->client->base.dev);
474 if (err)
475 goto fail;
476
477 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200478 if (err) {
479 host1x_job_unpin(job);
480 goto fail;
481 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200482
483 args->fence = job->syncpt_end;
484
Thierry Redingc40f0f12013-10-10 11:00:33 +0200485fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200486 while (num_refs--)
487 drm_gem_object_put_unlocked(refs[num_refs]);
488
489 kfree(refs);
490
491put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200492 host1x_job_put(job);
493 return err;
494}
495
496
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200497#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200498static int tegra_gem_create(struct drm_device *drm, void *data,
499 struct drm_file *file)
500{
501 struct drm_tegra_gem_create *args = data;
502 struct tegra_bo *bo;
503
Thierry Reding773af772013-10-04 22:34:01 +0200504 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200505 &args->handle);
506 if (IS_ERR(bo))
507 return PTR_ERR(bo);
508
509 return 0;
510}
511
512static int tegra_gem_mmap(struct drm_device *drm, void *data,
513 struct drm_file *file)
514{
515 struct drm_tegra_gem_mmap *args = data;
516 struct drm_gem_object *gem;
517 struct tegra_bo *bo;
518
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100519 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200520 if (!gem)
521 return -EINVAL;
522
523 bo = to_tegra_bo(gem);
524
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200525 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200526
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300527 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200528
529 return 0;
530}
531
532static int tegra_syncpt_read(struct drm_device *drm, void *data,
533 struct drm_file *file)
534{
Thierry Reding776dc382013-10-14 14:43:22 +0200535 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200536 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200537 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200538
Thierry Reding776dc382013-10-14 14:43:22 +0200539 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200540 if (!sp)
541 return -EINVAL;
542
543 args->value = host1x_syncpt_read_min(sp);
544 return 0;
545}
546
547static int tegra_syncpt_incr(struct drm_device *drm, void *data,
548 struct drm_file *file)
549{
Thierry Reding776dc382013-10-14 14:43:22 +0200550 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200551 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200552 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200553
Thierry Reding776dc382013-10-14 14:43:22 +0200554 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200555 if (!sp)
556 return -EINVAL;
557
Arto Merilainenebae30b2013-05-29 13:26:08 +0300558 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200559}
560
561static int tegra_syncpt_wait(struct drm_device *drm, void *data,
562 struct drm_file *file)
563{
Thierry Reding776dc382013-10-14 14:43:22 +0200564 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200565 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200566 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200567
Thierry Reding776dc382013-10-14 14:43:22 +0200568 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200569 if (!sp)
570 return -EINVAL;
571
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300572 return host1x_syncpt_wait(sp, args->thresh,
573 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200574 &args->value);
575}
576
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100577static int tegra_client_open(struct tegra_drm_file *fpriv,
578 struct tegra_drm_client *client,
579 struct tegra_drm_context *context)
580{
581 int err;
582
583 err = client->ops->open_channel(client, context);
584 if (err < 0)
585 return err;
586
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300587 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100588 if (err < 0) {
589 client->ops->close_channel(context);
590 return err;
591 }
592
593 context->client = client;
594 context->id = err;
595
596 return 0;
597}
598
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200599static int tegra_open_channel(struct drm_device *drm, void *data,
600 struct drm_file *file)
601{
Thierry Reding08943e62013-09-26 16:08:18 +0200602 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200603 struct tegra_drm *tegra = drm->dev_private;
604 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200605 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200606 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200607 int err = -ENODEV;
608
609 context = kzalloc(sizeof(*context), GFP_KERNEL);
610 if (!context)
611 return -ENOMEM;
612
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100613 mutex_lock(&fpriv->lock);
614
Thierry Reding776dc382013-10-14 14:43:22 +0200615 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200616 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100617 err = tegra_client_open(fpriv, client, context);
618 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200619 break;
620
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100621 args->context = context->id;
622 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200623 }
624
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100625 if (err < 0)
626 kfree(context);
627
628 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200629 return err;
630}
631
632static int tegra_close_channel(struct drm_device *drm, void *data,
633 struct drm_file *file)
634{
Thierry Reding08943e62013-09-26 16:08:18 +0200635 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200636 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200637 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100638 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200639
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100640 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200641
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300642 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100643 if (!context) {
644 err = -EINVAL;
645 goto unlock;
646 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200647
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100648 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200649 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200650
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100651unlock:
652 mutex_unlock(&fpriv->lock);
653 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200654}
655
656static int tegra_get_syncpt(struct drm_device *drm, void *data,
657 struct drm_file *file)
658{
Thierry Reding08943e62013-09-26 16:08:18 +0200659 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200660 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200661 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200662 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100663 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200664
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100665 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200666
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300667 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100668 if (!context) {
669 err = -ENODEV;
670 goto unlock;
671 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200672
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100673 if (args->index >= context->client->base.num_syncpts) {
674 err = -EINVAL;
675 goto unlock;
676 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200677
Thierry Reding53fa7f72013-09-24 15:35:40 +0200678 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200679 args->id = host1x_syncpt_id(syncpt);
680
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100681unlock:
682 mutex_unlock(&fpriv->lock);
683 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200684}
685
686static int tegra_submit(struct drm_device *drm, void *data,
687 struct drm_file *file)
688{
Thierry Reding08943e62013-09-26 16:08:18 +0200689 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200690 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200691 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100692 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200693
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100694 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200695
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300696 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100697 if (!context) {
698 err = -ENODEV;
699 goto unlock;
700 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200701
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100702 err = context->client->ops->submit(context, args, drm, file);
703
704unlock:
705 mutex_unlock(&fpriv->lock);
706 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200707}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300708
709static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
710 struct drm_file *file)
711{
712 struct tegra_drm_file *fpriv = file->driver_priv;
713 struct drm_tegra_get_syncpt_base *args = data;
714 struct tegra_drm_context *context;
715 struct host1x_syncpt_base *base;
716 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100717 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300718
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100719 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300720
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300721 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100722 if (!context) {
723 err = -ENODEV;
724 goto unlock;
725 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300726
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100727 if (args->syncpt >= context->client->base.num_syncpts) {
728 err = -EINVAL;
729 goto unlock;
730 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300731
732 syncpt = context->client->base.syncpts[args->syncpt];
733
734 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100735 if (!base) {
736 err = -ENXIO;
737 goto unlock;
738 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300739
740 args->id = host1x_syncpt_base_id(base);
741
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100742unlock:
743 mutex_unlock(&fpriv->lock);
744 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300745}
Thierry Reding7678d712014-06-03 14:56:57 +0200746
747static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
748 struct drm_file *file)
749{
750 struct drm_tegra_gem_set_tiling *args = data;
751 enum tegra_bo_tiling_mode mode;
752 struct drm_gem_object *gem;
753 unsigned long value = 0;
754 struct tegra_bo *bo;
755
756 switch (args->mode) {
757 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
758 mode = TEGRA_BO_TILING_MODE_PITCH;
759
760 if (args->value != 0)
761 return -EINVAL;
762
763 break;
764
765 case DRM_TEGRA_GEM_TILING_MODE_TILED:
766 mode = TEGRA_BO_TILING_MODE_TILED;
767
768 if (args->value != 0)
769 return -EINVAL;
770
771 break;
772
773 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
774 mode = TEGRA_BO_TILING_MODE_BLOCK;
775
776 if (args->value > 5)
777 return -EINVAL;
778
779 value = args->value;
780 break;
781
782 default:
783 return -EINVAL;
784 }
785
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100786 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200787 if (!gem)
788 return -ENOENT;
789
790 bo = to_tegra_bo(gem);
791
792 bo->tiling.mode = mode;
793 bo->tiling.value = value;
794
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300795 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200796
797 return 0;
798}
799
800static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
801 struct drm_file *file)
802{
803 struct drm_tegra_gem_get_tiling *args = data;
804 struct drm_gem_object *gem;
805 struct tegra_bo *bo;
806 int err = 0;
807
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100808 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200809 if (!gem)
810 return -ENOENT;
811
812 bo = to_tegra_bo(gem);
813
814 switch (bo->tiling.mode) {
815 case TEGRA_BO_TILING_MODE_PITCH:
816 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
817 args->value = 0;
818 break;
819
820 case TEGRA_BO_TILING_MODE_TILED:
821 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
822 args->value = 0;
823 break;
824
825 case TEGRA_BO_TILING_MODE_BLOCK:
826 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
827 args->value = bo->tiling.value;
828 break;
829
830 default:
831 err = -EINVAL;
832 break;
833 }
834
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300835 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200836
837 return err;
838}
Thierry Reding7b129082014-06-10 12:04:03 +0200839
840static int tegra_gem_set_flags(struct drm_device *drm, void *data,
841 struct drm_file *file)
842{
843 struct drm_tegra_gem_set_flags *args = data;
844 struct drm_gem_object *gem;
845 struct tegra_bo *bo;
846
847 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
848 return -EINVAL;
849
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100850 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200851 if (!gem)
852 return -ENOENT;
853
854 bo = to_tegra_bo(gem);
855 bo->flags = 0;
856
857 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
858 bo->flags |= TEGRA_BO_BOTTOM_UP;
859
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300860 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200861
862 return 0;
863}
864
865static int tegra_gem_get_flags(struct drm_device *drm, void *data,
866 struct drm_file *file)
867{
868 struct drm_tegra_gem_get_flags *args = data;
869 struct drm_gem_object *gem;
870 struct tegra_bo *bo;
871
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100872 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200873 if (!gem)
874 return -ENOENT;
875
876 bo = to_tegra_bo(gem);
877 args->flags = 0;
878
879 if (bo->flags & TEGRA_BO_BOTTOM_UP)
880 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
881
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300882 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200883
884 return 0;
885}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200886#endif
887
Rob Clarkbaa70942013-08-02 13:27:49 -0400888static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200889#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200890 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
891 DRM_UNLOCKED | DRM_RENDER_ALLOW),
892 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
893 DRM_UNLOCKED | DRM_RENDER_ALLOW),
894 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
895 DRM_UNLOCKED | DRM_RENDER_ALLOW),
896 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
897 DRM_UNLOCKED | DRM_RENDER_ALLOW),
898 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
899 DRM_UNLOCKED | DRM_RENDER_ALLOW),
900 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
901 DRM_UNLOCKED | DRM_RENDER_ALLOW),
902 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
903 DRM_UNLOCKED | DRM_RENDER_ALLOW),
904 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
905 DRM_UNLOCKED | DRM_RENDER_ALLOW),
906 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
907 DRM_UNLOCKED | DRM_RENDER_ALLOW),
908 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
909 DRM_UNLOCKED | DRM_RENDER_ALLOW),
910 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
911 DRM_UNLOCKED | DRM_RENDER_ALLOW),
912 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
913 DRM_UNLOCKED | DRM_RENDER_ALLOW),
914 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
915 DRM_UNLOCKED | DRM_RENDER_ALLOW),
916 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
917 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200918#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000919};
920
921static const struct file_operations tegra_drm_fops = {
922 .owner = THIS_MODULE,
923 .open = drm_open,
924 .release = drm_release,
925 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200926 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000927 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000928 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000929 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000930 .llseek = noop_llseek,
931};
932
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100933static int tegra_drm_context_cleanup(int id, void *p, void *data)
934{
935 struct tegra_drm_context *context = p;
936
937 tegra_drm_context_free(context);
938
939 return 0;
940}
941
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200942static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100943{
Thierry Reding08943e62013-09-26 16:08:18 +0200944 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100945
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100946 mutex_lock(&fpriv->lock);
947 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
948 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200949
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100950 idr_destroy(&fpriv->contexts);
951 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200952 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100953}
954
Thierry Redinge450fcc2013-02-13 16:13:16 +0100955#ifdef CONFIG_DEBUG_FS
956static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
957{
958 struct drm_info_node *node = (struct drm_info_node *)s->private;
959 struct drm_device *drm = node->minor->dev;
960 struct drm_framebuffer *fb;
961
962 mutex_lock(&drm->mode_config.fb_lock);
963
964 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
965 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200966 fb->base.id, fb->width, fb->height,
967 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200968 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000969 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100970 }
971
972 mutex_unlock(&drm->mode_config.fb_lock);
973
974 return 0;
975}
976
Thierry Reding28c23372015-01-23 09:16:03 +0100977static int tegra_debugfs_iova(struct seq_file *s, void *data)
978{
979 struct drm_info_node *node = (struct drm_info_node *)s->private;
980 struct drm_device *drm = node->minor->dev;
981 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100982 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100983
Michał Mirosław68d890a2017-08-14 23:53:45 +0200984 if (tegra->domain) {
985 mutex_lock(&tegra->mm_lock);
986 drm_mm_print(&tegra->mm, &p);
987 mutex_unlock(&tegra->mm_lock);
988 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100989
990 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100991}
992
Thierry Redinge450fcc2013-02-13 16:13:16 +0100993static struct drm_info_list tegra_debugfs_list[] = {
994 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +0100995 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +0100996};
997
998static int tegra_debugfs_init(struct drm_minor *minor)
999{
1000 return drm_debugfs_create_files(tegra_debugfs_list,
1001 ARRAY_SIZE(tegra_debugfs_list),
1002 minor->debugfs_root, minor);
1003}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001004#endif
1005
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001006static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001007 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001008 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001009 .load = tegra_drm_load,
1010 .unload = tegra_drm_unload,
1011 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001012 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001013 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001014
Thierry Redinge450fcc2013-02-13 16:13:16 +01001015#if defined(CONFIG_DEBUG_FS)
1016 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001017#endif
1018
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001019 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001020 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001021
1022 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1023 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1024 .gem_prime_export = tegra_gem_prime_export,
1025 .gem_prime_import = tegra_gem_prime_import,
1026
Arto Merilainende2ba662013-03-22 16:34:08 +02001027 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001028
1029 .ioctls = tegra_drm_ioctls,
1030 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1031 .fops = &tegra_drm_fops,
1032
1033 .name = DRIVER_NAME,
1034 .desc = DRIVER_DESC,
1035 .date = DRIVER_DATE,
1036 .major = DRIVER_MAJOR,
1037 .minor = DRIVER_MINOR,
1038 .patchlevel = DRIVER_PATCHLEVEL,
1039};
Thierry Reding776dc382013-10-14 14:43:22 +02001040
1041int tegra_drm_register_client(struct tegra_drm *tegra,
1042 struct tegra_drm_client *client)
1043{
1044 mutex_lock(&tegra->clients_lock);
1045 list_add_tail(&client->list, &tegra->clients);
Thierry Reding8e5d19c2019-02-01 14:28:31 +01001046 client->drm = tegra;
Thierry Reding776dc382013-10-14 14:43:22 +02001047 mutex_unlock(&tegra->clients_lock);
1048
1049 return 0;
1050}
1051
1052int tegra_drm_unregister_client(struct tegra_drm *tegra,
1053 struct tegra_drm_client *client)
1054{
1055 mutex_lock(&tegra->clients_lock);
1056 list_del_init(&client->list);
Thierry Reding8e5d19c2019-02-01 14:28:31 +01001057 client->drm = NULL;
Thierry Reding776dc382013-10-14 14:43:22 +02001058 mutex_unlock(&tegra->clients_lock);
1059
1060 return 0;
1061}
1062
Thierry Reding0c407de2018-05-04 15:02:24 +02001063struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1064 bool shared)
1065{
1066 struct drm_device *drm = dev_get_drvdata(client->parent);
1067 struct tegra_drm *tegra = drm->dev_private;
1068 struct iommu_group *group = NULL;
1069 int err;
1070
1071 if (tegra->domain) {
1072 group = iommu_group_get(client->dev);
1073 if (!group) {
1074 dev_err(client->dev, "failed to get IOMMU group\n");
1075 return ERR_PTR(-ENODEV);
1076 }
1077
1078 if (!shared || (shared && (group != tegra->group))) {
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +03001079#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
1080 if (client->dev->archdata.mapping) {
1081 struct dma_iommu_mapping *mapping =
1082 to_dma_iommu_mapping(client->dev);
1083 arm_iommu_detach_device(client->dev);
1084 arm_iommu_release_mapping(mapping);
1085 }
1086#endif
Thierry Reding0c407de2018-05-04 15:02:24 +02001087 err = iommu_attach_group(tegra->domain, group);
1088 if (err < 0) {
1089 iommu_group_put(group);
1090 return ERR_PTR(err);
1091 }
1092
1093 if (shared && !tegra->group)
1094 tegra->group = group;
1095 }
1096 }
1097
1098 return group;
1099}
1100
1101void host1x_client_iommu_detach(struct host1x_client *client,
1102 struct iommu_group *group)
1103{
1104 struct drm_device *drm = dev_get_drvdata(client->parent);
1105 struct tegra_drm *tegra = drm->dev_private;
1106
1107 if (group) {
1108 if (group == tegra->group) {
1109 iommu_detach_group(tegra->domain, group);
1110 tegra->group = NULL;
1111 }
1112
1113 iommu_group_put(group);
1114 }
1115}
1116
Thierry Reding67485fb2017-11-09 13:17:11 +01001117void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001118{
1119 struct iova *alloc;
1120 void *virt;
1121 gfp_t gfp;
1122 int err;
1123
1124 if (tegra->domain)
1125 size = iova_align(&tegra->carveout.domain, size);
1126 else
1127 size = PAGE_ALIGN(size);
1128
1129 gfp = GFP_KERNEL | __GFP_ZERO;
1130 if (!tegra->domain) {
1131 /*
1132 * Many units only support 32-bit addresses, even on 64-bit
1133 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1134 * virtual address space, force allocations to be in the
1135 * lower 32-bit range.
1136 */
1137 gfp |= GFP_DMA;
1138 }
1139
1140 virt = (void *)__get_free_pages(gfp, get_order(size));
1141 if (!virt)
1142 return ERR_PTR(-ENOMEM);
1143
1144 if (!tegra->domain) {
1145 /*
1146 * If IOMMU is disabled, devices address physical memory
1147 * directly.
1148 */
1149 *dma = virt_to_phys(virt);
1150 return virt;
1151 }
1152
1153 alloc = alloc_iova(&tegra->carveout.domain,
1154 size >> tegra->carveout.shift,
1155 tegra->carveout.limit, true);
1156 if (!alloc) {
1157 err = -EBUSY;
1158 goto free_pages;
1159 }
1160
1161 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1162 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1163 size, IOMMU_READ | IOMMU_WRITE);
1164 if (err < 0)
1165 goto free_iova;
1166
1167 return virt;
1168
1169free_iova:
1170 __free_iova(&tegra->carveout.domain, alloc);
1171free_pages:
1172 free_pages((unsigned long)virt, get_order(size));
1173
1174 return ERR_PTR(err);
1175}
1176
1177void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1178 dma_addr_t dma)
1179{
1180 if (tegra->domain)
1181 size = iova_align(&tegra->carveout.domain, size);
1182 else
1183 size = PAGE_ALIGN(size);
1184
1185 if (tegra->domain) {
1186 iommu_unmap(tegra->domain, dma, size);
1187 free_iova(&tegra->carveout.domain,
1188 iova_pfn(&tegra->carveout.domain, dma));
1189 }
1190
1191 free_pages((unsigned long)virt, get_order(size));
1192}
1193
Thierry Reding9910f5c2014-05-22 09:57:15 +02001194static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001195{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001196 struct drm_driver *driver = &tegra_drm_driver;
1197 struct drm_device *drm;
1198 int err;
1199
1200 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001201 if (IS_ERR(drm))
1202 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001203
Thierry Reding9910f5c2014-05-22 09:57:15 +02001204 dev_set_drvdata(&dev->dev, drm);
1205
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001206 err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false);
1207 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001208 goto put;
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001209
Thierry Reding9910f5c2014-05-22 09:57:15 +02001210 err = drm_dev_register(drm, 0);
1211 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001212 goto put;
Thierry Reding9910f5c2014-05-22 09:57:15 +02001213
Thierry Reding9910f5c2014-05-22 09:57:15 +02001214 return 0;
1215
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001216put:
1217 drm_dev_put(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001218 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001219}
1220
Thierry Reding9910f5c2014-05-22 09:57:15 +02001221static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001222{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001223 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1224
1225 drm_dev_unregister(drm);
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001226 drm_dev_put(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001227
1228 return 0;
1229}
1230
Thierry Reding359ae682014-12-18 17:15:25 +01001231#ifdef CONFIG_PM_SLEEP
1232static int host1x_drm_suspend(struct device *dev)
1233{
1234 struct drm_device *drm = dev_get_drvdata(dev);
1235
Souptick Joarder53f1e062018-08-01 01:37:05 +05301236 return drm_mode_config_helper_suspend(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001237}
1238
1239static int host1x_drm_resume(struct device *dev)
1240{
1241 struct drm_device *drm = dev_get_drvdata(dev);
1242
Souptick Joarder53f1e062018-08-01 01:37:05 +05301243 return drm_mode_config_helper_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001244}
1245#endif
1246
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001247static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1248 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001249
Thierry Reding776dc382013-10-14 14:43:22 +02001250static const struct of_device_id host1x_drm_subdevs[] = {
1251 { .compatible = "nvidia,tegra20-dc", },
1252 { .compatible = "nvidia,tegra20-hdmi", },
1253 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001254 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001255 { .compatible = "nvidia,tegra30-dc", },
1256 { .compatible = "nvidia,tegra30-hdmi", },
1257 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001258 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001259 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001260 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001261 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001262 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001263 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001264 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001265 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001266 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001267 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001268 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001269 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001270 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001271 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001272 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001273 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001274 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001275 { .compatible = "nvidia,tegra186-sor", },
1276 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001277 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding5725daa2018-09-21 12:27:43 +02001278 { .compatible = "nvidia,tegra194-display", },
Thierry Reding47443192018-09-21 12:27:44 +02001279 { .compatible = "nvidia,tegra194-dc", },
Thierry Reding9b6c14b2018-09-21 12:27:46 +02001280 { .compatible = "nvidia,tegra194-sor", },
Thierry Redingd6b9bc02018-10-26 10:59:38 +02001281 { .compatible = "nvidia,tegra194-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001282 { /* sentinel */ }
1283};
1284
1285static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001286 .driver = {
1287 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001288 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001289 },
Thierry Reding776dc382013-10-14 14:43:22 +02001290 .probe = host1x_drm_probe,
1291 .remove = host1x_drm_remove,
1292 .subdevs = host1x_drm_subdevs,
1293};
1294
Thierry Reding473112e2015-09-10 16:07:14 +02001295static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001296 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001297 &tegra_dc_driver,
1298 &tegra_hdmi_driver,
1299 &tegra_dsi_driver,
1300 &tegra_dpaux_driver,
1301 &tegra_sor_driver,
1302 &tegra_gr2d_driver,
1303 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001304 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001305};
1306
Thierry Reding776dc382013-10-14 14:43:22 +02001307static int __init host1x_drm_init(void)
1308{
1309 int err;
1310
1311 err = host1x_driver_register(&host1x_drm_driver);
1312 if (err < 0)
1313 return err;
1314
Thierry Reding473112e2015-09-10 16:07:14 +02001315 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001316 if (err < 0)
1317 goto unregister_host1x;
1318
Thierry Reding776dc382013-10-14 14:43:22 +02001319 return 0;
1320
Thierry Reding776dc382013-10-14 14:43:22 +02001321unregister_host1x:
1322 host1x_driver_unregister(&host1x_drm_driver);
1323 return err;
1324}
1325module_init(host1x_drm_init);
1326
1327static void __exit host1x_drm_exit(void)
1328{
Thierry Reding473112e2015-09-10 16:07:14 +02001329 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001330 host1x_driver_unregister(&host1x_drm_driver);
1331}
1332module_exit(host1x_drm_exit);
1333
1334MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1335MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1336MODULE_LICENSE("GPL v2");