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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingab7d3f52017-12-14 13:46:20 +010036static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010038{
Thierry Reding1503ca42014-11-24 17:41:23 +010039 int err;
40
Thierry Redingab7d3f52017-12-14 13:46:20 +010041 err = drm_atomic_helper_check_modeset(drm, state);
42 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010043 return err;
44
Thierry Reding0281c412017-11-28 11:20:40 +010045 err = tegra_display_hub_atomic_check(drm, state);
46 if (err < 0)
47 return err;
48
Thierry Redingab7d3f52017-12-14 13:46:20 +010049 err = drm_atomic_normalize_zpos(drm, state);
50 if (err < 0)
Maarten Lankhorst424624e2017-07-11 16:33:10 +020051 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010052
Thierry Redingab7d3f52017-12-14 13:46:20 +010053 err = drm_atomic_helper_check_planes(drm, state);
54 if (err < 0)
55 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010056
Thierry Redingab7d3f52017-12-14 13:46:20 +010057 if (state->legacy_cursor_update)
58 state->async_update = !drm_atomic_helper_async_check(drm, state);
59
Thierry Reding1503ca42014-11-24 17:41:23 +010060 return 0;
61}
62
Thierry Reding31b02ca2017-10-12 17:40:46 +020063static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010064 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053065#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010066 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010067#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010068 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020069 .atomic_commit = drm_atomic_helper_commit,
70};
71
Thierry Redingc4755fb2017-11-13 11:08:13 +010072static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
73{
74 struct drm_device *drm = old_state->dev;
75 struct tegra_drm *tegra = drm->dev_private;
76
77 if (tegra->hub) {
78 drm_atomic_helper_commit_modeset_disables(drm, old_state);
79 tegra_display_hub_atomic_commit(drm, old_state);
80 drm_atomic_helper_commit_planes(drm, old_state, 0);
81 drm_atomic_helper_commit_modeset_enables(drm, old_state);
82 drm_atomic_helper_commit_hw_done(old_state);
83 drm_atomic_helper_wait_for_vblanks(drm, old_state);
84 drm_atomic_helper_cleanup_planes(drm, old_state);
85 } else {
86 drm_atomic_helper_commit_tail_rpm(old_state);
87 }
88}
89
Thierry Reding31b02ca2017-10-12 17:40:46 +020090static const struct drm_mode_config_helper_funcs
91tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010092 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010093};
94
Thierry Reding776dc382013-10-14 14:43:22 +020095static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000096{
Thierry Reding776dc382013-10-14 14:43:22 +020097 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020098 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000099 int err;
100
Thierry Reding776dc382013-10-14 14:43:22 +0200101 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200102 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200103 return -ENOMEM;
104
Thierry Redingdf06b752014-06-26 21:41:53 +0200105 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200106 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100107 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200108 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100109
Thierry Redingdf06b752014-06-26 21:41:53 +0200110 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300111 if (!tegra->domain) {
112 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200113 goto free;
114 }
115
Thierry Reding4553f732015-01-19 16:15:04 +0100116 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200117 gem_start = geometry->aperture_start;
118 gem_end = geometry->aperture_end - CARVEOUT_SZ;
119 carveout_start = gem_end + 1;
120 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100121
Mikko Perttunenad926012016-12-14 13:16:11 +0200122 order = __ffs(tegra->domain->pgsize_bitmap);
123 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100124 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200125
126 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
127 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
128
129 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100130 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200131
132 DRM_DEBUG("IOMMU apertures:\n");
133 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
134 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
135 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200136 }
137
Thierry Reding386a2a72013-09-24 13:22:17 +0200138 mutex_init(&tegra->clients_lock);
139 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100140
Thierry Reding386a2a72013-09-24 13:22:17 +0200141 drm->dev_private = tegra;
142 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000143
144 drm_mode_config_init(drm);
145
Thierry Redingf9914212014-11-26 13:03:57 +0100146 drm->mode_config.min_width = 0;
147 drm->mode_config.min_height = 0;
148
149 drm->mode_config.max_width = 4096;
150 drm->mode_config.max_height = 4096;
151
Alexandre Courbot5e911442016-11-08 16:50:42 +0900152 drm->mode_config.allow_fb_modifiers = true;
153
Thierry Reding31b02ca2017-10-12 17:40:46 +0200154 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
155 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100156
Thierry Redinge2215322014-06-27 17:19:25 +0200157 err = tegra_drm_fb_prepare(drm);
158 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100159 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200160
161 drm_kms_helper_poll_init(drm);
162
Thierry Reding776dc382013-10-14 14:43:22 +0200163 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000164 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100165 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000166
Thierry Redingc4755fb2017-11-13 11:08:13 +0100167 if (tegra->hub) {
168 err = tegra_display_hub_prepare(tegra->hub);
169 if (err < 0)
170 goto device;
171 }
172
Thierry Reding603f0cc2013-04-22 21:22:14 +0200173 /*
174 * We don't use the drm_irq_install() helpers provided by the DRM
175 * core, so we need to set this manually in order to allow the
176 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
177 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300178 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200179
Thierry Reding42e9ce02015-01-28 14:43:05 +0100180 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100181 drm->max_vblank_count = 0xffffffff;
182
Thierry Reding6e5ff992012-11-28 11:45:47 +0100183 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
184 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100185 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100186
Thierry Reding31930d42015-07-02 17:04:06 +0200187 drm_mode_config_reset(drm);
188
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000189 err = tegra_drm_fb_init(drm);
190 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100191 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000192
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000193 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100194
Thierry Redingc4755fb2017-11-13 11:08:13 +0100195hub:
196 if (tegra->hub)
197 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100198device:
199 host1x_device_exit(device);
200fbdev:
201 drm_kms_helper_poll_fini(drm);
202 tegra_drm_fb_free(drm);
203config:
204 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200205
206 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100207 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200208 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200209 put_iova_domain(&tegra->carveout.domain);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200210 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200211 }
212free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100213 kfree(tegra);
214 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000215}
216
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200217static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000218{
Thierry Reding776dc382013-10-14 14:43:22 +0200219 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200220 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200221 int err;
222
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000223 drm_kms_helper_poll_fini(drm);
224 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100225 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200226 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000227
Thierry Reding776dc382013-10-14 14:43:22 +0200228 err = host1x_device_exit(device);
229 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200230 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200231
Thierry Redingdf06b752014-06-26 21:41:53 +0200232 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100233 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200234 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200235 put_iova_domain(&tegra->carveout.domain);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200236 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200237 }
238
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100239 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000240}
241
242static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
243{
Thierry Reding08943e62013-09-26 16:08:18 +0200244 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200245
246 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
247 if (!fpriv)
248 return -ENOMEM;
249
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100250 idr_init(&fpriv->contexts);
251 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200252 filp->driver_priv = fpriv;
253
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000254 return 0;
255}
256
Thierry Redingc88c3632013-09-26 16:08:22 +0200257static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200258{
259 context->client->ops->close_channel(context);
260 kfree(context);
261}
262
Thierry Redingc40f0f12013-10-10 11:00:33 +0200263static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100264host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200265{
266 struct drm_gem_object *gem;
267 struct tegra_bo *bo;
268
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100269 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200270 if (!gem)
271 return NULL;
272
Thierry Redingc40f0f12013-10-10 11:00:33 +0200273 bo = to_tegra_bo(gem);
274 return &bo->base;
275}
276
Thierry Reding961e3be2014-06-10 10:25:00 +0200277static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
278 struct drm_tegra_reloc __user *src,
279 struct drm_device *drm,
280 struct drm_file *file)
281{
282 u32 cmdbuf, target;
283 int err;
284
285 err = get_user(cmdbuf, &src->cmdbuf.handle);
286 if (err < 0)
287 return err;
288
289 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
290 if (err < 0)
291 return err;
292
293 err = get_user(target, &src->target.handle);
294 if (err < 0)
295 return err;
296
David Ung31f40f82015-01-20 18:37:35 -0800297 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200298 if (err < 0)
299 return err;
300
301 err = get_user(dest->shift, &src->shift);
302 if (err < 0)
303 return err;
304
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100305 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200306 if (!dest->cmdbuf.bo)
307 return -ENOENT;
308
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100309 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200310 if (!dest->target.bo)
311 return -ENOENT;
312
313 return 0;
314}
315
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300316static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
317 struct drm_tegra_waitchk __user *src,
318 struct drm_file *file)
319{
320 u32 cmdbuf;
321 int err;
322
323 err = get_user(cmdbuf, &src->handle);
324 if (err < 0)
325 return err;
326
327 err = get_user(dest->offset, &src->offset);
328 if (err < 0)
329 return err;
330
331 err = get_user(dest->syncpt_id, &src->syncpt);
332 if (err < 0)
333 return err;
334
335 err = get_user(dest->thresh, &src->thresh);
336 if (err < 0)
337 return err;
338
339 dest->bo = host1x_bo_lookup(file, cmdbuf);
340 if (!dest->bo)
341 return -ENOENT;
342
343 return 0;
344}
345
Thierry Redingc40f0f12013-10-10 11:00:33 +0200346int tegra_drm_submit(struct tegra_drm_context *context,
347 struct drm_tegra_submit *args, struct drm_device *drm,
348 struct drm_file *file)
349{
350 unsigned int num_cmdbufs = args->num_cmdbufs;
351 unsigned int num_relocs = args->num_relocs;
352 unsigned int num_waitchks = args->num_waitchks;
Mikko Perttunena176c672017-09-28 15:50:44 +0300353 struct drm_tegra_cmdbuf __user *user_cmdbufs;
354 struct drm_tegra_reloc __user *user_relocs;
355 struct drm_tegra_waitchk __user *user_waitchks;
356 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200357 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300358 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200359 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300360 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200361 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200362 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200363 int err;
364
Mikko Perttunena176c672017-09-28 15:50:44 +0300365 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
366 user_relocs = u64_to_user_ptr(args->relocs);
367 user_waitchks = u64_to_user_ptr(args->waitchks);
368 user_syncpt = u64_to_user_ptr(args->syncpts);
369
Thierry Redingc40f0f12013-10-10 11:00:33 +0200370 /* We don't yet support other than one syncpt_incr struct per submit */
371 if (args->num_syncpts != 1)
372 return -EINVAL;
373
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300374 /* We don't yet support waitchks */
375 if (args->num_waitchks != 0)
376 return -EINVAL;
377
Thierry Redingc40f0f12013-10-10 11:00:33 +0200378 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
379 args->num_relocs, args->num_waitchks);
380 if (!job)
381 return -ENOMEM;
382
383 job->num_relocs = args->num_relocs;
384 job->num_waitchk = args->num_waitchks;
385 job->client = (u32)args->context;
386 job->class = context->client->base.class;
387 job->serialize = true;
388
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200389 /*
390 * Track referenced BOs so that they can be unreferenced after the
391 * submission is complete.
392 */
393 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
394
395 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
396 if (!refs) {
397 err = -ENOMEM;
398 goto put;
399 }
400
401 /* reuse as an iterator later */
402 num_refs = 0;
403
Thierry Redingc40f0f12013-10-10 11:00:33 +0200404 while (num_cmdbufs) {
405 struct drm_tegra_cmdbuf cmdbuf;
406 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300407 struct tegra_bo *obj;
408 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200409
Mikko Perttunena176c672017-09-28 15:50:44 +0300410 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300411 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200412 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300413 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200414
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300415 /*
416 * The maximum number of CDMA gather fetches is 16383, a higher
417 * value means the words count is malformed.
418 */
419 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
420 err = -EINVAL;
421 goto fail;
422 }
423
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100424 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200425 if (!bo) {
426 err = -ENOENT;
427 goto fail;
428 }
429
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300430 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
431 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200432 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300433
434 /*
435 * Gather buffer base address must be 4-bytes aligned,
436 * unaligned offset is malformed and cause commands stream
437 * corruption on the buffer address relocation.
438 */
439 if (offset & 3 || offset >= obj->gem.size) {
440 err = -EINVAL;
441 goto fail;
442 }
443
Thierry Redingc40f0f12013-10-10 11:00:33 +0200444 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
445 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300446 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200447 }
448
Thierry Reding961e3be2014-06-10 10:25:00 +0200449 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200450 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300451 struct host1x_reloc *reloc;
452 struct tegra_bo *obj;
453
Thierry Reding961e3be2014-06-10 10:25:00 +0200454 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300455 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200456 file);
457 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200458 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300459
460 reloc = &job->relocarray[num_relocs];
461 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200462 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300463
464 /*
465 * The unaligned cmdbuf offset will cause an unaligned write
466 * during of the relocations patching, corrupting the commands
467 * stream.
468 */
469 if (reloc->cmdbuf.offset & 3 ||
470 reloc->cmdbuf.offset >= obj->gem.size) {
471 err = -EINVAL;
472 goto fail;
473 }
474
475 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200476 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300477
478 if (reloc->target.offset >= obj->gem.size) {
479 err = -EINVAL;
480 goto fail;
481 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200482 }
483
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300484 /* copy and resolve waitchks from submit */
485 while (num_waitchks--) {
486 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
487 struct tegra_bo *obj;
488
Mikko Perttunena176c672017-09-28 15:50:44 +0300489 err = host1x_waitchk_copy_from_user(
490 wait, &user_waitchks[num_waitchks], file);
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300491 if (err < 0)
492 goto fail;
493
494 obj = host1x_to_tegra_bo(wait->bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200495 refs[num_refs++] = &obj->gem;
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300496
497 /*
498 * The unaligned offset will cause an unaligned write during
499 * of the waitchks patching, corrupting the commands stream.
500 */
501 if (wait->offset & 3 ||
502 wait->offset >= obj->gem.size) {
503 err = -EINVAL;
504 goto fail;
505 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300506 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200507
Mikko Perttunena176c672017-09-28 15:50:44 +0300508 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300509 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200510 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300511 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200512
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300513 /* check whether syncpoint ID is valid */
514 sp = host1x_syncpt_get(host1x, syncpt.id);
515 if (!sp) {
516 err = -ENOENT;
517 goto fail;
518 }
519
Thierry Redingc40f0f12013-10-10 11:00:33 +0200520 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300521 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200522 job->syncpt_incrs = syncpt.incrs;
523 job->syncpt_id = syncpt.id;
524 job->timeout = 10000;
525
526 if (args->timeout && args->timeout < 10000)
527 job->timeout = args->timeout;
528
529 err = host1x_job_pin(job, context->client->base.dev);
530 if (err)
531 goto fail;
532
533 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200534 if (err) {
535 host1x_job_unpin(job);
536 goto fail;
537 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200538
539 args->fence = job->syncpt_end;
540
Thierry Redingc40f0f12013-10-10 11:00:33 +0200541fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200542 while (num_refs--)
543 drm_gem_object_put_unlocked(refs[num_refs]);
544
545 kfree(refs);
546
547put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200548 host1x_job_put(job);
549 return err;
550}
551
552
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200553#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200554static int tegra_gem_create(struct drm_device *drm, void *data,
555 struct drm_file *file)
556{
557 struct drm_tegra_gem_create *args = data;
558 struct tegra_bo *bo;
559
Thierry Reding773af772013-10-04 22:34:01 +0200560 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200561 &args->handle);
562 if (IS_ERR(bo))
563 return PTR_ERR(bo);
564
565 return 0;
566}
567
568static int tegra_gem_mmap(struct drm_device *drm, void *data,
569 struct drm_file *file)
570{
571 struct drm_tegra_gem_mmap *args = data;
572 struct drm_gem_object *gem;
573 struct tegra_bo *bo;
574
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100575 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200576 if (!gem)
577 return -EINVAL;
578
579 bo = to_tegra_bo(gem);
580
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200581 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200582
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300583 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200584
585 return 0;
586}
587
588static int tegra_syncpt_read(struct drm_device *drm, void *data,
589 struct drm_file *file)
590{
Thierry Reding776dc382013-10-14 14:43:22 +0200591 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200592 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200593 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200594
Thierry Reding776dc382013-10-14 14:43:22 +0200595 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200596 if (!sp)
597 return -EINVAL;
598
599 args->value = host1x_syncpt_read_min(sp);
600 return 0;
601}
602
603static int tegra_syncpt_incr(struct drm_device *drm, void *data,
604 struct drm_file *file)
605{
Thierry Reding776dc382013-10-14 14:43:22 +0200606 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200607 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200608 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200609
Thierry Reding776dc382013-10-14 14:43:22 +0200610 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200611 if (!sp)
612 return -EINVAL;
613
Arto Merilainenebae30b2013-05-29 13:26:08 +0300614 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200615}
616
617static int tegra_syncpt_wait(struct drm_device *drm, void *data,
618 struct drm_file *file)
619{
Thierry Reding776dc382013-10-14 14:43:22 +0200620 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200621 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200622 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200623
Thierry Reding776dc382013-10-14 14:43:22 +0200624 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200625 if (!sp)
626 return -EINVAL;
627
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300628 return host1x_syncpt_wait(sp, args->thresh,
629 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200630 &args->value);
631}
632
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100633static int tegra_client_open(struct tegra_drm_file *fpriv,
634 struct tegra_drm_client *client,
635 struct tegra_drm_context *context)
636{
637 int err;
638
639 err = client->ops->open_channel(client, context);
640 if (err < 0)
641 return err;
642
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300643 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100644 if (err < 0) {
645 client->ops->close_channel(context);
646 return err;
647 }
648
649 context->client = client;
650 context->id = err;
651
652 return 0;
653}
654
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200655static int tegra_open_channel(struct drm_device *drm, void *data,
656 struct drm_file *file)
657{
Thierry Reding08943e62013-09-26 16:08:18 +0200658 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200659 struct tegra_drm *tegra = drm->dev_private;
660 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200661 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200662 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200663 int err = -ENODEV;
664
665 context = kzalloc(sizeof(*context), GFP_KERNEL);
666 if (!context)
667 return -ENOMEM;
668
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100669 mutex_lock(&fpriv->lock);
670
Thierry Reding776dc382013-10-14 14:43:22 +0200671 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200672 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100673 err = tegra_client_open(fpriv, client, context);
674 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200675 break;
676
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100677 args->context = context->id;
678 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200679 }
680
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100681 if (err < 0)
682 kfree(context);
683
684 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200685 return err;
686}
687
688static int tegra_close_channel(struct drm_device *drm, void *data,
689 struct drm_file *file)
690{
Thierry Reding08943e62013-09-26 16:08:18 +0200691 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200692 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200693 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100694 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200695
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100696 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200697
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300698 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100699 if (!context) {
700 err = -EINVAL;
701 goto unlock;
702 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200703
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100704 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200705 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200706
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100707unlock:
708 mutex_unlock(&fpriv->lock);
709 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200710}
711
712static int tegra_get_syncpt(struct drm_device *drm, void *data,
713 struct drm_file *file)
714{
Thierry Reding08943e62013-09-26 16:08:18 +0200715 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200716 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200717 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200718 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100719 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200720
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100721 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200722
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300723 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100724 if (!context) {
725 err = -ENODEV;
726 goto unlock;
727 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200728
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100729 if (args->index >= context->client->base.num_syncpts) {
730 err = -EINVAL;
731 goto unlock;
732 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200733
Thierry Reding53fa7f72013-09-24 15:35:40 +0200734 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200735 args->id = host1x_syncpt_id(syncpt);
736
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100737unlock:
738 mutex_unlock(&fpriv->lock);
739 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200740}
741
742static int tegra_submit(struct drm_device *drm, void *data,
743 struct drm_file *file)
744{
Thierry Reding08943e62013-09-26 16:08:18 +0200745 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200746 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200747 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100748 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200749
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100750 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200751
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300752 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100753 if (!context) {
754 err = -ENODEV;
755 goto unlock;
756 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200757
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100758 err = context->client->ops->submit(context, args, drm, file);
759
760unlock:
761 mutex_unlock(&fpriv->lock);
762 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200763}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300764
765static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
766 struct drm_file *file)
767{
768 struct tegra_drm_file *fpriv = file->driver_priv;
769 struct drm_tegra_get_syncpt_base *args = data;
770 struct tegra_drm_context *context;
771 struct host1x_syncpt_base *base;
772 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100773 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300774
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100775 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300776
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300777 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100778 if (!context) {
779 err = -ENODEV;
780 goto unlock;
781 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300782
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100783 if (args->syncpt >= context->client->base.num_syncpts) {
784 err = -EINVAL;
785 goto unlock;
786 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300787
788 syncpt = context->client->base.syncpts[args->syncpt];
789
790 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100791 if (!base) {
792 err = -ENXIO;
793 goto unlock;
794 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300795
796 args->id = host1x_syncpt_base_id(base);
797
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100798unlock:
799 mutex_unlock(&fpriv->lock);
800 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300801}
Thierry Reding7678d712014-06-03 14:56:57 +0200802
803static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
804 struct drm_file *file)
805{
806 struct drm_tegra_gem_set_tiling *args = data;
807 enum tegra_bo_tiling_mode mode;
808 struct drm_gem_object *gem;
809 unsigned long value = 0;
810 struct tegra_bo *bo;
811
812 switch (args->mode) {
813 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
814 mode = TEGRA_BO_TILING_MODE_PITCH;
815
816 if (args->value != 0)
817 return -EINVAL;
818
819 break;
820
821 case DRM_TEGRA_GEM_TILING_MODE_TILED:
822 mode = TEGRA_BO_TILING_MODE_TILED;
823
824 if (args->value != 0)
825 return -EINVAL;
826
827 break;
828
829 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
830 mode = TEGRA_BO_TILING_MODE_BLOCK;
831
832 if (args->value > 5)
833 return -EINVAL;
834
835 value = args->value;
836 break;
837
838 default:
839 return -EINVAL;
840 }
841
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100842 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200843 if (!gem)
844 return -ENOENT;
845
846 bo = to_tegra_bo(gem);
847
848 bo->tiling.mode = mode;
849 bo->tiling.value = value;
850
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300851 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200852
853 return 0;
854}
855
856static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
857 struct drm_file *file)
858{
859 struct drm_tegra_gem_get_tiling *args = data;
860 struct drm_gem_object *gem;
861 struct tegra_bo *bo;
862 int err = 0;
863
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100864 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200865 if (!gem)
866 return -ENOENT;
867
868 bo = to_tegra_bo(gem);
869
870 switch (bo->tiling.mode) {
871 case TEGRA_BO_TILING_MODE_PITCH:
872 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
873 args->value = 0;
874 break;
875
876 case TEGRA_BO_TILING_MODE_TILED:
877 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
878 args->value = 0;
879 break;
880
881 case TEGRA_BO_TILING_MODE_BLOCK:
882 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
883 args->value = bo->tiling.value;
884 break;
885
886 default:
887 err = -EINVAL;
888 break;
889 }
890
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300891 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200892
893 return err;
894}
Thierry Reding7b129082014-06-10 12:04:03 +0200895
896static int tegra_gem_set_flags(struct drm_device *drm, void *data,
897 struct drm_file *file)
898{
899 struct drm_tegra_gem_set_flags *args = data;
900 struct drm_gem_object *gem;
901 struct tegra_bo *bo;
902
903 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
904 return -EINVAL;
905
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100906 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200907 if (!gem)
908 return -ENOENT;
909
910 bo = to_tegra_bo(gem);
911 bo->flags = 0;
912
913 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
914 bo->flags |= TEGRA_BO_BOTTOM_UP;
915
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300916 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200917
918 return 0;
919}
920
921static int tegra_gem_get_flags(struct drm_device *drm, void *data,
922 struct drm_file *file)
923{
924 struct drm_tegra_gem_get_flags *args = data;
925 struct drm_gem_object *gem;
926 struct tegra_bo *bo;
927
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100928 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200929 if (!gem)
930 return -ENOENT;
931
932 bo = to_tegra_bo(gem);
933 args->flags = 0;
934
935 if (bo->flags & TEGRA_BO_BOTTOM_UP)
936 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
937
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300938 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200939
940 return 0;
941}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200942#endif
943
Rob Clarkbaa70942013-08-02 13:27:49 -0400944static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200945#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200946 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
947 DRM_UNLOCKED | DRM_RENDER_ALLOW),
948 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
949 DRM_UNLOCKED | DRM_RENDER_ALLOW),
950 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
951 DRM_UNLOCKED | DRM_RENDER_ALLOW),
952 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
953 DRM_UNLOCKED | DRM_RENDER_ALLOW),
954 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
955 DRM_UNLOCKED | DRM_RENDER_ALLOW),
956 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
957 DRM_UNLOCKED | DRM_RENDER_ALLOW),
958 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
959 DRM_UNLOCKED | DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
961 DRM_UNLOCKED | DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
963 DRM_UNLOCKED | DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
965 DRM_UNLOCKED | DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
967 DRM_UNLOCKED | DRM_RENDER_ALLOW),
968 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
969 DRM_UNLOCKED | DRM_RENDER_ALLOW),
970 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
971 DRM_UNLOCKED | DRM_RENDER_ALLOW),
972 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
973 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200974#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000975};
976
977static const struct file_operations tegra_drm_fops = {
978 .owner = THIS_MODULE,
979 .open = drm_open,
980 .release = drm_release,
981 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200982 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000983 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000984 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000985 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000986 .llseek = noop_llseek,
987};
988
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100989static int tegra_drm_context_cleanup(int id, void *p, void *data)
990{
991 struct tegra_drm_context *context = p;
992
993 tegra_drm_context_free(context);
994
995 return 0;
996}
997
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200998static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100999{
Thierry Reding08943e62013-09-26 16:08:18 +02001000 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +01001001
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001002 mutex_lock(&fpriv->lock);
1003 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1004 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001005
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001006 idr_destroy(&fpriv->contexts);
1007 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001008 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001009}
1010
Thierry Redinge450fcc2013-02-13 16:13:16 +01001011#ifdef CONFIG_DEBUG_FS
1012static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1013{
1014 struct drm_info_node *node = (struct drm_info_node *)s->private;
1015 struct drm_device *drm = node->minor->dev;
1016 struct drm_framebuffer *fb;
1017
1018 mutex_lock(&drm->mode_config.fb_lock);
1019
1020 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1021 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001022 fb->base.id, fb->width, fb->height,
1023 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001024 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001025 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001026 }
1027
1028 mutex_unlock(&drm->mode_config.fb_lock);
1029
1030 return 0;
1031}
1032
Thierry Reding28c23372015-01-23 09:16:03 +01001033static int tegra_debugfs_iova(struct seq_file *s, void *data)
1034{
1035 struct drm_info_node *node = (struct drm_info_node *)s->private;
1036 struct drm_device *drm = node->minor->dev;
1037 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001038 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001039
Michał Mirosław68d890a2017-08-14 23:53:45 +02001040 if (tegra->domain) {
1041 mutex_lock(&tegra->mm_lock);
1042 drm_mm_print(&tegra->mm, &p);
1043 mutex_unlock(&tegra->mm_lock);
1044 }
Daniel Vetterb5c37142016-12-29 12:09:24 +01001045
1046 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001047}
1048
Thierry Redinge450fcc2013-02-13 16:13:16 +01001049static struct drm_info_list tegra_debugfs_list[] = {
1050 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001051 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001052};
1053
1054static int tegra_debugfs_init(struct drm_minor *minor)
1055{
1056 return drm_debugfs_create_files(tegra_debugfs_list,
1057 ARRAY_SIZE(tegra_debugfs_list),
1058 minor->debugfs_root, minor);
1059}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001060#endif
1061
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001062static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001063 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001064 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001065 .load = tegra_drm_load,
1066 .unload = tegra_drm_unload,
1067 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001068 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001069 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001070
Thierry Redinge450fcc2013-02-13 16:13:16 +01001071#if defined(CONFIG_DEBUG_FS)
1072 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001073#endif
1074
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001075 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001076 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001077
1078 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1079 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1080 .gem_prime_export = tegra_gem_prime_export,
1081 .gem_prime_import = tegra_gem_prime_import,
1082
Arto Merilainende2ba662013-03-22 16:34:08 +02001083 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001084
1085 .ioctls = tegra_drm_ioctls,
1086 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1087 .fops = &tegra_drm_fops,
1088
1089 .name = DRIVER_NAME,
1090 .desc = DRIVER_DESC,
1091 .date = DRIVER_DATE,
1092 .major = DRIVER_MAJOR,
1093 .minor = DRIVER_MINOR,
1094 .patchlevel = DRIVER_PATCHLEVEL,
1095};
Thierry Reding776dc382013-10-14 14:43:22 +02001096
1097int tegra_drm_register_client(struct tegra_drm *tegra,
1098 struct tegra_drm_client *client)
1099{
1100 mutex_lock(&tegra->clients_lock);
1101 list_add_tail(&client->list, &tegra->clients);
1102 mutex_unlock(&tegra->clients_lock);
1103
1104 return 0;
1105}
1106
1107int tegra_drm_unregister_client(struct tegra_drm *tegra,
1108 struct tegra_drm_client *client)
1109{
1110 mutex_lock(&tegra->clients_lock);
1111 list_del_init(&client->list);
1112 mutex_unlock(&tegra->clients_lock);
1113
1114 return 0;
1115}
1116
Thierry Reding0c407de2018-05-04 15:02:24 +02001117struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1118 bool shared)
1119{
1120 struct drm_device *drm = dev_get_drvdata(client->parent);
1121 struct tegra_drm *tegra = drm->dev_private;
1122 struct iommu_group *group = NULL;
1123 int err;
1124
1125 if (tegra->domain) {
1126 group = iommu_group_get(client->dev);
1127 if (!group) {
1128 dev_err(client->dev, "failed to get IOMMU group\n");
1129 return ERR_PTR(-ENODEV);
1130 }
1131
1132 if (!shared || (shared && (group != tegra->group))) {
1133 err = iommu_attach_group(tegra->domain, group);
1134 if (err < 0) {
1135 iommu_group_put(group);
1136 return ERR_PTR(err);
1137 }
1138
1139 if (shared && !tegra->group)
1140 tegra->group = group;
1141 }
1142 }
1143
1144 return group;
1145}
1146
1147void host1x_client_iommu_detach(struct host1x_client *client,
1148 struct iommu_group *group)
1149{
1150 struct drm_device *drm = dev_get_drvdata(client->parent);
1151 struct tegra_drm *tegra = drm->dev_private;
1152
1153 if (group) {
1154 if (group == tegra->group) {
1155 iommu_detach_group(tegra->domain, group);
1156 tegra->group = NULL;
1157 }
1158
1159 iommu_group_put(group);
1160 }
1161}
1162
Thierry Reding67485fb2017-11-09 13:17:11 +01001163void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001164{
1165 struct iova *alloc;
1166 void *virt;
1167 gfp_t gfp;
1168 int err;
1169
1170 if (tegra->domain)
1171 size = iova_align(&tegra->carveout.domain, size);
1172 else
1173 size = PAGE_ALIGN(size);
1174
1175 gfp = GFP_KERNEL | __GFP_ZERO;
1176 if (!tegra->domain) {
1177 /*
1178 * Many units only support 32-bit addresses, even on 64-bit
1179 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1180 * virtual address space, force allocations to be in the
1181 * lower 32-bit range.
1182 */
1183 gfp |= GFP_DMA;
1184 }
1185
1186 virt = (void *)__get_free_pages(gfp, get_order(size));
1187 if (!virt)
1188 return ERR_PTR(-ENOMEM);
1189
1190 if (!tegra->domain) {
1191 /*
1192 * If IOMMU is disabled, devices address physical memory
1193 * directly.
1194 */
1195 *dma = virt_to_phys(virt);
1196 return virt;
1197 }
1198
1199 alloc = alloc_iova(&tegra->carveout.domain,
1200 size >> tegra->carveout.shift,
1201 tegra->carveout.limit, true);
1202 if (!alloc) {
1203 err = -EBUSY;
1204 goto free_pages;
1205 }
1206
1207 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1208 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1209 size, IOMMU_READ | IOMMU_WRITE);
1210 if (err < 0)
1211 goto free_iova;
1212
1213 return virt;
1214
1215free_iova:
1216 __free_iova(&tegra->carveout.domain, alloc);
1217free_pages:
1218 free_pages((unsigned long)virt, get_order(size));
1219
1220 return ERR_PTR(err);
1221}
1222
1223void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1224 dma_addr_t dma)
1225{
1226 if (tegra->domain)
1227 size = iova_align(&tegra->carveout.domain, size);
1228 else
1229 size = PAGE_ALIGN(size);
1230
1231 if (tegra->domain) {
1232 iommu_unmap(tegra->domain, dma, size);
1233 free_iova(&tegra->carveout.domain,
1234 iova_pfn(&tegra->carveout.domain, dma));
1235 }
1236
1237 free_pages((unsigned long)virt, get_order(size));
1238}
1239
Thierry Reding9910f5c2014-05-22 09:57:15 +02001240static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001241{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001242 struct drm_driver *driver = &tegra_drm_driver;
1243 struct drm_device *drm;
1244 int err;
1245
1246 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001247 if (IS_ERR(drm))
1248 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001249
Thierry Reding9910f5c2014-05-22 09:57:15 +02001250 dev_set_drvdata(&dev->dev, drm);
1251
1252 err = drm_dev_register(drm, 0);
1253 if (err < 0)
1254 goto unref;
1255
Thierry Reding9910f5c2014-05-22 09:57:15 +02001256 return 0;
1257
1258unref:
1259 drm_dev_unref(drm);
1260 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001261}
1262
Thierry Reding9910f5c2014-05-22 09:57:15 +02001263static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001264{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001265 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1266
1267 drm_dev_unregister(drm);
1268 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001269
1270 return 0;
1271}
1272
Thierry Reding359ae682014-12-18 17:15:25 +01001273#ifdef CONFIG_PM_SLEEP
1274static int host1x_drm_suspend(struct device *dev)
1275{
1276 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001277 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001278
1279 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001280 tegra_drm_fb_suspend(drm);
1281
1282 tegra->state = drm_atomic_helper_suspend(drm);
1283 if (IS_ERR(tegra->state)) {
1284 tegra_drm_fb_resume(drm);
1285 drm_kms_helper_poll_enable(drm);
1286 return PTR_ERR(tegra->state);
1287 }
Thierry Reding359ae682014-12-18 17:15:25 +01001288
1289 return 0;
1290}
1291
1292static int host1x_drm_resume(struct device *dev)
1293{
1294 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001295 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001296
Thierry Reding986c58d2015-08-11 13:11:49 +02001297 drm_atomic_helper_resume(drm, tegra->state);
1298 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001299 drm_kms_helper_poll_enable(drm);
1300
1301 return 0;
1302}
1303#endif
1304
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001305static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1306 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001307
Thierry Reding776dc382013-10-14 14:43:22 +02001308static const struct of_device_id host1x_drm_subdevs[] = {
1309 { .compatible = "nvidia,tegra20-dc", },
1310 { .compatible = "nvidia,tegra20-hdmi", },
1311 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001312 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001313 { .compatible = "nvidia,tegra30-dc", },
1314 { .compatible = "nvidia,tegra30-hdmi", },
1315 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001316 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001317 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001318 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001319 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001320 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001321 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001322 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001323 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001324 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001325 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001326 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001327 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001328 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001329 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001330 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001331 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001332 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001333 { .compatible = "nvidia,tegra186-sor", },
1334 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001335 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001336 { /* sentinel */ }
1337};
1338
1339static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001340 .driver = {
1341 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001342 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001343 },
Thierry Reding776dc382013-10-14 14:43:22 +02001344 .probe = host1x_drm_probe,
1345 .remove = host1x_drm_remove,
1346 .subdevs = host1x_drm_subdevs,
1347};
1348
Thierry Reding473112e2015-09-10 16:07:14 +02001349static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001350 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001351 &tegra_dc_driver,
1352 &tegra_hdmi_driver,
1353 &tegra_dsi_driver,
1354 &tegra_dpaux_driver,
1355 &tegra_sor_driver,
1356 &tegra_gr2d_driver,
1357 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001358 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001359};
1360
Thierry Reding776dc382013-10-14 14:43:22 +02001361static int __init host1x_drm_init(void)
1362{
1363 int err;
1364
1365 err = host1x_driver_register(&host1x_drm_driver);
1366 if (err < 0)
1367 return err;
1368
Thierry Reding473112e2015-09-10 16:07:14 +02001369 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001370 if (err < 0)
1371 goto unregister_host1x;
1372
Thierry Reding776dc382013-10-14 14:43:22 +02001373 return 0;
1374
Thierry Reding776dc382013-10-14 14:43:22 +02001375unregister_host1x:
1376 host1x_driver_unregister(&host1x_drm_driver);
1377 return err;
1378}
1379module_init(host1x_drm_init);
1380
1381static void __exit host1x_drm_exit(void)
1382{
Thierry Reding473112e2015-09-10 16:07:14 +02001383 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001384 host1x_driver_unregister(&host1x_drm_driver);
1385}
1386module_exit(host1x_drm_exit);
1387
1388MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1389MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1390MODULE_LICENSE("GPL v2");