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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingab7d3f52017-12-14 13:46:20 +010036static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010038{
Thierry Reding1503ca42014-11-24 17:41:23 +010039 int err;
40
Thierry Redingab7d3f52017-12-14 13:46:20 +010041 err = drm_atomic_helper_check_modeset(drm, state);
42 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010043 return err;
44
Thierry Reding0281c412017-11-28 11:20:40 +010045 err = tegra_display_hub_atomic_check(drm, state);
46 if (err < 0)
47 return err;
48
Thierry Redingab7d3f52017-12-14 13:46:20 +010049 err = drm_atomic_normalize_zpos(drm, state);
50 if (err < 0)
Maarten Lankhorst424624e2017-07-11 16:33:10 +020051 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010052
Thierry Redingab7d3f52017-12-14 13:46:20 +010053 err = drm_atomic_helper_check_planes(drm, state);
54 if (err < 0)
55 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010056
Thierry Redingab7d3f52017-12-14 13:46:20 +010057 if (state->legacy_cursor_update)
58 state->async_update = !drm_atomic_helper_async_check(drm, state);
59
Thierry Reding1503ca42014-11-24 17:41:23 +010060 return 0;
61}
62
Thierry Reding31b02ca2017-10-12 17:40:46 +020063static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010064 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053065#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010066 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010067#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010068 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020069 .atomic_commit = drm_atomic_helper_commit,
70};
71
Thierry Redingc4755fb2017-11-13 11:08:13 +010072static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
73{
74 struct drm_device *drm = old_state->dev;
75 struct tegra_drm *tegra = drm->dev_private;
76
77 if (tegra->hub) {
78 drm_atomic_helper_commit_modeset_disables(drm, old_state);
79 tegra_display_hub_atomic_commit(drm, old_state);
80 drm_atomic_helper_commit_planes(drm, old_state, 0);
81 drm_atomic_helper_commit_modeset_enables(drm, old_state);
82 drm_atomic_helper_commit_hw_done(old_state);
83 drm_atomic_helper_wait_for_vblanks(drm, old_state);
84 drm_atomic_helper_cleanup_planes(drm, old_state);
85 } else {
86 drm_atomic_helper_commit_tail_rpm(old_state);
87 }
88}
89
Thierry Reding31b02ca2017-10-12 17:40:46 +020090static const struct drm_mode_config_helper_funcs
91tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010092 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010093};
94
Thierry Reding776dc382013-10-14 14:43:22 +020095static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000096{
Thierry Reding776dc382013-10-14 14:43:22 +020097 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020098 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000099 int err;
100
Thierry Reding776dc382013-10-14 14:43:22 +0200101 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200102 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200103 return -ENOMEM;
104
Thierry Redingdf06b752014-06-26 21:41:53 +0200105 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200106 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100107 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200108 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100109
Thierry Redingdf06b752014-06-26 21:41:53 +0200110 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300111 if (!tegra->domain) {
112 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200113 goto free;
114 }
115
Thierry Reding24cfdc12018-04-23 08:57:45 +0200116 err = iova_cache_get();
117 if (err < 0)
118 goto domain;
119
Thierry Reding4553f732015-01-19 16:15:04 +0100120 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200121 gem_start = geometry->aperture_start;
122 gem_end = geometry->aperture_end - CARVEOUT_SZ;
123 carveout_start = gem_end + 1;
124 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100125
Mikko Perttunenad926012016-12-14 13:16:11 +0200126 order = __ffs(tegra->domain->pgsize_bitmap);
127 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100128 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200129
130 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
131 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
132
133 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100134 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200135
136 DRM_DEBUG("IOMMU apertures:\n");
137 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
138 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
139 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200140 }
141
Thierry Reding386a2a72013-09-24 13:22:17 +0200142 mutex_init(&tegra->clients_lock);
143 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100144
Thierry Reding386a2a72013-09-24 13:22:17 +0200145 drm->dev_private = tegra;
146 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000147
148 drm_mode_config_init(drm);
149
Thierry Redingf9914212014-11-26 13:03:57 +0100150 drm->mode_config.min_width = 0;
151 drm->mode_config.min_height = 0;
152
153 drm->mode_config.max_width = 4096;
154 drm->mode_config.max_height = 4096;
155
Alexandre Courbot5e911442016-11-08 16:50:42 +0900156 drm->mode_config.allow_fb_modifiers = true;
157
Thierry Reding31b02ca2017-10-12 17:40:46 +0200158 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
159 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100160
Thierry Redinge2215322014-06-27 17:19:25 +0200161 err = tegra_drm_fb_prepare(drm);
162 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100163 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200164
165 drm_kms_helper_poll_init(drm);
166
Thierry Reding776dc382013-10-14 14:43:22 +0200167 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000168 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100169 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000170
Thierry Redingc4755fb2017-11-13 11:08:13 +0100171 if (tegra->hub) {
172 err = tegra_display_hub_prepare(tegra->hub);
173 if (err < 0)
174 goto device;
175 }
176
Thierry Reding603f0cc2013-04-22 21:22:14 +0200177 /*
178 * We don't use the drm_irq_install() helpers provided by the DRM
179 * core, so we need to set this manually in order to allow the
180 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
181 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300182 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200183
Thierry Reding42e9ce02015-01-28 14:43:05 +0100184 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100185 drm->max_vblank_count = 0xffffffff;
186
Thierry Reding6e5ff992012-11-28 11:45:47 +0100187 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
188 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100189 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100190
Thierry Reding31930d42015-07-02 17:04:06 +0200191 drm_mode_config_reset(drm);
192
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000193 err = tegra_drm_fb_init(drm);
194 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100195 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000196
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000197 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100198
Thierry Redingc4755fb2017-11-13 11:08:13 +0100199hub:
200 if (tegra->hub)
201 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100202device:
203 host1x_device_exit(device);
204fbdev:
205 drm_kms_helper_poll_fini(drm);
206 tegra_drm_fb_free(drm);
207config:
208 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200209
210 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100211 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200212 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200213 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200214 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200215 }
Thierry Reding24cfdc12018-04-23 08:57:45 +0200216domain:
217 if (tegra->domain)
218 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200219free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100220 kfree(tegra);
221 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000222}
223
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200224static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000225{
Thierry Reding776dc382013-10-14 14:43:22 +0200226 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200227 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200228 int err;
229
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000230 drm_kms_helper_poll_fini(drm);
231 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100232 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200233 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000234
Thierry Reding776dc382013-10-14 14:43:22 +0200235 err = host1x_device_exit(device);
236 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200237 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200238
Thierry Redingdf06b752014-06-26 21:41:53 +0200239 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100240 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200241 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200242 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200243 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200244 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200245 }
246
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100247 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000248}
249
250static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
251{
Thierry Reding08943e62013-09-26 16:08:18 +0200252 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200253
254 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
255 if (!fpriv)
256 return -ENOMEM;
257
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100258 idr_init(&fpriv->contexts);
259 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200260 filp->driver_priv = fpriv;
261
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000262 return 0;
263}
264
Thierry Redingc88c3632013-09-26 16:08:22 +0200265static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200266{
267 context->client->ops->close_channel(context);
268 kfree(context);
269}
270
Thierry Redingc40f0f12013-10-10 11:00:33 +0200271static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100272host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200273{
274 struct drm_gem_object *gem;
275 struct tegra_bo *bo;
276
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100277 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200278 if (!gem)
279 return NULL;
280
Thierry Redingc40f0f12013-10-10 11:00:33 +0200281 bo = to_tegra_bo(gem);
282 return &bo->base;
283}
284
Thierry Reding961e3be2014-06-10 10:25:00 +0200285static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
286 struct drm_tegra_reloc __user *src,
287 struct drm_device *drm,
288 struct drm_file *file)
289{
290 u32 cmdbuf, target;
291 int err;
292
293 err = get_user(cmdbuf, &src->cmdbuf.handle);
294 if (err < 0)
295 return err;
296
297 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
298 if (err < 0)
299 return err;
300
301 err = get_user(target, &src->target.handle);
302 if (err < 0)
303 return err;
304
David Ung31f40f82015-01-20 18:37:35 -0800305 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200306 if (err < 0)
307 return err;
308
309 err = get_user(dest->shift, &src->shift);
310 if (err < 0)
311 return err;
312
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100313 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200314 if (!dest->cmdbuf.bo)
315 return -ENOENT;
316
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100317 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200318 if (!dest->target.bo)
319 return -ENOENT;
320
321 return 0;
322}
323
Thierry Redingc40f0f12013-10-10 11:00:33 +0200324int tegra_drm_submit(struct tegra_drm_context *context,
325 struct drm_tegra_submit *args, struct drm_device *drm,
326 struct drm_file *file)
327{
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200328 struct host1x_client *client = &context->client->base;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200329 unsigned int num_cmdbufs = args->num_cmdbufs;
330 unsigned int num_relocs = args->num_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300331 struct drm_tegra_cmdbuf __user *user_cmdbufs;
332 struct drm_tegra_reloc __user *user_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300333 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200334 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300335 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200336 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300337 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200338 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200339 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200340 int err;
341
Mikko Perttunena176c672017-09-28 15:50:44 +0300342 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
343 user_relocs = u64_to_user_ptr(args->relocs);
Mikko Perttunena176c672017-09-28 15:50:44 +0300344 user_syncpt = u64_to_user_ptr(args->syncpts);
345
Thierry Redingc40f0f12013-10-10 11:00:33 +0200346 /* We don't yet support other than one syncpt_incr struct per submit */
347 if (args->num_syncpts != 1)
348 return -EINVAL;
349
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300350 /* We don't yet support waitchks */
351 if (args->num_waitchks != 0)
352 return -EINVAL;
353
Thierry Redingc40f0f12013-10-10 11:00:33 +0200354 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
Thierry Reding24c94e12018-05-05 08:45:47 +0200355 args->num_relocs);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200356 if (!job)
357 return -ENOMEM;
358
359 job->num_relocs = args->num_relocs;
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200360 job->client = client;
361 job->class = client->class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200362 job->serialize = true;
363
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200364 /*
365 * Track referenced BOs so that they can be unreferenced after the
366 * submission is complete.
367 */
Thierry Reding24c94e12018-05-05 08:45:47 +0200368 num_refs = num_cmdbufs + num_relocs * 2;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200369
370 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
371 if (!refs) {
372 err = -ENOMEM;
373 goto put;
374 }
375
376 /* reuse as an iterator later */
377 num_refs = 0;
378
Thierry Redingc40f0f12013-10-10 11:00:33 +0200379 while (num_cmdbufs) {
380 struct drm_tegra_cmdbuf cmdbuf;
381 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300382 struct tegra_bo *obj;
383 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200384
Mikko Perttunena176c672017-09-28 15:50:44 +0300385 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300386 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200387 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300388 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200389
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300390 /*
391 * The maximum number of CDMA gather fetches is 16383, a higher
392 * value means the words count is malformed.
393 */
394 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
395 err = -EINVAL;
396 goto fail;
397 }
398
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100399 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200400 if (!bo) {
401 err = -ENOENT;
402 goto fail;
403 }
404
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300405 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
406 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200407 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300408
409 /*
410 * Gather buffer base address must be 4-bytes aligned,
411 * unaligned offset is malformed and cause commands stream
412 * corruption on the buffer address relocation.
413 */
414 if (offset & 3 || offset >= obj->gem.size) {
415 err = -EINVAL;
416 goto fail;
417 }
418
Thierry Redingc40f0f12013-10-10 11:00:33 +0200419 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
420 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300421 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200422 }
423
Thierry Reding961e3be2014-06-10 10:25:00 +0200424 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200425 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300426 struct host1x_reloc *reloc;
427 struct tegra_bo *obj;
428
Thierry Reding06490bb2018-05-16 16:58:44 +0200429 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300430 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200431 file);
432 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200433 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300434
Thierry Reding06490bb2018-05-16 16:58:44 +0200435 reloc = &job->relocs[num_relocs];
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300436 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200437 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300438
439 /*
440 * The unaligned cmdbuf offset will cause an unaligned write
441 * during of the relocations patching, corrupting the commands
442 * stream.
443 */
444 if (reloc->cmdbuf.offset & 3 ||
445 reloc->cmdbuf.offset >= obj->gem.size) {
446 err = -EINVAL;
447 goto fail;
448 }
449
450 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200451 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300452
453 if (reloc->target.offset >= obj->gem.size) {
454 err = -EINVAL;
455 goto fail;
456 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200457 }
458
Mikko Perttunena176c672017-09-28 15:50:44 +0300459 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300460 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200461 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300462 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200463
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300464 /* check whether syncpoint ID is valid */
465 sp = host1x_syncpt_get(host1x, syncpt.id);
466 if (!sp) {
467 err = -ENOENT;
468 goto fail;
469 }
470
Thierry Redingc40f0f12013-10-10 11:00:33 +0200471 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300472 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200473 job->syncpt_incrs = syncpt.incrs;
474 job->syncpt_id = syncpt.id;
475 job->timeout = 10000;
476
477 if (args->timeout && args->timeout < 10000)
478 job->timeout = args->timeout;
479
480 err = host1x_job_pin(job, context->client->base.dev);
481 if (err)
482 goto fail;
483
484 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200485 if (err) {
486 host1x_job_unpin(job);
487 goto fail;
488 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200489
490 args->fence = job->syncpt_end;
491
Thierry Redingc40f0f12013-10-10 11:00:33 +0200492fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200493 while (num_refs--)
494 drm_gem_object_put_unlocked(refs[num_refs]);
495
496 kfree(refs);
497
498put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200499 host1x_job_put(job);
500 return err;
501}
502
503
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200504#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200505static int tegra_gem_create(struct drm_device *drm, void *data,
506 struct drm_file *file)
507{
508 struct drm_tegra_gem_create *args = data;
509 struct tegra_bo *bo;
510
Thierry Reding773af772013-10-04 22:34:01 +0200511 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200512 &args->handle);
513 if (IS_ERR(bo))
514 return PTR_ERR(bo);
515
516 return 0;
517}
518
519static int tegra_gem_mmap(struct drm_device *drm, void *data,
520 struct drm_file *file)
521{
522 struct drm_tegra_gem_mmap *args = data;
523 struct drm_gem_object *gem;
524 struct tegra_bo *bo;
525
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100526 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200527 if (!gem)
528 return -EINVAL;
529
530 bo = to_tegra_bo(gem);
531
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200532 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200533
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300534 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200535
536 return 0;
537}
538
539static int tegra_syncpt_read(struct drm_device *drm, void *data,
540 struct drm_file *file)
541{
Thierry Reding776dc382013-10-14 14:43:22 +0200542 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200543 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200544 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200545
Thierry Reding776dc382013-10-14 14:43:22 +0200546 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200547 if (!sp)
548 return -EINVAL;
549
550 args->value = host1x_syncpt_read_min(sp);
551 return 0;
552}
553
554static int tegra_syncpt_incr(struct drm_device *drm, void *data,
555 struct drm_file *file)
556{
Thierry Reding776dc382013-10-14 14:43:22 +0200557 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200558 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200559 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200560
Thierry Reding776dc382013-10-14 14:43:22 +0200561 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200562 if (!sp)
563 return -EINVAL;
564
Arto Merilainenebae30b2013-05-29 13:26:08 +0300565 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200566}
567
568static int tegra_syncpt_wait(struct drm_device *drm, void *data,
569 struct drm_file *file)
570{
Thierry Reding776dc382013-10-14 14:43:22 +0200571 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200572 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200573 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200574
Thierry Reding776dc382013-10-14 14:43:22 +0200575 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200576 if (!sp)
577 return -EINVAL;
578
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300579 return host1x_syncpt_wait(sp, args->thresh,
580 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200581 &args->value);
582}
583
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100584static int tegra_client_open(struct tegra_drm_file *fpriv,
585 struct tegra_drm_client *client,
586 struct tegra_drm_context *context)
587{
588 int err;
589
590 err = client->ops->open_channel(client, context);
591 if (err < 0)
592 return err;
593
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300594 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100595 if (err < 0) {
596 client->ops->close_channel(context);
597 return err;
598 }
599
600 context->client = client;
601 context->id = err;
602
603 return 0;
604}
605
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200606static int tegra_open_channel(struct drm_device *drm, void *data,
607 struct drm_file *file)
608{
Thierry Reding08943e62013-09-26 16:08:18 +0200609 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200610 struct tegra_drm *tegra = drm->dev_private;
611 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200612 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200613 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200614 int err = -ENODEV;
615
616 context = kzalloc(sizeof(*context), GFP_KERNEL);
617 if (!context)
618 return -ENOMEM;
619
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100620 mutex_lock(&fpriv->lock);
621
Thierry Reding776dc382013-10-14 14:43:22 +0200622 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200623 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100624 err = tegra_client_open(fpriv, client, context);
625 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200626 break;
627
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100628 args->context = context->id;
629 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200630 }
631
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100632 if (err < 0)
633 kfree(context);
634
635 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200636 return err;
637}
638
639static int tegra_close_channel(struct drm_device *drm, void *data,
640 struct drm_file *file)
641{
Thierry Reding08943e62013-09-26 16:08:18 +0200642 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200643 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200644 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100645 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200646
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100647 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200648
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300649 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100650 if (!context) {
651 err = -EINVAL;
652 goto unlock;
653 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200654
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100655 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200656 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200657
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100658unlock:
659 mutex_unlock(&fpriv->lock);
660 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200661}
662
663static int tegra_get_syncpt(struct drm_device *drm, void *data,
664 struct drm_file *file)
665{
Thierry Reding08943e62013-09-26 16:08:18 +0200666 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200667 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200668 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200669 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100670 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200671
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100672 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200673
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300674 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100675 if (!context) {
676 err = -ENODEV;
677 goto unlock;
678 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200679
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100680 if (args->index >= context->client->base.num_syncpts) {
681 err = -EINVAL;
682 goto unlock;
683 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200684
Thierry Reding53fa7f72013-09-24 15:35:40 +0200685 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200686 args->id = host1x_syncpt_id(syncpt);
687
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100688unlock:
689 mutex_unlock(&fpriv->lock);
690 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200691}
692
693static int tegra_submit(struct drm_device *drm, void *data,
694 struct drm_file *file)
695{
Thierry Reding08943e62013-09-26 16:08:18 +0200696 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200697 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200698 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100699 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200700
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100701 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200702
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300703 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100704 if (!context) {
705 err = -ENODEV;
706 goto unlock;
707 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200708
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100709 err = context->client->ops->submit(context, args, drm, file);
710
711unlock:
712 mutex_unlock(&fpriv->lock);
713 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200714}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300715
716static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
717 struct drm_file *file)
718{
719 struct tegra_drm_file *fpriv = file->driver_priv;
720 struct drm_tegra_get_syncpt_base *args = data;
721 struct tegra_drm_context *context;
722 struct host1x_syncpt_base *base;
723 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100724 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300725
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100726 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300727
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300728 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100729 if (!context) {
730 err = -ENODEV;
731 goto unlock;
732 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300733
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100734 if (args->syncpt >= context->client->base.num_syncpts) {
735 err = -EINVAL;
736 goto unlock;
737 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300738
739 syncpt = context->client->base.syncpts[args->syncpt];
740
741 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100742 if (!base) {
743 err = -ENXIO;
744 goto unlock;
745 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300746
747 args->id = host1x_syncpt_base_id(base);
748
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100749unlock:
750 mutex_unlock(&fpriv->lock);
751 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300752}
Thierry Reding7678d712014-06-03 14:56:57 +0200753
754static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
755 struct drm_file *file)
756{
757 struct drm_tegra_gem_set_tiling *args = data;
758 enum tegra_bo_tiling_mode mode;
759 struct drm_gem_object *gem;
760 unsigned long value = 0;
761 struct tegra_bo *bo;
762
763 switch (args->mode) {
764 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
765 mode = TEGRA_BO_TILING_MODE_PITCH;
766
767 if (args->value != 0)
768 return -EINVAL;
769
770 break;
771
772 case DRM_TEGRA_GEM_TILING_MODE_TILED:
773 mode = TEGRA_BO_TILING_MODE_TILED;
774
775 if (args->value != 0)
776 return -EINVAL;
777
778 break;
779
780 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
781 mode = TEGRA_BO_TILING_MODE_BLOCK;
782
783 if (args->value > 5)
784 return -EINVAL;
785
786 value = args->value;
787 break;
788
789 default:
790 return -EINVAL;
791 }
792
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100793 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200794 if (!gem)
795 return -ENOENT;
796
797 bo = to_tegra_bo(gem);
798
799 bo->tiling.mode = mode;
800 bo->tiling.value = value;
801
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300802 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200803
804 return 0;
805}
806
807static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
808 struct drm_file *file)
809{
810 struct drm_tegra_gem_get_tiling *args = data;
811 struct drm_gem_object *gem;
812 struct tegra_bo *bo;
813 int err = 0;
814
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100815 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200816 if (!gem)
817 return -ENOENT;
818
819 bo = to_tegra_bo(gem);
820
821 switch (bo->tiling.mode) {
822 case TEGRA_BO_TILING_MODE_PITCH:
823 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
824 args->value = 0;
825 break;
826
827 case TEGRA_BO_TILING_MODE_TILED:
828 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
829 args->value = 0;
830 break;
831
832 case TEGRA_BO_TILING_MODE_BLOCK:
833 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
834 args->value = bo->tiling.value;
835 break;
836
837 default:
838 err = -EINVAL;
839 break;
840 }
841
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300842 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200843
844 return err;
845}
Thierry Reding7b129082014-06-10 12:04:03 +0200846
847static int tegra_gem_set_flags(struct drm_device *drm, void *data,
848 struct drm_file *file)
849{
850 struct drm_tegra_gem_set_flags *args = data;
851 struct drm_gem_object *gem;
852 struct tegra_bo *bo;
853
854 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
855 return -EINVAL;
856
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100857 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200858 if (!gem)
859 return -ENOENT;
860
861 bo = to_tegra_bo(gem);
862 bo->flags = 0;
863
864 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
865 bo->flags |= TEGRA_BO_BOTTOM_UP;
866
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300867 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200868
869 return 0;
870}
871
872static int tegra_gem_get_flags(struct drm_device *drm, void *data,
873 struct drm_file *file)
874{
875 struct drm_tegra_gem_get_flags *args = data;
876 struct drm_gem_object *gem;
877 struct tegra_bo *bo;
878
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100879 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200880 if (!gem)
881 return -ENOENT;
882
883 bo = to_tegra_bo(gem);
884 args->flags = 0;
885
886 if (bo->flags & TEGRA_BO_BOTTOM_UP)
887 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
888
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300889 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200890
891 return 0;
892}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200893#endif
894
Rob Clarkbaa70942013-08-02 13:27:49 -0400895static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200896#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200897 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
898 DRM_UNLOCKED | DRM_RENDER_ALLOW),
899 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
900 DRM_UNLOCKED | DRM_RENDER_ALLOW),
901 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
902 DRM_UNLOCKED | DRM_RENDER_ALLOW),
903 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
904 DRM_UNLOCKED | DRM_RENDER_ALLOW),
905 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
906 DRM_UNLOCKED | DRM_RENDER_ALLOW),
907 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
908 DRM_UNLOCKED | DRM_RENDER_ALLOW),
909 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
910 DRM_UNLOCKED | DRM_RENDER_ALLOW),
911 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
912 DRM_UNLOCKED | DRM_RENDER_ALLOW),
913 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
914 DRM_UNLOCKED | DRM_RENDER_ALLOW),
915 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
916 DRM_UNLOCKED | DRM_RENDER_ALLOW),
917 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
918 DRM_UNLOCKED | DRM_RENDER_ALLOW),
919 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
920 DRM_UNLOCKED | DRM_RENDER_ALLOW),
921 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
922 DRM_UNLOCKED | DRM_RENDER_ALLOW),
923 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
924 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200925#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000926};
927
928static const struct file_operations tegra_drm_fops = {
929 .owner = THIS_MODULE,
930 .open = drm_open,
931 .release = drm_release,
932 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200933 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000934 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000935 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000936 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000937 .llseek = noop_llseek,
938};
939
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100940static int tegra_drm_context_cleanup(int id, void *p, void *data)
941{
942 struct tegra_drm_context *context = p;
943
944 tegra_drm_context_free(context);
945
946 return 0;
947}
948
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200949static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100950{
Thierry Reding08943e62013-09-26 16:08:18 +0200951 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100952
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100953 mutex_lock(&fpriv->lock);
954 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
955 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200956
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100957 idr_destroy(&fpriv->contexts);
958 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200959 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100960}
961
Thierry Redinge450fcc2013-02-13 16:13:16 +0100962#ifdef CONFIG_DEBUG_FS
963static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
964{
965 struct drm_info_node *node = (struct drm_info_node *)s->private;
966 struct drm_device *drm = node->minor->dev;
967 struct drm_framebuffer *fb;
968
969 mutex_lock(&drm->mode_config.fb_lock);
970
971 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
972 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200973 fb->base.id, fb->width, fb->height,
974 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200975 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000976 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100977 }
978
979 mutex_unlock(&drm->mode_config.fb_lock);
980
981 return 0;
982}
983
Thierry Reding28c23372015-01-23 09:16:03 +0100984static int tegra_debugfs_iova(struct seq_file *s, void *data)
985{
986 struct drm_info_node *node = (struct drm_info_node *)s->private;
987 struct drm_device *drm = node->minor->dev;
988 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100989 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100990
Michał Mirosław68d890a2017-08-14 23:53:45 +0200991 if (tegra->domain) {
992 mutex_lock(&tegra->mm_lock);
993 drm_mm_print(&tegra->mm, &p);
994 mutex_unlock(&tegra->mm_lock);
995 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100996
997 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100998}
999
Thierry Redinge450fcc2013-02-13 16:13:16 +01001000static struct drm_info_list tegra_debugfs_list[] = {
1001 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001002 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001003};
1004
1005static int tegra_debugfs_init(struct drm_minor *minor)
1006{
1007 return drm_debugfs_create_files(tegra_debugfs_list,
1008 ARRAY_SIZE(tegra_debugfs_list),
1009 minor->debugfs_root, minor);
1010}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001011#endif
1012
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001013static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001014 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001015 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001016 .load = tegra_drm_load,
1017 .unload = tegra_drm_unload,
1018 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001019 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001020 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001021
Thierry Redinge450fcc2013-02-13 16:13:16 +01001022#if defined(CONFIG_DEBUG_FS)
1023 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001024#endif
1025
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001026 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001027 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001028
1029 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1030 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1031 .gem_prime_export = tegra_gem_prime_export,
1032 .gem_prime_import = tegra_gem_prime_import,
1033
Arto Merilainende2ba662013-03-22 16:34:08 +02001034 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001035
1036 .ioctls = tegra_drm_ioctls,
1037 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1038 .fops = &tegra_drm_fops,
1039
1040 .name = DRIVER_NAME,
1041 .desc = DRIVER_DESC,
1042 .date = DRIVER_DATE,
1043 .major = DRIVER_MAJOR,
1044 .minor = DRIVER_MINOR,
1045 .patchlevel = DRIVER_PATCHLEVEL,
1046};
Thierry Reding776dc382013-10-14 14:43:22 +02001047
1048int tegra_drm_register_client(struct tegra_drm *tegra,
1049 struct tegra_drm_client *client)
1050{
1051 mutex_lock(&tegra->clients_lock);
1052 list_add_tail(&client->list, &tegra->clients);
1053 mutex_unlock(&tegra->clients_lock);
1054
1055 return 0;
1056}
1057
1058int tegra_drm_unregister_client(struct tegra_drm *tegra,
1059 struct tegra_drm_client *client)
1060{
1061 mutex_lock(&tegra->clients_lock);
1062 list_del_init(&client->list);
1063 mutex_unlock(&tegra->clients_lock);
1064
1065 return 0;
1066}
1067
Thierry Reding0c407de2018-05-04 15:02:24 +02001068struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1069 bool shared)
1070{
1071 struct drm_device *drm = dev_get_drvdata(client->parent);
1072 struct tegra_drm *tegra = drm->dev_private;
1073 struct iommu_group *group = NULL;
1074 int err;
1075
1076 if (tegra->domain) {
1077 group = iommu_group_get(client->dev);
1078 if (!group) {
1079 dev_err(client->dev, "failed to get IOMMU group\n");
1080 return ERR_PTR(-ENODEV);
1081 }
1082
1083 if (!shared || (shared && (group != tegra->group))) {
1084 err = iommu_attach_group(tegra->domain, group);
1085 if (err < 0) {
1086 iommu_group_put(group);
1087 return ERR_PTR(err);
1088 }
1089
1090 if (shared && !tegra->group)
1091 tegra->group = group;
1092 }
1093 }
1094
1095 return group;
1096}
1097
1098void host1x_client_iommu_detach(struct host1x_client *client,
1099 struct iommu_group *group)
1100{
1101 struct drm_device *drm = dev_get_drvdata(client->parent);
1102 struct tegra_drm *tegra = drm->dev_private;
1103
1104 if (group) {
1105 if (group == tegra->group) {
1106 iommu_detach_group(tegra->domain, group);
1107 tegra->group = NULL;
1108 }
1109
1110 iommu_group_put(group);
1111 }
1112}
1113
Thierry Reding67485fb2017-11-09 13:17:11 +01001114void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001115{
1116 struct iova *alloc;
1117 void *virt;
1118 gfp_t gfp;
1119 int err;
1120
1121 if (tegra->domain)
1122 size = iova_align(&tegra->carveout.domain, size);
1123 else
1124 size = PAGE_ALIGN(size);
1125
1126 gfp = GFP_KERNEL | __GFP_ZERO;
1127 if (!tegra->domain) {
1128 /*
1129 * Many units only support 32-bit addresses, even on 64-bit
1130 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1131 * virtual address space, force allocations to be in the
1132 * lower 32-bit range.
1133 */
1134 gfp |= GFP_DMA;
1135 }
1136
1137 virt = (void *)__get_free_pages(gfp, get_order(size));
1138 if (!virt)
1139 return ERR_PTR(-ENOMEM);
1140
1141 if (!tegra->domain) {
1142 /*
1143 * If IOMMU is disabled, devices address physical memory
1144 * directly.
1145 */
1146 *dma = virt_to_phys(virt);
1147 return virt;
1148 }
1149
1150 alloc = alloc_iova(&tegra->carveout.domain,
1151 size >> tegra->carveout.shift,
1152 tegra->carveout.limit, true);
1153 if (!alloc) {
1154 err = -EBUSY;
1155 goto free_pages;
1156 }
1157
1158 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1159 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1160 size, IOMMU_READ | IOMMU_WRITE);
1161 if (err < 0)
1162 goto free_iova;
1163
1164 return virt;
1165
1166free_iova:
1167 __free_iova(&tegra->carveout.domain, alloc);
1168free_pages:
1169 free_pages((unsigned long)virt, get_order(size));
1170
1171 return ERR_PTR(err);
1172}
1173
1174void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1175 dma_addr_t dma)
1176{
1177 if (tegra->domain)
1178 size = iova_align(&tegra->carveout.domain, size);
1179 else
1180 size = PAGE_ALIGN(size);
1181
1182 if (tegra->domain) {
1183 iommu_unmap(tegra->domain, dma, size);
1184 free_iova(&tegra->carveout.domain,
1185 iova_pfn(&tegra->carveout.domain, dma));
1186 }
1187
1188 free_pages((unsigned long)virt, get_order(size));
1189}
1190
Thierry Reding9910f5c2014-05-22 09:57:15 +02001191static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001192{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001193 struct drm_driver *driver = &tegra_drm_driver;
1194 struct drm_device *drm;
1195 int err;
1196
1197 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001198 if (IS_ERR(drm))
1199 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001200
Thierry Reding9910f5c2014-05-22 09:57:15 +02001201 dev_set_drvdata(&dev->dev, drm);
1202
1203 err = drm_dev_register(drm, 0);
1204 if (err < 0)
1205 goto unref;
1206
Thierry Reding9910f5c2014-05-22 09:57:15 +02001207 return 0;
1208
1209unref:
1210 drm_dev_unref(drm);
1211 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001212}
1213
Thierry Reding9910f5c2014-05-22 09:57:15 +02001214static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001215{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001216 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1217
1218 drm_dev_unregister(drm);
1219 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001220
1221 return 0;
1222}
1223
Thierry Reding359ae682014-12-18 17:15:25 +01001224#ifdef CONFIG_PM_SLEEP
1225static int host1x_drm_suspend(struct device *dev)
1226{
1227 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001228 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001229
1230 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001231 tegra_drm_fb_suspend(drm);
1232
1233 tegra->state = drm_atomic_helper_suspend(drm);
1234 if (IS_ERR(tegra->state)) {
1235 tegra_drm_fb_resume(drm);
1236 drm_kms_helper_poll_enable(drm);
1237 return PTR_ERR(tegra->state);
1238 }
Thierry Reding359ae682014-12-18 17:15:25 +01001239
1240 return 0;
1241}
1242
1243static int host1x_drm_resume(struct device *dev)
1244{
1245 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001246 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001247
Thierry Reding986c58d2015-08-11 13:11:49 +02001248 drm_atomic_helper_resume(drm, tegra->state);
1249 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001250 drm_kms_helper_poll_enable(drm);
1251
1252 return 0;
1253}
1254#endif
1255
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001256static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1257 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001258
Thierry Reding776dc382013-10-14 14:43:22 +02001259static const struct of_device_id host1x_drm_subdevs[] = {
1260 { .compatible = "nvidia,tegra20-dc", },
1261 { .compatible = "nvidia,tegra20-hdmi", },
1262 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001263 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001264 { .compatible = "nvidia,tegra30-dc", },
1265 { .compatible = "nvidia,tegra30-hdmi", },
1266 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001267 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001268 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001269 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001270 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001271 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001272 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001273 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001274 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001275 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001276 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001277 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001278 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001279 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001280 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001281 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001282 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001283 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001284 { .compatible = "nvidia,tegra186-sor", },
1285 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001286 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001287 { /* sentinel */ }
1288};
1289
1290static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001291 .driver = {
1292 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001293 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001294 },
Thierry Reding776dc382013-10-14 14:43:22 +02001295 .probe = host1x_drm_probe,
1296 .remove = host1x_drm_remove,
1297 .subdevs = host1x_drm_subdevs,
1298};
1299
Thierry Reding473112e2015-09-10 16:07:14 +02001300static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001301 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001302 &tegra_dc_driver,
1303 &tegra_hdmi_driver,
1304 &tegra_dsi_driver,
1305 &tegra_dpaux_driver,
1306 &tegra_sor_driver,
1307 &tegra_gr2d_driver,
1308 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001309 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001310};
1311
Thierry Reding776dc382013-10-14 14:43:22 +02001312static int __init host1x_drm_init(void)
1313{
1314 int err;
1315
1316 err = host1x_driver_register(&host1x_drm_driver);
1317 if (err < 0)
1318 return err;
1319
Thierry Reding473112e2015-09-10 16:07:14 +02001320 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001321 if (err < 0)
1322 goto unregister_host1x;
1323
Thierry Reding776dc382013-10-14 14:43:22 +02001324 return 0;
1325
Thierry Reding776dc382013-10-14 14:43:22 +02001326unregister_host1x:
1327 host1x_driver_unregister(&host1x_drm_driver);
1328 return err;
1329}
1330module_init(host1x_drm_init);
1331
1332static void __exit host1x_drm_exit(void)
1333{
Thierry Reding473112e2015-09-10 16:07:14 +02001334 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001335 host1x_driver_unregister(&host1x_drm_driver);
1336}
1337module_exit(host1x_drm_exit);
1338
1339MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1340MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1341MODULE_LICENSE("GPL v2");