blob: 3cdef659cd39a0cd6e7e72b5cce9dc4aef63f396 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingab7d3f52017-12-14 13:46:20 +010036static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010038{
Thierry Reding1503ca42014-11-24 17:41:23 +010039 int err;
40
Thierry Redingab7d3f52017-12-14 13:46:20 +010041 err = drm_atomic_helper_check_modeset(drm, state);
42 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010043 return err;
44
Thierry Reding0281c412017-11-28 11:20:40 +010045 err = tegra_display_hub_atomic_check(drm, state);
46 if (err < 0)
47 return err;
48
Thierry Redingab7d3f52017-12-14 13:46:20 +010049 err = drm_atomic_normalize_zpos(drm, state);
50 if (err < 0)
Maarten Lankhorst424624e2017-07-11 16:33:10 +020051 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010052
Thierry Redingab7d3f52017-12-14 13:46:20 +010053 err = drm_atomic_helper_check_planes(drm, state);
54 if (err < 0)
55 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010056
Thierry Redingab7d3f52017-12-14 13:46:20 +010057 if (state->legacy_cursor_update)
58 state->async_update = !drm_atomic_helper_async_check(drm, state);
59
Thierry Reding1503ca42014-11-24 17:41:23 +010060 return 0;
61}
62
Thierry Reding31b02ca2017-10-12 17:40:46 +020063static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010064 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053065#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010066 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010067#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010068 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020069 .atomic_commit = drm_atomic_helper_commit,
70};
71
Thierry Redingc4755fb2017-11-13 11:08:13 +010072static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
73{
74 struct drm_device *drm = old_state->dev;
75 struct tegra_drm *tegra = drm->dev_private;
76
77 if (tegra->hub) {
78 drm_atomic_helper_commit_modeset_disables(drm, old_state);
79 tegra_display_hub_atomic_commit(drm, old_state);
80 drm_atomic_helper_commit_planes(drm, old_state, 0);
81 drm_atomic_helper_commit_modeset_enables(drm, old_state);
82 drm_atomic_helper_commit_hw_done(old_state);
83 drm_atomic_helper_wait_for_vblanks(drm, old_state);
84 drm_atomic_helper_cleanup_planes(drm, old_state);
85 } else {
86 drm_atomic_helper_commit_tail_rpm(old_state);
87 }
88}
89
Thierry Reding31b02ca2017-10-12 17:40:46 +020090static const struct drm_mode_config_helper_funcs
91tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010092 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010093};
94
Thierry Reding776dc382013-10-14 14:43:22 +020095static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000096{
Thierry Reding776dc382013-10-14 14:43:22 +020097 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020098 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000099 int err;
100
Thierry Reding776dc382013-10-14 14:43:22 +0200101 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200102 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200103 return -ENOMEM;
104
Thierry Redingdf06b752014-06-26 21:41:53 +0200105 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200106 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100107 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200108 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100109
Thierry Redingdf06b752014-06-26 21:41:53 +0200110 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300111 if (!tegra->domain) {
112 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200113 goto free;
114 }
115
Thierry Reding24cfdc12018-04-23 08:57:45 +0200116 err = iova_cache_get();
117 if (err < 0)
118 goto domain;
119
Thierry Reding4553f732015-01-19 16:15:04 +0100120 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200121 gem_start = geometry->aperture_start;
122 gem_end = geometry->aperture_end - CARVEOUT_SZ;
123 carveout_start = gem_end + 1;
124 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100125
Mikko Perttunenad926012016-12-14 13:16:11 +0200126 order = __ffs(tegra->domain->pgsize_bitmap);
127 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100128 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200129
130 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
131 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
132
133 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100134 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200135
136 DRM_DEBUG("IOMMU apertures:\n");
137 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
138 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
139 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200140 }
141
Thierry Reding386a2a72013-09-24 13:22:17 +0200142 mutex_init(&tegra->clients_lock);
143 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100144
Thierry Reding386a2a72013-09-24 13:22:17 +0200145 drm->dev_private = tegra;
146 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000147
148 drm_mode_config_init(drm);
149
Thierry Redingf9914212014-11-26 13:03:57 +0100150 drm->mode_config.min_width = 0;
151 drm->mode_config.min_height = 0;
152
153 drm->mode_config.max_width = 4096;
154 drm->mode_config.max_height = 4096;
155
Alexandre Courbot5e911442016-11-08 16:50:42 +0900156 drm->mode_config.allow_fb_modifiers = true;
157
Thierry Reding31b02ca2017-10-12 17:40:46 +0200158 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
159 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100160
Thierry Redinge2215322014-06-27 17:19:25 +0200161 err = tegra_drm_fb_prepare(drm);
162 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100163 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200164
165 drm_kms_helper_poll_init(drm);
166
Thierry Reding776dc382013-10-14 14:43:22 +0200167 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000168 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100169 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000170
Thierry Redingc4755fb2017-11-13 11:08:13 +0100171 if (tegra->hub) {
172 err = tegra_display_hub_prepare(tegra->hub);
173 if (err < 0)
174 goto device;
175 }
176
Thierry Reding603f0cc2013-04-22 21:22:14 +0200177 /*
178 * We don't use the drm_irq_install() helpers provided by the DRM
179 * core, so we need to set this manually in order to allow the
180 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
181 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300182 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200183
Thierry Reding42e9ce02015-01-28 14:43:05 +0100184 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100185 drm->max_vblank_count = 0xffffffff;
186
Thierry Reding6e5ff992012-11-28 11:45:47 +0100187 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
188 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100189 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100190
Thierry Reding31930d42015-07-02 17:04:06 +0200191 drm_mode_config_reset(drm);
192
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000193 err = tegra_drm_fb_init(drm);
194 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100195 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000196
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000197 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100198
Thierry Redingc4755fb2017-11-13 11:08:13 +0100199hub:
200 if (tegra->hub)
201 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100202device:
203 host1x_device_exit(device);
204fbdev:
205 drm_kms_helper_poll_fini(drm);
206 tegra_drm_fb_free(drm);
207config:
208 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200209
210 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100211 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200212 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200213 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200214 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200215 }
Thierry Reding24cfdc12018-04-23 08:57:45 +0200216domain:
217 if (tegra->domain)
218 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200219free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100220 kfree(tegra);
221 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000222}
223
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200224static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000225{
Thierry Reding776dc382013-10-14 14:43:22 +0200226 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200227 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200228 int err;
229
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000230 drm_kms_helper_poll_fini(drm);
231 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100232 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200233 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000234
Thierry Reding776dc382013-10-14 14:43:22 +0200235 err = host1x_device_exit(device);
236 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200237 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200238
Thierry Redingdf06b752014-06-26 21:41:53 +0200239 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100240 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200241 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200242 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200243 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200244 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200245 }
246
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100247 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000248}
249
250static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
251{
Thierry Reding08943e62013-09-26 16:08:18 +0200252 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200253
254 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
255 if (!fpriv)
256 return -ENOMEM;
257
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100258 idr_init(&fpriv->contexts);
259 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200260 filp->driver_priv = fpriv;
261
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000262 return 0;
263}
264
Thierry Redingc88c3632013-09-26 16:08:22 +0200265static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200266{
267 context->client->ops->close_channel(context);
268 kfree(context);
269}
270
Thierry Redingc40f0f12013-10-10 11:00:33 +0200271static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100272host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200273{
274 struct drm_gem_object *gem;
275 struct tegra_bo *bo;
276
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100277 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200278 if (!gem)
279 return NULL;
280
Thierry Redingc40f0f12013-10-10 11:00:33 +0200281 bo = to_tegra_bo(gem);
282 return &bo->base;
283}
284
Thierry Reding961e3be2014-06-10 10:25:00 +0200285static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
286 struct drm_tegra_reloc __user *src,
287 struct drm_device *drm,
288 struct drm_file *file)
289{
290 u32 cmdbuf, target;
291 int err;
292
293 err = get_user(cmdbuf, &src->cmdbuf.handle);
294 if (err < 0)
295 return err;
296
297 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
298 if (err < 0)
299 return err;
300
301 err = get_user(target, &src->target.handle);
302 if (err < 0)
303 return err;
304
David Ung31f40f82015-01-20 18:37:35 -0800305 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200306 if (err < 0)
307 return err;
308
309 err = get_user(dest->shift, &src->shift);
310 if (err < 0)
311 return err;
312
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100313 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200314 if (!dest->cmdbuf.bo)
315 return -ENOENT;
316
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100317 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200318 if (!dest->target.bo)
319 return -ENOENT;
320
321 return 0;
322}
323
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300324static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
325 struct drm_tegra_waitchk __user *src,
326 struct drm_file *file)
327{
328 u32 cmdbuf;
329 int err;
330
331 err = get_user(cmdbuf, &src->handle);
332 if (err < 0)
333 return err;
334
335 err = get_user(dest->offset, &src->offset);
336 if (err < 0)
337 return err;
338
339 err = get_user(dest->syncpt_id, &src->syncpt);
340 if (err < 0)
341 return err;
342
343 err = get_user(dest->thresh, &src->thresh);
344 if (err < 0)
345 return err;
346
347 dest->bo = host1x_bo_lookup(file, cmdbuf);
348 if (!dest->bo)
349 return -ENOENT;
350
351 return 0;
352}
353
Thierry Redingc40f0f12013-10-10 11:00:33 +0200354int tegra_drm_submit(struct tegra_drm_context *context,
355 struct drm_tegra_submit *args, struct drm_device *drm,
356 struct drm_file *file)
357{
358 unsigned int num_cmdbufs = args->num_cmdbufs;
359 unsigned int num_relocs = args->num_relocs;
360 unsigned int num_waitchks = args->num_waitchks;
Mikko Perttunena176c672017-09-28 15:50:44 +0300361 struct drm_tegra_cmdbuf __user *user_cmdbufs;
362 struct drm_tegra_reloc __user *user_relocs;
363 struct drm_tegra_waitchk __user *user_waitchks;
364 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200365 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300366 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200367 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300368 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200369 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200370 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200371 int err;
372
Mikko Perttunena176c672017-09-28 15:50:44 +0300373 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
374 user_relocs = u64_to_user_ptr(args->relocs);
375 user_waitchks = u64_to_user_ptr(args->waitchks);
376 user_syncpt = u64_to_user_ptr(args->syncpts);
377
Thierry Redingc40f0f12013-10-10 11:00:33 +0200378 /* We don't yet support other than one syncpt_incr struct per submit */
379 if (args->num_syncpts != 1)
380 return -EINVAL;
381
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300382 /* We don't yet support waitchks */
383 if (args->num_waitchks != 0)
384 return -EINVAL;
385
Thierry Redingc40f0f12013-10-10 11:00:33 +0200386 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
387 args->num_relocs, args->num_waitchks);
388 if (!job)
389 return -ENOMEM;
390
391 job->num_relocs = args->num_relocs;
392 job->num_waitchk = args->num_waitchks;
393 job->client = (u32)args->context;
394 job->class = context->client->base.class;
395 job->serialize = true;
396
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200397 /*
398 * Track referenced BOs so that they can be unreferenced after the
399 * submission is complete.
400 */
401 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
402
403 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
404 if (!refs) {
405 err = -ENOMEM;
406 goto put;
407 }
408
409 /* reuse as an iterator later */
410 num_refs = 0;
411
Thierry Redingc40f0f12013-10-10 11:00:33 +0200412 while (num_cmdbufs) {
413 struct drm_tegra_cmdbuf cmdbuf;
414 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300415 struct tegra_bo *obj;
416 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200417
Mikko Perttunena176c672017-09-28 15:50:44 +0300418 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300419 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200420 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300421 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200422
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300423 /*
424 * The maximum number of CDMA gather fetches is 16383, a higher
425 * value means the words count is malformed.
426 */
427 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
428 err = -EINVAL;
429 goto fail;
430 }
431
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100432 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200433 if (!bo) {
434 err = -ENOENT;
435 goto fail;
436 }
437
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300438 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
439 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200440 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300441
442 /*
443 * Gather buffer base address must be 4-bytes aligned,
444 * unaligned offset is malformed and cause commands stream
445 * corruption on the buffer address relocation.
446 */
447 if (offset & 3 || offset >= obj->gem.size) {
448 err = -EINVAL;
449 goto fail;
450 }
451
Thierry Redingc40f0f12013-10-10 11:00:33 +0200452 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
453 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300454 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200455 }
456
Thierry Reding961e3be2014-06-10 10:25:00 +0200457 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200458 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300459 struct host1x_reloc *reloc;
460 struct tegra_bo *obj;
461
Thierry Reding961e3be2014-06-10 10:25:00 +0200462 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300463 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200464 file);
465 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200466 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300467
468 reloc = &job->relocarray[num_relocs];
469 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200470 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300471
472 /*
473 * The unaligned cmdbuf offset will cause an unaligned write
474 * during of the relocations patching, corrupting the commands
475 * stream.
476 */
477 if (reloc->cmdbuf.offset & 3 ||
478 reloc->cmdbuf.offset >= obj->gem.size) {
479 err = -EINVAL;
480 goto fail;
481 }
482
483 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200484 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300485
486 if (reloc->target.offset >= obj->gem.size) {
487 err = -EINVAL;
488 goto fail;
489 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200490 }
491
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300492 /* copy and resolve waitchks from submit */
493 while (num_waitchks--) {
494 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
495 struct tegra_bo *obj;
496
Mikko Perttunena176c672017-09-28 15:50:44 +0300497 err = host1x_waitchk_copy_from_user(
498 wait, &user_waitchks[num_waitchks], file);
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300499 if (err < 0)
500 goto fail;
501
502 obj = host1x_to_tegra_bo(wait->bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200503 refs[num_refs++] = &obj->gem;
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300504
505 /*
506 * The unaligned offset will cause an unaligned write during
507 * of the waitchks patching, corrupting the commands stream.
508 */
509 if (wait->offset & 3 ||
510 wait->offset >= obj->gem.size) {
511 err = -EINVAL;
512 goto fail;
513 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300514 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200515
Mikko Perttunena176c672017-09-28 15:50:44 +0300516 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300517 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200518 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300519 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200520
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300521 /* check whether syncpoint ID is valid */
522 sp = host1x_syncpt_get(host1x, syncpt.id);
523 if (!sp) {
524 err = -ENOENT;
525 goto fail;
526 }
527
Thierry Redingc40f0f12013-10-10 11:00:33 +0200528 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300529 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200530 job->syncpt_incrs = syncpt.incrs;
531 job->syncpt_id = syncpt.id;
532 job->timeout = 10000;
533
534 if (args->timeout && args->timeout < 10000)
535 job->timeout = args->timeout;
536
537 err = host1x_job_pin(job, context->client->base.dev);
538 if (err)
539 goto fail;
540
541 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200542 if (err) {
543 host1x_job_unpin(job);
544 goto fail;
545 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200546
547 args->fence = job->syncpt_end;
548
Thierry Redingc40f0f12013-10-10 11:00:33 +0200549fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200550 while (num_refs--)
551 drm_gem_object_put_unlocked(refs[num_refs]);
552
553 kfree(refs);
554
555put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200556 host1x_job_put(job);
557 return err;
558}
559
560
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200561#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200562static int tegra_gem_create(struct drm_device *drm, void *data,
563 struct drm_file *file)
564{
565 struct drm_tegra_gem_create *args = data;
566 struct tegra_bo *bo;
567
Thierry Reding773af772013-10-04 22:34:01 +0200568 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200569 &args->handle);
570 if (IS_ERR(bo))
571 return PTR_ERR(bo);
572
573 return 0;
574}
575
576static int tegra_gem_mmap(struct drm_device *drm, void *data,
577 struct drm_file *file)
578{
579 struct drm_tegra_gem_mmap *args = data;
580 struct drm_gem_object *gem;
581 struct tegra_bo *bo;
582
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100583 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200584 if (!gem)
585 return -EINVAL;
586
587 bo = to_tegra_bo(gem);
588
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200589 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200590
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300591 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200592
593 return 0;
594}
595
596static int tegra_syncpt_read(struct drm_device *drm, void *data,
597 struct drm_file *file)
598{
Thierry Reding776dc382013-10-14 14:43:22 +0200599 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200600 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200601 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200602
Thierry Reding776dc382013-10-14 14:43:22 +0200603 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200604 if (!sp)
605 return -EINVAL;
606
607 args->value = host1x_syncpt_read_min(sp);
608 return 0;
609}
610
611static int tegra_syncpt_incr(struct drm_device *drm, void *data,
612 struct drm_file *file)
613{
Thierry Reding776dc382013-10-14 14:43:22 +0200614 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200615 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200616 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200617
Thierry Reding776dc382013-10-14 14:43:22 +0200618 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200619 if (!sp)
620 return -EINVAL;
621
Arto Merilainenebae30b2013-05-29 13:26:08 +0300622 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200623}
624
625static int tegra_syncpt_wait(struct drm_device *drm, void *data,
626 struct drm_file *file)
627{
Thierry Reding776dc382013-10-14 14:43:22 +0200628 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200629 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200630 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200631
Thierry Reding776dc382013-10-14 14:43:22 +0200632 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200633 if (!sp)
634 return -EINVAL;
635
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300636 return host1x_syncpt_wait(sp, args->thresh,
637 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200638 &args->value);
639}
640
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100641static int tegra_client_open(struct tegra_drm_file *fpriv,
642 struct tegra_drm_client *client,
643 struct tegra_drm_context *context)
644{
645 int err;
646
647 err = client->ops->open_channel(client, context);
648 if (err < 0)
649 return err;
650
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300651 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100652 if (err < 0) {
653 client->ops->close_channel(context);
654 return err;
655 }
656
657 context->client = client;
658 context->id = err;
659
660 return 0;
661}
662
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200663static int tegra_open_channel(struct drm_device *drm, void *data,
664 struct drm_file *file)
665{
Thierry Reding08943e62013-09-26 16:08:18 +0200666 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200667 struct tegra_drm *tegra = drm->dev_private;
668 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200669 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200670 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200671 int err = -ENODEV;
672
673 context = kzalloc(sizeof(*context), GFP_KERNEL);
674 if (!context)
675 return -ENOMEM;
676
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100677 mutex_lock(&fpriv->lock);
678
Thierry Reding776dc382013-10-14 14:43:22 +0200679 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200680 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100681 err = tegra_client_open(fpriv, client, context);
682 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200683 break;
684
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100685 args->context = context->id;
686 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200687 }
688
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100689 if (err < 0)
690 kfree(context);
691
692 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200693 return err;
694}
695
696static int tegra_close_channel(struct drm_device *drm, void *data,
697 struct drm_file *file)
698{
Thierry Reding08943e62013-09-26 16:08:18 +0200699 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200700 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200701 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100702 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200703
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100704 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200705
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300706 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100707 if (!context) {
708 err = -EINVAL;
709 goto unlock;
710 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200711
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100712 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200713 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200714
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100715unlock:
716 mutex_unlock(&fpriv->lock);
717 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200718}
719
720static int tegra_get_syncpt(struct drm_device *drm, void *data,
721 struct drm_file *file)
722{
Thierry Reding08943e62013-09-26 16:08:18 +0200723 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200724 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200725 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200726 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100727 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200728
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100729 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200730
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300731 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100732 if (!context) {
733 err = -ENODEV;
734 goto unlock;
735 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200736
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100737 if (args->index >= context->client->base.num_syncpts) {
738 err = -EINVAL;
739 goto unlock;
740 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200741
Thierry Reding53fa7f72013-09-24 15:35:40 +0200742 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200743 args->id = host1x_syncpt_id(syncpt);
744
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100745unlock:
746 mutex_unlock(&fpriv->lock);
747 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200748}
749
750static int tegra_submit(struct drm_device *drm, void *data,
751 struct drm_file *file)
752{
Thierry Reding08943e62013-09-26 16:08:18 +0200753 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200754 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200755 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100756 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200757
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100758 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200759
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300760 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100761 if (!context) {
762 err = -ENODEV;
763 goto unlock;
764 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200765
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100766 err = context->client->ops->submit(context, args, drm, file);
767
768unlock:
769 mutex_unlock(&fpriv->lock);
770 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200771}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300772
773static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
774 struct drm_file *file)
775{
776 struct tegra_drm_file *fpriv = file->driver_priv;
777 struct drm_tegra_get_syncpt_base *args = data;
778 struct tegra_drm_context *context;
779 struct host1x_syncpt_base *base;
780 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100781 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300782
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100783 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300784
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300785 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100786 if (!context) {
787 err = -ENODEV;
788 goto unlock;
789 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300790
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100791 if (args->syncpt >= context->client->base.num_syncpts) {
792 err = -EINVAL;
793 goto unlock;
794 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300795
796 syncpt = context->client->base.syncpts[args->syncpt];
797
798 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100799 if (!base) {
800 err = -ENXIO;
801 goto unlock;
802 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300803
804 args->id = host1x_syncpt_base_id(base);
805
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100806unlock:
807 mutex_unlock(&fpriv->lock);
808 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300809}
Thierry Reding7678d712014-06-03 14:56:57 +0200810
811static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
812 struct drm_file *file)
813{
814 struct drm_tegra_gem_set_tiling *args = data;
815 enum tegra_bo_tiling_mode mode;
816 struct drm_gem_object *gem;
817 unsigned long value = 0;
818 struct tegra_bo *bo;
819
820 switch (args->mode) {
821 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
822 mode = TEGRA_BO_TILING_MODE_PITCH;
823
824 if (args->value != 0)
825 return -EINVAL;
826
827 break;
828
829 case DRM_TEGRA_GEM_TILING_MODE_TILED:
830 mode = TEGRA_BO_TILING_MODE_TILED;
831
832 if (args->value != 0)
833 return -EINVAL;
834
835 break;
836
837 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
838 mode = TEGRA_BO_TILING_MODE_BLOCK;
839
840 if (args->value > 5)
841 return -EINVAL;
842
843 value = args->value;
844 break;
845
846 default:
847 return -EINVAL;
848 }
849
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100850 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200851 if (!gem)
852 return -ENOENT;
853
854 bo = to_tegra_bo(gem);
855
856 bo->tiling.mode = mode;
857 bo->tiling.value = value;
858
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300859 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200860
861 return 0;
862}
863
864static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
865 struct drm_file *file)
866{
867 struct drm_tegra_gem_get_tiling *args = data;
868 struct drm_gem_object *gem;
869 struct tegra_bo *bo;
870 int err = 0;
871
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100872 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200873 if (!gem)
874 return -ENOENT;
875
876 bo = to_tegra_bo(gem);
877
878 switch (bo->tiling.mode) {
879 case TEGRA_BO_TILING_MODE_PITCH:
880 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
881 args->value = 0;
882 break;
883
884 case TEGRA_BO_TILING_MODE_TILED:
885 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
886 args->value = 0;
887 break;
888
889 case TEGRA_BO_TILING_MODE_BLOCK:
890 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
891 args->value = bo->tiling.value;
892 break;
893
894 default:
895 err = -EINVAL;
896 break;
897 }
898
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300899 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200900
901 return err;
902}
Thierry Reding7b129082014-06-10 12:04:03 +0200903
904static int tegra_gem_set_flags(struct drm_device *drm, void *data,
905 struct drm_file *file)
906{
907 struct drm_tegra_gem_set_flags *args = data;
908 struct drm_gem_object *gem;
909 struct tegra_bo *bo;
910
911 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
912 return -EINVAL;
913
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100914 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200915 if (!gem)
916 return -ENOENT;
917
918 bo = to_tegra_bo(gem);
919 bo->flags = 0;
920
921 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
922 bo->flags |= TEGRA_BO_BOTTOM_UP;
923
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300924 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200925
926 return 0;
927}
928
929static int tegra_gem_get_flags(struct drm_device *drm, void *data,
930 struct drm_file *file)
931{
932 struct drm_tegra_gem_get_flags *args = data;
933 struct drm_gem_object *gem;
934 struct tegra_bo *bo;
935
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100936 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200937 if (!gem)
938 return -ENOENT;
939
940 bo = to_tegra_bo(gem);
941 args->flags = 0;
942
943 if (bo->flags & TEGRA_BO_BOTTOM_UP)
944 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
945
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300946 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200947
948 return 0;
949}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200950#endif
951
Rob Clarkbaa70942013-08-02 13:27:49 -0400952static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200953#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200954 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
955 DRM_UNLOCKED | DRM_RENDER_ALLOW),
956 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
957 DRM_UNLOCKED | DRM_RENDER_ALLOW),
958 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
959 DRM_UNLOCKED | DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
961 DRM_UNLOCKED | DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
963 DRM_UNLOCKED | DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
965 DRM_UNLOCKED | DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
967 DRM_UNLOCKED | DRM_RENDER_ALLOW),
968 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
969 DRM_UNLOCKED | DRM_RENDER_ALLOW),
970 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
971 DRM_UNLOCKED | DRM_RENDER_ALLOW),
972 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
973 DRM_UNLOCKED | DRM_RENDER_ALLOW),
974 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
975 DRM_UNLOCKED | DRM_RENDER_ALLOW),
976 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
977 DRM_UNLOCKED | DRM_RENDER_ALLOW),
978 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
979 DRM_UNLOCKED | DRM_RENDER_ALLOW),
980 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
981 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200982#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000983};
984
985static const struct file_operations tegra_drm_fops = {
986 .owner = THIS_MODULE,
987 .open = drm_open,
988 .release = drm_release,
989 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200990 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000991 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000992 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000993 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000994 .llseek = noop_llseek,
995};
996
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100997static int tegra_drm_context_cleanup(int id, void *p, void *data)
998{
999 struct tegra_drm_context *context = p;
1000
1001 tegra_drm_context_free(context);
1002
1003 return 0;
1004}
1005
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001006static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +01001007{
Thierry Reding08943e62013-09-26 16:08:18 +02001008 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +01001009
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001010 mutex_lock(&fpriv->lock);
1011 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1012 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001013
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001014 idr_destroy(&fpriv->contexts);
1015 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001016 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001017}
1018
Thierry Redinge450fcc2013-02-13 16:13:16 +01001019#ifdef CONFIG_DEBUG_FS
1020static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1021{
1022 struct drm_info_node *node = (struct drm_info_node *)s->private;
1023 struct drm_device *drm = node->minor->dev;
1024 struct drm_framebuffer *fb;
1025
1026 mutex_lock(&drm->mode_config.fb_lock);
1027
1028 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1029 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001030 fb->base.id, fb->width, fb->height,
1031 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001032 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001033 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001034 }
1035
1036 mutex_unlock(&drm->mode_config.fb_lock);
1037
1038 return 0;
1039}
1040
Thierry Reding28c23372015-01-23 09:16:03 +01001041static int tegra_debugfs_iova(struct seq_file *s, void *data)
1042{
1043 struct drm_info_node *node = (struct drm_info_node *)s->private;
1044 struct drm_device *drm = node->minor->dev;
1045 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001046 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001047
Michał Mirosław68d890a2017-08-14 23:53:45 +02001048 if (tegra->domain) {
1049 mutex_lock(&tegra->mm_lock);
1050 drm_mm_print(&tegra->mm, &p);
1051 mutex_unlock(&tegra->mm_lock);
1052 }
Daniel Vetterb5c37142016-12-29 12:09:24 +01001053
1054 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001055}
1056
Thierry Redinge450fcc2013-02-13 16:13:16 +01001057static struct drm_info_list tegra_debugfs_list[] = {
1058 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001059 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001060};
1061
1062static int tegra_debugfs_init(struct drm_minor *minor)
1063{
1064 return drm_debugfs_create_files(tegra_debugfs_list,
1065 ARRAY_SIZE(tegra_debugfs_list),
1066 minor->debugfs_root, minor);
1067}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001068#endif
1069
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001070static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001071 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001072 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001073 .load = tegra_drm_load,
1074 .unload = tegra_drm_unload,
1075 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001076 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001077 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001078
Thierry Redinge450fcc2013-02-13 16:13:16 +01001079#if defined(CONFIG_DEBUG_FS)
1080 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001081#endif
1082
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001083 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001084 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001085
1086 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1087 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1088 .gem_prime_export = tegra_gem_prime_export,
1089 .gem_prime_import = tegra_gem_prime_import,
1090
Arto Merilainende2ba662013-03-22 16:34:08 +02001091 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001092
1093 .ioctls = tegra_drm_ioctls,
1094 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1095 .fops = &tegra_drm_fops,
1096
1097 .name = DRIVER_NAME,
1098 .desc = DRIVER_DESC,
1099 .date = DRIVER_DATE,
1100 .major = DRIVER_MAJOR,
1101 .minor = DRIVER_MINOR,
1102 .patchlevel = DRIVER_PATCHLEVEL,
1103};
Thierry Reding776dc382013-10-14 14:43:22 +02001104
1105int tegra_drm_register_client(struct tegra_drm *tegra,
1106 struct tegra_drm_client *client)
1107{
1108 mutex_lock(&tegra->clients_lock);
1109 list_add_tail(&client->list, &tegra->clients);
1110 mutex_unlock(&tegra->clients_lock);
1111
1112 return 0;
1113}
1114
1115int tegra_drm_unregister_client(struct tegra_drm *tegra,
1116 struct tegra_drm_client *client)
1117{
1118 mutex_lock(&tegra->clients_lock);
1119 list_del_init(&client->list);
1120 mutex_unlock(&tegra->clients_lock);
1121
1122 return 0;
1123}
1124
Thierry Reding0c407de2018-05-04 15:02:24 +02001125struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1126 bool shared)
1127{
1128 struct drm_device *drm = dev_get_drvdata(client->parent);
1129 struct tegra_drm *tegra = drm->dev_private;
1130 struct iommu_group *group = NULL;
1131 int err;
1132
1133 if (tegra->domain) {
1134 group = iommu_group_get(client->dev);
1135 if (!group) {
1136 dev_err(client->dev, "failed to get IOMMU group\n");
1137 return ERR_PTR(-ENODEV);
1138 }
1139
1140 if (!shared || (shared && (group != tegra->group))) {
1141 err = iommu_attach_group(tegra->domain, group);
1142 if (err < 0) {
1143 iommu_group_put(group);
1144 return ERR_PTR(err);
1145 }
1146
1147 if (shared && !tegra->group)
1148 tegra->group = group;
1149 }
1150 }
1151
1152 return group;
1153}
1154
1155void host1x_client_iommu_detach(struct host1x_client *client,
1156 struct iommu_group *group)
1157{
1158 struct drm_device *drm = dev_get_drvdata(client->parent);
1159 struct tegra_drm *tegra = drm->dev_private;
1160
1161 if (group) {
1162 if (group == tegra->group) {
1163 iommu_detach_group(tegra->domain, group);
1164 tegra->group = NULL;
1165 }
1166
1167 iommu_group_put(group);
1168 }
1169}
1170
Thierry Reding67485fb2017-11-09 13:17:11 +01001171void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001172{
1173 struct iova *alloc;
1174 void *virt;
1175 gfp_t gfp;
1176 int err;
1177
1178 if (tegra->domain)
1179 size = iova_align(&tegra->carveout.domain, size);
1180 else
1181 size = PAGE_ALIGN(size);
1182
1183 gfp = GFP_KERNEL | __GFP_ZERO;
1184 if (!tegra->domain) {
1185 /*
1186 * Many units only support 32-bit addresses, even on 64-bit
1187 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1188 * virtual address space, force allocations to be in the
1189 * lower 32-bit range.
1190 */
1191 gfp |= GFP_DMA;
1192 }
1193
1194 virt = (void *)__get_free_pages(gfp, get_order(size));
1195 if (!virt)
1196 return ERR_PTR(-ENOMEM);
1197
1198 if (!tegra->domain) {
1199 /*
1200 * If IOMMU is disabled, devices address physical memory
1201 * directly.
1202 */
1203 *dma = virt_to_phys(virt);
1204 return virt;
1205 }
1206
1207 alloc = alloc_iova(&tegra->carveout.domain,
1208 size >> tegra->carveout.shift,
1209 tegra->carveout.limit, true);
1210 if (!alloc) {
1211 err = -EBUSY;
1212 goto free_pages;
1213 }
1214
1215 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1216 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1217 size, IOMMU_READ | IOMMU_WRITE);
1218 if (err < 0)
1219 goto free_iova;
1220
1221 return virt;
1222
1223free_iova:
1224 __free_iova(&tegra->carveout.domain, alloc);
1225free_pages:
1226 free_pages((unsigned long)virt, get_order(size));
1227
1228 return ERR_PTR(err);
1229}
1230
1231void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1232 dma_addr_t dma)
1233{
1234 if (tegra->domain)
1235 size = iova_align(&tegra->carveout.domain, size);
1236 else
1237 size = PAGE_ALIGN(size);
1238
1239 if (tegra->domain) {
1240 iommu_unmap(tegra->domain, dma, size);
1241 free_iova(&tegra->carveout.domain,
1242 iova_pfn(&tegra->carveout.domain, dma));
1243 }
1244
1245 free_pages((unsigned long)virt, get_order(size));
1246}
1247
Thierry Reding9910f5c2014-05-22 09:57:15 +02001248static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001249{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001250 struct drm_driver *driver = &tegra_drm_driver;
1251 struct drm_device *drm;
1252 int err;
1253
1254 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001255 if (IS_ERR(drm))
1256 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001257
Thierry Reding9910f5c2014-05-22 09:57:15 +02001258 dev_set_drvdata(&dev->dev, drm);
1259
1260 err = drm_dev_register(drm, 0);
1261 if (err < 0)
1262 goto unref;
1263
Thierry Reding9910f5c2014-05-22 09:57:15 +02001264 return 0;
1265
1266unref:
1267 drm_dev_unref(drm);
1268 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001269}
1270
Thierry Reding9910f5c2014-05-22 09:57:15 +02001271static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001272{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001273 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1274
1275 drm_dev_unregister(drm);
1276 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001277
1278 return 0;
1279}
1280
Thierry Reding359ae682014-12-18 17:15:25 +01001281#ifdef CONFIG_PM_SLEEP
1282static int host1x_drm_suspend(struct device *dev)
1283{
1284 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001285 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001286
1287 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001288 tegra_drm_fb_suspend(drm);
1289
1290 tegra->state = drm_atomic_helper_suspend(drm);
1291 if (IS_ERR(tegra->state)) {
1292 tegra_drm_fb_resume(drm);
1293 drm_kms_helper_poll_enable(drm);
1294 return PTR_ERR(tegra->state);
1295 }
Thierry Reding359ae682014-12-18 17:15:25 +01001296
1297 return 0;
1298}
1299
1300static int host1x_drm_resume(struct device *dev)
1301{
1302 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001303 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001304
Thierry Reding986c58d2015-08-11 13:11:49 +02001305 drm_atomic_helper_resume(drm, tegra->state);
1306 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001307 drm_kms_helper_poll_enable(drm);
1308
1309 return 0;
1310}
1311#endif
1312
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001313static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1314 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001315
Thierry Reding776dc382013-10-14 14:43:22 +02001316static const struct of_device_id host1x_drm_subdevs[] = {
1317 { .compatible = "nvidia,tegra20-dc", },
1318 { .compatible = "nvidia,tegra20-hdmi", },
1319 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001320 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001321 { .compatible = "nvidia,tegra30-dc", },
1322 { .compatible = "nvidia,tegra30-hdmi", },
1323 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001324 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001325 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001326 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001327 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001328 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001329 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001330 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001331 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001332 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001333 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001334 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001335 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001336 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001337 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001338 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001339 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001340 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001341 { .compatible = "nvidia,tegra186-sor", },
1342 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001343 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001344 { /* sentinel */ }
1345};
1346
1347static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001348 .driver = {
1349 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001350 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001351 },
Thierry Reding776dc382013-10-14 14:43:22 +02001352 .probe = host1x_drm_probe,
1353 .remove = host1x_drm_remove,
1354 .subdevs = host1x_drm_subdevs,
1355};
1356
Thierry Reding473112e2015-09-10 16:07:14 +02001357static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001358 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001359 &tegra_dc_driver,
1360 &tegra_hdmi_driver,
1361 &tegra_dsi_driver,
1362 &tegra_dpaux_driver,
1363 &tegra_sor_driver,
1364 &tegra_gr2d_driver,
1365 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001366 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001367};
1368
Thierry Reding776dc382013-10-14 14:43:22 +02001369static int __init host1x_drm_init(void)
1370{
1371 int err;
1372
1373 err = host1x_driver_register(&host1x_drm_driver);
1374 if (err < 0)
1375 return err;
1376
Thierry Reding473112e2015-09-10 16:07:14 +02001377 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001378 if (err < 0)
1379 goto unregister_host1x;
1380
Thierry Reding776dc382013-10-14 14:43:22 +02001381 return 0;
1382
Thierry Reding776dc382013-10-14 14:43:22 +02001383unregister_host1x:
1384 host1x_driver_unregister(&host1x_drm_driver);
1385 return err;
1386}
1387module_init(host1x_drm_init);
1388
1389static void __exit host1x_drm_exit(void)
1390{
Thierry Reding473112e2015-09-10 16:07:14 +02001391 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001392 host1x_driver_unregister(&host1x_drm_driver);
1393}
1394module_exit(host1x_drm_exit);
1395
1396MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1397MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1398MODULE_LICENSE("GPL v2");