blob: 7fcf4a24284088ba798296016797032f70e5fa96 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingab7d3f52017-12-14 13:46:20 +010036static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010038{
Thierry Reding1503ca42014-11-24 17:41:23 +010039 int err;
40
Thierry Redingab7d3f52017-12-14 13:46:20 +010041 err = drm_atomic_helper_check_modeset(drm, state);
42 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010043 return err;
44
Thierry Redingab7d3f52017-12-14 13:46:20 +010045 err = drm_atomic_normalize_zpos(drm, state);
46 if (err < 0)
Maarten Lankhorst424624e2017-07-11 16:33:10 +020047 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010048
Thierry Redingab7d3f52017-12-14 13:46:20 +010049 err = drm_atomic_helper_check_planes(drm, state);
50 if (err < 0)
51 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010052
Thierry Redingab7d3f52017-12-14 13:46:20 +010053 if (state->legacy_cursor_update)
54 state->async_update = !drm_atomic_helper_async_check(drm, state);
55
Thierry Reding1503ca42014-11-24 17:41:23 +010056 return 0;
57}
58
Thierry Redingc4755fb2017-11-13 11:08:13 +010059static struct drm_atomic_state *
60tegra_atomic_state_alloc(struct drm_device *drm)
61{
62 struct tegra_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
63
64 if (!state || drm_atomic_state_init(drm, &state->base) < 0) {
65 kfree(state);
66 return NULL;
67 }
68
69 return &state->base;
70}
71
72static void tegra_atomic_state_clear(struct drm_atomic_state *state)
73{
74 struct tegra_atomic_state *tegra = to_tegra_atomic_state(state);
75
76 drm_atomic_state_default_clear(state);
77 tegra->clk_disp = NULL;
78 tegra->dc = NULL;
79 tegra->rate = 0;
80}
81
82static void tegra_atomic_state_free(struct drm_atomic_state *state)
83{
84 drm_atomic_state_default_release(state);
85 kfree(state);
86}
87
Thierry Reding31b02ca2017-10-12 17:40:46 +020088static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010089 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053090#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010091 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010092#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010093 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020094 .atomic_commit = drm_atomic_helper_commit,
Thierry Redingc4755fb2017-11-13 11:08:13 +010095 .atomic_state_alloc = tegra_atomic_state_alloc,
96 .atomic_state_clear = tegra_atomic_state_clear,
97 .atomic_state_free = tegra_atomic_state_free,
Thierry Reding31b02ca2017-10-12 17:40:46 +020098};
99
Thierry Redingc4755fb2017-11-13 11:08:13 +0100100static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
101{
102 struct drm_device *drm = old_state->dev;
103 struct tegra_drm *tegra = drm->dev_private;
104
105 if (tegra->hub) {
106 drm_atomic_helper_commit_modeset_disables(drm, old_state);
107 tegra_display_hub_atomic_commit(drm, old_state);
108 drm_atomic_helper_commit_planes(drm, old_state, 0);
109 drm_atomic_helper_commit_modeset_enables(drm, old_state);
110 drm_atomic_helper_commit_hw_done(old_state);
111 drm_atomic_helper_wait_for_vblanks(drm, old_state);
112 drm_atomic_helper_cleanup_planes(drm, old_state);
113 } else {
114 drm_atomic_helper_commit_tail_rpm(old_state);
115 }
116}
117
Thierry Reding31b02ca2017-10-12 17:40:46 +0200118static const struct drm_mode_config_helper_funcs
119tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +0100120 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +0100121};
122
Thierry Reding776dc382013-10-14 14:43:22 +0200123static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000124{
Thierry Reding776dc382013-10-14 14:43:22 +0200125 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200126 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000127 int err;
128
Thierry Reding776dc382013-10-14 14:43:22 +0200129 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200130 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200131 return -ENOMEM;
132
Thierry Redingdf06b752014-06-26 21:41:53 +0200133 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200134 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100135 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200136 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100137
Thierry Redingdf06b752014-06-26 21:41:53 +0200138 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300139 if (!tegra->domain) {
140 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200141 goto free;
142 }
143
Thierry Reding4553f732015-01-19 16:15:04 +0100144 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200145 gem_start = geometry->aperture_start;
146 gem_end = geometry->aperture_end - CARVEOUT_SZ;
147 carveout_start = gem_end + 1;
148 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100149
Mikko Perttunenad926012016-12-14 13:16:11 +0200150 order = __ffs(tegra->domain->pgsize_bitmap);
151 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100152 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200153
154 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
155 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
156
157 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100158 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200159
160 DRM_DEBUG("IOMMU apertures:\n");
161 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
162 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
163 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200164 }
165
Thierry Reding386a2a72013-09-24 13:22:17 +0200166 mutex_init(&tegra->clients_lock);
167 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100168
Thierry Reding386a2a72013-09-24 13:22:17 +0200169 drm->dev_private = tegra;
170 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000171
172 drm_mode_config_init(drm);
173
Thierry Redingf9914212014-11-26 13:03:57 +0100174 drm->mode_config.min_width = 0;
175 drm->mode_config.min_height = 0;
176
177 drm->mode_config.max_width = 4096;
178 drm->mode_config.max_height = 4096;
179
Alexandre Courbot5e911442016-11-08 16:50:42 +0900180 drm->mode_config.allow_fb_modifiers = true;
181
Thierry Reding31b02ca2017-10-12 17:40:46 +0200182 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
183 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100184
Thierry Redinge2215322014-06-27 17:19:25 +0200185 err = tegra_drm_fb_prepare(drm);
186 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100187 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200188
189 drm_kms_helper_poll_init(drm);
190
Thierry Reding776dc382013-10-14 14:43:22 +0200191 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000192 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100193 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000194
Thierry Redingc4755fb2017-11-13 11:08:13 +0100195 if (tegra->hub) {
196 err = tegra_display_hub_prepare(tegra->hub);
197 if (err < 0)
198 goto device;
199 }
200
Thierry Reding603f0cc2013-04-22 21:22:14 +0200201 /*
202 * We don't use the drm_irq_install() helpers provided by the DRM
203 * core, so we need to set this manually in order to allow the
204 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
205 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300206 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200207
Thierry Reding42e9ce02015-01-28 14:43:05 +0100208 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100209 drm->max_vblank_count = 0xffffffff;
210
Thierry Reding6e5ff992012-11-28 11:45:47 +0100211 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
212 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100213 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100214
Thierry Reding31930d42015-07-02 17:04:06 +0200215 drm_mode_config_reset(drm);
216
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000217 err = tegra_drm_fb_init(drm);
218 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100219 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000220
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000221 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100222
Thierry Redingc4755fb2017-11-13 11:08:13 +0100223hub:
224 if (tegra->hub)
225 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100226device:
227 host1x_device_exit(device);
228fbdev:
229 drm_kms_helper_poll_fini(drm);
230 tegra_drm_fb_free(drm);
231config:
232 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200233
234 if (tegra->domain) {
235 iommu_domain_free(tegra->domain);
236 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100237 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200238 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200239 }
240free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100241 kfree(tegra);
242 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000243}
244
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200245static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000246{
Thierry Reding776dc382013-10-14 14:43:22 +0200247 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200248 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200249 int err;
250
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000251 drm_kms_helper_poll_fini(drm);
252 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100253 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200254 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000255
Thierry Reding776dc382013-10-14 14:43:22 +0200256 err = host1x_device_exit(device);
257 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200258 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200259
Thierry Redingdf06b752014-06-26 21:41:53 +0200260 if (tegra->domain) {
261 iommu_domain_free(tegra->domain);
262 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100263 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200264 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200265 }
266
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100267 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000268}
269
270static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
271{
Thierry Reding08943e62013-09-26 16:08:18 +0200272 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200273
274 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
275 if (!fpriv)
276 return -ENOMEM;
277
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100278 idr_init(&fpriv->contexts);
279 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200280 filp->driver_priv = fpriv;
281
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000282 return 0;
283}
284
Thierry Redingc88c3632013-09-26 16:08:22 +0200285static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200286{
287 context->client->ops->close_channel(context);
288 kfree(context);
289}
290
Thierry Redingc40f0f12013-10-10 11:00:33 +0200291static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100292host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200293{
294 struct drm_gem_object *gem;
295 struct tegra_bo *bo;
296
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100297 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200298 if (!gem)
299 return NULL;
300
Thierry Redingc40f0f12013-10-10 11:00:33 +0200301 bo = to_tegra_bo(gem);
302 return &bo->base;
303}
304
Thierry Reding961e3be2014-06-10 10:25:00 +0200305static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
306 struct drm_tegra_reloc __user *src,
307 struct drm_device *drm,
308 struct drm_file *file)
309{
310 u32 cmdbuf, target;
311 int err;
312
313 err = get_user(cmdbuf, &src->cmdbuf.handle);
314 if (err < 0)
315 return err;
316
317 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
318 if (err < 0)
319 return err;
320
321 err = get_user(target, &src->target.handle);
322 if (err < 0)
323 return err;
324
David Ung31f40f82015-01-20 18:37:35 -0800325 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200326 if (err < 0)
327 return err;
328
329 err = get_user(dest->shift, &src->shift);
330 if (err < 0)
331 return err;
332
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100333 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200334 if (!dest->cmdbuf.bo)
335 return -ENOENT;
336
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100337 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200338 if (!dest->target.bo)
339 return -ENOENT;
340
341 return 0;
342}
343
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300344static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
345 struct drm_tegra_waitchk __user *src,
346 struct drm_file *file)
347{
348 u32 cmdbuf;
349 int err;
350
351 err = get_user(cmdbuf, &src->handle);
352 if (err < 0)
353 return err;
354
355 err = get_user(dest->offset, &src->offset);
356 if (err < 0)
357 return err;
358
359 err = get_user(dest->syncpt_id, &src->syncpt);
360 if (err < 0)
361 return err;
362
363 err = get_user(dest->thresh, &src->thresh);
364 if (err < 0)
365 return err;
366
367 dest->bo = host1x_bo_lookup(file, cmdbuf);
368 if (!dest->bo)
369 return -ENOENT;
370
371 return 0;
372}
373
Thierry Redingc40f0f12013-10-10 11:00:33 +0200374int tegra_drm_submit(struct tegra_drm_context *context,
375 struct drm_tegra_submit *args, struct drm_device *drm,
376 struct drm_file *file)
377{
378 unsigned int num_cmdbufs = args->num_cmdbufs;
379 unsigned int num_relocs = args->num_relocs;
380 unsigned int num_waitchks = args->num_waitchks;
Mikko Perttunena176c672017-09-28 15:50:44 +0300381 struct drm_tegra_cmdbuf __user *user_cmdbufs;
382 struct drm_tegra_reloc __user *user_relocs;
383 struct drm_tegra_waitchk __user *user_waitchks;
384 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200385 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300386 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200387 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300388 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200389 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200390 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200391 int err;
392
Mikko Perttunena176c672017-09-28 15:50:44 +0300393 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
394 user_relocs = u64_to_user_ptr(args->relocs);
395 user_waitchks = u64_to_user_ptr(args->waitchks);
396 user_syncpt = u64_to_user_ptr(args->syncpts);
397
Thierry Redingc40f0f12013-10-10 11:00:33 +0200398 /* We don't yet support other than one syncpt_incr struct per submit */
399 if (args->num_syncpts != 1)
400 return -EINVAL;
401
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300402 /* We don't yet support waitchks */
403 if (args->num_waitchks != 0)
404 return -EINVAL;
405
Thierry Redingc40f0f12013-10-10 11:00:33 +0200406 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
407 args->num_relocs, args->num_waitchks);
408 if (!job)
409 return -ENOMEM;
410
411 job->num_relocs = args->num_relocs;
412 job->num_waitchk = args->num_waitchks;
413 job->client = (u32)args->context;
414 job->class = context->client->base.class;
415 job->serialize = true;
416
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200417 /*
418 * Track referenced BOs so that they can be unreferenced after the
419 * submission is complete.
420 */
421 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
422
423 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
424 if (!refs) {
425 err = -ENOMEM;
426 goto put;
427 }
428
429 /* reuse as an iterator later */
430 num_refs = 0;
431
Thierry Redingc40f0f12013-10-10 11:00:33 +0200432 while (num_cmdbufs) {
433 struct drm_tegra_cmdbuf cmdbuf;
434 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300435 struct tegra_bo *obj;
436 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200437
Mikko Perttunena176c672017-09-28 15:50:44 +0300438 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300439 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200440 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300441 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200442
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300443 /*
444 * The maximum number of CDMA gather fetches is 16383, a higher
445 * value means the words count is malformed.
446 */
447 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
448 err = -EINVAL;
449 goto fail;
450 }
451
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100452 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200453 if (!bo) {
454 err = -ENOENT;
455 goto fail;
456 }
457
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300458 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
459 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200460 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300461
462 /*
463 * Gather buffer base address must be 4-bytes aligned,
464 * unaligned offset is malformed and cause commands stream
465 * corruption on the buffer address relocation.
466 */
467 if (offset & 3 || offset >= obj->gem.size) {
468 err = -EINVAL;
469 goto fail;
470 }
471
Thierry Redingc40f0f12013-10-10 11:00:33 +0200472 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
473 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300474 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200475 }
476
Thierry Reding961e3be2014-06-10 10:25:00 +0200477 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200478 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300479 struct host1x_reloc *reloc;
480 struct tegra_bo *obj;
481
Thierry Reding961e3be2014-06-10 10:25:00 +0200482 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300483 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200484 file);
485 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200486 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300487
488 reloc = &job->relocarray[num_relocs];
489 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200490 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300491
492 /*
493 * The unaligned cmdbuf offset will cause an unaligned write
494 * during of the relocations patching, corrupting the commands
495 * stream.
496 */
497 if (reloc->cmdbuf.offset & 3 ||
498 reloc->cmdbuf.offset >= obj->gem.size) {
499 err = -EINVAL;
500 goto fail;
501 }
502
503 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200504 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300505
506 if (reloc->target.offset >= obj->gem.size) {
507 err = -EINVAL;
508 goto fail;
509 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200510 }
511
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300512 /* copy and resolve waitchks from submit */
513 while (num_waitchks--) {
514 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
515 struct tegra_bo *obj;
516
Mikko Perttunena176c672017-09-28 15:50:44 +0300517 err = host1x_waitchk_copy_from_user(
518 wait, &user_waitchks[num_waitchks], file);
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300519 if (err < 0)
520 goto fail;
521
522 obj = host1x_to_tegra_bo(wait->bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200523 refs[num_refs++] = &obj->gem;
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300524
525 /*
526 * The unaligned offset will cause an unaligned write during
527 * of the waitchks patching, corrupting the commands stream.
528 */
529 if (wait->offset & 3 ||
530 wait->offset >= obj->gem.size) {
531 err = -EINVAL;
532 goto fail;
533 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300534 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200535
Mikko Perttunena176c672017-09-28 15:50:44 +0300536 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300537 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200538 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300539 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200540
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300541 /* check whether syncpoint ID is valid */
542 sp = host1x_syncpt_get(host1x, syncpt.id);
543 if (!sp) {
544 err = -ENOENT;
545 goto fail;
546 }
547
Thierry Redingc40f0f12013-10-10 11:00:33 +0200548 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300549 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200550 job->syncpt_incrs = syncpt.incrs;
551 job->syncpt_id = syncpt.id;
552 job->timeout = 10000;
553
554 if (args->timeout && args->timeout < 10000)
555 job->timeout = args->timeout;
556
557 err = host1x_job_pin(job, context->client->base.dev);
558 if (err)
559 goto fail;
560
561 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200562 if (err) {
563 host1x_job_unpin(job);
564 goto fail;
565 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200566
567 args->fence = job->syncpt_end;
568
Thierry Redingc40f0f12013-10-10 11:00:33 +0200569fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200570 while (num_refs--)
571 drm_gem_object_put_unlocked(refs[num_refs]);
572
573 kfree(refs);
574
575put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200576 host1x_job_put(job);
577 return err;
578}
579
580
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200581#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200582static int tegra_gem_create(struct drm_device *drm, void *data,
583 struct drm_file *file)
584{
585 struct drm_tegra_gem_create *args = data;
586 struct tegra_bo *bo;
587
Thierry Reding773af772013-10-04 22:34:01 +0200588 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200589 &args->handle);
590 if (IS_ERR(bo))
591 return PTR_ERR(bo);
592
593 return 0;
594}
595
596static int tegra_gem_mmap(struct drm_device *drm, void *data,
597 struct drm_file *file)
598{
599 struct drm_tegra_gem_mmap *args = data;
600 struct drm_gem_object *gem;
601 struct tegra_bo *bo;
602
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100603 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200604 if (!gem)
605 return -EINVAL;
606
607 bo = to_tegra_bo(gem);
608
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200609 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200610
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300611 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200612
613 return 0;
614}
615
616static int tegra_syncpt_read(struct drm_device *drm, void *data,
617 struct drm_file *file)
618{
Thierry Reding776dc382013-10-14 14:43:22 +0200619 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200620 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200621 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200622
Thierry Reding776dc382013-10-14 14:43:22 +0200623 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200624 if (!sp)
625 return -EINVAL;
626
627 args->value = host1x_syncpt_read_min(sp);
628 return 0;
629}
630
631static int tegra_syncpt_incr(struct drm_device *drm, void *data,
632 struct drm_file *file)
633{
Thierry Reding776dc382013-10-14 14:43:22 +0200634 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200635 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200636 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200637
Thierry Reding776dc382013-10-14 14:43:22 +0200638 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200639 if (!sp)
640 return -EINVAL;
641
Arto Merilainenebae30b2013-05-29 13:26:08 +0300642 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200643}
644
645static int tegra_syncpt_wait(struct drm_device *drm, void *data,
646 struct drm_file *file)
647{
Thierry Reding776dc382013-10-14 14:43:22 +0200648 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200649 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200650 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200651
Thierry Reding776dc382013-10-14 14:43:22 +0200652 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200653 if (!sp)
654 return -EINVAL;
655
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300656 return host1x_syncpt_wait(sp, args->thresh,
657 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200658 &args->value);
659}
660
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100661static int tegra_client_open(struct tegra_drm_file *fpriv,
662 struct tegra_drm_client *client,
663 struct tegra_drm_context *context)
664{
665 int err;
666
667 err = client->ops->open_channel(client, context);
668 if (err < 0)
669 return err;
670
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300671 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100672 if (err < 0) {
673 client->ops->close_channel(context);
674 return err;
675 }
676
677 context->client = client;
678 context->id = err;
679
680 return 0;
681}
682
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200683static int tegra_open_channel(struct drm_device *drm, void *data,
684 struct drm_file *file)
685{
Thierry Reding08943e62013-09-26 16:08:18 +0200686 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200687 struct tegra_drm *tegra = drm->dev_private;
688 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200689 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200690 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200691 int err = -ENODEV;
692
693 context = kzalloc(sizeof(*context), GFP_KERNEL);
694 if (!context)
695 return -ENOMEM;
696
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100697 mutex_lock(&fpriv->lock);
698
Thierry Reding776dc382013-10-14 14:43:22 +0200699 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200700 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100701 err = tegra_client_open(fpriv, client, context);
702 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200703 break;
704
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100705 args->context = context->id;
706 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200707 }
708
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100709 if (err < 0)
710 kfree(context);
711
712 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200713 return err;
714}
715
716static int tegra_close_channel(struct drm_device *drm, void *data,
717 struct drm_file *file)
718{
Thierry Reding08943e62013-09-26 16:08:18 +0200719 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200720 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200721 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100722 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200723
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100724 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200725
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300726 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100727 if (!context) {
728 err = -EINVAL;
729 goto unlock;
730 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200731
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100732 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200733 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200734
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100735unlock:
736 mutex_unlock(&fpriv->lock);
737 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200738}
739
740static int tegra_get_syncpt(struct drm_device *drm, void *data,
741 struct drm_file *file)
742{
Thierry Reding08943e62013-09-26 16:08:18 +0200743 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200744 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200745 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200746 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100747 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200748
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100749 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200750
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300751 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100752 if (!context) {
753 err = -ENODEV;
754 goto unlock;
755 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200756
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100757 if (args->index >= context->client->base.num_syncpts) {
758 err = -EINVAL;
759 goto unlock;
760 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200761
Thierry Reding53fa7f72013-09-24 15:35:40 +0200762 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200763 args->id = host1x_syncpt_id(syncpt);
764
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100765unlock:
766 mutex_unlock(&fpriv->lock);
767 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200768}
769
770static int tegra_submit(struct drm_device *drm, void *data,
771 struct drm_file *file)
772{
Thierry Reding08943e62013-09-26 16:08:18 +0200773 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200774 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200775 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100776 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200777
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100778 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200779
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300780 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100781 if (!context) {
782 err = -ENODEV;
783 goto unlock;
784 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200785
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100786 err = context->client->ops->submit(context, args, drm, file);
787
788unlock:
789 mutex_unlock(&fpriv->lock);
790 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200791}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300792
793static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
794 struct drm_file *file)
795{
796 struct tegra_drm_file *fpriv = file->driver_priv;
797 struct drm_tegra_get_syncpt_base *args = data;
798 struct tegra_drm_context *context;
799 struct host1x_syncpt_base *base;
800 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100801 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300802
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100803 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300804
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300805 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100806 if (!context) {
807 err = -ENODEV;
808 goto unlock;
809 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300810
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100811 if (args->syncpt >= context->client->base.num_syncpts) {
812 err = -EINVAL;
813 goto unlock;
814 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300815
816 syncpt = context->client->base.syncpts[args->syncpt];
817
818 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100819 if (!base) {
820 err = -ENXIO;
821 goto unlock;
822 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300823
824 args->id = host1x_syncpt_base_id(base);
825
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100826unlock:
827 mutex_unlock(&fpriv->lock);
828 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300829}
Thierry Reding7678d712014-06-03 14:56:57 +0200830
831static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
832 struct drm_file *file)
833{
834 struct drm_tegra_gem_set_tiling *args = data;
835 enum tegra_bo_tiling_mode mode;
836 struct drm_gem_object *gem;
837 unsigned long value = 0;
838 struct tegra_bo *bo;
839
840 switch (args->mode) {
841 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
842 mode = TEGRA_BO_TILING_MODE_PITCH;
843
844 if (args->value != 0)
845 return -EINVAL;
846
847 break;
848
849 case DRM_TEGRA_GEM_TILING_MODE_TILED:
850 mode = TEGRA_BO_TILING_MODE_TILED;
851
852 if (args->value != 0)
853 return -EINVAL;
854
855 break;
856
857 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
858 mode = TEGRA_BO_TILING_MODE_BLOCK;
859
860 if (args->value > 5)
861 return -EINVAL;
862
863 value = args->value;
864 break;
865
866 default:
867 return -EINVAL;
868 }
869
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100870 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200871 if (!gem)
872 return -ENOENT;
873
874 bo = to_tegra_bo(gem);
875
876 bo->tiling.mode = mode;
877 bo->tiling.value = value;
878
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300879 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200880
881 return 0;
882}
883
884static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
885 struct drm_file *file)
886{
887 struct drm_tegra_gem_get_tiling *args = data;
888 struct drm_gem_object *gem;
889 struct tegra_bo *bo;
890 int err = 0;
891
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100892 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200893 if (!gem)
894 return -ENOENT;
895
896 bo = to_tegra_bo(gem);
897
898 switch (bo->tiling.mode) {
899 case TEGRA_BO_TILING_MODE_PITCH:
900 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
901 args->value = 0;
902 break;
903
904 case TEGRA_BO_TILING_MODE_TILED:
905 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
906 args->value = 0;
907 break;
908
909 case TEGRA_BO_TILING_MODE_BLOCK:
910 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
911 args->value = bo->tiling.value;
912 break;
913
914 default:
915 err = -EINVAL;
916 break;
917 }
918
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300919 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200920
921 return err;
922}
Thierry Reding7b129082014-06-10 12:04:03 +0200923
924static int tegra_gem_set_flags(struct drm_device *drm, void *data,
925 struct drm_file *file)
926{
927 struct drm_tegra_gem_set_flags *args = data;
928 struct drm_gem_object *gem;
929 struct tegra_bo *bo;
930
931 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
932 return -EINVAL;
933
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100934 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200935 if (!gem)
936 return -ENOENT;
937
938 bo = to_tegra_bo(gem);
939 bo->flags = 0;
940
941 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
942 bo->flags |= TEGRA_BO_BOTTOM_UP;
943
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300944 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200945
946 return 0;
947}
948
949static int tegra_gem_get_flags(struct drm_device *drm, void *data,
950 struct drm_file *file)
951{
952 struct drm_tegra_gem_get_flags *args = data;
953 struct drm_gem_object *gem;
954 struct tegra_bo *bo;
955
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100956 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200957 if (!gem)
958 return -ENOENT;
959
960 bo = to_tegra_bo(gem);
961 args->flags = 0;
962
963 if (bo->flags & TEGRA_BO_BOTTOM_UP)
964 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
965
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300966 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200967
968 return 0;
969}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200970#endif
971
Rob Clarkbaa70942013-08-02 13:27:49 -0400972static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200973#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200974 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
975 DRM_UNLOCKED | DRM_RENDER_ALLOW),
976 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
977 DRM_UNLOCKED | DRM_RENDER_ALLOW),
978 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
979 DRM_UNLOCKED | DRM_RENDER_ALLOW),
980 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
981 DRM_UNLOCKED | DRM_RENDER_ALLOW),
982 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
983 DRM_UNLOCKED | DRM_RENDER_ALLOW),
984 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
985 DRM_UNLOCKED | DRM_RENDER_ALLOW),
986 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
987 DRM_UNLOCKED | DRM_RENDER_ALLOW),
988 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
989 DRM_UNLOCKED | DRM_RENDER_ALLOW),
990 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
991 DRM_UNLOCKED | DRM_RENDER_ALLOW),
992 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
993 DRM_UNLOCKED | DRM_RENDER_ALLOW),
994 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
995 DRM_UNLOCKED | DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
997 DRM_UNLOCKED | DRM_RENDER_ALLOW),
998 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
999 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1000 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
1001 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001002#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001003};
1004
1005static const struct file_operations tegra_drm_fops = {
1006 .owner = THIS_MODULE,
1007 .open = drm_open,
1008 .release = drm_release,
1009 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +02001010 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001011 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001012 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001013 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001014 .llseek = noop_llseek,
1015};
1016
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001017static int tegra_drm_context_cleanup(int id, void *p, void *data)
1018{
1019 struct tegra_drm_context *context = p;
1020
1021 tegra_drm_context_free(context);
1022
1023 return 0;
1024}
1025
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001026static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +01001027{
Thierry Reding08943e62013-09-26 16:08:18 +02001028 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +01001029
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001030 mutex_lock(&fpriv->lock);
1031 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1032 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001033
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001034 idr_destroy(&fpriv->contexts);
1035 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001036 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001037}
1038
Thierry Redinge450fcc2013-02-13 16:13:16 +01001039#ifdef CONFIG_DEBUG_FS
1040static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1041{
1042 struct drm_info_node *node = (struct drm_info_node *)s->private;
1043 struct drm_device *drm = node->minor->dev;
1044 struct drm_framebuffer *fb;
1045
1046 mutex_lock(&drm->mode_config.fb_lock);
1047
1048 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1049 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001050 fb->base.id, fb->width, fb->height,
1051 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001052 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001053 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001054 }
1055
1056 mutex_unlock(&drm->mode_config.fb_lock);
1057
1058 return 0;
1059}
1060
Thierry Reding28c23372015-01-23 09:16:03 +01001061static int tegra_debugfs_iova(struct seq_file *s, void *data)
1062{
1063 struct drm_info_node *node = (struct drm_info_node *)s->private;
1064 struct drm_device *drm = node->minor->dev;
1065 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001066 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001067
Michał Mirosław68d890a2017-08-14 23:53:45 +02001068 if (tegra->domain) {
1069 mutex_lock(&tegra->mm_lock);
1070 drm_mm_print(&tegra->mm, &p);
1071 mutex_unlock(&tegra->mm_lock);
1072 }
Daniel Vetterb5c37142016-12-29 12:09:24 +01001073
1074 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001075}
1076
Thierry Redinge450fcc2013-02-13 16:13:16 +01001077static struct drm_info_list tegra_debugfs_list[] = {
1078 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001079 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001080};
1081
1082static int tegra_debugfs_init(struct drm_minor *minor)
1083{
1084 return drm_debugfs_create_files(tegra_debugfs_list,
1085 ARRAY_SIZE(tegra_debugfs_list),
1086 minor->debugfs_root, minor);
1087}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001088#endif
1089
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001090static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001091 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001092 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001093 .load = tegra_drm_load,
1094 .unload = tegra_drm_unload,
1095 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001096 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001097 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001098
Thierry Redinge450fcc2013-02-13 16:13:16 +01001099#if defined(CONFIG_DEBUG_FS)
1100 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001101#endif
1102
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001103 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001104 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001105
1106 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1107 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1108 .gem_prime_export = tegra_gem_prime_export,
1109 .gem_prime_import = tegra_gem_prime_import,
1110
Arto Merilainende2ba662013-03-22 16:34:08 +02001111 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001112
1113 .ioctls = tegra_drm_ioctls,
1114 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1115 .fops = &tegra_drm_fops,
1116
1117 .name = DRIVER_NAME,
1118 .desc = DRIVER_DESC,
1119 .date = DRIVER_DATE,
1120 .major = DRIVER_MAJOR,
1121 .minor = DRIVER_MINOR,
1122 .patchlevel = DRIVER_PATCHLEVEL,
1123};
Thierry Reding776dc382013-10-14 14:43:22 +02001124
1125int tegra_drm_register_client(struct tegra_drm *tegra,
1126 struct tegra_drm_client *client)
1127{
1128 mutex_lock(&tegra->clients_lock);
1129 list_add_tail(&client->list, &tegra->clients);
1130 mutex_unlock(&tegra->clients_lock);
1131
1132 return 0;
1133}
1134
1135int tegra_drm_unregister_client(struct tegra_drm *tegra,
1136 struct tegra_drm_client *client)
1137{
1138 mutex_lock(&tegra->clients_lock);
1139 list_del_init(&client->list);
1140 mutex_unlock(&tegra->clients_lock);
1141
1142 return 0;
1143}
1144
Thierry Reding67485fb2017-11-09 13:17:11 +01001145void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001146{
1147 struct iova *alloc;
1148 void *virt;
1149 gfp_t gfp;
1150 int err;
1151
1152 if (tegra->domain)
1153 size = iova_align(&tegra->carveout.domain, size);
1154 else
1155 size = PAGE_ALIGN(size);
1156
1157 gfp = GFP_KERNEL | __GFP_ZERO;
1158 if (!tegra->domain) {
1159 /*
1160 * Many units only support 32-bit addresses, even on 64-bit
1161 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1162 * virtual address space, force allocations to be in the
1163 * lower 32-bit range.
1164 */
1165 gfp |= GFP_DMA;
1166 }
1167
1168 virt = (void *)__get_free_pages(gfp, get_order(size));
1169 if (!virt)
1170 return ERR_PTR(-ENOMEM);
1171
1172 if (!tegra->domain) {
1173 /*
1174 * If IOMMU is disabled, devices address physical memory
1175 * directly.
1176 */
1177 *dma = virt_to_phys(virt);
1178 return virt;
1179 }
1180
1181 alloc = alloc_iova(&tegra->carveout.domain,
1182 size >> tegra->carveout.shift,
1183 tegra->carveout.limit, true);
1184 if (!alloc) {
1185 err = -EBUSY;
1186 goto free_pages;
1187 }
1188
1189 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1190 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1191 size, IOMMU_READ | IOMMU_WRITE);
1192 if (err < 0)
1193 goto free_iova;
1194
1195 return virt;
1196
1197free_iova:
1198 __free_iova(&tegra->carveout.domain, alloc);
1199free_pages:
1200 free_pages((unsigned long)virt, get_order(size));
1201
1202 return ERR_PTR(err);
1203}
1204
1205void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1206 dma_addr_t dma)
1207{
1208 if (tegra->domain)
1209 size = iova_align(&tegra->carveout.domain, size);
1210 else
1211 size = PAGE_ALIGN(size);
1212
1213 if (tegra->domain) {
1214 iommu_unmap(tegra->domain, dma, size);
1215 free_iova(&tegra->carveout.domain,
1216 iova_pfn(&tegra->carveout.domain, dma));
1217 }
1218
1219 free_pages((unsigned long)virt, get_order(size));
1220}
1221
Thierry Reding9910f5c2014-05-22 09:57:15 +02001222static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001223{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001224 struct drm_driver *driver = &tegra_drm_driver;
1225 struct drm_device *drm;
1226 int err;
1227
1228 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001229 if (IS_ERR(drm))
1230 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001231
Thierry Reding9910f5c2014-05-22 09:57:15 +02001232 dev_set_drvdata(&dev->dev, drm);
1233
1234 err = drm_dev_register(drm, 0);
1235 if (err < 0)
1236 goto unref;
1237
Thierry Reding9910f5c2014-05-22 09:57:15 +02001238 return 0;
1239
1240unref:
1241 drm_dev_unref(drm);
1242 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001243}
1244
Thierry Reding9910f5c2014-05-22 09:57:15 +02001245static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001246{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001247 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1248
1249 drm_dev_unregister(drm);
1250 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001251
1252 return 0;
1253}
1254
Thierry Reding359ae682014-12-18 17:15:25 +01001255#ifdef CONFIG_PM_SLEEP
1256static int host1x_drm_suspend(struct device *dev)
1257{
1258 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001259 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001260
1261 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001262 tegra_drm_fb_suspend(drm);
1263
1264 tegra->state = drm_atomic_helper_suspend(drm);
1265 if (IS_ERR(tegra->state)) {
1266 tegra_drm_fb_resume(drm);
1267 drm_kms_helper_poll_enable(drm);
1268 return PTR_ERR(tegra->state);
1269 }
Thierry Reding359ae682014-12-18 17:15:25 +01001270
1271 return 0;
1272}
1273
1274static int host1x_drm_resume(struct device *dev)
1275{
1276 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001277 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001278
Thierry Reding986c58d2015-08-11 13:11:49 +02001279 drm_atomic_helper_resume(drm, tegra->state);
1280 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001281 drm_kms_helper_poll_enable(drm);
1282
1283 return 0;
1284}
1285#endif
1286
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001287static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1288 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001289
Thierry Reding776dc382013-10-14 14:43:22 +02001290static const struct of_device_id host1x_drm_subdevs[] = {
1291 { .compatible = "nvidia,tegra20-dc", },
1292 { .compatible = "nvidia,tegra20-hdmi", },
1293 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001294 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001295 { .compatible = "nvidia,tegra30-dc", },
1296 { .compatible = "nvidia,tegra30-hdmi", },
1297 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001298 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001299 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001300 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001301 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001302 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001303 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001304 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001305 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001306 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001307 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001308 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001309 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001310 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001311 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001312 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001313 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001314 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001315 { .compatible = "nvidia,tegra186-sor", },
1316 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001317 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001318 { /* sentinel */ }
1319};
1320
1321static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001322 .driver = {
1323 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001324 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001325 },
Thierry Reding776dc382013-10-14 14:43:22 +02001326 .probe = host1x_drm_probe,
1327 .remove = host1x_drm_remove,
1328 .subdevs = host1x_drm_subdevs,
1329};
1330
Thierry Reding473112e2015-09-10 16:07:14 +02001331static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001332 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001333 &tegra_dc_driver,
1334 &tegra_hdmi_driver,
1335 &tegra_dsi_driver,
1336 &tegra_dpaux_driver,
1337 &tegra_sor_driver,
1338 &tegra_gr2d_driver,
1339 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001340 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001341};
1342
Thierry Reding776dc382013-10-14 14:43:22 +02001343static int __init host1x_drm_init(void)
1344{
1345 int err;
1346
1347 err = host1x_driver_register(&host1x_drm_driver);
1348 if (err < 0)
1349 return err;
1350
Thierry Reding473112e2015-09-10 16:07:14 +02001351 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001352 if (err < 0)
1353 goto unregister_host1x;
1354
Thierry Reding776dc382013-10-14 14:43:22 +02001355 return 0;
1356
Thierry Reding776dc382013-10-14 14:43:22 +02001357unregister_host1x:
1358 host1x_driver_unregister(&host1x_drm_driver);
1359 return err;
1360}
1361module_init(host1x_drm_init);
1362
1363static void __exit host1x_drm_exit(void)
1364{
Thierry Reding473112e2015-09-10 16:07:14 +02001365 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001366 host1x_driver_unregister(&host1x_drm_driver);
1367}
1368module_exit(host1x_drm_exit);
1369
1370MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1371MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1372MODULE_LICENSE("GPL v2");