blob: 51e20e0150531f7587215b0d78552029e2609b82 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Reding1503ca42014-11-24 17:41:23 +010036static void tegra_atomic_schedule(struct tegra_drm *tegra,
37 struct drm_atomic_state *state)
38{
39 tegra->commit.state = state;
40 schedule_work(&tegra->commit.work);
41}
42
43static void tegra_atomic_complete(struct tegra_drm *tegra,
44 struct drm_atomic_state *state)
45{
46 struct drm_device *drm = tegra->drm;
47
48 /*
49 * Everything below can be run asynchronously without the need to grab
50 * any modeset locks at all under one condition: It must be guaranteed
51 * that the asynchronous work has either been cancelled (if the driver
52 * supports it, which at least requires that the framebuffers get
53 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
54 * before the new state gets committed on the software side with
55 * drm_atomic_helper_swap_state().
56 *
57 * This scheme allows new atomic state updates to be prepared and
58 * checked in parallel to the asynchronous completion of the previous
59 * update. Which is important since compositors need to figure out the
60 * composition of the next frame right after having submitted the
61 * current layout.
62 */
63
Daniel Vetter1af434a2015-02-22 12:24:19 +010064 drm_atomic_helper_commit_modeset_disables(drm, state);
Daniel Vetter1af434a2015-02-22 12:24:19 +010065 drm_atomic_helper_commit_modeset_enables(drm, state);
Liu Ying2b58e982016-08-29 17:12:03 +080066 drm_atomic_helper_commit_planes(drm, state,
67 DRM_PLANE_COMMIT_ACTIVE_ONLY);
Thierry Reding1503ca42014-11-24 17:41:23 +010068
69 drm_atomic_helper_wait_for_vblanks(drm, state);
70
71 drm_atomic_helper_cleanup_planes(drm, state);
Chris Wilson08536952016-10-14 13:18:18 +010072 drm_atomic_state_put(state);
Thierry Reding1503ca42014-11-24 17:41:23 +010073}
74
75static void tegra_atomic_work(struct work_struct *work)
76{
77 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
78 commit.work);
79
80 tegra_atomic_complete(tegra, tegra->commit.state);
81}
82
83static int tegra_atomic_commit(struct drm_device *drm,
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020084 struct drm_atomic_state *state, bool nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +010085{
86 struct tegra_drm *tegra = drm->dev_private;
87 int err;
88
89 err = drm_atomic_helper_prepare_planes(drm, state);
90 if (err)
91 return err;
92
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020093 /* serialize outstanding nonblocking commits */
Thierry Reding1503ca42014-11-24 17:41:23 +010094 mutex_lock(&tegra->commit.lock);
95 flush_work(&tegra->commit.work);
96
97 /*
98 * This is the point of no return - everything below never fails except
99 * when the hw goes bonghits. Which means we can commit the new state on
100 * the software side now.
101 */
102
Daniel Vetter5e84c262016-06-10 00:06:32 +0200103 drm_atomic_helper_swap_state(state, true);
Thierry Reding1503ca42014-11-24 17:41:23 +0100104
Chris Wilson08536952016-10-14 13:18:18 +0100105 drm_atomic_state_get(state);
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +0200106 if (nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +0100107 tegra_atomic_schedule(tegra, state);
108 else
109 tegra_atomic_complete(tegra, state);
110
111 mutex_unlock(&tegra->commit.lock);
112 return 0;
113}
114
Thierry Redingf9914212014-11-26 13:03:57 +0100115static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
116 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +0530117#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +0100118 .output_poll_changed = tegra_fb_output_poll_changed,
119#endif
Thierry Reding07866962014-11-24 17:08:06 +0100120 .atomic_check = drm_atomic_helper_check,
Thierry Reding1503ca42014-11-24 17:41:23 +0100121 .atomic_commit = tegra_atomic_commit,
Thierry Redingf9914212014-11-26 13:03:57 +0100122};
123
Thierry Reding776dc382013-10-14 14:43:22 +0200124static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000125{
Thierry Reding776dc382013-10-14 14:43:22 +0200126 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200127 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000128 int err;
129
Thierry Reding776dc382013-10-14 14:43:22 +0200130 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200131 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200132 return -ENOMEM;
133
Thierry Redingdf06b752014-06-26 21:41:53 +0200134 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200135 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100136 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200137 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100138
Thierry Redingdf06b752014-06-26 21:41:53 +0200139 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300140 if (!tegra->domain) {
141 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200142 goto free;
143 }
144
Thierry Reding4553f732015-01-19 16:15:04 +0100145 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200146 gem_start = geometry->aperture_start;
147 gem_end = geometry->aperture_end - CARVEOUT_SZ;
148 carveout_start = gem_end + 1;
149 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100150
Mikko Perttunenad926012016-12-14 13:16:11 +0200151 order = __ffs(tegra->domain->pgsize_bitmap);
152 init_iova_domain(&tegra->carveout.domain, 1UL << order,
153 carveout_start >> order,
154 carveout_end >> order);
155
156 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
157 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
158
159 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100160 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200161
162 DRM_DEBUG("IOMMU apertures:\n");
163 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
164 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
165 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200166 }
167
Thierry Reding386a2a72013-09-24 13:22:17 +0200168 mutex_init(&tegra->clients_lock);
169 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100170
171 mutex_init(&tegra->commit.lock);
172 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
173
Thierry Reding386a2a72013-09-24 13:22:17 +0200174 drm->dev_private = tegra;
175 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000176
177 drm_mode_config_init(drm);
178
Thierry Redingf9914212014-11-26 13:03:57 +0100179 drm->mode_config.min_width = 0;
180 drm->mode_config.min_height = 0;
181
182 drm->mode_config.max_width = 4096;
183 drm->mode_config.max_height = 4096;
184
Alexandre Courbot5e911442016-11-08 16:50:42 +0900185 drm->mode_config.allow_fb_modifiers = true;
186
Thierry Redingf9914212014-11-26 13:03:57 +0100187 drm->mode_config.funcs = &tegra_drm_mode_funcs;
188
Thierry Redinge2215322014-06-27 17:19:25 +0200189 err = tegra_drm_fb_prepare(drm);
190 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100191 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200192
193 drm_kms_helper_poll_init(drm);
194
Thierry Reding776dc382013-10-14 14:43:22 +0200195 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000196 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100197 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000198
Thierry Reding603f0cc2013-04-22 21:22:14 +0200199 /*
200 * We don't use the drm_irq_install() helpers provided by the DRM
201 * core, so we need to set this manually in order to allow the
202 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
203 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300204 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200205
Thierry Reding42e9ce02015-01-28 14:43:05 +0100206 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100207 drm->max_vblank_count = 0xffffffff;
208
Thierry Reding6e5ff992012-11-28 11:45:47 +0100209 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
210 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100211 goto device;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100212
Thierry Reding31930d42015-07-02 17:04:06 +0200213 drm_mode_config_reset(drm);
214
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000215 err = tegra_drm_fb_init(drm);
216 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100217 goto vblank;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000218
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000219 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100220
221vblank:
222 drm_vblank_cleanup(drm);
223device:
224 host1x_device_exit(device);
225fbdev:
226 drm_kms_helper_poll_fini(drm);
227 tegra_drm_fb_free(drm);
228config:
229 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200230
231 if (tegra->domain) {
232 iommu_domain_free(tegra->domain);
233 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100234 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200235 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200236 }
237free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100238 kfree(tegra);
239 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000240}
241
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200242static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000243{
Thierry Reding776dc382013-10-14 14:43:22 +0200244 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200245 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200246 int err;
247
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000248 drm_kms_helper_poll_fini(drm);
249 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200250 drm_mode_config_cleanup(drm);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100251 drm_vblank_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000252
Thierry Reding776dc382013-10-14 14:43:22 +0200253 err = host1x_device_exit(device);
254 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200255 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200256
Thierry Redingdf06b752014-06-26 21:41:53 +0200257 if (tegra->domain) {
258 iommu_domain_free(tegra->domain);
259 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100260 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200261 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200262 }
263
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100264 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000265}
266
267static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
268{
Thierry Reding08943e62013-09-26 16:08:18 +0200269 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200270
271 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
272 if (!fpriv)
273 return -ENOMEM;
274
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100275 idr_init(&fpriv->contexts);
276 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200277 filp->driver_priv = fpriv;
278
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000279 return 0;
280}
281
Thierry Redingc88c3632013-09-26 16:08:22 +0200282static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200283{
284 context->client->ops->close_channel(context);
285 kfree(context);
286}
287
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000288static void tegra_drm_lastclose(struct drm_device *drm)
289{
Archit Tanejab110ef32015-10-27 13:40:59 +0530290#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200291 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000292
Thierry Reding386a2a72013-09-24 13:22:17 +0200293 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100294#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000295}
296
Thierry Redingc40f0f12013-10-10 11:00:33 +0200297static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100298host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200299{
300 struct drm_gem_object *gem;
301 struct tegra_bo *bo;
302
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100303 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200304 if (!gem)
305 return NULL;
306
Daniel Vettera07cdfe2015-11-23 10:32:48 +0100307 drm_gem_object_unreference_unlocked(gem);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200308
309 bo = to_tegra_bo(gem);
310 return &bo->base;
311}
312
Thierry Reding961e3be2014-06-10 10:25:00 +0200313static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
314 struct drm_tegra_reloc __user *src,
315 struct drm_device *drm,
316 struct drm_file *file)
317{
318 u32 cmdbuf, target;
319 int err;
320
321 err = get_user(cmdbuf, &src->cmdbuf.handle);
322 if (err < 0)
323 return err;
324
325 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
326 if (err < 0)
327 return err;
328
329 err = get_user(target, &src->target.handle);
330 if (err < 0)
331 return err;
332
David Ung31f40f82015-01-20 18:37:35 -0800333 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200334 if (err < 0)
335 return err;
336
337 err = get_user(dest->shift, &src->shift);
338 if (err < 0)
339 return err;
340
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100341 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200342 if (!dest->cmdbuf.bo)
343 return -ENOENT;
344
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100345 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200346 if (!dest->target.bo)
347 return -ENOENT;
348
349 return 0;
350}
351
Thierry Redingc40f0f12013-10-10 11:00:33 +0200352int tegra_drm_submit(struct tegra_drm_context *context,
353 struct drm_tegra_submit *args, struct drm_device *drm,
354 struct drm_file *file)
355{
356 unsigned int num_cmdbufs = args->num_cmdbufs;
357 unsigned int num_relocs = args->num_relocs;
358 unsigned int num_waitchks = args->num_waitchks;
359 struct drm_tegra_cmdbuf __user *cmdbufs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100360 (void __user *)(uintptr_t)args->cmdbufs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200361 struct drm_tegra_reloc __user *relocs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100362 (void __user *)(uintptr_t)args->relocs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200363 struct drm_tegra_waitchk __user *waitchks =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100364 (void __user *)(uintptr_t)args->waitchks;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200365 struct drm_tegra_syncpt syncpt;
366 struct host1x_job *job;
367 int err;
368
369 /* We don't yet support other than one syncpt_incr struct per submit */
370 if (args->num_syncpts != 1)
371 return -EINVAL;
372
373 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
374 args->num_relocs, args->num_waitchks);
375 if (!job)
376 return -ENOMEM;
377
378 job->num_relocs = args->num_relocs;
379 job->num_waitchk = args->num_waitchks;
380 job->client = (u32)args->context;
381 job->class = context->client->base.class;
382 job->serialize = true;
383
384 while (num_cmdbufs) {
385 struct drm_tegra_cmdbuf cmdbuf;
386 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300387 struct tegra_bo *obj;
388 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200389
Dan Carpenter9a991602013-11-08 13:07:37 +0300390 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
391 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200392 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300393 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200394
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300395 /*
396 * The maximum number of CDMA gather fetches is 16383, a higher
397 * value means the words count is malformed.
398 */
399 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
400 err = -EINVAL;
401 goto fail;
402 }
403
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100404 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200405 if (!bo) {
406 err = -ENOENT;
407 goto fail;
408 }
409
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300410 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
411 obj = host1x_to_tegra_bo(bo);
412
413 /*
414 * Gather buffer base address must be 4-bytes aligned,
415 * unaligned offset is malformed and cause commands stream
416 * corruption on the buffer address relocation.
417 */
418 if (offset & 3 || offset >= obj->gem.size) {
419 err = -EINVAL;
420 goto fail;
421 }
422
Thierry Redingc40f0f12013-10-10 11:00:33 +0200423 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
424 num_cmdbufs--;
425 cmdbufs++;
426 }
427
Thierry Reding961e3be2014-06-10 10:25:00 +0200428 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200429 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300430 struct host1x_reloc *reloc;
431 struct tegra_bo *obj;
432
Thierry Reding961e3be2014-06-10 10:25:00 +0200433 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
434 &relocs[num_relocs], drm,
435 file);
436 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200437 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300438
439 reloc = &job->relocarray[num_relocs];
440 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
441
442 /*
443 * The unaligned cmdbuf offset will cause an unaligned write
444 * during of the relocations patching, corrupting the commands
445 * stream.
446 */
447 if (reloc->cmdbuf.offset & 3 ||
448 reloc->cmdbuf.offset >= obj->gem.size) {
449 err = -EINVAL;
450 goto fail;
451 }
452
453 obj = host1x_to_tegra_bo(reloc->target.bo);
454
455 if (reloc->target.offset >= obj->gem.size) {
456 err = -EINVAL;
457 goto fail;
458 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200459 }
460
Dan Carpenter9a991602013-11-08 13:07:37 +0300461 if (copy_from_user(job->waitchk, waitchks,
462 sizeof(*waitchks) * num_waitchks)) {
463 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200464 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300465 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200466
Dan Carpenter9a991602013-11-08 13:07:37 +0300467 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
468 sizeof(syncpt))) {
469 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200470 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300471 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200472
473 job->is_addr_reg = context->client->ops->is_addr_reg;
474 job->syncpt_incrs = syncpt.incrs;
475 job->syncpt_id = syncpt.id;
476 job->timeout = 10000;
477
478 if (args->timeout && args->timeout < 10000)
479 job->timeout = args->timeout;
480
481 err = host1x_job_pin(job, context->client->base.dev);
482 if (err)
483 goto fail;
484
485 err = host1x_job_submit(job);
486 if (err)
487 goto fail_submit;
488
489 args->fence = job->syncpt_end;
490
491 host1x_job_put(job);
492 return 0;
493
494fail_submit:
495 host1x_job_unpin(job);
496fail:
497 host1x_job_put(job);
498 return err;
499}
500
501
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200502#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100503static struct tegra_drm_context *
504tegra_drm_file_get_context(struct tegra_drm_file *file, u32 id)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200505{
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100506 struct tegra_drm_context *context;
Thierry Redingc88c3632013-09-26 16:08:22 +0200507
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100508 mutex_lock(&file->lock);
509 context = idr_find(&file->contexts, id);
510 mutex_unlock(&file->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200511
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100512 return context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200513}
514
515static int tegra_gem_create(struct drm_device *drm, void *data,
516 struct drm_file *file)
517{
518 struct drm_tegra_gem_create *args = data;
519 struct tegra_bo *bo;
520
Thierry Reding773af772013-10-04 22:34:01 +0200521 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200522 &args->handle);
523 if (IS_ERR(bo))
524 return PTR_ERR(bo);
525
526 return 0;
527}
528
529static int tegra_gem_mmap(struct drm_device *drm, void *data,
530 struct drm_file *file)
531{
532 struct drm_tegra_gem_mmap *args = data;
533 struct drm_gem_object *gem;
534 struct tegra_bo *bo;
535
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100536 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200537 if (!gem)
538 return -EINVAL;
539
540 bo = to_tegra_bo(gem);
541
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200542 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200543
Daniel Vetter11533302015-11-23 10:32:40 +0100544 drm_gem_object_unreference_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200545
546 return 0;
547}
548
549static int tegra_syncpt_read(struct drm_device *drm, void *data,
550 struct drm_file *file)
551{
Thierry Reding776dc382013-10-14 14:43:22 +0200552 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200553 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200554 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200555
Thierry Reding776dc382013-10-14 14:43:22 +0200556 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200557 if (!sp)
558 return -EINVAL;
559
560 args->value = host1x_syncpt_read_min(sp);
561 return 0;
562}
563
564static int tegra_syncpt_incr(struct drm_device *drm, void *data,
565 struct drm_file *file)
566{
Thierry Reding776dc382013-10-14 14:43:22 +0200567 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200568 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200569 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200570
Thierry Reding776dc382013-10-14 14:43:22 +0200571 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200572 if (!sp)
573 return -EINVAL;
574
Arto Merilainenebae30b2013-05-29 13:26:08 +0300575 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200576}
577
578static int tegra_syncpt_wait(struct drm_device *drm, void *data,
579 struct drm_file *file)
580{
Thierry Reding776dc382013-10-14 14:43:22 +0200581 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200582 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200583 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200584
Thierry Reding776dc382013-10-14 14:43:22 +0200585 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200586 if (!sp)
587 return -EINVAL;
588
589 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
590 &args->value);
591}
592
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100593static int tegra_client_open(struct tegra_drm_file *fpriv,
594 struct tegra_drm_client *client,
595 struct tegra_drm_context *context)
596{
597 int err;
598
599 err = client->ops->open_channel(client, context);
600 if (err < 0)
601 return err;
602
603 err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL);
604 if (err < 0) {
605 client->ops->close_channel(context);
606 return err;
607 }
608
609 context->client = client;
610 context->id = err;
611
612 return 0;
613}
614
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200615static int tegra_open_channel(struct drm_device *drm, void *data,
616 struct drm_file *file)
617{
Thierry Reding08943e62013-09-26 16:08:18 +0200618 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200619 struct tegra_drm *tegra = drm->dev_private;
620 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200621 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200622 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200623 int err = -ENODEV;
624
625 context = kzalloc(sizeof(*context), GFP_KERNEL);
626 if (!context)
627 return -ENOMEM;
628
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100629 mutex_lock(&fpriv->lock);
630
Thierry Reding776dc382013-10-14 14:43:22 +0200631 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200632 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100633 err = tegra_client_open(fpriv, client, context);
634 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200635 break;
636
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100637 args->context = context->id;
638 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200639 }
640
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100641 if (err < 0)
642 kfree(context);
643
644 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200645 return err;
646}
647
648static int tegra_close_channel(struct drm_device *drm, void *data,
649 struct drm_file *file)
650{
Thierry Reding08943e62013-09-26 16:08:18 +0200651 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200652 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200653 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100654 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200655
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100656 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200657
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100658 context = tegra_drm_file_get_context(fpriv, args->context);
659 if (!context) {
660 err = -EINVAL;
661 goto unlock;
662 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200663
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100664 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200665 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200666
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100667unlock:
668 mutex_unlock(&fpriv->lock);
669 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200670}
671
672static int tegra_get_syncpt(struct drm_device *drm, void *data,
673 struct drm_file *file)
674{
Thierry Reding08943e62013-09-26 16:08:18 +0200675 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200676 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200677 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200678 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100679 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200680
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100681 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200682
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100683 context = tegra_drm_file_get_context(fpriv, args->context);
684 if (!context) {
685 err = -ENODEV;
686 goto unlock;
687 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200688
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100689 if (args->index >= context->client->base.num_syncpts) {
690 err = -EINVAL;
691 goto unlock;
692 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200693
Thierry Reding53fa7f72013-09-24 15:35:40 +0200694 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200695 args->id = host1x_syncpt_id(syncpt);
696
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100697unlock:
698 mutex_unlock(&fpriv->lock);
699 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200700}
701
702static int tegra_submit(struct drm_device *drm, void *data,
703 struct drm_file *file)
704{
Thierry Reding08943e62013-09-26 16:08:18 +0200705 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200706 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200707 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100708 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200709
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100710 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200711
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100712 context = tegra_drm_file_get_context(fpriv, args->context);
713 if (!context) {
714 err = -ENODEV;
715 goto unlock;
716 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200717
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100718 err = context->client->ops->submit(context, args, drm, file);
719
720unlock:
721 mutex_unlock(&fpriv->lock);
722 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200723}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300724
725static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
726 struct drm_file *file)
727{
728 struct tegra_drm_file *fpriv = file->driver_priv;
729 struct drm_tegra_get_syncpt_base *args = data;
730 struct tegra_drm_context *context;
731 struct host1x_syncpt_base *base;
732 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100733 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300734
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100735 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300736
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100737 context = tegra_drm_file_get_context(fpriv, args->context);
738 if (!context) {
739 err = -ENODEV;
740 goto unlock;
741 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300742
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100743 if (args->syncpt >= context->client->base.num_syncpts) {
744 err = -EINVAL;
745 goto unlock;
746 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300747
748 syncpt = context->client->base.syncpts[args->syncpt];
749
750 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100751 if (!base) {
752 err = -ENXIO;
753 goto unlock;
754 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300755
756 args->id = host1x_syncpt_base_id(base);
757
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100758unlock:
759 mutex_unlock(&fpriv->lock);
760 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300761}
Thierry Reding7678d712014-06-03 14:56:57 +0200762
763static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
764 struct drm_file *file)
765{
766 struct drm_tegra_gem_set_tiling *args = data;
767 enum tegra_bo_tiling_mode mode;
768 struct drm_gem_object *gem;
769 unsigned long value = 0;
770 struct tegra_bo *bo;
771
772 switch (args->mode) {
773 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
774 mode = TEGRA_BO_TILING_MODE_PITCH;
775
776 if (args->value != 0)
777 return -EINVAL;
778
779 break;
780
781 case DRM_TEGRA_GEM_TILING_MODE_TILED:
782 mode = TEGRA_BO_TILING_MODE_TILED;
783
784 if (args->value != 0)
785 return -EINVAL;
786
787 break;
788
789 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
790 mode = TEGRA_BO_TILING_MODE_BLOCK;
791
792 if (args->value > 5)
793 return -EINVAL;
794
795 value = args->value;
796 break;
797
798 default:
799 return -EINVAL;
800 }
801
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100802 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200803 if (!gem)
804 return -ENOENT;
805
806 bo = to_tegra_bo(gem);
807
808 bo->tiling.mode = mode;
809 bo->tiling.value = value;
810
Daniel Vetter11533302015-11-23 10:32:40 +0100811 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200812
813 return 0;
814}
815
816static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
817 struct drm_file *file)
818{
819 struct drm_tegra_gem_get_tiling *args = data;
820 struct drm_gem_object *gem;
821 struct tegra_bo *bo;
822 int err = 0;
823
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100824 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200825 if (!gem)
826 return -ENOENT;
827
828 bo = to_tegra_bo(gem);
829
830 switch (bo->tiling.mode) {
831 case TEGRA_BO_TILING_MODE_PITCH:
832 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
833 args->value = 0;
834 break;
835
836 case TEGRA_BO_TILING_MODE_TILED:
837 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
838 args->value = 0;
839 break;
840
841 case TEGRA_BO_TILING_MODE_BLOCK:
842 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
843 args->value = bo->tiling.value;
844 break;
845
846 default:
847 err = -EINVAL;
848 break;
849 }
850
Daniel Vetter11533302015-11-23 10:32:40 +0100851 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200852
853 return err;
854}
Thierry Reding7b129082014-06-10 12:04:03 +0200855
856static int tegra_gem_set_flags(struct drm_device *drm, void *data,
857 struct drm_file *file)
858{
859 struct drm_tegra_gem_set_flags *args = data;
860 struct drm_gem_object *gem;
861 struct tegra_bo *bo;
862
863 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
864 return -EINVAL;
865
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100866 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200867 if (!gem)
868 return -ENOENT;
869
870 bo = to_tegra_bo(gem);
871 bo->flags = 0;
872
873 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
874 bo->flags |= TEGRA_BO_BOTTOM_UP;
875
Daniel Vetter11533302015-11-23 10:32:40 +0100876 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200877
878 return 0;
879}
880
881static int tegra_gem_get_flags(struct drm_device *drm, void *data,
882 struct drm_file *file)
883{
884 struct drm_tegra_gem_get_flags *args = data;
885 struct drm_gem_object *gem;
886 struct tegra_bo *bo;
887
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100888 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200889 if (!gem)
890 return -ENOENT;
891
892 bo = to_tegra_bo(gem);
893 args->flags = 0;
894
895 if (bo->flags & TEGRA_BO_BOTTOM_UP)
896 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
897
Daniel Vetter11533302015-11-23 10:32:40 +0100898 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200899
900 return 0;
901}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200902#endif
903
Rob Clarkbaa70942013-08-02 13:27:49 -0400904static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200905#ifdef CONFIG_DRM_TEGRA_STAGING
Daniel Vetterf8c47142015-09-08 13:56:30 +0200906 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
907 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
908 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
909 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
910 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
911 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
912 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
913 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
914 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
915 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
916 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
917 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
918 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
919 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200920#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000921};
922
923static const struct file_operations tegra_drm_fops = {
924 .owner = THIS_MODULE,
925 .open = drm_open,
926 .release = drm_release,
927 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200928 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000929 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000930 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000931 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000932 .llseek = noop_llseek,
933};
934
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100935static int tegra_drm_context_cleanup(int id, void *p, void *data)
936{
937 struct tegra_drm_context *context = p;
938
939 tegra_drm_context_free(context);
940
941 return 0;
942}
943
Thierry Reding3c03c462012-11-28 12:00:18 +0100944static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file)
945{
Thierry Reding08943e62013-09-26 16:08:18 +0200946 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100947
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100948 mutex_lock(&fpriv->lock);
949 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
950 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200951
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100952 idr_destroy(&fpriv->contexts);
953 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200954 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100955}
956
Thierry Redinge450fcc2013-02-13 16:13:16 +0100957#ifdef CONFIG_DEBUG_FS
958static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
959{
960 struct drm_info_node *node = (struct drm_info_node *)s->private;
961 struct drm_device *drm = node->minor->dev;
962 struct drm_framebuffer *fb;
963
964 mutex_lock(&drm->mode_config.fb_lock);
965
966 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
967 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200968 fb->base.id, fb->width, fb->height,
969 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200970 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000971 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100972 }
973
974 mutex_unlock(&drm->mode_config.fb_lock);
975
976 return 0;
977}
978
Thierry Reding28c23372015-01-23 09:16:03 +0100979static int tegra_debugfs_iova(struct seq_file *s, void *data)
980{
981 struct drm_info_node *node = (struct drm_info_node *)s->private;
982 struct drm_device *drm = node->minor->dev;
983 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100984 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100985
Thierry Reding347ad49d2017-03-09 20:04:56 +0100986 mutex_lock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +0100987 drm_mm_print(&tegra->mm, &p);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100988 mutex_unlock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +0100989
990 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100991}
992
Thierry Redinge450fcc2013-02-13 16:13:16 +0100993static struct drm_info_list tegra_debugfs_list[] = {
994 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +0100995 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +0100996};
997
998static int tegra_debugfs_init(struct drm_minor *minor)
999{
1000 return drm_debugfs_create_files(tegra_debugfs_list,
1001 ARRAY_SIZE(tegra_debugfs_list),
1002 minor->debugfs_root, minor);
1003}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001004#endif
1005
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001006static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001007 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
1008 DRIVER_ATOMIC,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001009 .load = tegra_drm_load,
1010 .unload = tegra_drm_unload,
1011 .open = tegra_drm_open,
Thierry Reding3c03c462012-11-28 12:00:18 +01001012 .preclose = tegra_drm_preclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001013 .lastclose = tegra_drm_lastclose,
1014
Thierry Redinge450fcc2013-02-13 16:13:16 +01001015#if defined(CONFIG_DEBUG_FS)
1016 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001017#endif
1018
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001019 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001020 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001021
1022 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1023 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1024 .gem_prime_export = tegra_gem_prime_export,
1025 .gem_prime_import = tegra_gem_prime_import,
1026
Arto Merilainende2ba662013-03-22 16:34:08 +02001027 .dumb_create = tegra_bo_dumb_create,
1028 .dumb_map_offset = tegra_bo_dumb_map_offset,
Daniel Vetter43387b32013-07-16 09:12:04 +02001029 .dumb_destroy = drm_gem_dumb_destroy,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001030
1031 .ioctls = tegra_drm_ioctls,
1032 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1033 .fops = &tegra_drm_fops,
1034
1035 .name = DRIVER_NAME,
1036 .desc = DRIVER_DESC,
1037 .date = DRIVER_DATE,
1038 .major = DRIVER_MAJOR,
1039 .minor = DRIVER_MINOR,
1040 .patchlevel = DRIVER_PATCHLEVEL,
1041};
Thierry Reding776dc382013-10-14 14:43:22 +02001042
1043int tegra_drm_register_client(struct tegra_drm *tegra,
1044 struct tegra_drm_client *client)
1045{
1046 mutex_lock(&tegra->clients_lock);
1047 list_add_tail(&client->list, &tegra->clients);
1048 mutex_unlock(&tegra->clients_lock);
1049
1050 return 0;
1051}
1052
1053int tegra_drm_unregister_client(struct tegra_drm *tegra,
1054 struct tegra_drm_client *client)
1055{
1056 mutex_lock(&tegra->clients_lock);
1057 list_del_init(&client->list);
1058 mutex_unlock(&tegra->clients_lock);
1059
1060 return 0;
1061}
1062
Mikko Perttunenad926012016-12-14 13:16:11 +02001063void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
1064 dma_addr_t *dma)
1065{
1066 struct iova *alloc;
1067 void *virt;
1068 gfp_t gfp;
1069 int err;
1070
1071 if (tegra->domain)
1072 size = iova_align(&tegra->carveout.domain, size);
1073 else
1074 size = PAGE_ALIGN(size);
1075
1076 gfp = GFP_KERNEL | __GFP_ZERO;
1077 if (!tegra->domain) {
1078 /*
1079 * Many units only support 32-bit addresses, even on 64-bit
1080 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1081 * virtual address space, force allocations to be in the
1082 * lower 32-bit range.
1083 */
1084 gfp |= GFP_DMA;
1085 }
1086
1087 virt = (void *)__get_free_pages(gfp, get_order(size));
1088 if (!virt)
1089 return ERR_PTR(-ENOMEM);
1090
1091 if (!tegra->domain) {
1092 /*
1093 * If IOMMU is disabled, devices address physical memory
1094 * directly.
1095 */
1096 *dma = virt_to_phys(virt);
1097 return virt;
1098 }
1099
1100 alloc = alloc_iova(&tegra->carveout.domain,
1101 size >> tegra->carveout.shift,
1102 tegra->carveout.limit, true);
1103 if (!alloc) {
1104 err = -EBUSY;
1105 goto free_pages;
1106 }
1107
1108 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1109 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1110 size, IOMMU_READ | IOMMU_WRITE);
1111 if (err < 0)
1112 goto free_iova;
1113
1114 return virt;
1115
1116free_iova:
1117 __free_iova(&tegra->carveout.domain, alloc);
1118free_pages:
1119 free_pages((unsigned long)virt, get_order(size));
1120
1121 return ERR_PTR(err);
1122}
1123
1124void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1125 dma_addr_t dma)
1126{
1127 if (tegra->domain)
1128 size = iova_align(&tegra->carveout.domain, size);
1129 else
1130 size = PAGE_ALIGN(size);
1131
1132 if (tegra->domain) {
1133 iommu_unmap(tegra->domain, dma, size);
1134 free_iova(&tegra->carveout.domain,
1135 iova_pfn(&tegra->carveout.domain, dma));
1136 }
1137
1138 free_pages((unsigned long)virt, get_order(size));
1139}
1140
Thierry Reding9910f5c2014-05-22 09:57:15 +02001141static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001142{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001143 struct drm_driver *driver = &tegra_drm_driver;
1144 struct drm_device *drm;
1145 int err;
1146
1147 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001148 if (IS_ERR(drm))
1149 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001150
Thierry Reding9910f5c2014-05-22 09:57:15 +02001151 dev_set_drvdata(&dev->dev, drm);
1152
1153 err = drm_dev_register(drm, 0);
1154 if (err < 0)
1155 goto unref;
1156
Thierry Reding9910f5c2014-05-22 09:57:15 +02001157 return 0;
1158
1159unref:
1160 drm_dev_unref(drm);
1161 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001162}
1163
Thierry Reding9910f5c2014-05-22 09:57:15 +02001164static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001165{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001166 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1167
1168 drm_dev_unregister(drm);
1169 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001170
1171 return 0;
1172}
1173
Thierry Reding359ae682014-12-18 17:15:25 +01001174#ifdef CONFIG_PM_SLEEP
1175static int host1x_drm_suspend(struct device *dev)
1176{
1177 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001178 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001179
1180 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001181 tegra_drm_fb_suspend(drm);
1182
1183 tegra->state = drm_atomic_helper_suspend(drm);
1184 if (IS_ERR(tegra->state)) {
1185 tegra_drm_fb_resume(drm);
1186 drm_kms_helper_poll_enable(drm);
1187 return PTR_ERR(tegra->state);
1188 }
Thierry Reding359ae682014-12-18 17:15:25 +01001189
1190 return 0;
1191}
1192
1193static int host1x_drm_resume(struct device *dev)
1194{
1195 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001196 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001197
Thierry Reding986c58d2015-08-11 13:11:49 +02001198 drm_atomic_helper_resume(drm, tegra->state);
1199 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001200 drm_kms_helper_poll_enable(drm);
1201
1202 return 0;
1203}
1204#endif
1205
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001206static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1207 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001208
Thierry Reding776dc382013-10-14 14:43:22 +02001209static const struct of_device_id host1x_drm_subdevs[] = {
1210 { .compatible = "nvidia,tegra20-dc", },
1211 { .compatible = "nvidia,tegra20-hdmi", },
1212 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001213 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001214 { .compatible = "nvidia,tegra30-dc", },
1215 { .compatible = "nvidia,tegra30-hdmi", },
1216 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001217 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001218 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001219 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001220 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001221 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001222 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001223 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001224 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001225 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001226 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001227 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001228 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001229 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001230 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001231 { .compatible = "nvidia,tegra210-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001232 { /* sentinel */ }
1233};
1234
1235static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001236 .driver = {
1237 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001238 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001239 },
Thierry Reding776dc382013-10-14 14:43:22 +02001240 .probe = host1x_drm_probe,
1241 .remove = host1x_drm_remove,
1242 .subdevs = host1x_drm_subdevs,
1243};
1244
Thierry Reding473112e2015-09-10 16:07:14 +02001245static struct platform_driver * const drivers[] = {
1246 &tegra_dc_driver,
1247 &tegra_hdmi_driver,
1248 &tegra_dsi_driver,
1249 &tegra_dpaux_driver,
1250 &tegra_sor_driver,
1251 &tegra_gr2d_driver,
1252 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001253 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001254};
1255
Thierry Reding776dc382013-10-14 14:43:22 +02001256static int __init host1x_drm_init(void)
1257{
1258 int err;
1259
1260 err = host1x_driver_register(&host1x_drm_driver);
1261 if (err < 0)
1262 return err;
1263
Thierry Reding473112e2015-09-10 16:07:14 +02001264 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001265 if (err < 0)
1266 goto unregister_host1x;
1267
Thierry Reding776dc382013-10-14 14:43:22 +02001268 return 0;
1269
Thierry Reding776dc382013-10-14 14:43:22 +02001270unregister_host1x:
1271 host1x_driver_unregister(&host1x_drm_driver);
1272 return err;
1273}
1274module_init(host1x_drm_init);
1275
1276static void __exit host1x_drm_exit(void)
1277{
Thierry Reding473112e2015-09-10 16:07:14 +02001278 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001279 host1x_driver_unregister(&host1x_drm_driver);
1280}
1281module_exit(host1x_drm_exit);
1282
1283MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1284MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1285MODULE_LICENSE("GPL v2");