Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 3 | * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 10 | #include <linux/bitops.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 11 | #include <linux/host1x.h> |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 12 | #include <linux/idr.h> |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 13 | #include <linux/iommu.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 14 | |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 15 | #include <drm/drm_atomic.h> |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 16 | #include <drm/drm_atomic_helper.h> |
| 17 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 18 | #include "drm.h" |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 19 | #include "gem.h" |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 20 | |
| 21 | #define DRIVER_NAME "tegra" |
| 22 | #define DRIVER_DESC "NVIDIA Tegra graphics" |
| 23 | #define DRIVER_DATE "20120330" |
| 24 | #define DRIVER_MAJOR 0 |
| 25 | #define DRIVER_MINOR 0 |
| 26 | #define DRIVER_PATCHLEVEL 0 |
| 27 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 28 | #define CARVEOUT_SZ SZ_64M |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 29 | #define CDMA_GATHER_FETCHES_MAX_NB 16383 |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 30 | |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 31 | struct tegra_drm_file { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 32 | struct idr contexts; |
| 33 | struct mutex lock; |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 34 | }; |
| 35 | |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 36 | static int tegra_atomic_check(struct drm_device *drm, |
| 37 | struct drm_atomic_state *state) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 38 | { |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 39 | int err; |
| 40 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame^] | 41 | err = drm_atomic_helper_check(drm, state); |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 42 | if (err < 0) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 43 | return err; |
| 44 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame^] | 45 | return tegra_display_hub_atomic_check(drm, state); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 46 | } |
| 47 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 48 | static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 49 | .fb_create = tegra_fb_create, |
Archit Taneja | b110ef3 | 2015-10-27 13:40:59 +0530 | [diff] [blame] | 50 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Noralf Trønnes | c94beda | 2017-12-05 19:25:04 +0100 | [diff] [blame] | 51 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 52 | #endif |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 53 | .atomic_check = tegra_atomic_check, |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 54 | .atomic_commit = drm_atomic_helper_commit, |
| 55 | }; |
| 56 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 57 | static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) |
| 58 | { |
| 59 | struct drm_device *drm = old_state->dev; |
| 60 | struct tegra_drm *tegra = drm->dev_private; |
| 61 | |
| 62 | if (tegra->hub) { |
| 63 | drm_atomic_helper_commit_modeset_disables(drm, old_state); |
| 64 | tegra_display_hub_atomic_commit(drm, old_state); |
| 65 | drm_atomic_helper_commit_planes(drm, old_state, 0); |
| 66 | drm_atomic_helper_commit_modeset_enables(drm, old_state); |
| 67 | drm_atomic_helper_commit_hw_done(old_state); |
| 68 | drm_atomic_helper_wait_for_vblanks(drm, old_state); |
| 69 | drm_atomic_helper_cleanup_planes(drm, old_state); |
| 70 | } else { |
| 71 | drm_atomic_helper_commit_tail_rpm(old_state); |
| 72 | } |
| 73 | } |
| 74 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 75 | static const struct drm_mode_config_helper_funcs |
| 76 | tegra_drm_mode_config_helpers = { |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 77 | .atomic_commit_tail = tegra_atomic_commit_tail, |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 78 | }; |
| 79 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 80 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 81 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 82 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 83 | struct tegra_drm *tegra; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 84 | int err; |
| 85 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 86 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 87 | if (!tegra) |
Terje Bergstrom | 692e6d7 | 2013-03-22 16:34:07 +0200 | [diff] [blame] | 88 | return -ENOMEM; |
| 89 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 90 | if (iommu_present(&platform_bus_type)) { |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 91 | u64 carveout_start, carveout_end, gem_start, gem_end; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 92 | struct iommu_domain_geometry *geometry; |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 93 | unsigned long order; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 94 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 95 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
Dan Carpenter | bf19b88 | 2014-12-04 14:00:35 +0300 | [diff] [blame] | 96 | if (!tegra->domain) { |
| 97 | err = -ENOMEM; |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 98 | goto free; |
| 99 | } |
| 100 | |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 101 | geometry = &tegra->domain->geometry; |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 102 | gem_start = geometry->aperture_start; |
| 103 | gem_end = geometry->aperture_end - CARVEOUT_SZ; |
| 104 | carveout_start = gem_end + 1; |
| 105 | carveout_end = geometry->aperture_end; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 106 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 107 | order = __ffs(tegra->domain->pgsize_bitmap); |
| 108 | init_iova_domain(&tegra->carveout.domain, 1UL << order, |
Zhen Lei | aa3ac94 | 2017-09-21 16:52:45 +0100 | [diff] [blame] | 109 | carveout_start >> order); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 110 | |
| 111 | tegra->carveout.shift = iova_shift(&tegra->carveout.domain); |
| 112 | tegra->carveout.limit = carveout_end >> tegra->carveout.shift; |
| 113 | |
| 114 | drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 115 | mutex_init(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 116 | |
| 117 | DRM_DEBUG("IOMMU apertures:\n"); |
| 118 | DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end); |
| 119 | DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start, |
| 120 | carveout_end); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 121 | } |
| 122 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 123 | mutex_init(&tegra->clients_lock); |
| 124 | INIT_LIST_HEAD(&tegra->clients); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 125 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 126 | drm->dev_private = tegra; |
| 127 | tegra->drm = drm; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 128 | |
| 129 | drm_mode_config_init(drm); |
| 130 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 131 | drm->mode_config.min_width = 0; |
| 132 | drm->mode_config.min_height = 0; |
| 133 | |
| 134 | drm->mode_config.max_width = 4096; |
| 135 | drm->mode_config.max_height = 4096; |
| 136 | |
Alexandre Courbot | 5e91144 | 2016-11-08 16:50:42 +0900 | [diff] [blame] | 137 | drm->mode_config.allow_fb_modifiers = true; |
| 138 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame^] | 139 | drm->mode_config.normalize_zpos = true; |
| 140 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 141 | drm->mode_config.funcs = &tegra_drm_mode_config_funcs; |
| 142 | drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 143 | |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 144 | err = tegra_drm_fb_prepare(drm); |
| 145 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 146 | goto config; |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 147 | |
| 148 | drm_kms_helper_poll_init(drm); |
| 149 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 150 | err = host1x_device_init(device); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 151 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 152 | goto fbdev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 153 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 154 | if (tegra->hub) { |
| 155 | err = tegra_display_hub_prepare(tegra->hub); |
| 156 | if (err < 0) |
| 157 | goto device; |
| 158 | } |
| 159 | |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 160 | /* |
| 161 | * We don't use the drm_irq_install() helpers provided by the DRM |
| 162 | * core, so we need to set this manually in order to allow the |
| 163 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. |
| 164 | */ |
Ville Syrjälä | 4423843 | 2013-10-04 14:53:37 +0300 | [diff] [blame] | 165 | drm->irq_enabled = true; |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 166 | |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 167 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 168 | drm->max_vblank_count = 0xffffffff; |
| 169 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 170 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
| 171 | if (err < 0) |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 172 | goto hub; |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 173 | |
Thierry Reding | 31930d4 | 2015-07-02 17:04:06 +0200 | [diff] [blame] | 174 | drm_mode_config_reset(drm); |
| 175 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 176 | err = tegra_drm_fb_init(drm); |
| 177 | if (err < 0) |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 178 | goto hub; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 179 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 180 | return 0; |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 181 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 182 | hub: |
| 183 | if (tegra->hub) |
| 184 | tegra_display_hub_cleanup(tegra->hub); |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 185 | device: |
| 186 | host1x_device_exit(device); |
| 187 | fbdev: |
| 188 | drm_kms_helper_poll_fini(drm); |
| 189 | tegra_drm_fb_free(drm); |
| 190 | config: |
| 191 | drm_mode_config_cleanup(drm); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 192 | |
| 193 | if (tegra->domain) { |
| 194 | iommu_domain_free(tegra->domain); |
| 195 | drm_mm_takedown(&tegra->mm); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 196 | mutex_destroy(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 197 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 198 | } |
| 199 | free: |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 200 | kfree(tegra); |
| 201 | return err; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 202 | } |
| 203 | |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 204 | static void tegra_drm_unload(struct drm_device *drm) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 205 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 206 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 207 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 208 | int err; |
| 209 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 210 | drm_kms_helper_poll_fini(drm); |
| 211 | tegra_drm_fb_exit(drm); |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 212 | drm_mode_config_cleanup(drm); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 213 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 214 | err = host1x_device_exit(device); |
| 215 | if (err < 0) |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 216 | return; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 217 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 218 | if (tegra->domain) { |
| 219 | iommu_domain_free(tegra->domain); |
| 220 | drm_mm_takedown(&tegra->mm); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 221 | mutex_destroy(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 222 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 223 | } |
| 224 | |
Thierry Reding | 1053f4dd | 2014-11-04 16:17:55 +0100 | [diff] [blame] | 225 | kfree(tegra); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) |
| 229 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 230 | struct tegra_drm_file *fpriv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 231 | |
| 232 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 233 | if (!fpriv) |
| 234 | return -ENOMEM; |
| 235 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 236 | idr_init(&fpriv->contexts); |
| 237 | mutex_init(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 238 | filp->driver_priv = fpriv; |
| 239 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 240 | return 0; |
| 241 | } |
| 242 | |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 243 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 244 | { |
| 245 | context->client->ops->close_channel(context); |
| 246 | kfree(context); |
| 247 | } |
| 248 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 249 | static struct host1x_bo * |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 250 | host1x_bo_lookup(struct drm_file *file, u32 handle) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 251 | { |
| 252 | struct drm_gem_object *gem; |
| 253 | struct tegra_bo *bo; |
| 254 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 255 | gem = drm_gem_object_lookup(file, handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 256 | if (!gem) |
| 257 | return NULL; |
| 258 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 259 | bo = to_tegra_bo(gem); |
| 260 | return &bo->base; |
| 261 | } |
| 262 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 263 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
| 264 | struct drm_tegra_reloc __user *src, |
| 265 | struct drm_device *drm, |
| 266 | struct drm_file *file) |
| 267 | { |
| 268 | u32 cmdbuf, target; |
| 269 | int err; |
| 270 | |
| 271 | err = get_user(cmdbuf, &src->cmdbuf.handle); |
| 272 | if (err < 0) |
| 273 | return err; |
| 274 | |
| 275 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); |
| 276 | if (err < 0) |
| 277 | return err; |
| 278 | |
| 279 | err = get_user(target, &src->target.handle); |
| 280 | if (err < 0) |
| 281 | return err; |
| 282 | |
David Ung | 31f40f8 | 2015-01-20 18:37:35 -0800 | [diff] [blame] | 283 | err = get_user(dest->target.offset, &src->target.offset); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 284 | if (err < 0) |
| 285 | return err; |
| 286 | |
| 287 | err = get_user(dest->shift, &src->shift); |
| 288 | if (err < 0) |
| 289 | return err; |
| 290 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 291 | dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 292 | if (!dest->cmdbuf.bo) |
| 293 | return -ENOENT; |
| 294 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 295 | dest->target.bo = host1x_bo_lookup(file, target); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 296 | if (!dest->target.bo) |
| 297 | return -ENOENT; |
| 298 | |
| 299 | return 0; |
| 300 | } |
| 301 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 302 | static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest, |
| 303 | struct drm_tegra_waitchk __user *src, |
| 304 | struct drm_file *file) |
| 305 | { |
| 306 | u32 cmdbuf; |
| 307 | int err; |
| 308 | |
| 309 | err = get_user(cmdbuf, &src->handle); |
| 310 | if (err < 0) |
| 311 | return err; |
| 312 | |
| 313 | err = get_user(dest->offset, &src->offset); |
| 314 | if (err < 0) |
| 315 | return err; |
| 316 | |
| 317 | err = get_user(dest->syncpt_id, &src->syncpt); |
| 318 | if (err < 0) |
| 319 | return err; |
| 320 | |
| 321 | err = get_user(dest->thresh, &src->thresh); |
| 322 | if (err < 0) |
| 323 | return err; |
| 324 | |
| 325 | dest->bo = host1x_bo_lookup(file, cmdbuf); |
| 326 | if (!dest->bo) |
| 327 | return -ENOENT; |
| 328 | |
| 329 | return 0; |
| 330 | } |
| 331 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 332 | int tegra_drm_submit(struct tegra_drm_context *context, |
| 333 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 334 | struct drm_file *file) |
| 335 | { |
| 336 | unsigned int num_cmdbufs = args->num_cmdbufs; |
| 337 | unsigned int num_relocs = args->num_relocs; |
| 338 | unsigned int num_waitchks = args->num_waitchks; |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 339 | struct drm_tegra_cmdbuf __user *user_cmdbufs; |
| 340 | struct drm_tegra_reloc __user *user_relocs; |
| 341 | struct drm_tegra_waitchk __user *user_waitchks; |
| 342 | struct drm_tegra_syncpt __user *user_syncpt; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 343 | struct drm_tegra_syncpt syncpt; |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 344 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 345 | struct drm_gem_object **refs; |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 346 | struct host1x_syncpt *sp; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 347 | struct host1x_job *job; |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 348 | unsigned int num_refs; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 349 | int err; |
| 350 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 351 | user_cmdbufs = u64_to_user_ptr(args->cmdbufs); |
| 352 | user_relocs = u64_to_user_ptr(args->relocs); |
| 353 | user_waitchks = u64_to_user_ptr(args->waitchks); |
| 354 | user_syncpt = u64_to_user_ptr(args->syncpts); |
| 355 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 356 | /* We don't yet support other than one syncpt_incr struct per submit */ |
| 357 | if (args->num_syncpts != 1) |
| 358 | return -EINVAL; |
| 359 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 360 | /* We don't yet support waitchks */ |
| 361 | if (args->num_waitchks != 0) |
| 362 | return -EINVAL; |
| 363 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 364 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, |
| 365 | args->num_relocs, args->num_waitchks); |
| 366 | if (!job) |
| 367 | return -ENOMEM; |
| 368 | |
| 369 | job->num_relocs = args->num_relocs; |
| 370 | job->num_waitchk = args->num_waitchks; |
| 371 | job->client = (u32)args->context; |
| 372 | job->class = context->client->base.class; |
| 373 | job->serialize = true; |
| 374 | |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 375 | /* |
| 376 | * Track referenced BOs so that they can be unreferenced after the |
| 377 | * submission is complete. |
| 378 | */ |
| 379 | num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks; |
| 380 | |
| 381 | refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL); |
| 382 | if (!refs) { |
| 383 | err = -ENOMEM; |
| 384 | goto put; |
| 385 | } |
| 386 | |
| 387 | /* reuse as an iterator later */ |
| 388 | num_refs = 0; |
| 389 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 390 | while (num_cmdbufs) { |
| 391 | struct drm_tegra_cmdbuf cmdbuf; |
| 392 | struct host1x_bo *bo; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 393 | struct tegra_bo *obj; |
| 394 | u64 offset; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 395 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 396 | if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) { |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 397 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 398 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 399 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 400 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 401 | /* |
| 402 | * The maximum number of CDMA gather fetches is 16383, a higher |
| 403 | * value means the words count is malformed. |
| 404 | */ |
| 405 | if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { |
| 406 | err = -EINVAL; |
| 407 | goto fail; |
| 408 | } |
| 409 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 410 | bo = host1x_bo_lookup(file, cmdbuf.handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 411 | if (!bo) { |
| 412 | err = -ENOENT; |
| 413 | goto fail; |
| 414 | } |
| 415 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 416 | offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); |
| 417 | obj = host1x_to_tegra_bo(bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 418 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 419 | |
| 420 | /* |
| 421 | * Gather buffer base address must be 4-bytes aligned, |
| 422 | * unaligned offset is malformed and cause commands stream |
| 423 | * corruption on the buffer address relocation. |
| 424 | */ |
| 425 | if (offset & 3 || offset >= obj->gem.size) { |
| 426 | err = -EINVAL; |
| 427 | goto fail; |
| 428 | } |
| 429 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 430 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); |
| 431 | num_cmdbufs--; |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 432 | user_cmdbufs++; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 433 | } |
| 434 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 435 | /* copy and resolve relocations from submit */ |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 436 | while (num_relocs--) { |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 437 | struct host1x_reloc *reloc; |
| 438 | struct tegra_bo *obj; |
| 439 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 440 | err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 441 | &user_relocs[num_relocs], drm, |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 442 | file); |
| 443 | if (err < 0) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 444 | goto fail; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 445 | |
| 446 | reloc = &job->relocarray[num_relocs]; |
| 447 | obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 448 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 449 | |
| 450 | /* |
| 451 | * The unaligned cmdbuf offset will cause an unaligned write |
| 452 | * during of the relocations patching, corrupting the commands |
| 453 | * stream. |
| 454 | */ |
| 455 | if (reloc->cmdbuf.offset & 3 || |
| 456 | reloc->cmdbuf.offset >= obj->gem.size) { |
| 457 | err = -EINVAL; |
| 458 | goto fail; |
| 459 | } |
| 460 | |
| 461 | obj = host1x_to_tegra_bo(reloc->target.bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 462 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 463 | |
| 464 | if (reloc->target.offset >= obj->gem.size) { |
| 465 | err = -EINVAL; |
| 466 | goto fail; |
| 467 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 468 | } |
| 469 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 470 | /* copy and resolve waitchks from submit */ |
| 471 | while (num_waitchks--) { |
| 472 | struct host1x_waitchk *wait = &job->waitchk[num_waitchks]; |
| 473 | struct tegra_bo *obj; |
| 474 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 475 | err = host1x_waitchk_copy_from_user( |
| 476 | wait, &user_waitchks[num_waitchks], file); |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 477 | if (err < 0) |
| 478 | goto fail; |
| 479 | |
| 480 | obj = host1x_to_tegra_bo(wait->bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 481 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 482 | |
| 483 | /* |
| 484 | * The unaligned offset will cause an unaligned write during |
| 485 | * of the waitchks patching, corrupting the commands stream. |
| 486 | */ |
| 487 | if (wait->offset & 3 || |
| 488 | wait->offset >= obj->gem.size) { |
| 489 | err = -EINVAL; |
| 490 | goto fail; |
| 491 | } |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 492 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 493 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 494 | if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) { |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 495 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 496 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 497 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 498 | |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 499 | /* check whether syncpoint ID is valid */ |
| 500 | sp = host1x_syncpt_get(host1x, syncpt.id); |
| 501 | if (!sp) { |
| 502 | err = -ENOENT; |
| 503 | goto fail; |
| 504 | } |
| 505 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 506 | job->is_addr_reg = context->client->ops->is_addr_reg; |
Dmitry Osipenko | 0f563a4 | 2017-06-15 02:18:37 +0300 | [diff] [blame] | 507 | job->is_valid_class = context->client->ops->is_valid_class; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 508 | job->syncpt_incrs = syncpt.incrs; |
| 509 | job->syncpt_id = syncpt.id; |
| 510 | job->timeout = 10000; |
| 511 | |
| 512 | if (args->timeout && args->timeout < 10000) |
| 513 | job->timeout = args->timeout; |
| 514 | |
| 515 | err = host1x_job_pin(job, context->client->base.dev); |
| 516 | if (err) |
| 517 | goto fail; |
| 518 | |
| 519 | err = host1x_job_submit(job); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 520 | if (err) { |
| 521 | host1x_job_unpin(job); |
| 522 | goto fail; |
| 523 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 524 | |
| 525 | args->fence = job->syncpt_end; |
| 526 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 527 | fail: |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 528 | while (num_refs--) |
| 529 | drm_gem_object_put_unlocked(refs[num_refs]); |
| 530 | |
| 531 | kfree(refs); |
| 532 | |
| 533 | put: |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 534 | host1x_job_put(job); |
| 535 | return err; |
| 536 | } |
| 537 | |
| 538 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 539 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 540 | static int tegra_gem_create(struct drm_device *drm, void *data, |
| 541 | struct drm_file *file) |
| 542 | { |
| 543 | struct drm_tegra_gem_create *args = data; |
| 544 | struct tegra_bo *bo; |
| 545 | |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 546 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 547 | &args->handle); |
| 548 | if (IS_ERR(bo)) |
| 549 | return PTR_ERR(bo); |
| 550 | |
| 551 | return 0; |
| 552 | } |
| 553 | |
| 554 | static int tegra_gem_mmap(struct drm_device *drm, void *data, |
| 555 | struct drm_file *file) |
| 556 | { |
| 557 | struct drm_tegra_gem_mmap *args = data; |
| 558 | struct drm_gem_object *gem; |
| 559 | struct tegra_bo *bo; |
| 560 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 561 | gem = drm_gem_object_lookup(file, args->handle); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 562 | if (!gem) |
| 563 | return -EINVAL; |
| 564 | |
| 565 | bo = to_tegra_bo(gem); |
| 566 | |
David Herrmann | 2bc7b0c | 2013-08-13 14:19:58 +0200 | [diff] [blame] | 567 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 568 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 569 | drm_gem_object_put_unlocked(gem); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 570 | |
| 571 | return 0; |
| 572 | } |
| 573 | |
| 574 | static int tegra_syncpt_read(struct drm_device *drm, void *data, |
| 575 | struct drm_file *file) |
| 576 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 577 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 578 | struct drm_tegra_syncpt_read *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 579 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 580 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 581 | sp = host1x_syncpt_get(host, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 582 | if (!sp) |
| 583 | return -EINVAL; |
| 584 | |
| 585 | args->value = host1x_syncpt_read_min(sp); |
| 586 | return 0; |
| 587 | } |
| 588 | |
| 589 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, |
| 590 | struct drm_file *file) |
| 591 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 592 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 593 | struct drm_tegra_syncpt_incr *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 594 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 595 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 596 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 597 | if (!sp) |
| 598 | return -EINVAL; |
| 599 | |
Arto Merilainen | ebae30b | 2013-05-29 13:26:08 +0300 | [diff] [blame] | 600 | return host1x_syncpt_incr(sp); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 601 | } |
| 602 | |
| 603 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, |
| 604 | struct drm_file *file) |
| 605 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 606 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 607 | struct drm_tegra_syncpt_wait *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 608 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 609 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 610 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 611 | if (!sp) |
| 612 | return -EINVAL; |
| 613 | |
Dmitry Osipenko | 4c69ac12 | 2017-12-20 18:46:14 +0300 | [diff] [blame] | 614 | return host1x_syncpt_wait(sp, args->thresh, |
| 615 | msecs_to_jiffies(args->timeout), |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 616 | &args->value); |
| 617 | } |
| 618 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 619 | static int tegra_client_open(struct tegra_drm_file *fpriv, |
| 620 | struct tegra_drm_client *client, |
| 621 | struct tegra_drm_context *context) |
| 622 | { |
| 623 | int err; |
| 624 | |
| 625 | err = client->ops->open_channel(client, context); |
| 626 | if (err < 0) |
| 627 | return err; |
| 628 | |
Dmitry Osipenko | d6c153e | 2017-06-15 02:18:25 +0300 | [diff] [blame] | 629 | err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 630 | if (err < 0) { |
| 631 | client->ops->close_channel(context); |
| 632 | return err; |
| 633 | } |
| 634 | |
| 635 | context->client = client; |
| 636 | context->id = err; |
| 637 | |
| 638 | return 0; |
| 639 | } |
| 640 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 641 | static int tegra_open_channel(struct drm_device *drm, void *data, |
| 642 | struct drm_file *file) |
| 643 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 644 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 645 | struct tegra_drm *tegra = drm->dev_private; |
| 646 | struct drm_tegra_open_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 647 | struct tegra_drm_context *context; |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 648 | struct tegra_drm_client *client; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 649 | int err = -ENODEV; |
| 650 | |
| 651 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
| 652 | if (!context) |
| 653 | return -ENOMEM; |
| 654 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 655 | mutex_lock(&fpriv->lock); |
| 656 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 657 | list_for_each_entry(client, &tegra->clients, list) |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 658 | if (client->base.class == args->client) { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 659 | err = tegra_client_open(fpriv, client, context); |
| 660 | if (err < 0) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 661 | break; |
| 662 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 663 | args->context = context->id; |
| 664 | break; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 665 | } |
| 666 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 667 | if (err < 0) |
| 668 | kfree(context); |
| 669 | |
| 670 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 671 | return err; |
| 672 | } |
| 673 | |
| 674 | static int tegra_close_channel(struct drm_device *drm, void *data, |
| 675 | struct drm_file *file) |
| 676 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 677 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 678 | struct drm_tegra_close_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 679 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 680 | int err = 0; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 681 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 682 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 683 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 684 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 685 | if (!context) { |
| 686 | err = -EINVAL; |
| 687 | goto unlock; |
| 688 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 689 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 690 | idr_remove(&fpriv->contexts, context->id); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 691 | tegra_drm_context_free(context); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 692 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 693 | unlock: |
| 694 | mutex_unlock(&fpriv->lock); |
| 695 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 696 | } |
| 697 | |
| 698 | static int tegra_get_syncpt(struct drm_device *drm, void *data, |
| 699 | struct drm_file *file) |
| 700 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 701 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 702 | struct drm_tegra_get_syncpt *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 703 | struct tegra_drm_context *context; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 704 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 705 | int err = 0; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 706 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 707 | mutex_lock(&fpriv->lock); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 708 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 709 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 710 | if (!context) { |
| 711 | err = -ENODEV; |
| 712 | goto unlock; |
| 713 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 714 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 715 | if (args->index >= context->client->base.num_syncpts) { |
| 716 | err = -EINVAL; |
| 717 | goto unlock; |
| 718 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 719 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 720 | syncpt = context->client->base.syncpts[args->index]; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 721 | args->id = host1x_syncpt_id(syncpt); |
| 722 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 723 | unlock: |
| 724 | mutex_unlock(&fpriv->lock); |
| 725 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 726 | } |
| 727 | |
| 728 | static int tegra_submit(struct drm_device *drm, void *data, |
| 729 | struct drm_file *file) |
| 730 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 731 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 732 | struct drm_tegra_submit *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 733 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 734 | int err; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 735 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 736 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 737 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 738 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 739 | if (!context) { |
| 740 | err = -ENODEV; |
| 741 | goto unlock; |
| 742 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 743 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 744 | err = context->client->ops->submit(context, args, drm, file); |
| 745 | |
| 746 | unlock: |
| 747 | mutex_unlock(&fpriv->lock); |
| 748 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 749 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 750 | |
| 751 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, |
| 752 | struct drm_file *file) |
| 753 | { |
| 754 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 755 | struct drm_tegra_get_syncpt_base *args = data; |
| 756 | struct tegra_drm_context *context; |
| 757 | struct host1x_syncpt_base *base; |
| 758 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 759 | int err = 0; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 760 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 761 | mutex_lock(&fpriv->lock); |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 762 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 763 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 764 | if (!context) { |
| 765 | err = -ENODEV; |
| 766 | goto unlock; |
| 767 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 768 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 769 | if (args->syncpt >= context->client->base.num_syncpts) { |
| 770 | err = -EINVAL; |
| 771 | goto unlock; |
| 772 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 773 | |
| 774 | syncpt = context->client->base.syncpts[args->syncpt]; |
| 775 | |
| 776 | base = host1x_syncpt_get_base(syncpt); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 777 | if (!base) { |
| 778 | err = -ENXIO; |
| 779 | goto unlock; |
| 780 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 781 | |
| 782 | args->id = host1x_syncpt_base_id(base); |
| 783 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 784 | unlock: |
| 785 | mutex_unlock(&fpriv->lock); |
| 786 | return err; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 787 | } |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 788 | |
| 789 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, |
| 790 | struct drm_file *file) |
| 791 | { |
| 792 | struct drm_tegra_gem_set_tiling *args = data; |
| 793 | enum tegra_bo_tiling_mode mode; |
| 794 | struct drm_gem_object *gem; |
| 795 | unsigned long value = 0; |
| 796 | struct tegra_bo *bo; |
| 797 | |
| 798 | switch (args->mode) { |
| 799 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: |
| 800 | mode = TEGRA_BO_TILING_MODE_PITCH; |
| 801 | |
| 802 | if (args->value != 0) |
| 803 | return -EINVAL; |
| 804 | |
| 805 | break; |
| 806 | |
| 807 | case DRM_TEGRA_GEM_TILING_MODE_TILED: |
| 808 | mode = TEGRA_BO_TILING_MODE_TILED; |
| 809 | |
| 810 | if (args->value != 0) |
| 811 | return -EINVAL; |
| 812 | |
| 813 | break; |
| 814 | |
| 815 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: |
| 816 | mode = TEGRA_BO_TILING_MODE_BLOCK; |
| 817 | |
| 818 | if (args->value > 5) |
| 819 | return -EINVAL; |
| 820 | |
| 821 | value = args->value; |
| 822 | break; |
| 823 | |
| 824 | default: |
| 825 | return -EINVAL; |
| 826 | } |
| 827 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 828 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 829 | if (!gem) |
| 830 | return -ENOENT; |
| 831 | |
| 832 | bo = to_tegra_bo(gem); |
| 833 | |
| 834 | bo->tiling.mode = mode; |
| 835 | bo->tiling.value = value; |
| 836 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 837 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 838 | |
| 839 | return 0; |
| 840 | } |
| 841 | |
| 842 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, |
| 843 | struct drm_file *file) |
| 844 | { |
| 845 | struct drm_tegra_gem_get_tiling *args = data; |
| 846 | struct drm_gem_object *gem; |
| 847 | struct tegra_bo *bo; |
| 848 | int err = 0; |
| 849 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 850 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 851 | if (!gem) |
| 852 | return -ENOENT; |
| 853 | |
| 854 | bo = to_tegra_bo(gem); |
| 855 | |
| 856 | switch (bo->tiling.mode) { |
| 857 | case TEGRA_BO_TILING_MODE_PITCH: |
| 858 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; |
| 859 | args->value = 0; |
| 860 | break; |
| 861 | |
| 862 | case TEGRA_BO_TILING_MODE_TILED: |
| 863 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; |
| 864 | args->value = 0; |
| 865 | break; |
| 866 | |
| 867 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 868 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; |
| 869 | args->value = bo->tiling.value; |
| 870 | break; |
| 871 | |
| 872 | default: |
| 873 | err = -EINVAL; |
| 874 | break; |
| 875 | } |
| 876 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 877 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 878 | |
| 879 | return err; |
| 880 | } |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 881 | |
| 882 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, |
| 883 | struct drm_file *file) |
| 884 | { |
| 885 | struct drm_tegra_gem_set_flags *args = data; |
| 886 | struct drm_gem_object *gem; |
| 887 | struct tegra_bo *bo; |
| 888 | |
| 889 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) |
| 890 | return -EINVAL; |
| 891 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 892 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 893 | if (!gem) |
| 894 | return -ENOENT; |
| 895 | |
| 896 | bo = to_tegra_bo(gem); |
| 897 | bo->flags = 0; |
| 898 | |
| 899 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) |
| 900 | bo->flags |= TEGRA_BO_BOTTOM_UP; |
| 901 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 902 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 903 | |
| 904 | return 0; |
| 905 | } |
| 906 | |
| 907 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, |
| 908 | struct drm_file *file) |
| 909 | { |
| 910 | struct drm_tegra_gem_get_flags *args = data; |
| 911 | struct drm_gem_object *gem; |
| 912 | struct tegra_bo *bo; |
| 913 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 914 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 915 | if (!gem) |
| 916 | return -ENOENT; |
| 917 | |
| 918 | bo = to_tegra_bo(gem); |
| 919 | args->flags = 0; |
| 920 | |
| 921 | if (bo->flags & TEGRA_BO_BOTTOM_UP) |
| 922 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; |
| 923 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 924 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 925 | |
| 926 | return 0; |
| 927 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 928 | #endif |
| 929 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 930 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 931 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 932 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, |
| 933 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 934 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, |
| 935 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 936 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, |
| 937 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 938 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, |
| 939 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 940 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, |
| 941 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 942 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, |
| 943 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 944 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, |
| 945 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 946 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, |
| 947 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 948 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, |
| 949 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 950 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, |
| 951 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 952 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, |
| 953 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 954 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, |
| 955 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 956 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, |
| 957 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 958 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, |
| 959 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 960 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 961 | }; |
| 962 | |
| 963 | static const struct file_operations tegra_drm_fops = { |
| 964 | .owner = THIS_MODULE, |
| 965 | .open = drm_open, |
| 966 | .release = drm_release, |
| 967 | .unlocked_ioctl = drm_ioctl, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 968 | .mmap = tegra_drm_mmap, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 969 | .poll = drm_poll, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 970 | .read = drm_read, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 971 | .compat_ioctl = drm_compat_ioctl, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 972 | .llseek = noop_llseek, |
| 973 | }; |
| 974 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 975 | static int tegra_drm_context_cleanup(int id, void *p, void *data) |
| 976 | { |
| 977 | struct tegra_drm_context *context = p; |
| 978 | |
| 979 | tegra_drm_context_free(context); |
| 980 | |
| 981 | return 0; |
| 982 | } |
| 983 | |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 984 | static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 985 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 986 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 987 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 988 | mutex_lock(&fpriv->lock); |
| 989 | idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); |
| 990 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 991 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 992 | idr_destroy(&fpriv->contexts); |
| 993 | mutex_destroy(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 994 | kfree(fpriv); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 995 | } |
| 996 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 997 | #ifdef CONFIG_DEBUG_FS |
| 998 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) |
| 999 | { |
| 1000 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 1001 | struct drm_device *drm = node->minor->dev; |
| 1002 | struct drm_framebuffer *fb; |
| 1003 | |
| 1004 | mutex_lock(&drm->mode_config.fb_lock); |
| 1005 | |
| 1006 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { |
| 1007 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", |
Ville Syrjälä | b00c600 | 2016-12-14 23:31:35 +0200 | [diff] [blame] | 1008 | fb->base.id, fb->width, fb->height, |
| 1009 | fb->format->depth, |
Ville Syrjälä | 272725c | 2016-12-14 23:32:20 +0200 | [diff] [blame] | 1010 | fb->format->cpp[0] * 8, |
Dave Airlie | 747a598 | 2016-04-15 15:10:35 +1000 | [diff] [blame] | 1011 | drm_framebuffer_read_refcount(fb)); |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1012 | } |
| 1013 | |
| 1014 | mutex_unlock(&drm->mode_config.fb_lock); |
| 1015 | |
| 1016 | return 0; |
| 1017 | } |
| 1018 | |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1019 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
| 1020 | { |
| 1021 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 1022 | struct drm_device *drm = node->minor->dev; |
| 1023 | struct tegra_drm *tegra = drm->dev_private; |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 1024 | struct drm_printer p = drm_seq_file_printer(s); |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1025 | |
Michał Mirosław | 68d890a | 2017-08-14 23:53:45 +0200 | [diff] [blame] | 1026 | if (tegra->domain) { |
| 1027 | mutex_lock(&tegra->mm_lock); |
| 1028 | drm_mm_print(&tegra->mm, &p); |
| 1029 | mutex_unlock(&tegra->mm_lock); |
| 1030 | } |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 1031 | |
| 1032 | return 0; |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1033 | } |
| 1034 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1035 | static struct drm_info_list tegra_debugfs_list[] = { |
| 1036 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1037 | { "iova", tegra_debugfs_iova, 0 }, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1038 | }; |
| 1039 | |
| 1040 | static int tegra_debugfs_init(struct drm_minor *minor) |
| 1041 | { |
| 1042 | return drm_debugfs_create_files(tegra_debugfs_list, |
| 1043 | ARRAY_SIZE(tegra_debugfs_list), |
| 1044 | minor->debugfs_root, minor); |
| 1045 | } |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1046 | #endif |
| 1047 | |
Thierry Reding | 9b57f5f | 2013-11-08 13:17:14 +0100 | [diff] [blame] | 1048 | static struct drm_driver tegra_drm_driver = { |
Thierry Reding | ad90659 | 2015-09-24 18:38:09 +0200 | [diff] [blame] | 1049 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 1050 | DRIVER_ATOMIC | DRIVER_RENDER, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1051 | .load = tegra_drm_load, |
| 1052 | .unload = tegra_drm_unload, |
| 1053 | .open = tegra_drm_open, |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 1054 | .postclose = tegra_drm_postclose, |
Noralf Trønnes | c94beda | 2017-12-05 19:25:04 +0100 | [diff] [blame] | 1055 | .lastclose = drm_fb_helper_lastclose, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1056 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1057 | #if defined(CONFIG_DEBUG_FS) |
| 1058 | .debugfs_init = tegra_debugfs_init, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1059 | #endif |
| 1060 | |
Daniel Vetter | 1ddbdbd | 2016-04-26 19:30:00 +0200 | [diff] [blame] | 1061 | .gem_free_object_unlocked = tegra_bo_free_object, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1062 | .gem_vm_ops = &tegra_bo_vm_ops, |
Thierry Reding | 3800391 | 2013-12-12 10:00:43 +0100 | [diff] [blame] | 1063 | |
| 1064 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1065 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1066 | .gem_prime_export = tegra_gem_prime_export, |
| 1067 | .gem_prime_import = tegra_gem_prime_import, |
| 1068 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1069 | .dumb_create = tegra_bo_dumb_create, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1070 | |
| 1071 | .ioctls = tegra_drm_ioctls, |
| 1072 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), |
| 1073 | .fops = &tegra_drm_fops, |
| 1074 | |
| 1075 | .name = DRIVER_NAME, |
| 1076 | .desc = DRIVER_DESC, |
| 1077 | .date = DRIVER_DATE, |
| 1078 | .major = DRIVER_MAJOR, |
| 1079 | .minor = DRIVER_MINOR, |
| 1080 | .patchlevel = DRIVER_PATCHLEVEL, |
| 1081 | }; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1082 | |
| 1083 | int tegra_drm_register_client(struct tegra_drm *tegra, |
| 1084 | struct tegra_drm_client *client) |
| 1085 | { |
| 1086 | mutex_lock(&tegra->clients_lock); |
| 1087 | list_add_tail(&client->list, &tegra->clients); |
| 1088 | mutex_unlock(&tegra->clients_lock); |
| 1089 | |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
| 1093 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
| 1094 | struct tegra_drm_client *client) |
| 1095 | { |
| 1096 | mutex_lock(&tegra->clients_lock); |
| 1097 | list_del_init(&client->list); |
| 1098 | mutex_unlock(&tegra->clients_lock); |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
Thierry Reding | 67485fb | 2017-11-09 13:17:11 +0100 | [diff] [blame] | 1103 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma) |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 1104 | { |
| 1105 | struct iova *alloc; |
| 1106 | void *virt; |
| 1107 | gfp_t gfp; |
| 1108 | int err; |
| 1109 | |
| 1110 | if (tegra->domain) |
| 1111 | size = iova_align(&tegra->carveout.domain, size); |
| 1112 | else |
| 1113 | size = PAGE_ALIGN(size); |
| 1114 | |
| 1115 | gfp = GFP_KERNEL | __GFP_ZERO; |
| 1116 | if (!tegra->domain) { |
| 1117 | /* |
| 1118 | * Many units only support 32-bit addresses, even on 64-bit |
| 1119 | * SoCs. If there is no IOMMU to translate into a 32-bit IO |
| 1120 | * virtual address space, force allocations to be in the |
| 1121 | * lower 32-bit range. |
| 1122 | */ |
| 1123 | gfp |= GFP_DMA; |
| 1124 | } |
| 1125 | |
| 1126 | virt = (void *)__get_free_pages(gfp, get_order(size)); |
| 1127 | if (!virt) |
| 1128 | return ERR_PTR(-ENOMEM); |
| 1129 | |
| 1130 | if (!tegra->domain) { |
| 1131 | /* |
| 1132 | * If IOMMU is disabled, devices address physical memory |
| 1133 | * directly. |
| 1134 | */ |
| 1135 | *dma = virt_to_phys(virt); |
| 1136 | return virt; |
| 1137 | } |
| 1138 | |
| 1139 | alloc = alloc_iova(&tegra->carveout.domain, |
| 1140 | size >> tegra->carveout.shift, |
| 1141 | tegra->carveout.limit, true); |
| 1142 | if (!alloc) { |
| 1143 | err = -EBUSY; |
| 1144 | goto free_pages; |
| 1145 | } |
| 1146 | |
| 1147 | *dma = iova_dma_addr(&tegra->carveout.domain, alloc); |
| 1148 | err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), |
| 1149 | size, IOMMU_READ | IOMMU_WRITE); |
| 1150 | if (err < 0) |
| 1151 | goto free_iova; |
| 1152 | |
| 1153 | return virt; |
| 1154 | |
| 1155 | free_iova: |
| 1156 | __free_iova(&tegra->carveout.domain, alloc); |
| 1157 | free_pages: |
| 1158 | free_pages((unsigned long)virt, get_order(size)); |
| 1159 | |
| 1160 | return ERR_PTR(err); |
| 1161 | } |
| 1162 | |
| 1163 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, |
| 1164 | dma_addr_t dma) |
| 1165 | { |
| 1166 | if (tegra->domain) |
| 1167 | size = iova_align(&tegra->carveout.domain, size); |
| 1168 | else |
| 1169 | size = PAGE_ALIGN(size); |
| 1170 | |
| 1171 | if (tegra->domain) { |
| 1172 | iommu_unmap(tegra->domain, dma, size); |
| 1173 | free_iova(&tegra->carveout.domain, |
| 1174 | iova_pfn(&tegra->carveout.domain, dma)); |
| 1175 | } |
| 1176 | |
| 1177 | free_pages((unsigned long)virt, get_order(size)); |
| 1178 | } |
| 1179 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1180 | static int host1x_drm_probe(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1181 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1182 | struct drm_driver *driver = &tegra_drm_driver; |
| 1183 | struct drm_device *drm; |
| 1184 | int err; |
| 1185 | |
| 1186 | drm = drm_dev_alloc(driver, &dev->dev); |
Tom Gundersen | 0f28860 | 2016-09-21 16:59:19 +0200 | [diff] [blame] | 1187 | if (IS_ERR(drm)) |
| 1188 | return PTR_ERR(drm); |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1189 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1190 | dev_set_drvdata(&dev->dev, drm); |
| 1191 | |
| 1192 | err = drm_dev_register(drm, 0); |
| 1193 | if (err < 0) |
| 1194 | goto unref; |
| 1195 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1196 | return 0; |
| 1197 | |
| 1198 | unref: |
| 1199 | drm_dev_unref(drm); |
| 1200 | return err; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1201 | } |
| 1202 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1203 | static int host1x_drm_remove(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1204 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1205 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
| 1206 | |
| 1207 | drm_dev_unregister(drm); |
| 1208 | drm_dev_unref(drm); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1209 | |
| 1210 | return 0; |
| 1211 | } |
| 1212 | |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1213 | #ifdef CONFIG_PM_SLEEP |
| 1214 | static int host1x_drm_suspend(struct device *dev) |
| 1215 | { |
| 1216 | struct drm_device *drm = dev_get_drvdata(dev); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1217 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1218 | |
| 1219 | drm_kms_helper_poll_disable(drm); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1220 | tegra_drm_fb_suspend(drm); |
| 1221 | |
| 1222 | tegra->state = drm_atomic_helper_suspend(drm); |
| 1223 | if (IS_ERR(tegra->state)) { |
| 1224 | tegra_drm_fb_resume(drm); |
| 1225 | drm_kms_helper_poll_enable(drm); |
| 1226 | return PTR_ERR(tegra->state); |
| 1227 | } |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1228 | |
| 1229 | return 0; |
| 1230 | } |
| 1231 | |
| 1232 | static int host1x_drm_resume(struct device *dev) |
| 1233 | { |
| 1234 | struct drm_device *drm = dev_get_drvdata(dev); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1235 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1236 | |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1237 | drm_atomic_helper_resume(drm, tegra->state); |
| 1238 | tegra_drm_fb_resume(drm); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1239 | drm_kms_helper_poll_enable(drm); |
| 1240 | |
| 1241 | return 0; |
| 1242 | } |
| 1243 | #endif |
| 1244 | |
Thierry Reding | a13f1dc | 2015-08-11 13:22:44 +0200 | [diff] [blame] | 1245 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
| 1246 | host1x_drm_resume); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1247 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1248 | static const struct of_device_id host1x_drm_subdevs[] = { |
| 1249 | { .compatible = "nvidia,tegra20-dc", }, |
| 1250 | { .compatible = "nvidia,tegra20-hdmi", }, |
| 1251 | { .compatible = "nvidia,tegra20-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1252 | { .compatible = "nvidia,tegra20-gr3d", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1253 | { .compatible = "nvidia,tegra30-dc", }, |
| 1254 | { .compatible = "nvidia,tegra30-hdmi", }, |
| 1255 | { .compatible = "nvidia,tegra30-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1256 | { .compatible = "nvidia,tegra30-gr3d", }, |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 1257 | { .compatible = "nvidia,tegra114-dsi", }, |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1258 | { .compatible = "nvidia,tegra114-hdmi", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1259 | { .compatible = "nvidia,tegra114-gr3d", }, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1260 | { .compatible = "nvidia,tegra124-dc", }, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1261 | { .compatible = "nvidia,tegra124-sor", }, |
Thierry Reding | fb7be70 | 2013-11-15 16:07:32 +0100 | [diff] [blame] | 1262 | { .compatible = "nvidia,tegra124-hdmi", }, |
Thierry Reding | 7d33858 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1263 | { .compatible = "nvidia,tegra124-dsi", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1264 | { .compatible = "nvidia,tegra124-vic", }, |
Thierry Reding | c06c793 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1265 | { .compatible = "nvidia,tegra132-dsi", }, |
Thierry Reding | 5b4f516 | 2015-03-27 10:31:58 +0100 | [diff] [blame] | 1266 | { .compatible = "nvidia,tegra210-dc", }, |
Thierry Reding | ddfb406 | 2015-04-08 16:56:22 +0200 | [diff] [blame] | 1267 | { .compatible = "nvidia,tegra210-dsi", }, |
Thierry Reding | 3309ac8 | 2015-07-30 10:32:46 +0200 | [diff] [blame] | 1268 | { .compatible = "nvidia,tegra210-sor", }, |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1269 | { .compatible = "nvidia,tegra210-sor1", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1270 | { .compatible = "nvidia,tegra210-vic", }, |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 1271 | { .compatible = "nvidia,tegra186-display", }, |
Thierry Reding | 4730795 | 2017-08-30 17:42:54 +0200 | [diff] [blame] | 1272 | { .compatible = "nvidia,tegra186-dc", }, |
Thierry Reding | c57997b | 2017-10-12 19:12:57 +0200 | [diff] [blame] | 1273 | { .compatible = "nvidia,tegra186-sor", }, |
| 1274 | { .compatible = "nvidia,tegra186-sor1", }, |
Mikko Perttunen | 6e44b9a | 2017-09-05 11:43:06 +0300 | [diff] [blame] | 1275 | { .compatible = "nvidia,tegra186-vic", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1276 | { /* sentinel */ } |
| 1277 | }; |
| 1278 | |
| 1279 | static struct host1x_driver host1x_drm_driver = { |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1280 | .driver = { |
| 1281 | .name = "drm", |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1282 | .pm = &host1x_drm_pm_ops, |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1283 | }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1284 | .probe = host1x_drm_probe, |
| 1285 | .remove = host1x_drm_remove, |
| 1286 | .subdevs = host1x_drm_subdevs, |
| 1287 | }; |
| 1288 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1289 | static struct platform_driver * const drivers[] = { |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 1290 | &tegra_display_hub_driver, |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1291 | &tegra_dc_driver, |
| 1292 | &tegra_hdmi_driver, |
| 1293 | &tegra_dsi_driver, |
| 1294 | &tegra_dpaux_driver, |
| 1295 | &tegra_sor_driver, |
| 1296 | &tegra_gr2d_driver, |
| 1297 | &tegra_gr3d_driver, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1298 | &tegra_vic_driver, |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1299 | }; |
| 1300 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1301 | static int __init host1x_drm_init(void) |
| 1302 | { |
| 1303 | int err; |
| 1304 | |
| 1305 | err = host1x_driver_register(&host1x_drm_driver); |
| 1306 | if (err < 0) |
| 1307 | return err; |
| 1308 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1309 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1310 | if (err < 0) |
| 1311 | goto unregister_host1x; |
| 1312 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1313 | return 0; |
| 1314 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1315 | unregister_host1x: |
| 1316 | host1x_driver_unregister(&host1x_drm_driver); |
| 1317 | return err; |
| 1318 | } |
| 1319 | module_init(host1x_drm_init); |
| 1320 | |
| 1321 | static void __exit host1x_drm_exit(void) |
| 1322 | { |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1323 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1324 | host1x_driver_unregister(&host1x_drm_driver); |
| 1325 | } |
| 1326 | module_exit(host1x_drm_exit); |
| 1327 | |
| 1328 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); |
| 1329 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); |
| 1330 | MODULE_LICENSE("GPL v2"); |