blob: 204b10e33f16e745bd0c246b52f60c9ab489989b [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingab7d3f52017-12-14 13:46:20 +010036static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010038{
Thierry Reding1503ca42014-11-24 17:41:23 +010039 int err;
40
Thierry Redingab7d3f52017-12-14 13:46:20 +010041 err = drm_atomic_helper_check_modeset(drm, state);
42 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010043 return err;
44
Thierry Reding0281c412017-11-28 11:20:40 +010045 err = tegra_display_hub_atomic_check(drm, state);
46 if (err < 0)
47 return err;
48
Thierry Redingab7d3f52017-12-14 13:46:20 +010049 err = drm_atomic_normalize_zpos(drm, state);
50 if (err < 0)
Maarten Lankhorst424624e2017-07-11 16:33:10 +020051 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010052
Thierry Redingab7d3f52017-12-14 13:46:20 +010053 err = drm_atomic_helper_check_planes(drm, state);
54 if (err < 0)
55 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010056
Thierry Redingab7d3f52017-12-14 13:46:20 +010057 if (state->legacy_cursor_update)
58 state->async_update = !drm_atomic_helper_async_check(drm, state);
59
Thierry Reding1503ca42014-11-24 17:41:23 +010060 return 0;
61}
62
Thierry Reding31b02ca2017-10-12 17:40:46 +020063static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010064 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053065#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010066 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010067#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010068 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020069 .atomic_commit = drm_atomic_helper_commit,
70};
71
Thierry Redingc4755fb2017-11-13 11:08:13 +010072static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
73{
74 struct drm_device *drm = old_state->dev;
75 struct tegra_drm *tegra = drm->dev_private;
76
77 if (tegra->hub) {
78 drm_atomic_helper_commit_modeset_disables(drm, old_state);
79 tegra_display_hub_atomic_commit(drm, old_state);
80 drm_atomic_helper_commit_planes(drm, old_state, 0);
81 drm_atomic_helper_commit_modeset_enables(drm, old_state);
82 drm_atomic_helper_commit_hw_done(old_state);
83 drm_atomic_helper_wait_for_vblanks(drm, old_state);
84 drm_atomic_helper_cleanup_planes(drm, old_state);
85 } else {
86 drm_atomic_helper_commit_tail_rpm(old_state);
87 }
88}
89
Thierry Reding31b02ca2017-10-12 17:40:46 +020090static const struct drm_mode_config_helper_funcs
91tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010092 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010093};
94
Thierry Reding776dc382013-10-14 14:43:22 +020095static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000096{
Thierry Reding776dc382013-10-14 14:43:22 +020097 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020098 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000099 int err;
100
Thierry Reding776dc382013-10-14 14:43:22 +0200101 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200102 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200103 return -ENOMEM;
104
Thierry Redingdf06b752014-06-26 21:41:53 +0200105 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200106 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100107 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200108 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100109
Thierry Redingdf06b752014-06-26 21:41:53 +0200110 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300111 if (!tegra->domain) {
112 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200113 goto free;
114 }
115
Thierry Reding24cfdc12018-04-23 08:57:45 +0200116 err = iova_cache_get();
117 if (err < 0)
118 goto domain;
119
Thierry Reding4553f732015-01-19 16:15:04 +0100120 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200121 gem_start = geometry->aperture_start;
122 gem_end = geometry->aperture_end - CARVEOUT_SZ;
123 carveout_start = gem_end + 1;
124 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100125
Mikko Perttunenad926012016-12-14 13:16:11 +0200126 order = __ffs(tegra->domain->pgsize_bitmap);
127 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100128 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200129
130 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
131 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
132
133 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100134 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200135
136 DRM_DEBUG("IOMMU apertures:\n");
137 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
138 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
139 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200140 }
141
Thierry Reding386a2a72013-09-24 13:22:17 +0200142 mutex_init(&tegra->clients_lock);
143 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100144
Thierry Reding386a2a72013-09-24 13:22:17 +0200145 drm->dev_private = tegra;
146 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000147
148 drm_mode_config_init(drm);
149
Thierry Redingf9914212014-11-26 13:03:57 +0100150 drm->mode_config.min_width = 0;
151 drm->mode_config.min_height = 0;
152
153 drm->mode_config.max_width = 4096;
154 drm->mode_config.max_height = 4096;
155
Alexandre Courbot5e911442016-11-08 16:50:42 +0900156 drm->mode_config.allow_fb_modifiers = true;
157
Thierry Reding31b02ca2017-10-12 17:40:46 +0200158 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
159 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100160
Thierry Redinge2215322014-06-27 17:19:25 +0200161 err = tegra_drm_fb_prepare(drm);
162 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100163 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200164
165 drm_kms_helper_poll_init(drm);
166
Thierry Reding776dc382013-10-14 14:43:22 +0200167 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000168 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100169 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000170
Thierry Redingc4755fb2017-11-13 11:08:13 +0100171 if (tegra->hub) {
172 err = tegra_display_hub_prepare(tegra->hub);
173 if (err < 0)
174 goto device;
175 }
176
Thierry Reding603f0cc2013-04-22 21:22:14 +0200177 /*
178 * We don't use the drm_irq_install() helpers provided by the DRM
179 * core, so we need to set this manually in order to allow the
180 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
181 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300182 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200183
Thierry Reding42e9ce02015-01-28 14:43:05 +0100184 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100185 drm->max_vblank_count = 0xffffffff;
186
Thierry Reding6e5ff992012-11-28 11:45:47 +0100187 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
188 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100189 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100190
Thierry Reding31930d42015-07-02 17:04:06 +0200191 drm_mode_config_reset(drm);
192
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000193 err = tegra_drm_fb_init(drm);
194 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100195 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000196
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000197 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100198
Thierry Redingc4755fb2017-11-13 11:08:13 +0100199hub:
200 if (tegra->hub)
201 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100202device:
203 host1x_device_exit(device);
204fbdev:
205 drm_kms_helper_poll_fini(drm);
206 tegra_drm_fb_free(drm);
207config:
208 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200209
210 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100211 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200212 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200213 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200214 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200215 }
Thierry Reding24cfdc12018-04-23 08:57:45 +0200216domain:
217 if (tegra->domain)
218 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200219free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100220 kfree(tegra);
221 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000222}
223
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200224static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000225{
Thierry Reding776dc382013-10-14 14:43:22 +0200226 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200227 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200228 int err;
229
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000230 drm_kms_helper_poll_fini(drm);
231 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100232 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200233 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000234
Thierry Reding776dc382013-10-14 14:43:22 +0200235 err = host1x_device_exit(device);
236 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200237 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200238
Thierry Redingdf06b752014-06-26 21:41:53 +0200239 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100240 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200241 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200242 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200243 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200244 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200245 }
246
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100247 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000248}
249
250static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
251{
Thierry Reding08943e62013-09-26 16:08:18 +0200252 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200253
254 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
255 if (!fpriv)
256 return -ENOMEM;
257
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100258 idr_init(&fpriv->contexts);
259 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200260 filp->driver_priv = fpriv;
261
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000262 return 0;
263}
264
Thierry Redingc88c3632013-09-26 16:08:22 +0200265static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200266{
267 context->client->ops->close_channel(context);
268 kfree(context);
269}
270
Thierry Redingc40f0f12013-10-10 11:00:33 +0200271static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100272host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200273{
274 struct drm_gem_object *gem;
275 struct tegra_bo *bo;
276
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100277 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200278 if (!gem)
279 return NULL;
280
Thierry Redingc40f0f12013-10-10 11:00:33 +0200281 bo = to_tegra_bo(gem);
282 return &bo->base;
283}
284
Thierry Reding961e3be2014-06-10 10:25:00 +0200285static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
286 struct drm_tegra_reloc __user *src,
287 struct drm_device *drm,
288 struct drm_file *file)
289{
290 u32 cmdbuf, target;
291 int err;
292
293 err = get_user(cmdbuf, &src->cmdbuf.handle);
294 if (err < 0)
295 return err;
296
297 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
298 if (err < 0)
299 return err;
300
301 err = get_user(target, &src->target.handle);
302 if (err < 0)
303 return err;
304
David Ung31f40f82015-01-20 18:37:35 -0800305 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200306 if (err < 0)
307 return err;
308
309 err = get_user(dest->shift, &src->shift);
310 if (err < 0)
311 return err;
312
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100313 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200314 if (!dest->cmdbuf.bo)
315 return -ENOENT;
316
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100317 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200318 if (!dest->target.bo)
319 return -ENOENT;
320
321 return 0;
322}
323
Thierry Redingc40f0f12013-10-10 11:00:33 +0200324int tegra_drm_submit(struct tegra_drm_context *context,
325 struct drm_tegra_submit *args, struct drm_device *drm,
326 struct drm_file *file)
327{
328 unsigned int num_cmdbufs = args->num_cmdbufs;
329 unsigned int num_relocs = args->num_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300330 struct drm_tegra_cmdbuf __user *user_cmdbufs;
331 struct drm_tegra_reloc __user *user_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300332 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200333 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300334 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200335 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300336 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200337 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200338 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200339 int err;
340
Mikko Perttunena176c672017-09-28 15:50:44 +0300341 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
342 user_relocs = u64_to_user_ptr(args->relocs);
Mikko Perttunena176c672017-09-28 15:50:44 +0300343 user_syncpt = u64_to_user_ptr(args->syncpts);
344
Thierry Redingc40f0f12013-10-10 11:00:33 +0200345 /* We don't yet support other than one syncpt_incr struct per submit */
346 if (args->num_syncpts != 1)
347 return -EINVAL;
348
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300349 /* We don't yet support waitchks */
350 if (args->num_waitchks != 0)
351 return -EINVAL;
352
Thierry Redingc40f0f12013-10-10 11:00:33 +0200353 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
Thierry Reding24c94e12018-05-05 08:45:47 +0200354 args->num_relocs);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200355 if (!job)
356 return -ENOMEM;
357
358 job->num_relocs = args->num_relocs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200359 job->client = (u32)args->context;
360 job->class = context->client->base.class;
361 job->serialize = true;
362
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200363 /*
364 * Track referenced BOs so that they can be unreferenced after the
365 * submission is complete.
366 */
Thierry Reding24c94e12018-05-05 08:45:47 +0200367 num_refs = num_cmdbufs + num_relocs * 2;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200368
369 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
370 if (!refs) {
371 err = -ENOMEM;
372 goto put;
373 }
374
375 /* reuse as an iterator later */
376 num_refs = 0;
377
Thierry Redingc40f0f12013-10-10 11:00:33 +0200378 while (num_cmdbufs) {
379 struct drm_tegra_cmdbuf cmdbuf;
380 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300381 struct tegra_bo *obj;
382 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200383
Mikko Perttunena176c672017-09-28 15:50:44 +0300384 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300385 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200386 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300387 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200388
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300389 /*
390 * The maximum number of CDMA gather fetches is 16383, a higher
391 * value means the words count is malformed.
392 */
393 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
394 err = -EINVAL;
395 goto fail;
396 }
397
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100398 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200399 if (!bo) {
400 err = -ENOENT;
401 goto fail;
402 }
403
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300404 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
405 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200406 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300407
408 /*
409 * Gather buffer base address must be 4-bytes aligned,
410 * unaligned offset is malformed and cause commands stream
411 * corruption on the buffer address relocation.
412 */
413 if (offset & 3 || offset >= obj->gem.size) {
414 err = -EINVAL;
415 goto fail;
416 }
417
Thierry Redingc40f0f12013-10-10 11:00:33 +0200418 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
419 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300420 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200421 }
422
Thierry Reding961e3be2014-06-10 10:25:00 +0200423 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200424 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300425 struct host1x_reloc *reloc;
426 struct tegra_bo *obj;
427
Thierry Reding961e3be2014-06-10 10:25:00 +0200428 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300429 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200430 file);
431 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200432 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300433
434 reloc = &job->relocarray[num_relocs];
435 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200436 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300437
438 /*
439 * The unaligned cmdbuf offset will cause an unaligned write
440 * during of the relocations patching, corrupting the commands
441 * stream.
442 */
443 if (reloc->cmdbuf.offset & 3 ||
444 reloc->cmdbuf.offset >= obj->gem.size) {
445 err = -EINVAL;
446 goto fail;
447 }
448
449 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200450 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300451
452 if (reloc->target.offset >= obj->gem.size) {
453 err = -EINVAL;
454 goto fail;
455 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200456 }
457
Mikko Perttunena176c672017-09-28 15:50:44 +0300458 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300459 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200460 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300461 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200462
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300463 /* check whether syncpoint ID is valid */
464 sp = host1x_syncpt_get(host1x, syncpt.id);
465 if (!sp) {
466 err = -ENOENT;
467 goto fail;
468 }
469
Thierry Redingc40f0f12013-10-10 11:00:33 +0200470 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300471 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200472 job->syncpt_incrs = syncpt.incrs;
473 job->syncpt_id = syncpt.id;
474 job->timeout = 10000;
475
476 if (args->timeout && args->timeout < 10000)
477 job->timeout = args->timeout;
478
479 err = host1x_job_pin(job, context->client->base.dev);
480 if (err)
481 goto fail;
482
483 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200484 if (err) {
485 host1x_job_unpin(job);
486 goto fail;
487 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200488
489 args->fence = job->syncpt_end;
490
Thierry Redingc40f0f12013-10-10 11:00:33 +0200491fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200492 while (num_refs--)
493 drm_gem_object_put_unlocked(refs[num_refs]);
494
495 kfree(refs);
496
497put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200498 host1x_job_put(job);
499 return err;
500}
501
502
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200503#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200504static int tegra_gem_create(struct drm_device *drm, void *data,
505 struct drm_file *file)
506{
507 struct drm_tegra_gem_create *args = data;
508 struct tegra_bo *bo;
509
Thierry Reding773af772013-10-04 22:34:01 +0200510 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200511 &args->handle);
512 if (IS_ERR(bo))
513 return PTR_ERR(bo);
514
515 return 0;
516}
517
518static int tegra_gem_mmap(struct drm_device *drm, void *data,
519 struct drm_file *file)
520{
521 struct drm_tegra_gem_mmap *args = data;
522 struct drm_gem_object *gem;
523 struct tegra_bo *bo;
524
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100525 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200526 if (!gem)
527 return -EINVAL;
528
529 bo = to_tegra_bo(gem);
530
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200531 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200532
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300533 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200534
535 return 0;
536}
537
538static int tegra_syncpt_read(struct drm_device *drm, void *data,
539 struct drm_file *file)
540{
Thierry Reding776dc382013-10-14 14:43:22 +0200541 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200542 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200543 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200544
Thierry Reding776dc382013-10-14 14:43:22 +0200545 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200546 if (!sp)
547 return -EINVAL;
548
549 args->value = host1x_syncpt_read_min(sp);
550 return 0;
551}
552
553static int tegra_syncpt_incr(struct drm_device *drm, void *data,
554 struct drm_file *file)
555{
Thierry Reding776dc382013-10-14 14:43:22 +0200556 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200557 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200558 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200559
Thierry Reding776dc382013-10-14 14:43:22 +0200560 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200561 if (!sp)
562 return -EINVAL;
563
Arto Merilainenebae30b2013-05-29 13:26:08 +0300564 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200565}
566
567static int tegra_syncpt_wait(struct drm_device *drm, void *data,
568 struct drm_file *file)
569{
Thierry Reding776dc382013-10-14 14:43:22 +0200570 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200571 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200572 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200573
Thierry Reding776dc382013-10-14 14:43:22 +0200574 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200575 if (!sp)
576 return -EINVAL;
577
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300578 return host1x_syncpt_wait(sp, args->thresh,
579 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200580 &args->value);
581}
582
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100583static int tegra_client_open(struct tegra_drm_file *fpriv,
584 struct tegra_drm_client *client,
585 struct tegra_drm_context *context)
586{
587 int err;
588
589 err = client->ops->open_channel(client, context);
590 if (err < 0)
591 return err;
592
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300593 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100594 if (err < 0) {
595 client->ops->close_channel(context);
596 return err;
597 }
598
599 context->client = client;
600 context->id = err;
601
602 return 0;
603}
604
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200605static int tegra_open_channel(struct drm_device *drm, void *data,
606 struct drm_file *file)
607{
Thierry Reding08943e62013-09-26 16:08:18 +0200608 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200609 struct tegra_drm *tegra = drm->dev_private;
610 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200611 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200612 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200613 int err = -ENODEV;
614
615 context = kzalloc(sizeof(*context), GFP_KERNEL);
616 if (!context)
617 return -ENOMEM;
618
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100619 mutex_lock(&fpriv->lock);
620
Thierry Reding776dc382013-10-14 14:43:22 +0200621 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200622 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100623 err = tegra_client_open(fpriv, client, context);
624 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200625 break;
626
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100627 args->context = context->id;
628 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200629 }
630
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100631 if (err < 0)
632 kfree(context);
633
634 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200635 return err;
636}
637
638static int tegra_close_channel(struct drm_device *drm, void *data,
639 struct drm_file *file)
640{
Thierry Reding08943e62013-09-26 16:08:18 +0200641 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200642 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200643 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100644 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200645
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100646 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200647
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300648 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100649 if (!context) {
650 err = -EINVAL;
651 goto unlock;
652 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200653
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100654 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200655 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200656
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100657unlock:
658 mutex_unlock(&fpriv->lock);
659 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200660}
661
662static int tegra_get_syncpt(struct drm_device *drm, void *data,
663 struct drm_file *file)
664{
Thierry Reding08943e62013-09-26 16:08:18 +0200665 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200666 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200667 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200668 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100669 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200670
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100671 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200672
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300673 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100674 if (!context) {
675 err = -ENODEV;
676 goto unlock;
677 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200678
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100679 if (args->index >= context->client->base.num_syncpts) {
680 err = -EINVAL;
681 goto unlock;
682 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200683
Thierry Reding53fa7f72013-09-24 15:35:40 +0200684 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200685 args->id = host1x_syncpt_id(syncpt);
686
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100687unlock:
688 mutex_unlock(&fpriv->lock);
689 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200690}
691
692static int tegra_submit(struct drm_device *drm, void *data,
693 struct drm_file *file)
694{
Thierry Reding08943e62013-09-26 16:08:18 +0200695 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200696 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200697 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100698 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200699
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100700 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200701
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300702 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100703 if (!context) {
704 err = -ENODEV;
705 goto unlock;
706 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200707
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100708 err = context->client->ops->submit(context, args, drm, file);
709
710unlock:
711 mutex_unlock(&fpriv->lock);
712 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200713}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300714
715static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
716 struct drm_file *file)
717{
718 struct tegra_drm_file *fpriv = file->driver_priv;
719 struct drm_tegra_get_syncpt_base *args = data;
720 struct tegra_drm_context *context;
721 struct host1x_syncpt_base *base;
722 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100723 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300724
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100725 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300726
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300727 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100728 if (!context) {
729 err = -ENODEV;
730 goto unlock;
731 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300732
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100733 if (args->syncpt >= context->client->base.num_syncpts) {
734 err = -EINVAL;
735 goto unlock;
736 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300737
738 syncpt = context->client->base.syncpts[args->syncpt];
739
740 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100741 if (!base) {
742 err = -ENXIO;
743 goto unlock;
744 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300745
746 args->id = host1x_syncpt_base_id(base);
747
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100748unlock:
749 mutex_unlock(&fpriv->lock);
750 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300751}
Thierry Reding7678d712014-06-03 14:56:57 +0200752
753static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
754 struct drm_file *file)
755{
756 struct drm_tegra_gem_set_tiling *args = data;
757 enum tegra_bo_tiling_mode mode;
758 struct drm_gem_object *gem;
759 unsigned long value = 0;
760 struct tegra_bo *bo;
761
762 switch (args->mode) {
763 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
764 mode = TEGRA_BO_TILING_MODE_PITCH;
765
766 if (args->value != 0)
767 return -EINVAL;
768
769 break;
770
771 case DRM_TEGRA_GEM_TILING_MODE_TILED:
772 mode = TEGRA_BO_TILING_MODE_TILED;
773
774 if (args->value != 0)
775 return -EINVAL;
776
777 break;
778
779 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
780 mode = TEGRA_BO_TILING_MODE_BLOCK;
781
782 if (args->value > 5)
783 return -EINVAL;
784
785 value = args->value;
786 break;
787
788 default:
789 return -EINVAL;
790 }
791
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100792 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200793 if (!gem)
794 return -ENOENT;
795
796 bo = to_tegra_bo(gem);
797
798 bo->tiling.mode = mode;
799 bo->tiling.value = value;
800
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300801 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200802
803 return 0;
804}
805
806static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
807 struct drm_file *file)
808{
809 struct drm_tegra_gem_get_tiling *args = data;
810 struct drm_gem_object *gem;
811 struct tegra_bo *bo;
812 int err = 0;
813
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100814 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200815 if (!gem)
816 return -ENOENT;
817
818 bo = to_tegra_bo(gem);
819
820 switch (bo->tiling.mode) {
821 case TEGRA_BO_TILING_MODE_PITCH:
822 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
823 args->value = 0;
824 break;
825
826 case TEGRA_BO_TILING_MODE_TILED:
827 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
828 args->value = 0;
829 break;
830
831 case TEGRA_BO_TILING_MODE_BLOCK:
832 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
833 args->value = bo->tiling.value;
834 break;
835
836 default:
837 err = -EINVAL;
838 break;
839 }
840
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300841 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200842
843 return err;
844}
Thierry Reding7b129082014-06-10 12:04:03 +0200845
846static int tegra_gem_set_flags(struct drm_device *drm, void *data,
847 struct drm_file *file)
848{
849 struct drm_tegra_gem_set_flags *args = data;
850 struct drm_gem_object *gem;
851 struct tegra_bo *bo;
852
853 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
854 return -EINVAL;
855
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100856 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200857 if (!gem)
858 return -ENOENT;
859
860 bo = to_tegra_bo(gem);
861 bo->flags = 0;
862
863 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
864 bo->flags |= TEGRA_BO_BOTTOM_UP;
865
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300866 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200867
868 return 0;
869}
870
871static int tegra_gem_get_flags(struct drm_device *drm, void *data,
872 struct drm_file *file)
873{
874 struct drm_tegra_gem_get_flags *args = data;
875 struct drm_gem_object *gem;
876 struct tegra_bo *bo;
877
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100878 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200879 if (!gem)
880 return -ENOENT;
881
882 bo = to_tegra_bo(gem);
883 args->flags = 0;
884
885 if (bo->flags & TEGRA_BO_BOTTOM_UP)
886 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
887
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300888 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200889
890 return 0;
891}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200892#endif
893
Rob Clarkbaa70942013-08-02 13:27:49 -0400894static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200895#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200896 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
897 DRM_UNLOCKED | DRM_RENDER_ALLOW),
898 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
899 DRM_UNLOCKED | DRM_RENDER_ALLOW),
900 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
901 DRM_UNLOCKED | DRM_RENDER_ALLOW),
902 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
903 DRM_UNLOCKED | DRM_RENDER_ALLOW),
904 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
905 DRM_UNLOCKED | DRM_RENDER_ALLOW),
906 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
907 DRM_UNLOCKED | DRM_RENDER_ALLOW),
908 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
909 DRM_UNLOCKED | DRM_RENDER_ALLOW),
910 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
911 DRM_UNLOCKED | DRM_RENDER_ALLOW),
912 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
913 DRM_UNLOCKED | DRM_RENDER_ALLOW),
914 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
915 DRM_UNLOCKED | DRM_RENDER_ALLOW),
916 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
917 DRM_UNLOCKED | DRM_RENDER_ALLOW),
918 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
919 DRM_UNLOCKED | DRM_RENDER_ALLOW),
920 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
921 DRM_UNLOCKED | DRM_RENDER_ALLOW),
922 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
923 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200924#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000925};
926
927static const struct file_operations tegra_drm_fops = {
928 .owner = THIS_MODULE,
929 .open = drm_open,
930 .release = drm_release,
931 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200932 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000933 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000934 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000935 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000936 .llseek = noop_llseek,
937};
938
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100939static int tegra_drm_context_cleanup(int id, void *p, void *data)
940{
941 struct tegra_drm_context *context = p;
942
943 tegra_drm_context_free(context);
944
945 return 0;
946}
947
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200948static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100949{
Thierry Reding08943e62013-09-26 16:08:18 +0200950 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100951
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100952 mutex_lock(&fpriv->lock);
953 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
954 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200955
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100956 idr_destroy(&fpriv->contexts);
957 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200958 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100959}
960
Thierry Redinge450fcc2013-02-13 16:13:16 +0100961#ifdef CONFIG_DEBUG_FS
962static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
963{
964 struct drm_info_node *node = (struct drm_info_node *)s->private;
965 struct drm_device *drm = node->minor->dev;
966 struct drm_framebuffer *fb;
967
968 mutex_lock(&drm->mode_config.fb_lock);
969
970 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
971 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200972 fb->base.id, fb->width, fb->height,
973 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200974 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000975 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100976 }
977
978 mutex_unlock(&drm->mode_config.fb_lock);
979
980 return 0;
981}
982
Thierry Reding28c23372015-01-23 09:16:03 +0100983static int tegra_debugfs_iova(struct seq_file *s, void *data)
984{
985 struct drm_info_node *node = (struct drm_info_node *)s->private;
986 struct drm_device *drm = node->minor->dev;
987 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100988 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100989
Michał Mirosław68d890a2017-08-14 23:53:45 +0200990 if (tegra->domain) {
991 mutex_lock(&tegra->mm_lock);
992 drm_mm_print(&tegra->mm, &p);
993 mutex_unlock(&tegra->mm_lock);
994 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100995
996 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100997}
998
Thierry Redinge450fcc2013-02-13 16:13:16 +0100999static struct drm_info_list tegra_debugfs_list[] = {
1000 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001001 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001002};
1003
1004static int tegra_debugfs_init(struct drm_minor *minor)
1005{
1006 return drm_debugfs_create_files(tegra_debugfs_list,
1007 ARRAY_SIZE(tegra_debugfs_list),
1008 minor->debugfs_root, minor);
1009}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001010#endif
1011
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001012static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001013 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001014 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001015 .load = tegra_drm_load,
1016 .unload = tegra_drm_unload,
1017 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001018 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001019 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001020
Thierry Redinge450fcc2013-02-13 16:13:16 +01001021#if defined(CONFIG_DEBUG_FS)
1022 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001023#endif
1024
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001025 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001026 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001027
1028 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1029 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1030 .gem_prime_export = tegra_gem_prime_export,
1031 .gem_prime_import = tegra_gem_prime_import,
1032
Arto Merilainende2ba662013-03-22 16:34:08 +02001033 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001034
1035 .ioctls = tegra_drm_ioctls,
1036 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1037 .fops = &tegra_drm_fops,
1038
1039 .name = DRIVER_NAME,
1040 .desc = DRIVER_DESC,
1041 .date = DRIVER_DATE,
1042 .major = DRIVER_MAJOR,
1043 .minor = DRIVER_MINOR,
1044 .patchlevel = DRIVER_PATCHLEVEL,
1045};
Thierry Reding776dc382013-10-14 14:43:22 +02001046
1047int tegra_drm_register_client(struct tegra_drm *tegra,
1048 struct tegra_drm_client *client)
1049{
1050 mutex_lock(&tegra->clients_lock);
1051 list_add_tail(&client->list, &tegra->clients);
1052 mutex_unlock(&tegra->clients_lock);
1053
1054 return 0;
1055}
1056
1057int tegra_drm_unregister_client(struct tegra_drm *tegra,
1058 struct tegra_drm_client *client)
1059{
1060 mutex_lock(&tegra->clients_lock);
1061 list_del_init(&client->list);
1062 mutex_unlock(&tegra->clients_lock);
1063
1064 return 0;
1065}
1066
Thierry Reding0c407de2018-05-04 15:02:24 +02001067struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1068 bool shared)
1069{
1070 struct drm_device *drm = dev_get_drvdata(client->parent);
1071 struct tegra_drm *tegra = drm->dev_private;
1072 struct iommu_group *group = NULL;
1073 int err;
1074
1075 if (tegra->domain) {
1076 group = iommu_group_get(client->dev);
1077 if (!group) {
1078 dev_err(client->dev, "failed to get IOMMU group\n");
1079 return ERR_PTR(-ENODEV);
1080 }
1081
1082 if (!shared || (shared && (group != tegra->group))) {
1083 err = iommu_attach_group(tegra->domain, group);
1084 if (err < 0) {
1085 iommu_group_put(group);
1086 return ERR_PTR(err);
1087 }
1088
1089 if (shared && !tegra->group)
1090 tegra->group = group;
1091 }
1092 }
1093
1094 return group;
1095}
1096
1097void host1x_client_iommu_detach(struct host1x_client *client,
1098 struct iommu_group *group)
1099{
1100 struct drm_device *drm = dev_get_drvdata(client->parent);
1101 struct tegra_drm *tegra = drm->dev_private;
1102
1103 if (group) {
1104 if (group == tegra->group) {
1105 iommu_detach_group(tegra->domain, group);
1106 tegra->group = NULL;
1107 }
1108
1109 iommu_group_put(group);
1110 }
1111}
1112
Thierry Reding67485fb2017-11-09 13:17:11 +01001113void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001114{
1115 struct iova *alloc;
1116 void *virt;
1117 gfp_t gfp;
1118 int err;
1119
1120 if (tegra->domain)
1121 size = iova_align(&tegra->carveout.domain, size);
1122 else
1123 size = PAGE_ALIGN(size);
1124
1125 gfp = GFP_KERNEL | __GFP_ZERO;
1126 if (!tegra->domain) {
1127 /*
1128 * Many units only support 32-bit addresses, even on 64-bit
1129 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1130 * virtual address space, force allocations to be in the
1131 * lower 32-bit range.
1132 */
1133 gfp |= GFP_DMA;
1134 }
1135
1136 virt = (void *)__get_free_pages(gfp, get_order(size));
1137 if (!virt)
1138 return ERR_PTR(-ENOMEM);
1139
1140 if (!tegra->domain) {
1141 /*
1142 * If IOMMU is disabled, devices address physical memory
1143 * directly.
1144 */
1145 *dma = virt_to_phys(virt);
1146 return virt;
1147 }
1148
1149 alloc = alloc_iova(&tegra->carveout.domain,
1150 size >> tegra->carveout.shift,
1151 tegra->carveout.limit, true);
1152 if (!alloc) {
1153 err = -EBUSY;
1154 goto free_pages;
1155 }
1156
1157 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1158 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1159 size, IOMMU_READ | IOMMU_WRITE);
1160 if (err < 0)
1161 goto free_iova;
1162
1163 return virt;
1164
1165free_iova:
1166 __free_iova(&tegra->carveout.domain, alloc);
1167free_pages:
1168 free_pages((unsigned long)virt, get_order(size));
1169
1170 return ERR_PTR(err);
1171}
1172
1173void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1174 dma_addr_t dma)
1175{
1176 if (tegra->domain)
1177 size = iova_align(&tegra->carveout.domain, size);
1178 else
1179 size = PAGE_ALIGN(size);
1180
1181 if (tegra->domain) {
1182 iommu_unmap(tegra->domain, dma, size);
1183 free_iova(&tegra->carveout.domain,
1184 iova_pfn(&tegra->carveout.domain, dma));
1185 }
1186
1187 free_pages((unsigned long)virt, get_order(size));
1188}
1189
Thierry Reding9910f5c2014-05-22 09:57:15 +02001190static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001191{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001192 struct drm_driver *driver = &tegra_drm_driver;
1193 struct drm_device *drm;
1194 int err;
1195
1196 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001197 if (IS_ERR(drm))
1198 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001199
Thierry Reding9910f5c2014-05-22 09:57:15 +02001200 dev_set_drvdata(&dev->dev, drm);
1201
1202 err = drm_dev_register(drm, 0);
1203 if (err < 0)
1204 goto unref;
1205
Thierry Reding9910f5c2014-05-22 09:57:15 +02001206 return 0;
1207
1208unref:
1209 drm_dev_unref(drm);
1210 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001211}
1212
Thierry Reding9910f5c2014-05-22 09:57:15 +02001213static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001214{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001215 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1216
1217 drm_dev_unregister(drm);
1218 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001219
1220 return 0;
1221}
1222
Thierry Reding359ae682014-12-18 17:15:25 +01001223#ifdef CONFIG_PM_SLEEP
1224static int host1x_drm_suspend(struct device *dev)
1225{
1226 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001227 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001228
1229 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001230 tegra_drm_fb_suspend(drm);
1231
1232 tegra->state = drm_atomic_helper_suspend(drm);
1233 if (IS_ERR(tegra->state)) {
1234 tegra_drm_fb_resume(drm);
1235 drm_kms_helper_poll_enable(drm);
1236 return PTR_ERR(tegra->state);
1237 }
Thierry Reding359ae682014-12-18 17:15:25 +01001238
1239 return 0;
1240}
1241
1242static int host1x_drm_resume(struct device *dev)
1243{
1244 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001245 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001246
Thierry Reding986c58d2015-08-11 13:11:49 +02001247 drm_atomic_helper_resume(drm, tegra->state);
1248 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001249 drm_kms_helper_poll_enable(drm);
1250
1251 return 0;
1252}
1253#endif
1254
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001255static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1256 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001257
Thierry Reding776dc382013-10-14 14:43:22 +02001258static const struct of_device_id host1x_drm_subdevs[] = {
1259 { .compatible = "nvidia,tegra20-dc", },
1260 { .compatible = "nvidia,tegra20-hdmi", },
1261 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001262 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001263 { .compatible = "nvidia,tegra30-dc", },
1264 { .compatible = "nvidia,tegra30-hdmi", },
1265 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001266 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001267 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001268 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001269 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001270 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001271 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001272 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001273 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001274 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001275 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001276 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001277 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001278 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001279 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001280 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001281 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001282 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001283 { .compatible = "nvidia,tegra186-sor", },
1284 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001285 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001286 { /* sentinel */ }
1287};
1288
1289static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001290 .driver = {
1291 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001292 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001293 },
Thierry Reding776dc382013-10-14 14:43:22 +02001294 .probe = host1x_drm_probe,
1295 .remove = host1x_drm_remove,
1296 .subdevs = host1x_drm_subdevs,
1297};
1298
Thierry Reding473112e2015-09-10 16:07:14 +02001299static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001300 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001301 &tegra_dc_driver,
1302 &tegra_hdmi_driver,
1303 &tegra_dsi_driver,
1304 &tegra_dpaux_driver,
1305 &tegra_sor_driver,
1306 &tegra_gr2d_driver,
1307 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001308 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001309};
1310
Thierry Reding776dc382013-10-14 14:43:22 +02001311static int __init host1x_drm_init(void)
1312{
1313 int err;
1314
1315 err = host1x_driver_register(&host1x_drm_driver);
1316 if (err < 0)
1317 return err;
1318
Thierry Reding473112e2015-09-10 16:07:14 +02001319 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001320 if (err < 0)
1321 goto unregister_host1x;
1322
Thierry Reding776dc382013-10-14 14:43:22 +02001323 return 0;
1324
Thierry Reding776dc382013-10-14 14:43:22 +02001325unregister_host1x:
1326 host1x_driver_unregister(&host1x_drm_driver);
1327 return err;
1328}
1329module_init(host1x_drm_init);
1330
1331static void __exit host1x_drm_exit(void)
1332{
Thierry Reding473112e2015-09-10 16:07:14 +02001333 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001334 host1x_driver_unregister(&host1x_drm_driver);
1335}
1336module_exit(host1x_drm_exit);
1337
1338MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1339MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1340MODULE_LICENSE("GPL v2");