blob: 552046062ec85174d045c651894091fb8efeefc1 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +030018#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
19#include <asm/dma-iommu.h>
20#endif
21
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000022#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020023#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000024
25#define DRIVER_NAME "tegra"
26#define DRIVER_DESC "NVIDIA Tegra graphics"
27#define DRIVER_DATE "20120330"
28#define DRIVER_MAJOR 0
29#define DRIVER_MINOR 0
30#define DRIVER_PATCHLEVEL 0
31
Mikko Perttunenad926012016-12-14 13:16:11 +020032#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030033#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020034
Thierry Reding08943e62013-09-26 16:08:18 +020035struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010036 struct idr contexts;
37 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020038};
39
Thierry Redingab7d3f52017-12-14 13:46:20 +010040static int tegra_atomic_check(struct drm_device *drm,
41 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010042{
Thierry Reding1503ca42014-11-24 17:41:23 +010043 int err;
44
Peter Ujfalusia18301b2018-03-21 12:20:26 +020045 err = drm_atomic_helper_check(drm, state);
Thierry Redingab7d3f52017-12-14 13:46:20 +010046 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010047 return err;
48
Peter Ujfalusia18301b2018-03-21 12:20:26 +020049 return tegra_display_hub_atomic_check(drm, state);
Thierry Reding1503ca42014-11-24 17:41:23 +010050}
51
Thierry Reding31b02ca2017-10-12 17:40:46 +020052static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010053 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053054#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010055 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010056#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010057 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020058 .atomic_commit = drm_atomic_helper_commit,
59};
60
Thierry Redingc4755fb2017-11-13 11:08:13 +010061static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
62{
63 struct drm_device *drm = old_state->dev;
64 struct tegra_drm *tegra = drm->dev_private;
65
66 if (tegra->hub) {
67 drm_atomic_helper_commit_modeset_disables(drm, old_state);
68 tegra_display_hub_atomic_commit(drm, old_state);
69 drm_atomic_helper_commit_planes(drm, old_state, 0);
70 drm_atomic_helper_commit_modeset_enables(drm, old_state);
71 drm_atomic_helper_commit_hw_done(old_state);
72 drm_atomic_helper_wait_for_vblanks(drm, old_state);
73 drm_atomic_helper_cleanup_planes(drm, old_state);
74 } else {
75 drm_atomic_helper_commit_tail_rpm(old_state);
76 }
77}
78
Thierry Reding31b02ca2017-10-12 17:40:46 +020079static const struct drm_mode_config_helper_funcs
80tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010081 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010082};
83
Thierry Reding776dc382013-10-14 14:43:22 +020084static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000085{
Thierry Reding776dc382013-10-14 14:43:22 +020086 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020087 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000088 int err;
89
Thierry Reding776dc382013-10-14 14:43:22 +020090 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +020091 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +020092 return -ENOMEM;
93
Thierry Redingdf06b752014-06-26 21:41:53 +020094 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +020095 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +010096 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +020097 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +010098
Thierry Redingdf06b752014-06-26 21:41:53 +020099 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300100 if (!tegra->domain) {
101 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200102 goto free;
103 }
104
Thierry Reding24cfdc12018-04-23 08:57:45 +0200105 err = iova_cache_get();
106 if (err < 0)
107 goto domain;
108
Thierry Reding4553f732015-01-19 16:15:04 +0100109 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200110 gem_start = geometry->aperture_start;
111 gem_end = geometry->aperture_end - CARVEOUT_SZ;
112 carveout_start = gem_end + 1;
113 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100114
Mikko Perttunenad926012016-12-14 13:16:11 +0200115 order = __ffs(tegra->domain->pgsize_bitmap);
116 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100117 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200118
119 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
120 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
121
122 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100123 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200124
125 DRM_DEBUG("IOMMU apertures:\n");
126 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
127 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
128 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200129 }
130
Thierry Reding386a2a72013-09-24 13:22:17 +0200131 mutex_init(&tegra->clients_lock);
132 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100133
Thierry Reding386a2a72013-09-24 13:22:17 +0200134 drm->dev_private = tegra;
135 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000136
137 drm_mode_config_init(drm);
138
Thierry Redingf9914212014-11-26 13:03:57 +0100139 drm->mode_config.min_width = 0;
140 drm->mode_config.min_height = 0;
141
142 drm->mode_config.max_width = 4096;
143 drm->mode_config.max_height = 4096;
144
Alexandre Courbot5e911442016-11-08 16:50:42 +0900145 drm->mode_config.allow_fb_modifiers = true;
146
Peter Ujfalusia18301b2018-03-21 12:20:26 +0200147 drm->mode_config.normalize_zpos = true;
148
Thierry Reding31b02ca2017-10-12 17:40:46 +0200149 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
150 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100151
Thierry Redinge2215322014-06-27 17:19:25 +0200152 err = tegra_drm_fb_prepare(drm);
153 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100154 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200155
156 drm_kms_helper_poll_init(drm);
157
Thierry Reding776dc382013-10-14 14:43:22 +0200158 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000159 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100160 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000161
Thierry Redingc4755fb2017-11-13 11:08:13 +0100162 if (tegra->hub) {
163 err = tegra_display_hub_prepare(tegra->hub);
164 if (err < 0)
165 goto device;
166 }
167
Thierry Reding603f0cc2013-04-22 21:22:14 +0200168 /*
169 * We don't use the drm_irq_install() helpers provided by the DRM
170 * core, so we need to set this manually in order to allow the
171 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
172 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300173 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200174
Thierry Reding42e9ce02015-01-28 14:43:05 +0100175 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100176 drm->max_vblank_count = 0xffffffff;
177
Thierry Reding6e5ff992012-11-28 11:45:47 +0100178 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
179 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100180 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100181
Thierry Reding31930d42015-07-02 17:04:06 +0200182 drm_mode_config_reset(drm);
183
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000184 err = tegra_drm_fb_init(drm);
185 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100186 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000187
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000188 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100189
Thierry Redingc4755fb2017-11-13 11:08:13 +0100190hub:
191 if (tegra->hub)
192 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100193device:
194 host1x_device_exit(device);
195fbdev:
196 drm_kms_helper_poll_fini(drm);
197 tegra_drm_fb_free(drm);
198config:
199 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200200
201 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100202 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200203 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200204 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200205 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200206 }
Thierry Reding24cfdc12018-04-23 08:57:45 +0200207domain:
208 if (tegra->domain)
209 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200210free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100211 kfree(tegra);
212 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000213}
214
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200215static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000216{
Thierry Reding776dc382013-10-14 14:43:22 +0200217 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200218 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200219 int err;
220
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000221 drm_kms_helper_poll_fini(drm);
222 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100223 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200224 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000225
Thierry Reding776dc382013-10-14 14:43:22 +0200226 err = host1x_device_exit(device);
227 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200228 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200229
Thierry Redingdf06b752014-06-26 21:41:53 +0200230 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100231 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200232 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200233 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200234 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200235 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200236 }
237
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100238 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000239}
240
241static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
242{
Thierry Reding08943e62013-09-26 16:08:18 +0200243 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200244
245 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
246 if (!fpriv)
247 return -ENOMEM;
248
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100249 idr_init(&fpriv->contexts);
250 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200251 filp->driver_priv = fpriv;
252
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000253 return 0;
254}
255
Thierry Redingc88c3632013-09-26 16:08:22 +0200256static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200257{
258 context->client->ops->close_channel(context);
259 kfree(context);
260}
261
Thierry Redingc40f0f12013-10-10 11:00:33 +0200262static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100263host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200264{
265 struct drm_gem_object *gem;
266 struct tegra_bo *bo;
267
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100268 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200269 if (!gem)
270 return NULL;
271
Thierry Redingc40f0f12013-10-10 11:00:33 +0200272 bo = to_tegra_bo(gem);
273 return &bo->base;
274}
275
Thierry Reding961e3be2014-06-10 10:25:00 +0200276static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
277 struct drm_tegra_reloc __user *src,
278 struct drm_device *drm,
279 struct drm_file *file)
280{
281 u32 cmdbuf, target;
282 int err;
283
284 err = get_user(cmdbuf, &src->cmdbuf.handle);
285 if (err < 0)
286 return err;
287
288 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
289 if (err < 0)
290 return err;
291
292 err = get_user(target, &src->target.handle);
293 if (err < 0)
294 return err;
295
David Ung31f40f82015-01-20 18:37:35 -0800296 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200297 if (err < 0)
298 return err;
299
300 err = get_user(dest->shift, &src->shift);
301 if (err < 0)
302 return err;
303
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100304 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200305 if (!dest->cmdbuf.bo)
306 return -ENOENT;
307
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100308 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200309 if (!dest->target.bo)
310 return -ENOENT;
311
312 return 0;
313}
314
Thierry Redingc40f0f12013-10-10 11:00:33 +0200315int tegra_drm_submit(struct tegra_drm_context *context,
316 struct drm_tegra_submit *args, struct drm_device *drm,
317 struct drm_file *file)
318{
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200319 struct host1x_client *client = &context->client->base;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200320 unsigned int num_cmdbufs = args->num_cmdbufs;
321 unsigned int num_relocs = args->num_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300322 struct drm_tegra_cmdbuf __user *user_cmdbufs;
323 struct drm_tegra_reloc __user *user_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300324 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200325 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300326 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200327 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300328 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200329 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200330 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200331 int err;
332
Mikko Perttunena176c672017-09-28 15:50:44 +0300333 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
334 user_relocs = u64_to_user_ptr(args->relocs);
Mikko Perttunena176c672017-09-28 15:50:44 +0300335 user_syncpt = u64_to_user_ptr(args->syncpts);
336
Thierry Redingc40f0f12013-10-10 11:00:33 +0200337 /* We don't yet support other than one syncpt_incr struct per submit */
338 if (args->num_syncpts != 1)
339 return -EINVAL;
340
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300341 /* We don't yet support waitchks */
342 if (args->num_waitchks != 0)
343 return -EINVAL;
344
Thierry Redingc40f0f12013-10-10 11:00:33 +0200345 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
Thierry Reding24c94e12018-05-05 08:45:47 +0200346 args->num_relocs);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200347 if (!job)
348 return -ENOMEM;
349
350 job->num_relocs = args->num_relocs;
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200351 job->client = client;
352 job->class = client->class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200353 job->serialize = true;
354
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200355 /*
356 * Track referenced BOs so that they can be unreferenced after the
357 * submission is complete.
358 */
Thierry Reding24c94e12018-05-05 08:45:47 +0200359 num_refs = num_cmdbufs + num_relocs * 2;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200360
361 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
362 if (!refs) {
363 err = -ENOMEM;
364 goto put;
365 }
366
367 /* reuse as an iterator later */
368 num_refs = 0;
369
Thierry Redingc40f0f12013-10-10 11:00:33 +0200370 while (num_cmdbufs) {
371 struct drm_tegra_cmdbuf cmdbuf;
372 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300373 struct tegra_bo *obj;
374 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200375
Mikko Perttunena176c672017-09-28 15:50:44 +0300376 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300377 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200378 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300379 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200380
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300381 /*
382 * The maximum number of CDMA gather fetches is 16383, a higher
383 * value means the words count is malformed.
384 */
385 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
386 err = -EINVAL;
387 goto fail;
388 }
389
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100390 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200391 if (!bo) {
392 err = -ENOENT;
393 goto fail;
394 }
395
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300396 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
397 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200398 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300399
400 /*
401 * Gather buffer base address must be 4-bytes aligned,
402 * unaligned offset is malformed and cause commands stream
403 * corruption on the buffer address relocation.
404 */
Mikko Perttunen5265f032018-06-20 16:03:58 +0300405 if (offset & 3 || offset > obj->gem.size) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300406 err = -EINVAL;
407 goto fail;
408 }
409
Thierry Redingc40f0f12013-10-10 11:00:33 +0200410 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
411 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300412 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200413 }
414
Thierry Reding961e3be2014-06-10 10:25:00 +0200415 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200416 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300417 struct host1x_reloc *reloc;
418 struct tegra_bo *obj;
419
Thierry Reding06490bb2018-05-16 16:58:44 +0200420 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300421 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200422 file);
423 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200424 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300425
Thierry Reding06490bb2018-05-16 16:58:44 +0200426 reloc = &job->relocs[num_relocs];
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300427 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200428 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300429
430 /*
431 * The unaligned cmdbuf offset will cause an unaligned write
432 * during of the relocations patching, corrupting the commands
433 * stream.
434 */
435 if (reloc->cmdbuf.offset & 3 ||
436 reloc->cmdbuf.offset >= obj->gem.size) {
437 err = -EINVAL;
438 goto fail;
439 }
440
441 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200442 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300443
444 if (reloc->target.offset >= obj->gem.size) {
445 err = -EINVAL;
446 goto fail;
447 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200448 }
449
Mikko Perttunena176c672017-09-28 15:50:44 +0300450 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300451 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200452 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300453 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200454
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300455 /* check whether syncpoint ID is valid */
456 sp = host1x_syncpt_get(host1x, syncpt.id);
457 if (!sp) {
458 err = -ENOENT;
459 goto fail;
460 }
461
Thierry Redingc40f0f12013-10-10 11:00:33 +0200462 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300463 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200464 job->syncpt_incrs = syncpt.incrs;
465 job->syncpt_id = syncpt.id;
466 job->timeout = 10000;
467
468 if (args->timeout && args->timeout < 10000)
469 job->timeout = args->timeout;
470
471 err = host1x_job_pin(job, context->client->base.dev);
472 if (err)
473 goto fail;
474
475 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200476 if (err) {
477 host1x_job_unpin(job);
478 goto fail;
479 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200480
481 args->fence = job->syncpt_end;
482
Thierry Redingc40f0f12013-10-10 11:00:33 +0200483fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200484 while (num_refs--)
485 drm_gem_object_put_unlocked(refs[num_refs]);
486
487 kfree(refs);
488
489put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200490 host1x_job_put(job);
491 return err;
492}
493
494
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200495#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200496static int tegra_gem_create(struct drm_device *drm, void *data,
497 struct drm_file *file)
498{
499 struct drm_tegra_gem_create *args = data;
500 struct tegra_bo *bo;
501
Thierry Reding773af772013-10-04 22:34:01 +0200502 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200503 &args->handle);
504 if (IS_ERR(bo))
505 return PTR_ERR(bo);
506
507 return 0;
508}
509
510static int tegra_gem_mmap(struct drm_device *drm, void *data,
511 struct drm_file *file)
512{
513 struct drm_tegra_gem_mmap *args = data;
514 struct drm_gem_object *gem;
515 struct tegra_bo *bo;
516
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100517 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200518 if (!gem)
519 return -EINVAL;
520
521 bo = to_tegra_bo(gem);
522
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200523 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200524
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300525 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200526
527 return 0;
528}
529
530static int tegra_syncpt_read(struct drm_device *drm, void *data,
531 struct drm_file *file)
532{
Thierry Reding776dc382013-10-14 14:43:22 +0200533 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200534 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200535 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200536
Thierry Reding776dc382013-10-14 14:43:22 +0200537 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200538 if (!sp)
539 return -EINVAL;
540
541 args->value = host1x_syncpt_read_min(sp);
542 return 0;
543}
544
545static int tegra_syncpt_incr(struct drm_device *drm, void *data,
546 struct drm_file *file)
547{
Thierry Reding776dc382013-10-14 14:43:22 +0200548 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200549 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200550 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200551
Thierry Reding776dc382013-10-14 14:43:22 +0200552 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200553 if (!sp)
554 return -EINVAL;
555
Arto Merilainenebae30b2013-05-29 13:26:08 +0300556 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200557}
558
559static int tegra_syncpt_wait(struct drm_device *drm, void *data,
560 struct drm_file *file)
561{
Thierry Reding776dc382013-10-14 14:43:22 +0200562 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200563 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200564 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200565
Thierry Reding776dc382013-10-14 14:43:22 +0200566 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200567 if (!sp)
568 return -EINVAL;
569
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300570 return host1x_syncpt_wait(sp, args->thresh,
571 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200572 &args->value);
573}
574
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100575static int tegra_client_open(struct tegra_drm_file *fpriv,
576 struct tegra_drm_client *client,
577 struct tegra_drm_context *context)
578{
579 int err;
580
581 err = client->ops->open_channel(client, context);
582 if (err < 0)
583 return err;
584
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300585 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100586 if (err < 0) {
587 client->ops->close_channel(context);
588 return err;
589 }
590
591 context->client = client;
592 context->id = err;
593
594 return 0;
595}
596
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200597static int tegra_open_channel(struct drm_device *drm, void *data,
598 struct drm_file *file)
599{
Thierry Reding08943e62013-09-26 16:08:18 +0200600 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200601 struct tegra_drm *tegra = drm->dev_private;
602 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200603 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200604 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200605 int err = -ENODEV;
606
607 context = kzalloc(sizeof(*context), GFP_KERNEL);
608 if (!context)
609 return -ENOMEM;
610
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100611 mutex_lock(&fpriv->lock);
612
Thierry Reding776dc382013-10-14 14:43:22 +0200613 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200614 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100615 err = tegra_client_open(fpriv, client, context);
616 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200617 break;
618
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100619 args->context = context->id;
620 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200621 }
622
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100623 if (err < 0)
624 kfree(context);
625
626 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200627 return err;
628}
629
630static int tegra_close_channel(struct drm_device *drm, void *data,
631 struct drm_file *file)
632{
Thierry Reding08943e62013-09-26 16:08:18 +0200633 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200634 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200635 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100636 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200637
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100638 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200639
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300640 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100641 if (!context) {
642 err = -EINVAL;
643 goto unlock;
644 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200645
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100646 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200647 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200648
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100649unlock:
650 mutex_unlock(&fpriv->lock);
651 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200652}
653
654static int tegra_get_syncpt(struct drm_device *drm, void *data,
655 struct drm_file *file)
656{
Thierry Reding08943e62013-09-26 16:08:18 +0200657 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200658 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200659 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200660 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100661 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200662
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100663 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200664
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300665 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100666 if (!context) {
667 err = -ENODEV;
668 goto unlock;
669 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200670
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100671 if (args->index >= context->client->base.num_syncpts) {
672 err = -EINVAL;
673 goto unlock;
674 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200675
Thierry Reding53fa7f72013-09-24 15:35:40 +0200676 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200677 args->id = host1x_syncpt_id(syncpt);
678
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100679unlock:
680 mutex_unlock(&fpriv->lock);
681 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200682}
683
684static int tegra_submit(struct drm_device *drm, void *data,
685 struct drm_file *file)
686{
Thierry Reding08943e62013-09-26 16:08:18 +0200687 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200688 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200689 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100690 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200691
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100692 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200693
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300694 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100695 if (!context) {
696 err = -ENODEV;
697 goto unlock;
698 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200699
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100700 err = context->client->ops->submit(context, args, drm, file);
701
702unlock:
703 mutex_unlock(&fpriv->lock);
704 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200705}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300706
707static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
708 struct drm_file *file)
709{
710 struct tegra_drm_file *fpriv = file->driver_priv;
711 struct drm_tegra_get_syncpt_base *args = data;
712 struct tegra_drm_context *context;
713 struct host1x_syncpt_base *base;
714 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100715 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300716
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100717 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300718
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300719 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100720 if (!context) {
721 err = -ENODEV;
722 goto unlock;
723 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300724
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100725 if (args->syncpt >= context->client->base.num_syncpts) {
726 err = -EINVAL;
727 goto unlock;
728 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300729
730 syncpt = context->client->base.syncpts[args->syncpt];
731
732 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100733 if (!base) {
734 err = -ENXIO;
735 goto unlock;
736 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300737
738 args->id = host1x_syncpt_base_id(base);
739
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100740unlock:
741 mutex_unlock(&fpriv->lock);
742 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300743}
Thierry Reding7678d712014-06-03 14:56:57 +0200744
745static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
746 struct drm_file *file)
747{
748 struct drm_tegra_gem_set_tiling *args = data;
749 enum tegra_bo_tiling_mode mode;
750 struct drm_gem_object *gem;
751 unsigned long value = 0;
752 struct tegra_bo *bo;
753
754 switch (args->mode) {
755 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
756 mode = TEGRA_BO_TILING_MODE_PITCH;
757
758 if (args->value != 0)
759 return -EINVAL;
760
761 break;
762
763 case DRM_TEGRA_GEM_TILING_MODE_TILED:
764 mode = TEGRA_BO_TILING_MODE_TILED;
765
766 if (args->value != 0)
767 return -EINVAL;
768
769 break;
770
771 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
772 mode = TEGRA_BO_TILING_MODE_BLOCK;
773
774 if (args->value > 5)
775 return -EINVAL;
776
777 value = args->value;
778 break;
779
780 default:
781 return -EINVAL;
782 }
783
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100784 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200785 if (!gem)
786 return -ENOENT;
787
788 bo = to_tegra_bo(gem);
789
790 bo->tiling.mode = mode;
791 bo->tiling.value = value;
792
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300793 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200794
795 return 0;
796}
797
798static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
799 struct drm_file *file)
800{
801 struct drm_tegra_gem_get_tiling *args = data;
802 struct drm_gem_object *gem;
803 struct tegra_bo *bo;
804 int err = 0;
805
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100806 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200807 if (!gem)
808 return -ENOENT;
809
810 bo = to_tegra_bo(gem);
811
812 switch (bo->tiling.mode) {
813 case TEGRA_BO_TILING_MODE_PITCH:
814 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
815 args->value = 0;
816 break;
817
818 case TEGRA_BO_TILING_MODE_TILED:
819 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
820 args->value = 0;
821 break;
822
823 case TEGRA_BO_TILING_MODE_BLOCK:
824 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
825 args->value = bo->tiling.value;
826 break;
827
828 default:
829 err = -EINVAL;
830 break;
831 }
832
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300833 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200834
835 return err;
836}
Thierry Reding7b129082014-06-10 12:04:03 +0200837
838static int tegra_gem_set_flags(struct drm_device *drm, void *data,
839 struct drm_file *file)
840{
841 struct drm_tegra_gem_set_flags *args = data;
842 struct drm_gem_object *gem;
843 struct tegra_bo *bo;
844
845 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
846 return -EINVAL;
847
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100848 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200849 if (!gem)
850 return -ENOENT;
851
852 bo = to_tegra_bo(gem);
853 bo->flags = 0;
854
855 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
856 bo->flags |= TEGRA_BO_BOTTOM_UP;
857
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300858 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200859
860 return 0;
861}
862
863static int tegra_gem_get_flags(struct drm_device *drm, void *data,
864 struct drm_file *file)
865{
866 struct drm_tegra_gem_get_flags *args = data;
867 struct drm_gem_object *gem;
868 struct tegra_bo *bo;
869
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100870 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200871 if (!gem)
872 return -ENOENT;
873
874 bo = to_tegra_bo(gem);
875 args->flags = 0;
876
877 if (bo->flags & TEGRA_BO_BOTTOM_UP)
878 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
879
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300880 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200881
882 return 0;
883}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200884#endif
885
Rob Clarkbaa70942013-08-02 13:27:49 -0400886static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200887#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200888 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
889 DRM_UNLOCKED | DRM_RENDER_ALLOW),
890 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
891 DRM_UNLOCKED | DRM_RENDER_ALLOW),
892 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
893 DRM_UNLOCKED | DRM_RENDER_ALLOW),
894 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
895 DRM_UNLOCKED | DRM_RENDER_ALLOW),
896 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
897 DRM_UNLOCKED | DRM_RENDER_ALLOW),
898 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
899 DRM_UNLOCKED | DRM_RENDER_ALLOW),
900 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
901 DRM_UNLOCKED | DRM_RENDER_ALLOW),
902 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
903 DRM_UNLOCKED | DRM_RENDER_ALLOW),
904 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
905 DRM_UNLOCKED | DRM_RENDER_ALLOW),
906 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
907 DRM_UNLOCKED | DRM_RENDER_ALLOW),
908 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
909 DRM_UNLOCKED | DRM_RENDER_ALLOW),
910 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
911 DRM_UNLOCKED | DRM_RENDER_ALLOW),
912 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
913 DRM_UNLOCKED | DRM_RENDER_ALLOW),
914 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
915 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200916#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000917};
918
919static const struct file_operations tegra_drm_fops = {
920 .owner = THIS_MODULE,
921 .open = drm_open,
922 .release = drm_release,
923 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200924 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000925 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000926 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000927 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000928 .llseek = noop_llseek,
929};
930
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100931static int tegra_drm_context_cleanup(int id, void *p, void *data)
932{
933 struct tegra_drm_context *context = p;
934
935 tegra_drm_context_free(context);
936
937 return 0;
938}
939
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200940static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100941{
Thierry Reding08943e62013-09-26 16:08:18 +0200942 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100943
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100944 mutex_lock(&fpriv->lock);
945 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
946 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200947
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100948 idr_destroy(&fpriv->contexts);
949 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200950 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100951}
952
Thierry Redinge450fcc2013-02-13 16:13:16 +0100953#ifdef CONFIG_DEBUG_FS
954static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
955{
956 struct drm_info_node *node = (struct drm_info_node *)s->private;
957 struct drm_device *drm = node->minor->dev;
958 struct drm_framebuffer *fb;
959
960 mutex_lock(&drm->mode_config.fb_lock);
961
962 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
963 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200964 fb->base.id, fb->width, fb->height,
965 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200966 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000967 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100968 }
969
970 mutex_unlock(&drm->mode_config.fb_lock);
971
972 return 0;
973}
974
Thierry Reding28c23372015-01-23 09:16:03 +0100975static int tegra_debugfs_iova(struct seq_file *s, void *data)
976{
977 struct drm_info_node *node = (struct drm_info_node *)s->private;
978 struct drm_device *drm = node->minor->dev;
979 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100980 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100981
Michał Mirosław68d890a2017-08-14 23:53:45 +0200982 if (tegra->domain) {
983 mutex_lock(&tegra->mm_lock);
984 drm_mm_print(&tegra->mm, &p);
985 mutex_unlock(&tegra->mm_lock);
986 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100987
988 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100989}
990
Thierry Redinge450fcc2013-02-13 16:13:16 +0100991static struct drm_info_list tegra_debugfs_list[] = {
992 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +0100993 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +0100994};
995
996static int tegra_debugfs_init(struct drm_minor *minor)
997{
998 return drm_debugfs_create_files(tegra_debugfs_list,
999 ARRAY_SIZE(tegra_debugfs_list),
1000 minor->debugfs_root, minor);
1001}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001002#endif
1003
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001004static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001005 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001006 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001007 .load = tegra_drm_load,
1008 .unload = tegra_drm_unload,
1009 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001010 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001011 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001012
Thierry Redinge450fcc2013-02-13 16:13:16 +01001013#if defined(CONFIG_DEBUG_FS)
1014 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001015#endif
1016
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001017 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001018 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001019
1020 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1021 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1022 .gem_prime_export = tegra_gem_prime_export,
1023 .gem_prime_import = tegra_gem_prime_import,
1024
Arto Merilainende2ba662013-03-22 16:34:08 +02001025 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001026
1027 .ioctls = tegra_drm_ioctls,
1028 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1029 .fops = &tegra_drm_fops,
1030
1031 .name = DRIVER_NAME,
1032 .desc = DRIVER_DESC,
1033 .date = DRIVER_DATE,
1034 .major = DRIVER_MAJOR,
1035 .minor = DRIVER_MINOR,
1036 .patchlevel = DRIVER_PATCHLEVEL,
1037};
Thierry Reding776dc382013-10-14 14:43:22 +02001038
1039int tegra_drm_register_client(struct tegra_drm *tegra,
1040 struct tegra_drm_client *client)
1041{
1042 mutex_lock(&tegra->clients_lock);
1043 list_add_tail(&client->list, &tegra->clients);
1044 mutex_unlock(&tegra->clients_lock);
1045
1046 return 0;
1047}
1048
1049int tegra_drm_unregister_client(struct tegra_drm *tegra,
1050 struct tegra_drm_client *client)
1051{
1052 mutex_lock(&tegra->clients_lock);
1053 list_del_init(&client->list);
1054 mutex_unlock(&tegra->clients_lock);
1055
1056 return 0;
1057}
1058
Thierry Reding0c407de2018-05-04 15:02:24 +02001059struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1060 bool shared)
1061{
1062 struct drm_device *drm = dev_get_drvdata(client->parent);
1063 struct tegra_drm *tegra = drm->dev_private;
1064 struct iommu_group *group = NULL;
1065 int err;
1066
1067 if (tegra->domain) {
1068 group = iommu_group_get(client->dev);
1069 if (!group) {
1070 dev_err(client->dev, "failed to get IOMMU group\n");
1071 return ERR_PTR(-ENODEV);
1072 }
1073
1074 if (!shared || (shared && (group != tegra->group))) {
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +03001075#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
1076 if (client->dev->archdata.mapping) {
1077 struct dma_iommu_mapping *mapping =
1078 to_dma_iommu_mapping(client->dev);
1079 arm_iommu_detach_device(client->dev);
1080 arm_iommu_release_mapping(mapping);
1081 }
1082#endif
Thierry Reding0c407de2018-05-04 15:02:24 +02001083 err = iommu_attach_group(tegra->domain, group);
1084 if (err < 0) {
1085 iommu_group_put(group);
1086 return ERR_PTR(err);
1087 }
1088
1089 if (shared && !tegra->group)
1090 tegra->group = group;
1091 }
1092 }
1093
1094 return group;
1095}
1096
1097void host1x_client_iommu_detach(struct host1x_client *client,
1098 struct iommu_group *group)
1099{
1100 struct drm_device *drm = dev_get_drvdata(client->parent);
1101 struct tegra_drm *tegra = drm->dev_private;
1102
1103 if (group) {
1104 if (group == tegra->group) {
1105 iommu_detach_group(tegra->domain, group);
1106 tegra->group = NULL;
1107 }
1108
1109 iommu_group_put(group);
1110 }
1111}
1112
Thierry Reding67485fb2017-11-09 13:17:11 +01001113void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001114{
1115 struct iova *alloc;
1116 void *virt;
1117 gfp_t gfp;
1118 int err;
1119
1120 if (tegra->domain)
1121 size = iova_align(&tegra->carveout.domain, size);
1122 else
1123 size = PAGE_ALIGN(size);
1124
1125 gfp = GFP_KERNEL | __GFP_ZERO;
1126 if (!tegra->domain) {
1127 /*
1128 * Many units only support 32-bit addresses, even on 64-bit
1129 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1130 * virtual address space, force allocations to be in the
1131 * lower 32-bit range.
1132 */
1133 gfp |= GFP_DMA;
1134 }
1135
1136 virt = (void *)__get_free_pages(gfp, get_order(size));
1137 if (!virt)
1138 return ERR_PTR(-ENOMEM);
1139
1140 if (!tegra->domain) {
1141 /*
1142 * If IOMMU is disabled, devices address physical memory
1143 * directly.
1144 */
1145 *dma = virt_to_phys(virt);
1146 return virt;
1147 }
1148
1149 alloc = alloc_iova(&tegra->carveout.domain,
1150 size >> tegra->carveout.shift,
1151 tegra->carveout.limit, true);
1152 if (!alloc) {
1153 err = -EBUSY;
1154 goto free_pages;
1155 }
1156
1157 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1158 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1159 size, IOMMU_READ | IOMMU_WRITE);
1160 if (err < 0)
1161 goto free_iova;
1162
1163 return virt;
1164
1165free_iova:
1166 __free_iova(&tegra->carveout.domain, alloc);
1167free_pages:
1168 free_pages((unsigned long)virt, get_order(size));
1169
1170 return ERR_PTR(err);
1171}
1172
1173void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1174 dma_addr_t dma)
1175{
1176 if (tegra->domain)
1177 size = iova_align(&tegra->carveout.domain, size);
1178 else
1179 size = PAGE_ALIGN(size);
1180
1181 if (tegra->domain) {
1182 iommu_unmap(tegra->domain, dma, size);
1183 free_iova(&tegra->carveout.domain,
1184 iova_pfn(&tegra->carveout.domain, dma));
1185 }
1186
1187 free_pages((unsigned long)virt, get_order(size));
1188}
1189
Thierry Reding9910f5c2014-05-22 09:57:15 +02001190static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001191{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001192 struct drm_driver *driver = &tegra_drm_driver;
1193 struct drm_device *drm;
1194 int err;
1195
1196 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001197 if (IS_ERR(drm))
1198 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001199
Thierry Reding9910f5c2014-05-22 09:57:15 +02001200 dev_set_drvdata(&dev->dev, drm);
1201
1202 err = drm_dev_register(drm, 0);
1203 if (err < 0)
1204 goto unref;
1205
Thierry Reding9910f5c2014-05-22 09:57:15 +02001206 return 0;
1207
1208unref:
1209 drm_dev_unref(drm);
1210 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001211}
1212
Thierry Reding9910f5c2014-05-22 09:57:15 +02001213static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001214{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001215 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1216
1217 drm_dev_unregister(drm);
1218 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001219
1220 return 0;
1221}
1222
Thierry Reding359ae682014-12-18 17:15:25 +01001223#ifdef CONFIG_PM_SLEEP
1224static int host1x_drm_suspend(struct device *dev)
1225{
1226 struct drm_device *drm = dev_get_drvdata(dev);
1227
Souptick Joarder53f1e062018-08-01 01:37:05 +05301228 return drm_mode_config_helper_suspend(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001229}
1230
1231static int host1x_drm_resume(struct device *dev)
1232{
1233 struct drm_device *drm = dev_get_drvdata(dev);
1234
Souptick Joarder53f1e062018-08-01 01:37:05 +05301235 return drm_mode_config_helper_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001236}
1237#endif
1238
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001239static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1240 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001241
Thierry Reding776dc382013-10-14 14:43:22 +02001242static const struct of_device_id host1x_drm_subdevs[] = {
1243 { .compatible = "nvidia,tegra20-dc", },
1244 { .compatible = "nvidia,tegra20-hdmi", },
1245 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001246 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001247 { .compatible = "nvidia,tegra30-dc", },
1248 { .compatible = "nvidia,tegra30-hdmi", },
1249 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001250 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001251 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001252 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001253 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001254 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001255 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001256 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001257 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001258 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001259 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001260 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001261 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001262 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001263 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001264 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001265 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001266 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001267 { .compatible = "nvidia,tegra186-sor", },
1268 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001269 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding5725daa2018-09-21 12:27:43 +02001270 { .compatible = "nvidia,tegra194-display", },
Thierry Reding47443192018-09-21 12:27:44 +02001271 { .compatible = "nvidia,tegra194-dc", },
Thierry Reding9b6c14b2018-09-21 12:27:46 +02001272 { .compatible = "nvidia,tegra194-sor", },
Thierry Reding776dc382013-10-14 14:43:22 +02001273 { /* sentinel */ }
1274};
1275
1276static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001277 .driver = {
1278 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001279 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001280 },
Thierry Reding776dc382013-10-14 14:43:22 +02001281 .probe = host1x_drm_probe,
1282 .remove = host1x_drm_remove,
1283 .subdevs = host1x_drm_subdevs,
1284};
1285
Thierry Reding473112e2015-09-10 16:07:14 +02001286static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001287 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001288 &tegra_dc_driver,
1289 &tegra_hdmi_driver,
1290 &tegra_dsi_driver,
1291 &tegra_dpaux_driver,
1292 &tegra_sor_driver,
1293 &tegra_gr2d_driver,
1294 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001295 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001296};
1297
Thierry Reding776dc382013-10-14 14:43:22 +02001298static int __init host1x_drm_init(void)
1299{
1300 int err;
1301
1302 err = host1x_driver_register(&host1x_drm_driver);
1303 if (err < 0)
1304 return err;
1305
Thierry Reding473112e2015-09-10 16:07:14 +02001306 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001307 if (err < 0)
1308 goto unregister_host1x;
1309
Thierry Reding776dc382013-10-14 14:43:22 +02001310 return 0;
1311
Thierry Reding776dc382013-10-14 14:43:22 +02001312unregister_host1x:
1313 host1x_driver_unregister(&host1x_drm_driver);
1314 return err;
1315}
1316module_init(host1x_drm_init);
1317
1318static void __exit host1x_drm_exit(void)
1319{
Thierry Reding473112e2015-09-10 16:07:14 +02001320 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001321 host1x_driver_unregister(&host1x_drm_driver);
1322}
1323module_exit(host1x_drm_exit);
1324
1325MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1326MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1327MODULE_LICENSE("GPL v2");