blob: ff931d3508a99f259cad5a4ab9d3dac9eca8f4da [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingab7d3f52017-12-14 13:46:20 +010036static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
38{
39 int err;
40
41 err = drm_atomic_helper_check_modeset(drm, state);
42 if (err < 0)
43 return err;
44
45 err = drm_atomic_normalize_zpos(drm, state);
46 if (err < 0)
47 return err;
48
49 err = drm_atomic_helper_check_planes(drm, state);
50 if (err < 0)
51 return err;
52
53 if (state->legacy_cursor_update)
54 state->async_update = !drm_atomic_helper_async_check(drm, state);
55
56 return 0;
57}
58
Thierry Redingc4755fb2017-11-13 11:08:13 +010059static struct drm_atomic_state *
60tegra_atomic_state_alloc(struct drm_device *drm)
61{
62 struct tegra_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
63
64 if (!state || drm_atomic_state_init(drm, &state->base) < 0) {
65 kfree(state);
66 return NULL;
67 }
68
69 return &state->base;
70}
71
72static void tegra_atomic_state_clear(struct drm_atomic_state *state)
73{
74 struct tegra_atomic_state *tegra = to_tegra_atomic_state(state);
75
76 drm_atomic_state_default_clear(state);
77 tegra->clk_disp = NULL;
78 tegra->dc = NULL;
79 tegra->rate = 0;
80}
81
82static void tegra_atomic_state_free(struct drm_atomic_state *state)
83{
84 drm_atomic_state_default_release(state);
85 kfree(state);
86}
87
Thierry Reding31b02ca2017-10-12 17:40:46 +020088static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010089 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053090#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +010091 .output_poll_changed = tegra_fb_output_poll_changed,
92#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010093 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020094 .atomic_commit = drm_atomic_helper_commit,
Thierry Redingc4755fb2017-11-13 11:08:13 +010095 .atomic_state_alloc = tegra_atomic_state_alloc,
96 .atomic_state_clear = tegra_atomic_state_clear,
97 .atomic_state_free = tegra_atomic_state_free,
Thierry Reding31b02ca2017-10-12 17:40:46 +020098};
99
Thierry Redingc4755fb2017-11-13 11:08:13 +0100100static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
101{
102 struct drm_device *drm = old_state->dev;
103 struct tegra_drm *tegra = drm->dev_private;
104
105 if (tegra->hub) {
106 drm_atomic_helper_commit_modeset_disables(drm, old_state);
107 tegra_display_hub_atomic_commit(drm, old_state);
108 drm_atomic_helper_commit_planes(drm, old_state, 0);
109 drm_atomic_helper_commit_modeset_enables(drm, old_state);
110 drm_atomic_helper_commit_hw_done(old_state);
111 drm_atomic_helper_wait_for_vblanks(drm, old_state);
112 drm_atomic_helper_cleanup_planes(drm, old_state);
113 } else {
114 drm_atomic_helper_commit_tail_rpm(old_state);
115 }
116}
117
Thierry Reding31b02ca2017-10-12 17:40:46 +0200118static const struct drm_mode_config_helper_funcs
119tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +0100120 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +0100121};
122
Thierry Reding776dc382013-10-14 14:43:22 +0200123static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000124{
Thierry Reding776dc382013-10-14 14:43:22 +0200125 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200126 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000127 int err;
128
Thierry Reding776dc382013-10-14 14:43:22 +0200129 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200130 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200131 return -ENOMEM;
132
Thierry Redingdf06b752014-06-26 21:41:53 +0200133 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200134 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100135 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200136 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100137
Thierry Redingdf06b752014-06-26 21:41:53 +0200138 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300139 if (!tegra->domain) {
140 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200141 goto free;
142 }
143
Thierry Reding4553f732015-01-19 16:15:04 +0100144 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200145 gem_start = geometry->aperture_start;
146 gem_end = geometry->aperture_end - CARVEOUT_SZ;
147 carveout_start = gem_end + 1;
148 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100149
Mikko Perttunenad926012016-12-14 13:16:11 +0200150 order = __ffs(tegra->domain->pgsize_bitmap);
151 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100152 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200153
154 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
155 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
156
157 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100158 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200159
160 DRM_DEBUG("IOMMU apertures:\n");
161 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
162 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
163 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200164 }
165
Thierry Reding386a2a72013-09-24 13:22:17 +0200166 mutex_init(&tegra->clients_lock);
167 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100168
Thierry Reding386a2a72013-09-24 13:22:17 +0200169 drm->dev_private = tegra;
170 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000171
172 drm_mode_config_init(drm);
173
Thierry Redingf9914212014-11-26 13:03:57 +0100174 drm->mode_config.min_width = 0;
175 drm->mode_config.min_height = 0;
176
177 drm->mode_config.max_width = 4096;
178 drm->mode_config.max_height = 4096;
179
Alexandre Courbot5e911442016-11-08 16:50:42 +0900180 drm->mode_config.allow_fb_modifiers = true;
181
Thierry Reding31b02ca2017-10-12 17:40:46 +0200182 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
183 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100184
Thierry Redinge2215322014-06-27 17:19:25 +0200185 err = tegra_drm_fb_prepare(drm);
186 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100187 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200188
189 drm_kms_helper_poll_init(drm);
190
Thierry Reding776dc382013-10-14 14:43:22 +0200191 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000192 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100193 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000194
Thierry Redingc4755fb2017-11-13 11:08:13 +0100195 if (tegra->hub) {
196 err = tegra_display_hub_prepare(tegra->hub);
197 if (err < 0)
198 goto device;
199 }
200
Thierry Reding603f0cc2013-04-22 21:22:14 +0200201 /*
202 * We don't use the drm_irq_install() helpers provided by the DRM
203 * core, so we need to set this manually in order to allow the
204 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
205 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300206 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200207
Thierry Reding42e9ce02015-01-28 14:43:05 +0100208 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100209 drm->max_vblank_count = 0xffffffff;
210
Thierry Reding6e5ff992012-11-28 11:45:47 +0100211 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
212 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100213 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100214
Thierry Reding31930d42015-07-02 17:04:06 +0200215 drm_mode_config_reset(drm);
216
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000217 err = tegra_drm_fb_init(drm);
218 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100219 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000220
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000221 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100222
Thierry Redingc4755fb2017-11-13 11:08:13 +0100223hub:
224 if (tegra->hub)
225 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100226device:
227 host1x_device_exit(device);
228fbdev:
229 drm_kms_helper_poll_fini(drm);
230 tegra_drm_fb_free(drm);
231config:
232 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200233
234 if (tegra->domain) {
235 iommu_domain_free(tegra->domain);
236 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100237 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200238 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200239 }
240free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100241 kfree(tegra);
242 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000243}
244
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200245static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000246{
Thierry Reding776dc382013-10-14 14:43:22 +0200247 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200248 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200249 int err;
250
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000251 drm_kms_helper_poll_fini(drm);
252 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200253 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000254
Thierry Reding776dc382013-10-14 14:43:22 +0200255 err = host1x_device_exit(device);
256 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200257 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200258
Thierry Redingdf06b752014-06-26 21:41:53 +0200259 if (tegra->domain) {
260 iommu_domain_free(tegra->domain);
261 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100262 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200263 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200264 }
265
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100266 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000267}
268
269static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
270{
Thierry Reding08943e62013-09-26 16:08:18 +0200271 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200272
273 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
274 if (!fpriv)
275 return -ENOMEM;
276
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100277 idr_init(&fpriv->contexts);
278 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200279 filp->driver_priv = fpriv;
280
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000281 return 0;
282}
283
Thierry Redingc88c3632013-09-26 16:08:22 +0200284static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200285{
286 context->client->ops->close_channel(context);
287 kfree(context);
288}
289
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000290static void tegra_drm_lastclose(struct drm_device *drm)
291{
Archit Tanejab110ef32015-10-27 13:40:59 +0530292#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200293 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000294
Thierry Reding386a2a72013-09-24 13:22:17 +0200295 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100296#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000297}
298
Thierry Redingc40f0f12013-10-10 11:00:33 +0200299static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100300host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200301{
302 struct drm_gem_object *gem;
303 struct tegra_bo *bo;
304
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100305 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200306 if (!gem)
307 return NULL;
308
Thierry Redingc40f0f12013-10-10 11:00:33 +0200309 bo = to_tegra_bo(gem);
310 return &bo->base;
311}
312
Thierry Reding961e3be2014-06-10 10:25:00 +0200313static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
314 struct drm_tegra_reloc __user *src,
315 struct drm_device *drm,
316 struct drm_file *file)
317{
318 u32 cmdbuf, target;
319 int err;
320
321 err = get_user(cmdbuf, &src->cmdbuf.handle);
322 if (err < 0)
323 return err;
324
325 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
326 if (err < 0)
327 return err;
328
329 err = get_user(target, &src->target.handle);
330 if (err < 0)
331 return err;
332
David Ung31f40f82015-01-20 18:37:35 -0800333 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200334 if (err < 0)
335 return err;
336
337 err = get_user(dest->shift, &src->shift);
338 if (err < 0)
339 return err;
340
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100341 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200342 if (!dest->cmdbuf.bo)
343 return -ENOENT;
344
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100345 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200346 if (!dest->target.bo)
347 return -ENOENT;
348
349 return 0;
350}
351
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300352static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
353 struct drm_tegra_waitchk __user *src,
354 struct drm_file *file)
355{
356 u32 cmdbuf;
357 int err;
358
359 err = get_user(cmdbuf, &src->handle);
360 if (err < 0)
361 return err;
362
363 err = get_user(dest->offset, &src->offset);
364 if (err < 0)
365 return err;
366
367 err = get_user(dest->syncpt_id, &src->syncpt);
368 if (err < 0)
369 return err;
370
371 err = get_user(dest->thresh, &src->thresh);
372 if (err < 0)
373 return err;
374
375 dest->bo = host1x_bo_lookup(file, cmdbuf);
376 if (!dest->bo)
377 return -ENOENT;
378
379 return 0;
380}
381
Thierry Redingc40f0f12013-10-10 11:00:33 +0200382int tegra_drm_submit(struct tegra_drm_context *context,
383 struct drm_tegra_submit *args, struct drm_device *drm,
384 struct drm_file *file)
385{
386 unsigned int num_cmdbufs = args->num_cmdbufs;
387 unsigned int num_relocs = args->num_relocs;
388 unsigned int num_waitchks = args->num_waitchks;
Mikko Perttunena176c672017-09-28 15:50:44 +0300389 struct drm_tegra_cmdbuf __user *user_cmdbufs;
390 struct drm_tegra_reloc __user *user_relocs;
391 struct drm_tegra_waitchk __user *user_waitchks;
392 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200393 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300394 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200395 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300396 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200397 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200398 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200399 int err;
400
Mikko Perttunena176c672017-09-28 15:50:44 +0300401 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
402 user_relocs = u64_to_user_ptr(args->relocs);
403 user_waitchks = u64_to_user_ptr(args->waitchks);
404 user_syncpt = u64_to_user_ptr(args->syncpts);
405
Thierry Redingc40f0f12013-10-10 11:00:33 +0200406 /* We don't yet support other than one syncpt_incr struct per submit */
407 if (args->num_syncpts != 1)
408 return -EINVAL;
409
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300410 /* We don't yet support waitchks */
411 if (args->num_waitchks != 0)
412 return -EINVAL;
413
Thierry Redingc40f0f12013-10-10 11:00:33 +0200414 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
415 args->num_relocs, args->num_waitchks);
416 if (!job)
417 return -ENOMEM;
418
419 job->num_relocs = args->num_relocs;
420 job->num_waitchk = args->num_waitchks;
421 job->client = (u32)args->context;
422 job->class = context->client->base.class;
423 job->serialize = true;
424
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200425 /*
426 * Track referenced BOs so that they can be unreferenced after the
427 * submission is complete.
428 */
429 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
430
431 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
432 if (!refs) {
433 err = -ENOMEM;
434 goto put;
435 }
436
437 /* reuse as an iterator later */
438 num_refs = 0;
439
Thierry Redingc40f0f12013-10-10 11:00:33 +0200440 while (num_cmdbufs) {
441 struct drm_tegra_cmdbuf cmdbuf;
442 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300443 struct tegra_bo *obj;
444 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200445
Mikko Perttunena176c672017-09-28 15:50:44 +0300446 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300447 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200448 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300449 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200450
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300451 /*
452 * The maximum number of CDMA gather fetches is 16383, a higher
453 * value means the words count is malformed.
454 */
455 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
456 err = -EINVAL;
457 goto fail;
458 }
459
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100460 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200461 if (!bo) {
462 err = -ENOENT;
463 goto fail;
464 }
465
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300466 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
467 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200468 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300469
470 /*
471 * Gather buffer base address must be 4-bytes aligned,
472 * unaligned offset is malformed and cause commands stream
473 * corruption on the buffer address relocation.
474 */
475 if (offset & 3 || offset >= obj->gem.size) {
476 err = -EINVAL;
477 goto fail;
478 }
479
Thierry Redingc40f0f12013-10-10 11:00:33 +0200480 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
481 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300482 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200483 }
484
Thierry Reding961e3be2014-06-10 10:25:00 +0200485 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200486 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300487 struct host1x_reloc *reloc;
488 struct tegra_bo *obj;
489
Thierry Reding961e3be2014-06-10 10:25:00 +0200490 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300491 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200492 file);
493 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200494 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300495
496 reloc = &job->relocarray[num_relocs];
497 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200498 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300499
500 /*
501 * The unaligned cmdbuf offset will cause an unaligned write
502 * during of the relocations patching, corrupting the commands
503 * stream.
504 */
505 if (reloc->cmdbuf.offset & 3 ||
506 reloc->cmdbuf.offset >= obj->gem.size) {
507 err = -EINVAL;
508 goto fail;
509 }
510
511 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200512 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300513
514 if (reloc->target.offset >= obj->gem.size) {
515 err = -EINVAL;
516 goto fail;
517 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200518 }
519
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300520 /* copy and resolve waitchks from submit */
521 while (num_waitchks--) {
522 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
523 struct tegra_bo *obj;
524
Mikko Perttunena176c672017-09-28 15:50:44 +0300525 err = host1x_waitchk_copy_from_user(
526 wait, &user_waitchks[num_waitchks], file);
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300527 if (err < 0)
528 goto fail;
529
530 obj = host1x_to_tegra_bo(wait->bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200531 refs[num_refs++] = &obj->gem;
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300532
533 /*
534 * The unaligned offset will cause an unaligned write during
535 * of the waitchks patching, corrupting the commands stream.
536 */
537 if (wait->offset & 3 ||
538 wait->offset >= obj->gem.size) {
539 err = -EINVAL;
540 goto fail;
541 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300542 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200543
Mikko Perttunena176c672017-09-28 15:50:44 +0300544 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300545 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200546 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300547 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200548
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300549 /* check whether syncpoint ID is valid */
550 sp = host1x_syncpt_get(host1x, syncpt.id);
551 if (!sp) {
552 err = -ENOENT;
553 goto fail;
554 }
555
Thierry Redingc40f0f12013-10-10 11:00:33 +0200556 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300557 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200558 job->syncpt_incrs = syncpt.incrs;
559 job->syncpt_id = syncpt.id;
560 job->timeout = 10000;
561
562 if (args->timeout && args->timeout < 10000)
563 job->timeout = args->timeout;
564
565 err = host1x_job_pin(job, context->client->base.dev);
566 if (err)
567 goto fail;
568
569 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200570 if (err) {
571 host1x_job_unpin(job);
572 goto fail;
573 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200574
575 args->fence = job->syncpt_end;
576
Thierry Redingc40f0f12013-10-10 11:00:33 +0200577fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200578 while (num_refs--)
579 drm_gem_object_put_unlocked(refs[num_refs]);
580
581 kfree(refs);
582
583put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200584 host1x_job_put(job);
585 return err;
586}
587
588
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200589#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200590static int tegra_gem_create(struct drm_device *drm, void *data,
591 struct drm_file *file)
592{
593 struct drm_tegra_gem_create *args = data;
594 struct tegra_bo *bo;
595
Thierry Reding773af772013-10-04 22:34:01 +0200596 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200597 &args->handle);
598 if (IS_ERR(bo))
599 return PTR_ERR(bo);
600
601 return 0;
602}
603
604static int tegra_gem_mmap(struct drm_device *drm, void *data,
605 struct drm_file *file)
606{
607 struct drm_tegra_gem_mmap *args = data;
608 struct drm_gem_object *gem;
609 struct tegra_bo *bo;
610
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100611 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200612 if (!gem)
613 return -EINVAL;
614
615 bo = to_tegra_bo(gem);
616
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200617 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200618
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300619 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200620
621 return 0;
622}
623
624static int tegra_syncpt_read(struct drm_device *drm, void *data,
625 struct drm_file *file)
626{
Thierry Reding776dc382013-10-14 14:43:22 +0200627 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200628 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200629 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200630
Thierry Reding776dc382013-10-14 14:43:22 +0200631 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200632 if (!sp)
633 return -EINVAL;
634
635 args->value = host1x_syncpt_read_min(sp);
636 return 0;
637}
638
639static int tegra_syncpt_incr(struct drm_device *drm, void *data,
640 struct drm_file *file)
641{
Thierry Reding776dc382013-10-14 14:43:22 +0200642 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200643 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200644 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200645
Thierry Reding776dc382013-10-14 14:43:22 +0200646 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200647 if (!sp)
648 return -EINVAL;
649
Arto Merilainenebae30b2013-05-29 13:26:08 +0300650 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200651}
652
653static int tegra_syncpt_wait(struct drm_device *drm, void *data,
654 struct drm_file *file)
655{
Thierry Reding776dc382013-10-14 14:43:22 +0200656 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200657 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200658 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200659
Thierry Reding776dc382013-10-14 14:43:22 +0200660 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200661 if (!sp)
662 return -EINVAL;
663
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300664 return host1x_syncpt_wait(sp, args->thresh,
665 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200666 &args->value);
667}
668
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100669static int tegra_client_open(struct tegra_drm_file *fpriv,
670 struct tegra_drm_client *client,
671 struct tegra_drm_context *context)
672{
673 int err;
674
675 err = client->ops->open_channel(client, context);
676 if (err < 0)
677 return err;
678
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300679 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100680 if (err < 0) {
681 client->ops->close_channel(context);
682 return err;
683 }
684
685 context->client = client;
686 context->id = err;
687
688 return 0;
689}
690
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200691static int tegra_open_channel(struct drm_device *drm, void *data,
692 struct drm_file *file)
693{
Thierry Reding08943e62013-09-26 16:08:18 +0200694 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200695 struct tegra_drm *tegra = drm->dev_private;
696 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200697 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200698 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200699 int err = -ENODEV;
700
701 context = kzalloc(sizeof(*context), GFP_KERNEL);
702 if (!context)
703 return -ENOMEM;
704
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100705 mutex_lock(&fpriv->lock);
706
Thierry Reding776dc382013-10-14 14:43:22 +0200707 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200708 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100709 err = tegra_client_open(fpriv, client, context);
710 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200711 break;
712
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100713 args->context = context->id;
714 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200715 }
716
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100717 if (err < 0)
718 kfree(context);
719
720 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200721 return err;
722}
723
724static int tegra_close_channel(struct drm_device *drm, void *data,
725 struct drm_file *file)
726{
Thierry Reding08943e62013-09-26 16:08:18 +0200727 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200728 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200729 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100730 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200731
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100732 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200733
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300734 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100735 if (!context) {
736 err = -EINVAL;
737 goto unlock;
738 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200739
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100740 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200741 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200742
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100743unlock:
744 mutex_unlock(&fpriv->lock);
745 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200746}
747
748static int tegra_get_syncpt(struct drm_device *drm, void *data,
749 struct drm_file *file)
750{
Thierry Reding08943e62013-09-26 16:08:18 +0200751 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200752 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200753 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200754 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100755 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200756
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100757 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200758
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300759 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100760 if (!context) {
761 err = -ENODEV;
762 goto unlock;
763 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200764
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100765 if (args->index >= context->client->base.num_syncpts) {
766 err = -EINVAL;
767 goto unlock;
768 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200769
Thierry Reding53fa7f72013-09-24 15:35:40 +0200770 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200771 args->id = host1x_syncpt_id(syncpt);
772
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100773unlock:
774 mutex_unlock(&fpriv->lock);
775 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200776}
777
778static int tegra_submit(struct drm_device *drm, void *data,
779 struct drm_file *file)
780{
Thierry Reding08943e62013-09-26 16:08:18 +0200781 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200782 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200783 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100784 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200785
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100786 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200787
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300788 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100789 if (!context) {
790 err = -ENODEV;
791 goto unlock;
792 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200793
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100794 err = context->client->ops->submit(context, args, drm, file);
795
796unlock:
797 mutex_unlock(&fpriv->lock);
798 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200799}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300800
801static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
802 struct drm_file *file)
803{
804 struct tegra_drm_file *fpriv = file->driver_priv;
805 struct drm_tegra_get_syncpt_base *args = data;
806 struct tegra_drm_context *context;
807 struct host1x_syncpt_base *base;
808 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100809 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300810
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100811 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300812
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300813 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100814 if (!context) {
815 err = -ENODEV;
816 goto unlock;
817 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300818
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100819 if (args->syncpt >= context->client->base.num_syncpts) {
820 err = -EINVAL;
821 goto unlock;
822 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300823
824 syncpt = context->client->base.syncpts[args->syncpt];
825
826 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100827 if (!base) {
828 err = -ENXIO;
829 goto unlock;
830 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300831
832 args->id = host1x_syncpt_base_id(base);
833
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100834unlock:
835 mutex_unlock(&fpriv->lock);
836 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300837}
Thierry Reding7678d712014-06-03 14:56:57 +0200838
839static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
840 struct drm_file *file)
841{
842 struct drm_tegra_gem_set_tiling *args = data;
843 enum tegra_bo_tiling_mode mode;
844 struct drm_gem_object *gem;
845 unsigned long value = 0;
846 struct tegra_bo *bo;
847
848 switch (args->mode) {
849 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
850 mode = TEGRA_BO_TILING_MODE_PITCH;
851
852 if (args->value != 0)
853 return -EINVAL;
854
855 break;
856
857 case DRM_TEGRA_GEM_TILING_MODE_TILED:
858 mode = TEGRA_BO_TILING_MODE_TILED;
859
860 if (args->value != 0)
861 return -EINVAL;
862
863 break;
864
865 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
866 mode = TEGRA_BO_TILING_MODE_BLOCK;
867
868 if (args->value > 5)
869 return -EINVAL;
870
871 value = args->value;
872 break;
873
874 default:
875 return -EINVAL;
876 }
877
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100878 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200879 if (!gem)
880 return -ENOENT;
881
882 bo = to_tegra_bo(gem);
883
884 bo->tiling.mode = mode;
885 bo->tiling.value = value;
886
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300887 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200888
889 return 0;
890}
891
892static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
893 struct drm_file *file)
894{
895 struct drm_tegra_gem_get_tiling *args = data;
896 struct drm_gem_object *gem;
897 struct tegra_bo *bo;
898 int err = 0;
899
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100900 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200901 if (!gem)
902 return -ENOENT;
903
904 bo = to_tegra_bo(gem);
905
906 switch (bo->tiling.mode) {
907 case TEGRA_BO_TILING_MODE_PITCH:
908 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
909 args->value = 0;
910 break;
911
912 case TEGRA_BO_TILING_MODE_TILED:
913 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
914 args->value = 0;
915 break;
916
917 case TEGRA_BO_TILING_MODE_BLOCK:
918 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
919 args->value = bo->tiling.value;
920 break;
921
922 default:
923 err = -EINVAL;
924 break;
925 }
926
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300927 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200928
929 return err;
930}
Thierry Reding7b129082014-06-10 12:04:03 +0200931
932static int tegra_gem_set_flags(struct drm_device *drm, void *data,
933 struct drm_file *file)
934{
935 struct drm_tegra_gem_set_flags *args = data;
936 struct drm_gem_object *gem;
937 struct tegra_bo *bo;
938
939 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
940 return -EINVAL;
941
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100942 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200943 if (!gem)
944 return -ENOENT;
945
946 bo = to_tegra_bo(gem);
947 bo->flags = 0;
948
949 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
950 bo->flags |= TEGRA_BO_BOTTOM_UP;
951
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300952 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200953
954 return 0;
955}
956
957static int tegra_gem_get_flags(struct drm_device *drm, void *data,
958 struct drm_file *file)
959{
960 struct drm_tegra_gem_get_flags *args = data;
961 struct drm_gem_object *gem;
962 struct tegra_bo *bo;
963
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100964 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200965 if (!gem)
966 return -ENOENT;
967
968 bo = to_tegra_bo(gem);
969 args->flags = 0;
970
971 if (bo->flags & TEGRA_BO_BOTTOM_UP)
972 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
973
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300974 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200975
976 return 0;
977}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200978#endif
979
Rob Clarkbaa70942013-08-02 13:27:49 -0400980static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200981#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200982 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
983 DRM_UNLOCKED | DRM_RENDER_ALLOW),
984 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
985 DRM_UNLOCKED | DRM_RENDER_ALLOW),
986 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
987 DRM_UNLOCKED | DRM_RENDER_ALLOW),
988 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
989 DRM_UNLOCKED | DRM_RENDER_ALLOW),
990 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
991 DRM_UNLOCKED | DRM_RENDER_ALLOW),
992 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
993 DRM_UNLOCKED | DRM_RENDER_ALLOW),
994 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
995 DRM_UNLOCKED | DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
997 DRM_UNLOCKED | DRM_RENDER_ALLOW),
998 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
999 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1000 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
1001 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1002 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
1003 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1004 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
1005 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1006 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
1007 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1008 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
1009 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001010#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001011};
1012
1013static const struct file_operations tegra_drm_fops = {
1014 .owner = THIS_MODULE,
1015 .open = drm_open,
1016 .release = drm_release,
1017 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +02001018 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001019 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001020 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001021 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001022 .llseek = noop_llseek,
1023};
1024
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001025static int tegra_drm_context_cleanup(int id, void *p, void *data)
1026{
1027 struct tegra_drm_context *context = p;
1028
1029 tegra_drm_context_free(context);
1030
1031 return 0;
1032}
1033
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001034static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +01001035{
Thierry Reding08943e62013-09-26 16:08:18 +02001036 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +01001037
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001038 mutex_lock(&fpriv->lock);
1039 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1040 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001041
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001042 idr_destroy(&fpriv->contexts);
1043 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001044 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001045}
1046
Thierry Redinge450fcc2013-02-13 16:13:16 +01001047#ifdef CONFIG_DEBUG_FS
1048static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1049{
1050 struct drm_info_node *node = (struct drm_info_node *)s->private;
1051 struct drm_device *drm = node->minor->dev;
1052 struct drm_framebuffer *fb;
1053
1054 mutex_lock(&drm->mode_config.fb_lock);
1055
1056 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1057 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001058 fb->base.id, fb->width, fb->height,
1059 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001060 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001061 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001062 }
1063
1064 mutex_unlock(&drm->mode_config.fb_lock);
1065
1066 return 0;
1067}
1068
Thierry Reding28c23372015-01-23 09:16:03 +01001069static int tegra_debugfs_iova(struct seq_file *s, void *data)
1070{
1071 struct drm_info_node *node = (struct drm_info_node *)s->private;
1072 struct drm_device *drm = node->minor->dev;
1073 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001074 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001075
Michał Mirosław68d890a2017-08-14 23:53:45 +02001076 if (tegra->domain) {
1077 mutex_lock(&tegra->mm_lock);
1078 drm_mm_print(&tegra->mm, &p);
1079 mutex_unlock(&tegra->mm_lock);
1080 }
Daniel Vetterb5c37142016-12-29 12:09:24 +01001081
1082 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001083}
1084
Thierry Redinge450fcc2013-02-13 16:13:16 +01001085static struct drm_info_list tegra_debugfs_list[] = {
1086 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001087 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001088};
1089
1090static int tegra_debugfs_init(struct drm_minor *minor)
1091{
1092 return drm_debugfs_create_files(tegra_debugfs_list,
1093 ARRAY_SIZE(tegra_debugfs_list),
1094 minor->debugfs_root, minor);
1095}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001096#endif
1097
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001098static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001099 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001100 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001101 .load = tegra_drm_load,
1102 .unload = tegra_drm_unload,
1103 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001104 .postclose = tegra_drm_postclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001105 .lastclose = tegra_drm_lastclose,
1106
Thierry Redinge450fcc2013-02-13 16:13:16 +01001107#if defined(CONFIG_DEBUG_FS)
1108 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001109#endif
1110
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001111 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001112 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001113
1114 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1115 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1116 .gem_prime_export = tegra_gem_prime_export,
1117 .gem_prime_import = tegra_gem_prime_import,
1118
Arto Merilainende2ba662013-03-22 16:34:08 +02001119 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001120
1121 .ioctls = tegra_drm_ioctls,
1122 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1123 .fops = &tegra_drm_fops,
1124
1125 .name = DRIVER_NAME,
1126 .desc = DRIVER_DESC,
1127 .date = DRIVER_DATE,
1128 .major = DRIVER_MAJOR,
1129 .minor = DRIVER_MINOR,
1130 .patchlevel = DRIVER_PATCHLEVEL,
1131};
Thierry Reding776dc382013-10-14 14:43:22 +02001132
1133int tegra_drm_register_client(struct tegra_drm *tegra,
1134 struct tegra_drm_client *client)
1135{
1136 mutex_lock(&tegra->clients_lock);
1137 list_add_tail(&client->list, &tegra->clients);
1138 mutex_unlock(&tegra->clients_lock);
1139
1140 return 0;
1141}
1142
1143int tegra_drm_unregister_client(struct tegra_drm *tegra,
1144 struct tegra_drm_client *client)
1145{
1146 mutex_lock(&tegra->clients_lock);
1147 list_del_init(&client->list);
1148 mutex_unlock(&tegra->clients_lock);
1149
1150 return 0;
1151}
1152
Thierry Reding67485fb2017-11-09 13:17:11 +01001153void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001154{
1155 struct iova *alloc;
1156 void *virt;
1157 gfp_t gfp;
1158 int err;
1159
1160 if (tegra->domain)
1161 size = iova_align(&tegra->carveout.domain, size);
1162 else
1163 size = PAGE_ALIGN(size);
1164
1165 gfp = GFP_KERNEL | __GFP_ZERO;
1166 if (!tegra->domain) {
1167 /*
1168 * Many units only support 32-bit addresses, even on 64-bit
1169 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1170 * virtual address space, force allocations to be in the
1171 * lower 32-bit range.
1172 */
1173 gfp |= GFP_DMA;
1174 }
1175
1176 virt = (void *)__get_free_pages(gfp, get_order(size));
1177 if (!virt)
1178 return ERR_PTR(-ENOMEM);
1179
1180 if (!tegra->domain) {
1181 /*
1182 * If IOMMU is disabled, devices address physical memory
1183 * directly.
1184 */
1185 *dma = virt_to_phys(virt);
1186 return virt;
1187 }
1188
1189 alloc = alloc_iova(&tegra->carveout.domain,
1190 size >> tegra->carveout.shift,
1191 tegra->carveout.limit, true);
1192 if (!alloc) {
1193 err = -EBUSY;
1194 goto free_pages;
1195 }
1196
1197 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1198 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1199 size, IOMMU_READ | IOMMU_WRITE);
1200 if (err < 0)
1201 goto free_iova;
1202
1203 return virt;
1204
1205free_iova:
1206 __free_iova(&tegra->carveout.domain, alloc);
1207free_pages:
1208 free_pages((unsigned long)virt, get_order(size));
1209
1210 return ERR_PTR(err);
1211}
1212
1213void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1214 dma_addr_t dma)
1215{
1216 if (tegra->domain)
1217 size = iova_align(&tegra->carveout.domain, size);
1218 else
1219 size = PAGE_ALIGN(size);
1220
1221 if (tegra->domain) {
1222 iommu_unmap(tegra->domain, dma, size);
1223 free_iova(&tegra->carveout.domain,
1224 iova_pfn(&tegra->carveout.domain, dma));
1225 }
1226
1227 free_pages((unsigned long)virt, get_order(size));
1228}
1229
Thierry Reding9910f5c2014-05-22 09:57:15 +02001230static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001231{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001232 struct drm_driver *driver = &tegra_drm_driver;
1233 struct drm_device *drm;
1234 int err;
1235
1236 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001237 if (IS_ERR(drm))
1238 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001239
Thierry Reding9910f5c2014-05-22 09:57:15 +02001240 dev_set_drvdata(&dev->dev, drm);
1241
1242 err = drm_dev_register(drm, 0);
1243 if (err < 0)
1244 goto unref;
1245
Thierry Reding9910f5c2014-05-22 09:57:15 +02001246 return 0;
1247
1248unref:
1249 drm_dev_unref(drm);
1250 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001251}
1252
Thierry Reding9910f5c2014-05-22 09:57:15 +02001253static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001254{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001255 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1256
1257 drm_dev_unregister(drm);
1258 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001259
1260 return 0;
1261}
1262
Thierry Reding359ae682014-12-18 17:15:25 +01001263#ifdef CONFIG_PM_SLEEP
1264static int host1x_drm_suspend(struct device *dev)
1265{
1266 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001267 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001268
1269 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001270 tegra_drm_fb_suspend(drm);
1271
1272 tegra->state = drm_atomic_helper_suspend(drm);
1273 if (IS_ERR(tegra->state)) {
1274 tegra_drm_fb_resume(drm);
1275 drm_kms_helper_poll_enable(drm);
1276 return PTR_ERR(tegra->state);
1277 }
Thierry Reding359ae682014-12-18 17:15:25 +01001278
1279 return 0;
1280}
1281
1282static int host1x_drm_resume(struct device *dev)
1283{
1284 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001285 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001286
Thierry Reding986c58d2015-08-11 13:11:49 +02001287 drm_atomic_helper_resume(drm, tegra->state);
1288 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001289 drm_kms_helper_poll_enable(drm);
1290
1291 return 0;
1292}
1293#endif
1294
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001295static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1296 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001297
Thierry Reding776dc382013-10-14 14:43:22 +02001298static const struct of_device_id host1x_drm_subdevs[] = {
1299 { .compatible = "nvidia,tegra20-dc", },
1300 { .compatible = "nvidia,tegra20-hdmi", },
1301 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001302 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001303 { .compatible = "nvidia,tegra30-dc", },
1304 { .compatible = "nvidia,tegra30-hdmi", },
1305 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001306 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001307 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001308 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001309 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001310 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001311 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001312 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001313 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001314 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001315 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001316 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001317 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001318 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001319 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001320 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001321 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001322 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001323 { .compatible = "nvidia,tegra186-sor", },
1324 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001325 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001326 { /* sentinel */ }
1327};
1328
1329static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001330 .driver = {
1331 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001332 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001333 },
Thierry Reding776dc382013-10-14 14:43:22 +02001334 .probe = host1x_drm_probe,
1335 .remove = host1x_drm_remove,
1336 .subdevs = host1x_drm_subdevs,
1337};
1338
Thierry Reding473112e2015-09-10 16:07:14 +02001339static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001340 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001341 &tegra_dc_driver,
1342 &tegra_hdmi_driver,
1343 &tegra_dsi_driver,
1344 &tegra_dpaux_driver,
1345 &tegra_sor_driver,
1346 &tegra_gr2d_driver,
1347 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001348 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001349};
1350
Thierry Reding776dc382013-10-14 14:43:22 +02001351static int __init host1x_drm_init(void)
1352{
1353 int err;
1354
1355 err = host1x_driver_register(&host1x_drm_driver);
1356 if (err < 0)
1357 return err;
1358
Thierry Reding473112e2015-09-10 16:07:14 +02001359 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001360 if (err < 0)
1361 goto unregister_host1x;
1362
Thierry Reding776dc382013-10-14 14:43:22 +02001363 return 0;
1364
Thierry Reding776dc382013-10-14 14:43:22 +02001365unregister_host1x:
1366 host1x_driver_unregister(&host1x_drm_driver);
1367 return err;
1368}
1369module_init(host1x_drm_init);
1370
1371static void __exit host1x_drm_exit(void)
1372{
Thierry Reding473112e2015-09-10 16:07:14 +02001373 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001374 host1x_driver_unregister(&host1x_drm_driver);
1375}
1376module_exit(host1x_drm_exit);
1377
1378MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1379MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1380MODULE_LICENSE("GPL v2");