blob: 271c7a5fc954a2773896ab881be90c4d0fb9804a [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +030018#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
19#include <asm/dma-iommu.h>
20#endif
21
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000022#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020023#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000024
25#define DRIVER_NAME "tegra"
26#define DRIVER_DESC "NVIDIA Tegra graphics"
27#define DRIVER_DATE "20120330"
28#define DRIVER_MAJOR 0
29#define DRIVER_MINOR 0
30#define DRIVER_PATCHLEVEL 0
31
Mikko Perttunenad926012016-12-14 13:16:11 +020032#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030033#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020034
Thierry Reding08943e62013-09-26 16:08:18 +020035struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010036 struct idr contexts;
37 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020038};
39
Thierry Redingab7d3f52017-12-14 13:46:20 +010040static int tegra_atomic_check(struct drm_device *drm,
41 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010042{
Thierry Reding1503ca42014-11-24 17:41:23 +010043 int err;
44
Peter Ujfalusia18301b2018-03-21 12:20:26 +020045 err = drm_atomic_helper_check(drm, state);
Thierry Redingab7d3f52017-12-14 13:46:20 +010046 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010047 return err;
48
Peter Ujfalusia18301b2018-03-21 12:20:26 +020049 return tegra_display_hub_atomic_check(drm, state);
Thierry Reding1503ca42014-11-24 17:41:23 +010050}
51
Thierry Reding31b02ca2017-10-12 17:40:46 +020052static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010053 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053054#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010055 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010056#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010057 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020058 .atomic_commit = drm_atomic_helper_commit,
59};
60
Thierry Redingc4755fb2017-11-13 11:08:13 +010061static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
62{
63 struct drm_device *drm = old_state->dev;
64 struct tegra_drm *tegra = drm->dev_private;
65
66 if (tegra->hub) {
67 drm_atomic_helper_commit_modeset_disables(drm, old_state);
68 tegra_display_hub_atomic_commit(drm, old_state);
69 drm_atomic_helper_commit_planes(drm, old_state, 0);
70 drm_atomic_helper_commit_modeset_enables(drm, old_state);
71 drm_atomic_helper_commit_hw_done(old_state);
72 drm_atomic_helper_wait_for_vblanks(drm, old_state);
73 drm_atomic_helper_cleanup_planes(drm, old_state);
74 } else {
75 drm_atomic_helper_commit_tail_rpm(old_state);
76 }
77}
78
Thierry Reding31b02ca2017-10-12 17:40:46 +020079static const struct drm_mode_config_helper_funcs
80tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +010081 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +010082};
83
Thierry Reding776dc382013-10-14 14:43:22 +020084static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000085{
Thierry Reding776dc382013-10-14 14:43:22 +020086 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +020087 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000088 int err;
89
Thierry Reding776dc382013-10-14 14:43:22 +020090 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +020091 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +020092 return -ENOMEM;
93
Thierry Redingdf06b752014-06-26 21:41:53 +020094 if (iommu_present(&platform_bus_type)) {
95 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +030096 if (!tegra->domain) {
97 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +020098 goto free;
99 }
100
Thierry Reding24cfdc12018-04-23 08:57:45 +0200101 err = iova_cache_get();
102 if (err < 0)
103 goto domain;
Thierry Redingdf06b752014-06-26 21:41:53 +0200104 }
105
Thierry Reding386a2a72013-09-24 13:22:17 +0200106 mutex_init(&tegra->clients_lock);
107 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100108
Thierry Reding386a2a72013-09-24 13:22:17 +0200109 drm->dev_private = tegra;
110 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000111
112 drm_mode_config_init(drm);
113
Thierry Redingf9914212014-11-26 13:03:57 +0100114 drm->mode_config.min_width = 0;
115 drm->mode_config.min_height = 0;
116
117 drm->mode_config.max_width = 4096;
118 drm->mode_config.max_height = 4096;
119
Alexandre Courbot5e911442016-11-08 16:50:42 +0900120 drm->mode_config.allow_fb_modifiers = true;
121
Peter Ujfalusia18301b2018-03-21 12:20:26 +0200122 drm->mode_config.normalize_zpos = true;
123
Thierry Reding31b02ca2017-10-12 17:40:46 +0200124 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
125 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100126
Thierry Redinge2215322014-06-27 17:19:25 +0200127 err = tegra_drm_fb_prepare(drm);
128 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100129 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200130
131 drm_kms_helper_poll_init(drm);
132
Thierry Reding776dc382013-10-14 14:43:22 +0200133 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000134 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100135 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000136
Thierry Redingb9f8b092019-02-01 14:28:33 +0100137 if (tegra->domain) {
138 u64 carveout_start, carveout_end, gem_start, gem_end;
139 dma_addr_t start, end;
140 unsigned long order;
141
142 start = tegra->domain->geometry.aperture_start;
143 end = tegra->domain->geometry.aperture_end;
144
145 gem_start = start;
146 gem_end = end - CARVEOUT_SZ;
147 carveout_start = gem_end + 1;
148 carveout_end = end;
149
150 order = __ffs(tegra->domain->pgsize_bitmap);
151 init_iova_domain(&tegra->carveout.domain, 1UL << order,
152 carveout_start >> order);
153
154 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
155 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
156
157 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
158 mutex_init(&tegra->mm_lock);
159
160 DRM_DEBUG("IOMMU apertures:\n");
161 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
162 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
163 carveout_end);
164 }
165
Thierry Redingc4755fb2017-11-13 11:08:13 +0100166 if (tegra->hub) {
167 err = tegra_display_hub_prepare(tegra->hub);
168 if (err < 0)
169 goto device;
170 }
171
Thierry Reding603f0cc2013-04-22 21:22:14 +0200172 /*
173 * We don't use the drm_irq_install() helpers provided by the DRM
174 * core, so we need to set this manually in order to allow the
175 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
176 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300177 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200178
Thierry Reding42e9ce02015-01-28 14:43:05 +0100179 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100180 drm->max_vblank_count = 0xffffffff;
181
Thierry Reding6e5ff992012-11-28 11:45:47 +0100182 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
183 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100184 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100185
Thierry Reding31930d42015-07-02 17:04:06 +0200186 drm_mode_config_reset(drm);
187
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000188 err = tegra_drm_fb_init(drm);
189 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100190 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000191
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000192 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100193
Thierry Redingc4755fb2017-11-13 11:08:13 +0100194hub:
195 if (tegra->hub)
196 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100197device:
198 host1x_device_exit(device);
199fbdev:
200 drm_kms_helper_poll_fini(drm);
201 tegra_drm_fb_free(drm);
202config:
203 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200204
205 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100206 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200207 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200208 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200209 iova_cache_put();
Thierry Redingdf06b752014-06-26 21:41:53 +0200210 }
Thierry Reding24cfdc12018-04-23 08:57:45 +0200211domain:
212 if (tegra->domain)
213 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200214free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100215 kfree(tegra);
216 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000217}
218
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200219static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000220{
Thierry Reding776dc382013-10-14 14:43:22 +0200221 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200222 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200223 int err;
224
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000225 drm_kms_helper_poll_fini(drm);
226 tegra_drm_fb_exit(drm);
Thierry Reding192b4af2018-03-18 01:13:39 +0100227 drm_atomic_helper_shutdown(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200228 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000229
Thierry Reding776dc382013-10-14 14:43:22 +0200230 err = host1x_device_exit(device);
231 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200232 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200233
Thierry Redingdf06b752014-06-26 21:41:53 +0200234 if (tegra->domain) {
Thierry Reding347ad49d2017-03-09 20:04:56 +0100235 mutex_destroy(&tegra->mm_lock);
Thierry Reding5f43ac82018-04-23 08:57:44 +0200236 drm_mm_takedown(&tegra->mm);
Mikko Perttunenad926012016-12-14 13:16:11 +0200237 put_iova_domain(&tegra->carveout.domain);
Thierry Reding24cfdc12018-04-23 08:57:45 +0200238 iova_cache_put();
Thierry Reding5f43ac82018-04-23 08:57:44 +0200239 iommu_domain_free(tegra->domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200240 }
241
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100242 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000243}
244
245static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
246{
Thierry Reding08943e62013-09-26 16:08:18 +0200247 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200248
249 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
250 if (!fpriv)
251 return -ENOMEM;
252
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100253 idr_init(&fpriv->contexts);
254 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200255 filp->driver_priv = fpriv;
256
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000257 return 0;
258}
259
Thierry Redingc88c3632013-09-26 16:08:22 +0200260static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200261{
262 context->client->ops->close_channel(context);
263 kfree(context);
264}
265
Thierry Redingc40f0f12013-10-10 11:00:33 +0200266static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100267host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200268{
269 struct drm_gem_object *gem;
270 struct tegra_bo *bo;
271
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100272 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200273 if (!gem)
274 return NULL;
275
Thierry Redingc40f0f12013-10-10 11:00:33 +0200276 bo = to_tegra_bo(gem);
277 return &bo->base;
278}
279
Thierry Reding961e3be2014-06-10 10:25:00 +0200280static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
281 struct drm_tegra_reloc __user *src,
282 struct drm_device *drm,
283 struct drm_file *file)
284{
285 u32 cmdbuf, target;
286 int err;
287
288 err = get_user(cmdbuf, &src->cmdbuf.handle);
289 if (err < 0)
290 return err;
291
292 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
293 if (err < 0)
294 return err;
295
296 err = get_user(target, &src->target.handle);
297 if (err < 0)
298 return err;
299
David Ung31f40f82015-01-20 18:37:35 -0800300 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200301 if (err < 0)
302 return err;
303
304 err = get_user(dest->shift, &src->shift);
305 if (err < 0)
306 return err;
307
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100308 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200309 if (!dest->cmdbuf.bo)
310 return -ENOENT;
311
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100312 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200313 if (!dest->target.bo)
314 return -ENOENT;
315
316 return 0;
317}
318
Thierry Redingc40f0f12013-10-10 11:00:33 +0200319int tegra_drm_submit(struct tegra_drm_context *context,
320 struct drm_tegra_submit *args, struct drm_device *drm,
321 struct drm_file *file)
322{
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200323 struct host1x_client *client = &context->client->base;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200324 unsigned int num_cmdbufs = args->num_cmdbufs;
325 unsigned int num_relocs = args->num_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300326 struct drm_tegra_cmdbuf __user *user_cmdbufs;
327 struct drm_tegra_reloc __user *user_relocs;
Mikko Perttunena176c672017-09-28 15:50:44 +0300328 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200329 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300330 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200331 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300332 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200333 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200334 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200335 int err;
336
Mikko Perttunena176c672017-09-28 15:50:44 +0300337 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
338 user_relocs = u64_to_user_ptr(args->relocs);
Mikko Perttunena176c672017-09-28 15:50:44 +0300339 user_syncpt = u64_to_user_ptr(args->syncpts);
340
Thierry Redingc40f0f12013-10-10 11:00:33 +0200341 /* We don't yet support other than one syncpt_incr struct per submit */
342 if (args->num_syncpts != 1)
343 return -EINVAL;
344
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300345 /* We don't yet support waitchks */
346 if (args->num_waitchks != 0)
347 return -EINVAL;
348
Thierry Redingc40f0f12013-10-10 11:00:33 +0200349 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
Thierry Reding24c94e12018-05-05 08:45:47 +0200350 args->num_relocs);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200351 if (!job)
352 return -ENOMEM;
353
354 job->num_relocs = args->num_relocs;
Thierry Redingbf3d41c2018-05-16 14:12:33 +0200355 job->client = client;
356 job->class = client->class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200357 job->serialize = true;
358
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200359 /*
360 * Track referenced BOs so that they can be unreferenced after the
361 * submission is complete.
362 */
Thierry Reding24c94e12018-05-05 08:45:47 +0200363 num_refs = num_cmdbufs + num_relocs * 2;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200364
365 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
366 if (!refs) {
367 err = -ENOMEM;
368 goto put;
369 }
370
371 /* reuse as an iterator later */
372 num_refs = 0;
373
Thierry Redingc40f0f12013-10-10 11:00:33 +0200374 while (num_cmdbufs) {
375 struct drm_tegra_cmdbuf cmdbuf;
376 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300377 struct tegra_bo *obj;
378 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200379
Mikko Perttunena176c672017-09-28 15:50:44 +0300380 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300381 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200382 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300383 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200384
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300385 /*
386 * The maximum number of CDMA gather fetches is 16383, a higher
387 * value means the words count is malformed.
388 */
389 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
390 err = -EINVAL;
391 goto fail;
392 }
393
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100394 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200395 if (!bo) {
396 err = -ENOENT;
397 goto fail;
398 }
399
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300400 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
401 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200402 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300403
404 /*
405 * Gather buffer base address must be 4-bytes aligned,
406 * unaligned offset is malformed and cause commands stream
407 * corruption on the buffer address relocation.
408 */
Mikko Perttunen5265f032018-06-20 16:03:58 +0300409 if (offset & 3 || offset > obj->gem.size) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300410 err = -EINVAL;
411 goto fail;
412 }
413
Thierry Redingc40f0f12013-10-10 11:00:33 +0200414 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
415 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300416 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200417 }
418
Thierry Reding961e3be2014-06-10 10:25:00 +0200419 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200420 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300421 struct host1x_reloc *reloc;
422 struct tegra_bo *obj;
423
Thierry Reding06490bb2018-05-16 16:58:44 +0200424 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300425 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200426 file);
427 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200428 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300429
Thierry Reding06490bb2018-05-16 16:58:44 +0200430 reloc = &job->relocs[num_relocs];
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300431 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200432 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300433
434 /*
435 * The unaligned cmdbuf offset will cause an unaligned write
436 * during of the relocations patching, corrupting the commands
437 * stream.
438 */
439 if (reloc->cmdbuf.offset & 3 ||
440 reloc->cmdbuf.offset >= obj->gem.size) {
441 err = -EINVAL;
442 goto fail;
443 }
444
445 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200446 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300447
448 if (reloc->target.offset >= obj->gem.size) {
449 err = -EINVAL;
450 goto fail;
451 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200452 }
453
Mikko Perttunena176c672017-09-28 15:50:44 +0300454 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300455 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200456 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300457 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200458
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300459 /* check whether syncpoint ID is valid */
460 sp = host1x_syncpt_get(host1x, syncpt.id);
461 if (!sp) {
462 err = -ENOENT;
463 goto fail;
464 }
465
Thierry Redingc40f0f12013-10-10 11:00:33 +0200466 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300467 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200468 job->syncpt_incrs = syncpt.incrs;
469 job->syncpt_id = syncpt.id;
470 job->timeout = 10000;
471
472 if (args->timeout && args->timeout < 10000)
473 job->timeout = args->timeout;
474
475 err = host1x_job_pin(job, context->client->base.dev);
476 if (err)
477 goto fail;
478
479 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200480 if (err) {
481 host1x_job_unpin(job);
482 goto fail;
483 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200484
485 args->fence = job->syncpt_end;
486
Thierry Redingc40f0f12013-10-10 11:00:33 +0200487fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200488 while (num_refs--)
489 drm_gem_object_put_unlocked(refs[num_refs]);
490
491 kfree(refs);
492
493put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200494 host1x_job_put(job);
495 return err;
496}
497
498
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200499#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200500static int tegra_gem_create(struct drm_device *drm, void *data,
501 struct drm_file *file)
502{
503 struct drm_tegra_gem_create *args = data;
504 struct tegra_bo *bo;
505
Thierry Reding773af772013-10-04 22:34:01 +0200506 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200507 &args->handle);
508 if (IS_ERR(bo))
509 return PTR_ERR(bo);
510
511 return 0;
512}
513
514static int tegra_gem_mmap(struct drm_device *drm, void *data,
515 struct drm_file *file)
516{
517 struct drm_tegra_gem_mmap *args = data;
518 struct drm_gem_object *gem;
519 struct tegra_bo *bo;
520
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100521 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200522 if (!gem)
523 return -EINVAL;
524
525 bo = to_tegra_bo(gem);
526
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200527 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200528
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300529 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200530
531 return 0;
532}
533
534static int tegra_syncpt_read(struct drm_device *drm, void *data,
535 struct drm_file *file)
536{
Thierry Reding776dc382013-10-14 14:43:22 +0200537 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200538 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200539 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200540
Thierry Reding776dc382013-10-14 14:43:22 +0200541 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200542 if (!sp)
543 return -EINVAL;
544
545 args->value = host1x_syncpt_read_min(sp);
546 return 0;
547}
548
549static int tegra_syncpt_incr(struct drm_device *drm, void *data,
550 struct drm_file *file)
551{
Thierry Reding776dc382013-10-14 14:43:22 +0200552 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200553 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200554 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200555
Thierry Reding776dc382013-10-14 14:43:22 +0200556 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200557 if (!sp)
558 return -EINVAL;
559
Arto Merilainenebae30b2013-05-29 13:26:08 +0300560 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200561}
562
563static int tegra_syncpt_wait(struct drm_device *drm, void *data,
564 struct drm_file *file)
565{
Thierry Reding776dc382013-10-14 14:43:22 +0200566 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200567 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200568 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200569
Thierry Reding776dc382013-10-14 14:43:22 +0200570 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200571 if (!sp)
572 return -EINVAL;
573
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300574 return host1x_syncpt_wait(sp, args->thresh,
575 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200576 &args->value);
577}
578
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100579static int tegra_client_open(struct tegra_drm_file *fpriv,
580 struct tegra_drm_client *client,
581 struct tegra_drm_context *context)
582{
583 int err;
584
585 err = client->ops->open_channel(client, context);
586 if (err < 0)
587 return err;
588
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300589 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100590 if (err < 0) {
591 client->ops->close_channel(context);
592 return err;
593 }
594
595 context->client = client;
596 context->id = err;
597
598 return 0;
599}
600
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200601static int tegra_open_channel(struct drm_device *drm, void *data,
602 struct drm_file *file)
603{
Thierry Reding08943e62013-09-26 16:08:18 +0200604 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200605 struct tegra_drm *tegra = drm->dev_private;
606 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200607 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200608 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200609 int err = -ENODEV;
610
611 context = kzalloc(sizeof(*context), GFP_KERNEL);
612 if (!context)
613 return -ENOMEM;
614
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100615 mutex_lock(&fpriv->lock);
616
Thierry Reding776dc382013-10-14 14:43:22 +0200617 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200618 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100619 err = tegra_client_open(fpriv, client, context);
620 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200621 break;
622
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100623 args->context = context->id;
624 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200625 }
626
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100627 if (err < 0)
628 kfree(context);
629
630 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200631 return err;
632}
633
634static int tegra_close_channel(struct drm_device *drm, void *data,
635 struct drm_file *file)
636{
Thierry Reding08943e62013-09-26 16:08:18 +0200637 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200638 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200639 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100640 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200641
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100642 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200643
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300644 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100645 if (!context) {
646 err = -EINVAL;
647 goto unlock;
648 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200649
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100650 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200651 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200652
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100653unlock:
654 mutex_unlock(&fpriv->lock);
655 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200656}
657
658static int tegra_get_syncpt(struct drm_device *drm, void *data,
659 struct drm_file *file)
660{
Thierry Reding08943e62013-09-26 16:08:18 +0200661 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200662 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200663 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200664 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100665 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200666
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100667 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200668
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300669 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100670 if (!context) {
671 err = -ENODEV;
672 goto unlock;
673 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200674
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100675 if (args->index >= context->client->base.num_syncpts) {
676 err = -EINVAL;
677 goto unlock;
678 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200679
Thierry Reding53fa7f72013-09-24 15:35:40 +0200680 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200681 args->id = host1x_syncpt_id(syncpt);
682
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100683unlock:
684 mutex_unlock(&fpriv->lock);
685 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200686}
687
688static int tegra_submit(struct drm_device *drm, void *data,
689 struct drm_file *file)
690{
Thierry Reding08943e62013-09-26 16:08:18 +0200691 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200692 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200693 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100694 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200695
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100696 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200697
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300698 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100699 if (!context) {
700 err = -ENODEV;
701 goto unlock;
702 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200703
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100704 err = context->client->ops->submit(context, args, drm, file);
705
706unlock:
707 mutex_unlock(&fpriv->lock);
708 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200709}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300710
711static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
712 struct drm_file *file)
713{
714 struct tegra_drm_file *fpriv = file->driver_priv;
715 struct drm_tegra_get_syncpt_base *args = data;
716 struct tegra_drm_context *context;
717 struct host1x_syncpt_base *base;
718 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100719 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300720
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100721 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300722
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300723 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100724 if (!context) {
725 err = -ENODEV;
726 goto unlock;
727 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300728
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100729 if (args->syncpt >= context->client->base.num_syncpts) {
730 err = -EINVAL;
731 goto unlock;
732 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300733
734 syncpt = context->client->base.syncpts[args->syncpt];
735
736 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100737 if (!base) {
738 err = -ENXIO;
739 goto unlock;
740 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300741
742 args->id = host1x_syncpt_base_id(base);
743
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100744unlock:
745 mutex_unlock(&fpriv->lock);
746 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300747}
Thierry Reding7678d712014-06-03 14:56:57 +0200748
749static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
750 struct drm_file *file)
751{
752 struct drm_tegra_gem_set_tiling *args = data;
753 enum tegra_bo_tiling_mode mode;
754 struct drm_gem_object *gem;
755 unsigned long value = 0;
756 struct tegra_bo *bo;
757
758 switch (args->mode) {
759 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
760 mode = TEGRA_BO_TILING_MODE_PITCH;
761
762 if (args->value != 0)
763 return -EINVAL;
764
765 break;
766
767 case DRM_TEGRA_GEM_TILING_MODE_TILED:
768 mode = TEGRA_BO_TILING_MODE_TILED;
769
770 if (args->value != 0)
771 return -EINVAL;
772
773 break;
774
775 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
776 mode = TEGRA_BO_TILING_MODE_BLOCK;
777
778 if (args->value > 5)
779 return -EINVAL;
780
781 value = args->value;
782 break;
783
784 default:
785 return -EINVAL;
786 }
787
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100788 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200789 if (!gem)
790 return -ENOENT;
791
792 bo = to_tegra_bo(gem);
793
794 bo->tiling.mode = mode;
795 bo->tiling.value = value;
796
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300797 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200798
799 return 0;
800}
801
802static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
803 struct drm_file *file)
804{
805 struct drm_tegra_gem_get_tiling *args = data;
806 struct drm_gem_object *gem;
807 struct tegra_bo *bo;
808 int err = 0;
809
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100810 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200811 if (!gem)
812 return -ENOENT;
813
814 bo = to_tegra_bo(gem);
815
816 switch (bo->tiling.mode) {
817 case TEGRA_BO_TILING_MODE_PITCH:
818 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
819 args->value = 0;
820 break;
821
822 case TEGRA_BO_TILING_MODE_TILED:
823 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
824 args->value = 0;
825 break;
826
827 case TEGRA_BO_TILING_MODE_BLOCK:
828 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
829 args->value = bo->tiling.value;
830 break;
831
832 default:
833 err = -EINVAL;
834 break;
835 }
836
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300837 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200838
839 return err;
840}
Thierry Reding7b129082014-06-10 12:04:03 +0200841
842static int tegra_gem_set_flags(struct drm_device *drm, void *data,
843 struct drm_file *file)
844{
845 struct drm_tegra_gem_set_flags *args = data;
846 struct drm_gem_object *gem;
847 struct tegra_bo *bo;
848
849 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
850 return -EINVAL;
851
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100852 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200853 if (!gem)
854 return -ENOENT;
855
856 bo = to_tegra_bo(gem);
857 bo->flags = 0;
858
859 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
860 bo->flags |= TEGRA_BO_BOTTOM_UP;
861
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300862 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200863
864 return 0;
865}
866
867static int tegra_gem_get_flags(struct drm_device *drm, void *data,
868 struct drm_file *file)
869{
870 struct drm_tegra_gem_get_flags *args = data;
871 struct drm_gem_object *gem;
872 struct tegra_bo *bo;
873
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100874 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200875 if (!gem)
876 return -ENOENT;
877
878 bo = to_tegra_bo(gem);
879 args->flags = 0;
880
881 if (bo->flags & TEGRA_BO_BOTTOM_UP)
882 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
883
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300884 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200885
886 return 0;
887}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200888#endif
889
Rob Clarkbaa70942013-08-02 13:27:49 -0400890static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200891#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200892 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
893 DRM_UNLOCKED | DRM_RENDER_ALLOW),
894 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
895 DRM_UNLOCKED | DRM_RENDER_ALLOW),
896 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
897 DRM_UNLOCKED | DRM_RENDER_ALLOW),
898 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
899 DRM_UNLOCKED | DRM_RENDER_ALLOW),
900 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
901 DRM_UNLOCKED | DRM_RENDER_ALLOW),
902 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
903 DRM_UNLOCKED | DRM_RENDER_ALLOW),
904 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
905 DRM_UNLOCKED | DRM_RENDER_ALLOW),
906 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
907 DRM_UNLOCKED | DRM_RENDER_ALLOW),
908 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
909 DRM_UNLOCKED | DRM_RENDER_ALLOW),
910 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
911 DRM_UNLOCKED | DRM_RENDER_ALLOW),
912 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
913 DRM_UNLOCKED | DRM_RENDER_ALLOW),
914 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
915 DRM_UNLOCKED | DRM_RENDER_ALLOW),
916 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
917 DRM_UNLOCKED | DRM_RENDER_ALLOW),
918 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
919 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200920#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000921};
922
923static const struct file_operations tegra_drm_fops = {
924 .owner = THIS_MODULE,
925 .open = drm_open,
926 .release = drm_release,
927 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200928 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000929 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000930 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000931 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000932 .llseek = noop_llseek,
933};
934
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100935static int tegra_drm_context_cleanup(int id, void *p, void *data)
936{
937 struct tegra_drm_context *context = p;
938
939 tegra_drm_context_free(context);
940
941 return 0;
942}
943
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200944static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100945{
Thierry Reding08943e62013-09-26 16:08:18 +0200946 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100947
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100948 mutex_lock(&fpriv->lock);
949 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
950 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200951
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100952 idr_destroy(&fpriv->contexts);
953 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200954 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +0100955}
956
Thierry Redinge450fcc2013-02-13 16:13:16 +0100957#ifdef CONFIG_DEBUG_FS
958static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
959{
960 struct drm_info_node *node = (struct drm_info_node *)s->private;
961 struct drm_device *drm = node->minor->dev;
962 struct drm_framebuffer *fb;
963
964 mutex_lock(&drm->mode_config.fb_lock);
965
966 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
967 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200968 fb->base.id, fb->width, fb->height,
969 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +0200970 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +1000971 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +0100972 }
973
974 mutex_unlock(&drm->mode_config.fb_lock);
975
976 return 0;
977}
978
Thierry Reding28c23372015-01-23 09:16:03 +0100979static int tegra_debugfs_iova(struct seq_file *s, void *data)
980{
981 struct drm_info_node *node = (struct drm_info_node *)s->private;
982 struct drm_device *drm = node->minor->dev;
983 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +0100984 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +0100985
Michał Mirosław68d890a2017-08-14 23:53:45 +0200986 if (tegra->domain) {
987 mutex_lock(&tegra->mm_lock);
988 drm_mm_print(&tegra->mm, &p);
989 mutex_unlock(&tegra->mm_lock);
990 }
Daniel Vetterb5c37142016-12-29 12:09:24 +0100991
992 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +0100993}
994
Thierry Redinge450fcc2013-02-13 16:13:16 +0100995static struct drm_info_list tegra_debugfs_list[] = {
996 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +0100997 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +0100998};
999
1000static int tegra_debugfs_init(struct drm_minor *minor)
1001{
1002 return drm_debugfs_create_files(tegra_debugfs_list,
1003 ARRAY_SIZE(tegra_debugfs_list),
1004 minor->debugfs_root, minor);
1005}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001006#endif
1007
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001008static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001009 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001010 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001011 .load = tegra_drm_load,
1012 .unload = tegra_drm_unload,
1013 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001014 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001015 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001016
Thierry Redinge450fcc2013-02-13 16:13:16 +01001017#if defined(CONFIG_DEBUG_FS)
1018 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001019#endif
1020
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001021 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001022 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001023
1024 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1025 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1026 .gem_prime_export = tegra_gem_prime_export,
1027 .gem_prime_import = tegra_gem_prime_import,
1028
Arto Merilainende2ba662013-03-22 16:34:08 +02001029 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001030
1031 .ioctls = tegra_drm_ioctls,
1032 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1033 .fops = &tegra_drm_fops,
1034
1035 .name = DRIVER_NAME,
1036 .desc = DRIVER_DESC,
1037 .date = DRIVER_DATE,
1038 .major = DRIVER_MAJOR,
1039 .minor = DRIVER_MINOR,
1040 .patchlevel = DRIVER_PATCHLEVEL,
1041};
Thierry Reding776dc382013-10-14 14:43:22 +02001042
1043int tegra_drm_register_client(struct tegra_drm *tegra,
1044 struct tegra_drm_client *client)
1045{
1046 mutex_lock(&tegra->clients_lock);
1047 list_add_tail(&client->list, &tegra->clients);
Thierry Reding8e5d19c2019-02-01 14:28:31 +01001048 client->drm = tegra;
Thierry Reding776dc382013-10-14 14:43:22 +02001049 mutex_unlock(&tegra->clients_lock);
1050
1051 return 0;
1052}
1053
1054int tegra_drm_unregister_client(struct tegra_drm *tegra,
1055 struct tegra_drm_client *client)
1056{
1057 mutex_lock(&tegra->clients_lock);
1058 list_del_init(&client->list);
Thierry Reding8e5d19c2019-02-01 14:28:31 +01001059 client->drm = NULL;
Thierry Reding776dc382013-10-14 14:43:22 +02001060 mutex_unlock(&tegra->clients_lock);
1061
1062 return 0;
1063}
1064
Thierry Reding0c407de2018-05-04 15:02:24 +02001065struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
1066 bool shared)
1067{
1068 struct drm_device *drm = dev_get_drvdata(client->parent);
1069 struct tegra_drm *tegra = drm->dev_private;
1070 struct iommu_group *group = NULL;
1071 int err;
1072
1073 if (tegra->domain) {
1074 group = iommu_group_get(client->dev);
1075 if (!group) {
1076 dev_err(client->dev, "failed to get IOMMU group\n");
1077 return ERR_PTR(-ENODEV);
1078 }
1079
1080 if (!shared || (shared && (group != tegra->group))) {
Dmitry Osipenko5ac93f812018-08-19 17:24:20 +03001081#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
1082 if (client->dev->archdata.mapping) {
1083 struct dma_iommu_mapping *mapping =
1084 to_dma_iommu_mapping(client->dev);
1085 arm_iommu_detach_device(client->dev);
1086 arm_iommu_release_mapping(mapping);
1087 }
1088#endif
Thierry Reding0c407de2018-05-04 15:02:24 +02001089 err = iommu_attach_group(tegra->domain, group);
1090 if (err < 0) {
1091 iommu_group_put(group);
1092 return ERR_PTR(err);
1093 }
1094
1095 if (shared && !tegra->group)
1096 tegra->group = group;
1097 }
1098 }
1099
1100 return group;
1101}
1102
1103void host1x_client_iommu_detach(struct host1x_client *client,
1104 struct iommu_group *group)
1105{
1106 struct drm_device *drm = dev_get_drvdata(client->parent);
1107 struct tegra_drm *tegra = drm->dev_private;
1108
1109 if (group) {
1110 if (group == tegra->group) {
1111 iommu_detach_group(tegra->domain, group);
1112 tegra->group = NULL;
1113 }
1114
1115 iommu_group_put(group);
1116 }
1117}
1118
Thierry Reding67485fb2017-11-09 13:17:11 +01001119void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001120{
1121 struct iova *alloc;
1122 void *virt;
1123 gfp_t gfp;
1124 int err;
1125
1126 if (tegra->domain)
1127 size = iova_align(&tegra->carveout.domain, size);
1128 else
1129 size = PAGE_ALIGN(size);
1130
1131 gfp = GFP_KERNEL | __GFP_ZERO;
1132 if (!tegra->domain) {
1133 /*
1134 * Many units only support 32-bit addresses, even on 64-bit
1135 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1136 * virtual address space, force allocations to be in the
1137 * lower 32-bit range.
1138 */
1139 gfp |= GFP_DMA;
1140 }
1141
1142 virt = (void *)__get_free_pages(gfp, get_order(size));
1143 if (!virt)
1144 return ERR_PTR(-ENOMEM);
1145
1146 if (!tegra->domain) {
1147 /*
1148 * If IOMMU is disabled, devices address physical memory
1149 * directly.
1150 */
1151 *dma = virt_to_phys(virt);
1152 return virt;
1153 }
1154
1155 alloc = alloc_iova(&tegra->carveout.domain,
1156 size >> tegra->carveout.shift,
1157 tegra->carveout.limit, true);
1158 if (!alloc) {
1159 err = -EBUSY;
1160 goto free_pages;
1161 }
1162
1163 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1164 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1165 size, IOMMU_READ | IOMMU_WRITE);
1166 if (err < 0)
1167 goto free_iova;
1168
1169 return virt;
1170
1171free_iova:
1172 __free_iova(&tegra->carveout.domain, alloc);
1173free_pages:
1174 free_pages((unsigned long)virt, get_order(size));
1175
1176 return ERR_PTR(err);
1177}
1178
1179void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1180 dma_addr_t dma)
1181{
1182 if (tegra->domain)
1183 size = iova_align(&tegra->carveout.domain, size);
1184 else
1185 size = PAGE_ALIGN(size);
1186
1187 if (tegra->domain) {
1188 iommu_unmap(tegra->domain, dma, size);
1189 free_iova(&tegra->carveout.domain,
1190 iova_pfn(&tegra->carveout.domain, dma));
1191 }
1192
1193 free_pages((unsigned long)virt, get_order(size));
1194}
1195
Thierry Reding9910f5c2014-05-22 09:57:15 +02001196static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001197{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001198 struct drm_driver *driver = &tegra_drm_driver;
1199 struct drm_device *drm;
1200 int err;
1201
1202 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001203 if (IS_ERR(drm))
1204 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001205
Thierry Reding9910f5c2014-05-22 09:57:15 +02001206 dev_set_drvdata(&dev->dev, drm);
1207
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001208 err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false);
1209 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001210 goto put;
Michał Mirosław6e4228f2018-09-01 16:08:51 +02001211
Thierry Reding9910f5c2014-05-22 09:57:15 +02001212 err = drm_dev_register(drm, 0);
1213 if (err < 0)
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001214 goto put;
Thierry Reding9910f5c2014-05-22 09:57:15 +02001215
Thierry Reding9910f5c2014-05-22 09:57:15 +02001216 return 0;
1217
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001218put:
1219 drm_dev_put(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001220 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001221}
1222
Thierry Reding9910f5c2014-05-22 09:57:15 +02001223static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001224{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001225 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1226
1227 drm_dev_unregister(drm);
Thomas Zimmermann9c942092018-09-26 13:56:40 +02001228 drm_dev_put(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001229
1230 return 0;
1231}
1232
Thierry Reding359ae682014-12-18 17:15:25 +01001233#ifdef CONFIG_PM_SLEEP
1234static int host1x_drm_suspend(struct device *dev)
1235{
1236 struct drm_device *drm = dev_get_drvdata(dev);
1237
Souptick Joarder53f1e062018-08-01 01:37:05 +05301238 return drm_mode_config_helper_suspend(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001239}
1240
1241static int host1x_drm_resume(struct device *dev)
1242{
1243 struct drm_device *drm = dev_get_drvdata(dev);
1244
Souptick Joarder53f1e062018-08-01 01:37:05 +05301245 return drm_mode_config_helper_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001246}
1247#endif
1248
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001249static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1250 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001251
Thierry Reding776dc382013-10-14 14:43:22 +02001252static const struct of_device_id host1x_drm_subdevs[] = {
1253 { .compatible = "nvidia,tegra20-dc", },
1254 { .compatible = "nvidia,tegra20-hdmi", },
1255 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001256 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001257 { .compatible = "nvidia,tegra30-dc", },
1258 { .compatible = "nvidia,tegra30-hdmi", },
1259 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001260 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001261 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001262 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001263 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001264 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001265 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001266 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001267 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001268 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001269 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001270 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001271 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001272 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001273 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001274 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001275 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001276 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001277 { .compatible = "nvidia,tegra186-sor", },
1278 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001279 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding5725daa2018-09-21 12:27:43 +02001280 { .compatible = "nvidia,tegra194-display", },
Thierry Reding47443192018-09-21 12:27:44 +02001281 { .compatible = "nvidia,tegra194-dc", },
Thierry Reding9b6c14b2018-09-21 12:27:46 +02001282 { .compatible = "nvidia,tegra194-sor", },
Thierry Redingd6b9bc02018-10-26 10:59:38 +02001283 { .compatible = "nvidia,tegra194-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001284 { /* sentinel */ }
1285};
1286
1287static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001288 .driver = {
1289 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001290 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001291 },
Thierry Reding776dc382013-10-14 14:43:22 +02001292 .probe = host1x_drm_probe,
1293 .remove = host1x_drm_remove,
1294 .subdevs = host1x_drm_subdevs,
1295};
1296
Thierry Reding473112e2015-09-10 16:07:14 +02001297static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001298 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001299 &tegra_dc_driver,
1300 &tegra_hdmi_driver,
1301 &tegra_dsi_driver,
1302 &tegra_dpaux_driver,
1303 &tegra_sor_driver,
1304 &tegra_gr2d_driver,
1305 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001306 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001307};
1308
Thierry Reding776dc382013-10-14 14:43:22 +02001309static int __init host1x_drm_init(void)
1310{
1311 int err;
1312
1313 err = host1x_driver_register(&host1x_drm_driver);
1314 if (err < 0)
1315 return err;
1316
Thierry Reding473112e2015-09-10 16:07:14 +02001317 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001318 if (err < 0)
1319 goto unregister_host1x;
1320
Thierry Reding776dc382013-10-14 14:43:22 +02001321 return 0;
1322
Thierry Reding776dc382013-10-14 14:43:22 +02001323unregister_host1x:
1324 host1x_driver_unregister(&host1x_drm_driver);
1325 return err;
1326}
1327module_init(host1x_drm_init);
1328
1329static void __exit host1x_drm_exit(void)
1330{
Thierry Reding473112e2015-09-10 16:07:14 +02001331 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001332 host1x_driver_unregister(&host1x_drm_driver);
1333}
1334module_exit(host1x_drm_exit);
1335
1336MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1337MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1338MODULE_LICENSE("GPL v2");