Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 3 | * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 10 | #include <linux/bitops.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 11 | #include <linux/host1x.h> |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 12 | #include <linux/idr.h> |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 13 | #include <linux/iommu.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 14 | |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 15 | #include <drm/drm_atomic.h> |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 16 | #include <drm/drm_atomic_helper.h> |
| 17 | |
Dmitry Osipenko | 5ac93f81 | 2018-08-19 17:24:20 +0300 | [diff] [blame] | 18 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) |
| 19 | #include <asm/dma-iommu.h> |
| 20 | #endif |
| 21 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 22 | #include "drm.h" |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 23 | #include "gem.h" |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 24 | |
| 25 | #define DRIVER_NAME "tegra" |
| 26 | #define DRIVER_DESC "NVIDIA Tegra graphics" |
| 27 | #define DRIVER_DATE "20120330" |
| 28 | #define DRIVER_MAJOR 0 |
| 29 | #define DRIVER_MINOR 0 |
| 30 | #define DRIVER_PATCHLEVEL 0 |
| 31 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 32 | #define CARVEOUT_SZ SZ_64M |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 33 | #define CDMA_GATHER_FETCHES_MAX_NB 16383 |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 34 | |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 35 | struct tegra_drm_file { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 36 | struct idr contexts; |
| 37 | struct mutex lock; |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 38 | }; |
| 39 | |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 40 | static int tegra_atomic_check(struct drm_device *drm, |
| 41 | struct drm_atomic_state *state) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 42 | { |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 43 | int err; |
| 44 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame] | 45 | err = drm_atomic_helper_check(drm, state); |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 46 | if (err < 0) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 47 | return err; |
| 48 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame] | 49 | return tegra_display_hub_atomic_check(drm, state); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 50 | } |
| 51 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 52 | static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 53 | .fb_create = tegra_fb_create, |
Archit Taneja | b110ef3 | 2015-10-27 13:40:59 +0530 | [diff] [blame] | 54 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Noralf Trønnes | c94beda | 2017-12-05 19:25:04 +0100 | [diff] [blame] | 55 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 56 | #endif |
Thierry Reding | ab7d3f5 | 2017-12-14 13:46:20 +0100 | [diff] [blame] | 57 | .atomic_check = tegra_atomic_check, |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 58 | .atomic_commit = drm_atomic_helper_commit, |
| 59 | }; |
| 60 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 61 | static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) |
| 62 | { |
| 63 | struct drm_device *drm = old_state->dev; |
| 64 | struct tegra_drm *tegra = drm->dev_private; |
| 65 | |
| 66 | if (tegra->hub) { |
| 67 | drm_atomic_helper_commit_modeset_disables(drm, old_state); |
| 68 | tegra_display_hub_atomic_commit(drm, old_state); |
| 69 | drm_atomic_helper_commit_planes(drm, old_state, 0); |
| 70 | drm_atomic_helper_commit_modeset_enables(drm, old_state); |
| 71 | drm_atomic_helper_commit_hw_done(old_state); |
| 72 | drm_atomic_helper_wait_for_vblanks(drm, old_state); |
| 73 | drm_atomic_helper_cleanup_planes(drm, old_state); |
| 74 | } else { |
| 75 | drm_atomic_helper_commit_tail_rpm(old_state); |
| 76 | } |
| 77 | } |
| 78 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 79 | static const struct drm_mode_config_helper_funcs |
| 80 | tegra_drm_mode_config_helpers = { |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 81 | .atomic_commit_tail = tegra_atomic_commit_tail, |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 82 | }; |
| 83 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 84 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 85 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 86 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 87 | struct tegra_drm *tegra; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 88 | int err; |
| 89 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 90 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 91 | if (!tegra) |
Terje Bergstrom | 692e6d7 | 2013-03-22 16:34:07 +0200 | [diff] [blame] | 92 | return -ENOMEM; |
| 93 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 94 | if (iommu_present(&platform_bus_type)) { |
| 95 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
Dan Carpenter | bf19b88 | 2014-12-04 14:00:35 +0300 | [diff] [blame] | 96 | if (!tegra->domain) { |
| 97 | err = -ENOMEM; |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 98 | goto free; |
| 99 | } |
| 100 | |
Thierry Reding | 24cfdc1 | 2018-04-23 08:57:45 +0200 | [diff] [blame] | 101 | err = iova_cache_get(); |
| 102 | if (err < 0) |
| 103 | goto domain; |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 104 | } |
| 105 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 106 | mutex_init(&tegra->clients_lock); |
| 107 | INIT_LIST_HEAD(&tegra->clients); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 108 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 109 | drm->dev_private = tegra; |
| 110 | tegra->drm = drm; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 111 | |
| 112 | drm_mode_config_init(drm); |
| 113 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 114 | drm->mode_config.min_width = 0; |
| 115 | drm->mode_config.min_height = 0; |
| 116 | |
| 117 | drm->mode_config.max_width = 4096; |
| 118 | drm->mode_config.max_height = 4096; |
| 119 | |
Alexandre Courbot | 5e91144 | 2016-11-08 16:50:42 +0900 | [diff] [blame] | 120 | drm->mode_config.allow_fb_modifiers = true; |
| 121 | |
Peter Ujfalusi | a18301b | 2018-03-21 12:20:26 +0200 | [diff] [blame] | 122 | drm->mode_config.normalize_zpos = true; |
| 123 | |
Thierry Reding | 31b02ca | 2017-10-12 17:40:46 +0200 | [diff] [blame] | 124 | drm->mode_config.funcs = &tegra_drm_mode_config_funcs; |
| 125 | drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 126 | |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 127 | err = tegra_drm_fb_prepare(drm); |
| 128 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 129 | goto config; |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 130 | |
| 131 | drm_kms_helper_poll_init(drm); |
| 132 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 133 | err = host1x_device_init(device); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 134 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 135 | goto fbdev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 136 | |
Thierry Reding | b9f8b09 | 2019-02-01 14:28:33 +0100 | [diff] [blame^] | 137 | if (tegra->domain) { |
| 138 | u64 carveout_start, carveout_end, gem_start, gem_end; |
| 139 | dma_addr_t start, end; |
| 140 | unsigned long order; |
| 141 | |
| 142 | start = tegra->domain->geometry.aperture_start; |
| 143 | end = tegra->domain->geometry.aperture_end; |
| 144 | |
| 145 | gem_start = start; |
| 146 | gem_end = end - CARVEOUT_SZ; |
| 147 | carveout_start = gem_end + 1; |
| 148 | carveout_end = end; |
| 149 | |
| 150 | order = __ffs(tegra->domain->pgsize_bitmap); |
| 151 | init_iova_domain(&tegra->carveout.domain, 1UL << order, |
| 152 | carveout_start >> order); |
| 153 | |
| 154 | tegra->carveout.shift = iova_shift(&tegra->carveout.domain); |
| 155 | tegra->carveout.limit = carveout_end >> tegra->carveout.shift; |
| 156 | |
| 157 | drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); |
| 158 | mutex_init(&tegra->mm_lock); |
| 159 | |
| 160 | DRM_DEBUG("IOMMU apertures:\n"); |
| 161 | DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end); |
| 162 | DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start, |
| 163 | carveout_end); |
| 164 | } |
| 165 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 166 | if (tegra->hub) { |
| 167 | err = tegra_display_hub_prepare(tegra->hub); |
| 168 | if (err < 0) |
| 169 | goto device; |
| 170 | } |
| 171 | |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 172 | /* |
| 173 | * We don't use the drm_irq_install() helpers provided by the DRM |
| 174 | * core, so we need to set this manually in order to allow the |
| 175 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. |
| 176 | */ |
Ville Syrjälä | 4423843 | 2013-10-04 14:53:37 +0300 | [diff] [blame] | 177 | drm->irq_enabled = true; |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 178 | |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 179 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 180 | drm->max_vblank_count = 0xffffffff; |
| 181 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 182 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
| 183 | if (err < 0) |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 184 | goto hub; |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 185 | |
Thierry Reding | 31930d4 | 2015-07-02 17:04:06 +0200 | [diff] [blame] | 186 | drm_mode_config_reset(drm); |
| 187 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 188 | err = tegra_drm_fb_init(drm); |
| 189 | if (err < 0) |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 190 | goto hub; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 191 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 192 | return 0; |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 193 | |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 194 | hub: |
| 195 | if (tegra->hub) |
| 196 | tegra_display_hub_cleanup(tegra->hub); |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 197 | device: |
| 198 | host1x_device_exit(device); |
| 199 | fbdev: |
| 200 | drm_kms_helper_poll_fini(drm); |
| 201 | tegra_drm_fb_free(drm); |
| 202 | config: |
| 203 | drm_mode_config_cleanup(drm); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 204 | |
| 205 | if (tegra->domain) { |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 206 | mutex_destroy(&tegra->mm_lock); |
Thierry Reding | 5f43ac8 | 2018-04-23 08:57:44 +0200 | [diff] [blame] | 207 | drm_mm_takedown(&tegra->mm); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 208 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | 24cfdc1 | 2018-04-23 08:57:45 +0200 | [diff] [blame] | 209 | iova_cache_put(); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 210 | } |
Thierry Reding | 24cfdc1 | 2018-04-23 08:57:45 +0200 | [diff] [blame] | 211 | domain: |
| 212 | if (tegra->domain) |
| 213 | iommu_domain_free(tegra->domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 214 | free: |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 215 | kfree(tegra); |
| 216 | return err; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 217 | } |
| 218 | |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 219 | static void tegra_drm_unload(struct drm_device *drm) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 220 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 221 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 222 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 223 | int err; |
| 224 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 225 | drm_kms_helper_poll_fini(drm); |
| 226 | tegra_drm_fb_exit(drm); |
Thierry Reding | 192b4af | 2018-03-18 01:13:39 +0100 | [diff] [blame] | 227 | drm_atomic_helper_shutdown(drm); |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 228 | drm_mode_config_cleanup(drm); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 229 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 230 | err = host1x_device_exit(device); |
| 231 | if (err < 0) |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 232 | return; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 233 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 234 | if (tegra->domain) { |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 235 | mutex_destroy(&tegra->mm_lock); |
Thierry Reding | 5f43ac8 | 2018-04-23 08:57:44 +0200 | [diff] [blame] | 236 | drm_mm_takedown(&tegra->mm); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 237 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | 24cfdc1 | 2018-04-23 08:57:45 +0200 | [diff] [blame] | 238 | iova_cache_put(); |
Thierry Reding | 5f43ac8 | 2018-04-23 08:57:44 +0200 | [diff] [blame] | 239 | iommu_domain_free(tegra->domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 240 | } |
| 241 | |
Thierry Reding | 1053f4dd | 2014-11-04 16:17:55 +0100 | [diff] [blame] | 242 | kfree(tegra); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) |
| 246 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 247 | struct tegra_drm_file *fpriv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 248 | |
| 249 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 250 | if (!fpriv) |
| 251 | return -ENOMEM; |
| 252 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 253 | idr_init(&fpriv->contexts); |
| 254 | mutex_init(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 255 | filp->driver_priv = fpriv; |
| 256 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 257 | return 0; |
| 258 | } |
| 259 | |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 260 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 261 | { |
| 262 | context->client->ops->close_channel(context); |
| 263 | kfree(context); |
| 264 | } |
| 265 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 266 | static struct host1x_bo * |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 267 | host1x_bo_lookup(struct drm_file *file, u32 handle) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 268 | { |
| 269 | struct drm_gem_object *gem; |
| 270 | struct tegra_bo *bo; |
| 271 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 272 | gem = drm_gem_object_lookup(file, handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 273 | if (!gem) |
| 274 | return NULL; |
| 275 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 276 | bo = to_tegra_bo(gem); |
| 277 | return &bo->base; |
| 278 | } |
| 279 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 280 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
| 281 | struct drm_tegra_reloc __user *src, |
| 282 | struct drm_device *drm, |
| 283 | struct drm_file *file) |
| 284 | { |
| 285 | u32 cmdbuf, target; |
| 286 | int err; |
| 287 | |
| 288 | err = get_user(cmdbuf, &src->cmdbuf.handle); |
| 289 | if (err < 0) |
| 290 | return err; |
| 291 | |
| 292 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); |
| 293 | if (err < 0) |
| 294 | return err; |
| 295 | |
| 296 | err = get_user(target, &src->target.handle); |
| 297 | if (err < 0) |
| 298 | return err; |
| 299 | |
David Ung | 31f40f8 | 2015-01-20 18:37:35 -0800 | [diff] [blame] | 300 | err = get_user(dest->target.offset, &src->target.offset); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 301 | if (err < 0) |
| 302 | return err; |
| 303 | |
| 304 | err = get_user(dest->shift, &src->shift); |
| 305 | if (err < 0) |
| 306 | return err; |
| 307 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 308 | dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 309 | if (!dest->cmdbuf.bo) |
| 310 | return -ENOENT; |
| 311 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 312 | dest->target.bo = host1x_bo_lookup(file, target); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 313 | if (!dest->target.bo) |
| 314 | return -ENOENT; |
| 315 | |
| 316 | return 0; |
| 317 | } |
| 318 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 319 | int tegra_drm_submit(struct tegra_drm_context *context, |
| 320 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 321 | struct drm_file *file) |
| 322 | { |
Thierry Reding | bf3d41c | 2018-05-16 14:12:33 +0200 | [diff] [blame] | 323 | struct host1x_client *client = &context->client->base; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 324 | unsigned int num_cmdbufs = args->num_cmdbufs; |
| 325 | unsigned int num_relocs = args->num_relocs; |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 326 | struct drm_tegra_cmdbuf __user *user_cmdbufs; |
| 327 | struct drm_tegra_reloc __user *user_relocs; |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 328 | struct drm_tegra_syncpt __user *user_syncpt; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 329 | struct drm_tegra_syncpt syncpt; |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 330 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 331 | struct drm_gem_object **refs; |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 332 | struct host1x_syncpt *sp; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 333 | struct host1x_job *job; |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 334 | unsigned int num_refs; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 335 | int err; |
| 336 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 337 | user_cmdbufs = u64_to_user_ptr(args->cmdbufs); |
| 338 | user_relocs = u64_to_user_ptr(args->relocs); |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 339 | user_syncpt = u64_to_user_ptr(args->syncpts); |
| 340 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 341 | /* We don't yet support other than one syncpt_incr struct per submit */ |
| 342 | if (args->num_syncpts != 1) |
| 343 | return -EINVAL; |
| 344 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 345 | /* We don't yet support waitchks */ |
| 346 | if (args->num_waitchks != 0) |
| 347 | return -EINVAL; |
| 348 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 349 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, |
Thierry Reding | 24c94e1 | 2018-05-05 08:45:47 +0200 | [diff] [blame] | 350 | args->num_relocs); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 351 | if (!job) |
| 352 | return -ENOMEM; |
| 353 | |
| 354 | job->num_relocs = args->num_relocs; |
Thierry Reding | bf3d41c | 2018-05-16 14:12:33 +0200 | [diff] [blame] | 355 | job->client = client; |
| 356 | job->class = client->class; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 357 | job->serialize = true; |
| 358 | |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 359 | /* |
| 360 | * Track referenced BOs so that they can be unreferenced after the |
| 361 | * submission is complete. |
| 362 | */ |
Thierry Reding | 24c94e1 | 2018-05-05 08:45:47 +0200 | [diff] [blame] | 363 | num_refs = num_cmdbufs + num_relocs * 2; |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 364 | |
| 365 | refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL); |
| 366 | if (!refs) { |
| 367 | err = -ENOMEM; |
| 368 | goto put; |
| 369 | } |
| 370 | |
| 371 | /* reuse as an iterator later */ |
| 372 | num_refs = 0; |
| 373 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 374 | while (num_cmdbufs) { |
| 375 | struct drm_tegra_cmdbuf cmdbuf; |
| 376 | struct host1x_bo *bo; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 377 | struct tegra_bo *obj; |
| 378 | u64 offset; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 379 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 380 | if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) { |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 381 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 382 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 383 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 384 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 385 | /* |
| 386 | * The maximum number of CDMA gather fetches is 16383, a higher |
| 387 | * value means the words count is malformed. |
| 388 | */ |
| 389 | if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { |
| 390 | err = -EINVAL; |
| 391 | goto fail; |
| 392 | } |
| 393 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 394 | bo = host1x_bo_lookup(file, cmdbuf.handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 395 | if (!bo) { |
| 396 | err = -ENOENT; |
| 397 | goto fail; |
| 398 | } |
| 399 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 400 | offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); |
| 401 | obj = host1x_to_tegra_bo(bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 402 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 403 | |
| 404 | /* |
| 405 | * Gather buffer base address must be 4-bytes aligned, |
| 406 | * unaligned offset is malformed and cause commands stream |
| 407 | * corruption on the buffer address relocation. |
| 408 | */ |
Mikko Perttunen | 5265f03 | 2018-06-20 16:03:58 +0300 | [diff] [blame] | 409 | if (offset & 3 || offset > obj->gem.size) { |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 410 | err = -EINVAL; |
| 411 | goto fail; |
| 412 | } |
| 413 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 414 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); |
| 415 | num_cmdbufs--; |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 416 | user_cmdbufs++; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 417 | } |
| 418 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 419 | /* copy and resolve relocations from submit */ |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 420 | while (num_relocs--) { |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 421 | struct host1x_reloc *reloc; |
| 422 | struct tegra_bo *obj; |
| 423 | |
Thierry Reding | 06490bb | 2018-05-16 16:58:44 +0200 | [diff] [blame] | 424 | err = host1x_reloc_copy_from_user(&job->relocs[num_relocs], |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 425 | &user_relocs[num_relocs], drm, |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 426 | file); |
| 427 | if (err < 0) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 428 | goto fail; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 429 | |
Thierry Reding | 06490bb | 2018-05-16 16:58:44 +0200 | [diff] [blame] | 430 | reloc = &job->relocs[num_relocs]; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 431 | obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 432 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 433 | |
| 434 | /* |
| 435 | * The unaligned cmdbuf offset will cause an unaligned write |
| 436 | * during of the relocations patching, corrupting the commands |
| 437 | * stream. |
| 438 | */ |
| 439 | if (reloc->cmdbuf.offset & 3 || |
| 440 | reloc->cmdbuf.offset >= obj->gem.size) { |
| 441 | err = -EINVAL; |
| 442 | goto fail; |
| 443 | } |
| 444 | |
| 445 | obj = host1x_to_tegra_bo(reloc->target.bo); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 446 | refs[num_refs++] = &obj->gem; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 447 | |
| 448 | if (reloc->target.offset >= obj->gem.size) { |
| 449 | err = -EINVAL; |
| 450 | goto fail; |
| 451 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 452 | } |
| 453 | |
Mikko Perttunen | a176c67 | 2017-09-28 15:50:44 +0300 | [diff] [blame] | 454 | if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) { |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 455 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 456 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 457 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 458 | |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 459 | /* check whether syncpoint ID is valid */ |
| 460 | sp = host1x_syncpt_get(host1x, syncpt.id); |
| 461 | if (!sp) { |
| 462 | err = -ENOENT; |
| 463 | goto fail; |
| 464 | } |
| 465 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 466 | job->is_addr_reg = context->client->ops->is_addr_reg; |
Dmitry Osipenko | 0f563a4 | 2017-06-15 02:18:37 +0300 | [diff] [blame] | 467 | job->is_valid_class = context->client->ops->is_valid_class; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 468 | job->syncpt_incrs = syncpt.incrs; |
| 469 | job->syncpt_id = syncpt.id; |
| 470 | job->timeout = 10000; |
| 471 | |
| 472 | if (args->timeout && args->timeout < 10000) |
| 473 | job->timeout = args->timeout; |
| 474 | |
| 475 | err = host1x_job_pin(job, context->client->base.dev); |
| 476 | if (err) |
| 477 | goto fail; |
| 478 | |
| 479 | err = host1x_job_submit(job); |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 480 | if (err) { |
| 481 | host1x_job_unpin(job); |
| 482 | goto fail; |
| 483 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 484 | |
| 485 | args->fence = job->syncpt_end; |
| 486 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 487 | fail: |
Dmitry Osipenko | ec73c4c | 2017-08-11 19:54:56 +0200 | [diff] [blame] | 488 | while (num_refs--) |
| 489 | drm_gem_object_put_unlocked(refs[num_refs]); |
| 490 | |
| 491 | kfree(refs); |
| 492 | |
| 493 | put: |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 494 | host1x_job_put(job); |
| 495 | return err; |
| 496 | } |
| 497 | |
| 498 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 499 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 500 | static int tegra_gem_create(struct drm_device *drm, void *data, |
| 501 | struct drm_file *file) |
| 502 | { |
| 503 | struct drm_tegra_gem_create *args = data; |
| 504 | struct tegra_bo *bo; |
| 505 | |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 506 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 507 | &args->handle); |
| 508 | if (IS_ERR(bo)) |
| 509 | return PTR_ERR(bo); |
| 510 | |
| 511 | return 0; |
| 512 | } |
| 513 | |
| 514 | static int tegra_gem_mmap(struct drm_device *drm, void *data, |
| 515 | struct drm_file *file) |
| 516 | { |
| 517 | struct drm_tegra_gem_mmap *args = data; |
| 518 | struct drm_gem_object *gem; |
| 519 | struct tegra_bo *bo; |
| 520 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 521 | gem = drm_gem_object_lookup(file, args->handle); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 522 | if (!gem) |
| 523 | return -EINVAL; |
| 524 | |
| 525 | bo = to_tegra_bo(gem); |
| 526 | |
David Herrmann | 2bc7b0c | 2013-08-13 14:19:58 +0200 | [diff] [blame] | 527 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 528 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 529 | drm_gem_object_put_unlocked(gem); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 530 | |
| 531 | return 0; |
| 532 | } |
| 533 | |
| 534 | static int tegra_syncpt_read(struct drm_device *drm, void *data, |
| 535 | struct drm_file *file) |
| 536 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 537 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 538 | struct drm_tegra_syncpt_read *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 539 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 540 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 541 | sp = host1x_syncpt_get(host, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 542 | if (!sp) |
| 543 | return -EINVAL; |
| 544 | |
| 545 | args->value = host1x_syncpt_read_min(sp); |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, |
| 550 | struct drm_file *file) |
| 551 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 552 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 553 | struct drm_tegra_syncpt_incr *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 554 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 555 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 556 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 557 | if (!sp) |
| 558 | return -EINVAL; |
| 559 | |
Arto Merilainen | ebae30b | 2013-05-29 13:26:08 +0300 | [diff] [blame] | 560 | return host1x_syncpt_incr(sp); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, |
| 564 | struct drm_file *file) |
| 565 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 566 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 567 | struct drm_tegra_syncpt_wait *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 568 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 569 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 570 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 571 | if (!sp) |
| 572 | return -EINVAL; |
| 573 | |
Dmitry Osipenko | 4c69ac12 | 2017-12-20 18:46:14 +0300 | [diff] [blame] | 574 | return host1x_syncpt_wait(sp, args->thresh, |
| 575 | msecs_to_jiffies(args->timeout), |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 576 | &args->value); |
| 577 | } |
| 578 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 579 | static int tegra_client_open(struct tegra_drm_file *fpriv, |
| 580 | struct tegra_drm_client *client, |
| 581 | struct tegra_drm_context *context) |
| 582 | { |
| 583 | int err; |
| 584 | |
| 585 | err = client->ops->open_channel(client, context); |
| 586 | if (err < 0) |
| 587 | return err; |
| 588 | |
Dmitry Osipenko | d6c153e | 2017-06-15 02:18:25 +0300 | [diff] [blame] | 589 | err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 590 | if (err < 0) { |
| 591 | client->ops->close_channel(context); |
| 592 | return err; |
| 593 | } |
| 594 | |
| 595 | context->client = client; |
| 596 | context->id = err; |
| 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 601 | static int tegra_open_channel(struct drm_device *drm, void *data, |
| 602 | struct drm_file *file) |
| 603 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 604 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 605 | struct tegra_drm *tegra = drm->dev_private; |
| 606 | struct drm_tegra_open_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 607 | struct tegra_drm_context *context; |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 608 | struct tegra_drm_client *client; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 609 | int err = -ENODEV; |
| 610 | |
| 611 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
| 612 | if (!context) |
| 613 | return -ENOMEM; |
| 614 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 615 | mutex_lock(&fpriv->lock); |
| 616 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 617 | list_for_each_entry(client, &tegra->clients, list) |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 618 | if (client->base.class == args->client) { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 619 | err = tegra_client_open(fpriv, client, context); |
| 620 | if (err < 0) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 621 | break; |
| 622 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 623 | args->context = context->id; |
| 624 | break; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 625 | } |
| 626 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 627 | if (err < 0) |
| 628 | kfree(context); |
| 629 | |
| 630 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 631 | return err; |
| 632 | } |
| 633 | |
| 634 | static int tegra_close_channel(struct drm_device *drm, void *data, |
| 635 | struct drm_file *file) |
| 636 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 637 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 638 | struct drm_tegra_close_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 639 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 640 | int err = 0; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 641 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 642 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 643 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 644 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 645 | if (!context) { |
| 646 | err = -EINVAL; |
| 647 | goto unlock; |
| 648 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 649 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 650 | idr_remove(&fpriv->contexts, context->id); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 651 | tegra_drm_context_free(context); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 652 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 653 | unlock: |
| 654 | mutex_unlock(&fpriv->lock); |
| 655 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 656 | } |
| 657 | |
| 658 | static int tegra_get_syncpt(struct drm_device *drm, void *data, |
| 659 | struct drm_file *file) |
| 660 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 661 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 662 | struct drm_tegra_get_syncpt *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 663 | struct tegra_drm_context *context; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 664 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 665 | int err = 0; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 666 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 667 | mutex_lock(&fpriv->lock); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 668 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 669 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 670 | if (!context) { |
| 671 | err = -ENODEV; |
| 672 | goto unlock; |
| 673 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 674 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 675 | if (args->index >= context->client->base.num_syncpts) { |
| 676 | err = -EINVAL; |
| 677 | goto unlock; |
| 678 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 679 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 680 | syncpt = context->client->base.syncpts[args->index]; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 681 | args->id = host1x_syncpt_id(syncpt); |
| 682 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 683 | unlock: |
| 684 | mutex_unlock(&fpriv->lock); |
| 685 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 686 | } |
| 687 | |
| 688 | static int tegra_submit(struct drm_device *drm, void *data, |
| 689 | struct drm_file *file) |
| 690 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 691 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 692 | struct drm_tegra_submit *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 693 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 694 | int err; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 695 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 696 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 697 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 698 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 699 | if (!context) { |
| 700 | err = -ENODEV; |
| 701 | goto unlock; |
| 702 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 703 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 704 | err = context->client->ops->submit(context, args, drm, file); |
| 705 | |
| 706 | unlock: |
| 707 | mutex_unlock(&fpriv->lock); |
| 708 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 709 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 710 | |
| 711 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, |
| 712 | struct drm_file *file) |
| 713 | { |
| 714 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 715 | struct drm_tegra_get_syncpt_base *args = data; |
| 716 | struct tegra_drm_context *context; |
| 717 | struct host1x_syncpt_base *base; |
| 718 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 719 | int err = 0; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 720 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 721 | mutex_lock(&fpriv->lock); |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 722 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 723 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 724 | if (!context) { |
| 725 | err = -ENODEV; |
| 726 | goto unlock; |
| 727 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 728 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 729 | if (args->syncpt >= context->client->base.num_syncpts) { |
| 730 | err = -EINVAL; |
| 731 | goto unlock; |
| 732 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 733 | |
| 734 | syncpt = context->client->base.syncpts[args->syncpt]; |
| 735 | |
| 736 | base = host1x_syncpt_get_base(syncpt); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 737 | if (!base) { |
| 738 | err = -ENXIO; |
| 739 | goto unlock; |
| 740 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 741 | |
| 742 | args->id = host1x_syncpt_base_id(base); |
| 743 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 744 | unlock: |
| 745 | mutex_unlock(&fpriv->lock); |
| 746 | return err; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 747 | } |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 748 | |
| 749 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, |
| 750 | struct drm_file *file) |
| 751 | { |
| 752 | struct drm_tegra_gem_set_tiling *args = data; |
| 753 | enum tegra_bo_tiling_mode mode; |
| 754 | struct drm_gem_object *gem; |
| 755 | unsigned long value = 0; |
| 756 | struct tegra_bo *bo; |
| 757 | |
| 758 | switch (args->mode) { |
| 759 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: |
| 760 | mode = TEGRA_BO_TILING_MODE_PITCH; |
| 761 | |
| 762 | if (args->value != 0) |
| 763 | return -EINVAL; |
| 764 | |
| 765 | break; |
| 766 | |
| 767 | case DRM_TEGRA_GEM_TILING_MODE_TILED: |
| 768 | mode = TEGRA_BO_TILING_MODE_TILED; |
| 769 | |
| 770 | if (args->value != 0) |
| 771 | return -EINVAL; |
| 772 | |
| 773 | break; |
| 774 | |
| 775 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: |
| 776 | mode = TEGRA_BO_TILING_MODE_BLOCK; |
| 777 | |
| 778 | if (args->value > 5) |
| 779 | return -EINVAL; |
| 780 | |
| 781 | value = args->value; |
| 782 | break; |
| 783 | |
| 784 | default: |
| 785 | return -EINVAL; |
| 786 | } |
| 787 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 788 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 789 | if (!gem) |
| 790 | return -ENOENT; |
| 791 | |
| 792 | bo = to_tegra_bo(gem); |
| 793 | |
| 794 | bo->tiling.mode = mode; |
| 795 | bo->tiling.value = value; |
| 796 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 797 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 798 | |
| 799 | return 0; |
| 800 | } |
| 801 | |
| 802 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, |
| 803 | struct drm_file *file) |
| 804 | { |
| 805 | struct drm_tegra_gem_get_tiling *args = data; |
| 806 | struct drm_gem_object *gem; |
| 807 | struct tegra_bo *bo; |
| 808 | int err = 0; |
| 809 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 810 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 811 | if (!gem) |
| 812 | return -ENOENT; |
| 813 | |
| 814 | bo = to_tegra_bo(gem); |
| 815 | |
| 816 | switch (bo->tiling.mode) { |
| 817 | case TEGRA_BO_TILING_MODE_PITCH: |
| 818 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; |
| 819 | args->value = 0; |
| 820 | break; |
| 821 | |
| 822 | case TEGRA_BO_TILING_MODE_TILED: |
| 823 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; |
| 824 | args->value = 0; |
| 825 | break; |
| 826 | |
| 827 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 828 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; |
| 829 | args->value = bo->tiling.value; |
| 830 | break; |
| 831 | |
| 832 | default: |
| 833 | err = -EINVAL; |
| 834 | break; |
| 835 | } |
| 836 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 837 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 838 | |
| 839 | return err; |
| 840 | } |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 841 | |
| 842 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, |
| 843 | struct drm_file *file) |
| 844 | { |
| 845 | struct drm_tegra_gem_set_flags *args = data; |
| 846 | struct drm_gem_object *gem; |
| 847 | struct tegra_bo *bo; |
| 848 | |
| 849 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) |
| 850 | return -EINVAL; |
| 851 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 852 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 853 | if (!gem) |
| 854 | return -ENOENT; |
| 855 | |
| 856 | bo = to_tegra_bo(gem); |
| 857 | bo->flags = 0; |
| 858 | |
| 859 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) |
| 860 | bo->flags |= TEGRA_BO_BOTTOM_UP; |
| 861 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 862 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 863 | |
| 864 | return 0; |
| 865 | } |
| 866 | |
| 867 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, |
| 868 | struct drm_file *file) |
| 869 | { |
| 870 | struct drm_tegra_gem_get_flags *args = data; |
| 871 | struct drm_gem_object *gem; |
| 872 | struct tegra_bo *bo; |
| 873 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 874 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 875 | if (!gem) |
| 876 | return -ENOENT; |
| 877 | |
| 878 | bo = to_tegra_bo(gem); |
| 879 | args->flags = 0; |
| 880 | |
| 881 | if (bo->flags & TEGRA_BO_BOTTOM_UP) |
| 882 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; |
| 883 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame] | 884 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 885 | |
| 886 | return 0; |
| 887 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 888 | #endif |
| 889 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 890 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 891 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 892 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, |
| 893 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 894 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, |
| 895 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 896 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, |
| 897 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 898 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, |
| 899 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 900 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, |
| 901 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 902 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, |
| 903 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 904 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, |
| 905 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 906 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, |
| 907 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 908 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, |
| 909 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 910 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, |
| 911 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 912 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, |
| 913 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 914 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, |
| 915 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 916 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, |
| 917 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
| 918 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, |
| 919 | DRM_UNLOCKED | DRM_RENDER_ALLOW), |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 920 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 921 | }; |
| 922 | |
| 923 | static const struct file_operations tegra_drm_fops = { |
| 924 | .owner = THIS_MODULE, |
| 925 | .open = drm_open, |
| 926 | .release = drm_release, |
| 927 | .unlocked_ioctl = drm_ioctl, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 928 | .mmap = tegra_drm_mmap, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 929 | .poll = drm_poll, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 930 | .read = drm_read, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 931 | .compat_ioctl = drm_compat_ioctl, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 932 | .llseek = noop_llseek, |
| 933 | }; |
| 934 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 935 | static int tegra_drm_context_cleanup(int id, void *p, void *data) |
| 936 | { |
| 937 | struct tegra_drm_context *context = p; |
| 938 | |
| 939 | tegra_drm_context_free(context); |
| 940 | |
| 941 | return 0; |
| 942 | } |
| 943 | |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 944 | static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 945 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 946 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 947 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 948 | mutex_lock(&fpriv->lock); |
| 949 | idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); |
| 950 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 951 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 952 | idr_destroy(&fpriv->contexts); |
| 953 | mutex_destroy(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 954 | kfree(fpriv); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 955 | } |
| 956 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 957 | #ifdef CONFIG_DEBUG_FS |
| 958 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) |
| 959 | { |
| 960 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 961 | struct drm_device *drm = node->minor->dev; |
| 962 | struct drm_framebuffer *fb; |
| 963 | |
| 964 | mutex_lock(&drm->mode_config.fb_lock); |
| 965 | |
| 966 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { |
| 967 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", |
Ville Syrjälä | b00c600 | 2016-12-14 23:31:35 +0200 | [diff] [blame] | 968 | fb->base.id, fb->width, fb->height, |
| 969 | fb->format->depth, |
Ville Syrjälä | 272725c | 2016-12-14 23:32:20 +0200 | [diff] [blame] | 970 | fb->format->cpp[0] * 8, |
Dave Airlie | 747a598 | 2016-04-15 15:10:35 +1000 | [diff] [blame] | 971 | drm_framebuffer_read_refcount(fb)); |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 972 | } |
| 973 | |
| 974 | mutex_unlock(&drm->mode_config.fb_lock); |
| 975 | |
| 976 | return 0; |
| 977 | } |
| 978 | |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 979 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
| 980 | { |
| 981 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 982 | struct drm_device *drm = node->minor->dev; |
| 983 | struct tegra_drm *tegra = drm->dev_private; |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 984 | struct drm_printer p = drm_seq_file_printer(s); |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 985 | |
Michał Mirosław | 68d890a | 2017-08-14 23:53:45 +0200 | [diff] [blame] | 986 | if (tegra->domain) { |
| 987 | mutex_lock(&tegra->mm_lock); |
| 988 | drm_mm_print(&tegra->mm, &p); |
| 989 | mutex_unlock(&tegra->mm_lock); |
| 990 | } |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 991 | |
| 992 | return 0; |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 993 | } |
| 994 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 995 | static struct drm_info_list tegra_debugfs_list[] = { |
| 996 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 997 | { "iova", tegra_debugfs_iova, 0 }, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 998 | }; |
| 999 | |
| 1000 | static int tegra_debugfs_init(struct drm_minor *minor) |
| 1001 | { |
| 1002 | return drm_debugfs_create_files(tegra_debugfs_list, |
| 1003 | ARRAY_SIZE(tegra_debugfs_list), |
| 1004 | minor->debugfs_root, minor); |
| 1005 | } |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1006 | #endif |
| 1007 | |
Thierry Reding | 9b57f5f | 2013-11-08 13:17:14 +0100 | [diff] [blame] | 1008 | static struct drm_driver tegra_drm_driver = { |
Thierry Reding | ad90659 | 2015-09-24 18:38:09 +0200 | [diff] [blame] | 1009 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
Thierry Reding | 6c68b71 | 2017-08-15 15:42:39 +0200 | [diff] [blame] | 1010 | DRIVER_ATOMIC | DRIVER_RENDER, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1011 | .load = tegra_drm_load, |
| 1012 | .unload = tegra_drm_unload, |
| 1013 | .open = tegra_drm_open, |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 1014 | .postclose = tegra_drm_postclose, |
Noralf Trønnes | c94beda | 2017-12-05 19:25:04 +0100 | [diff] [blame] | 1015 | .lastclose = drm_fb_helper_lastclose, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1016 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1017 | #if defined(CONFIG_DEBUG_FS) |
| 1018 | .debugfs_init = tegra_debugfs_init, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1019 | #endif |
| 1020 | |
Daniel Vetter | 1ddbdbd | 2016-04-26 19:30:00 +0200 | [diff] [blame] | 1021 | .gem_free_object_unlocked = tegra_bo_free_object, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1022 | .gem_vm_ops = &tegra_bo_vm_ops, |
Thierry Reding | 3800391 | 2013-12-12 10:00:43 +0100 | [diff] [blame] | 1023 | |
| 1024 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1025 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1026 | .gem_prime_export = tegra_gem_prime_export, |
| 1027 | .gem_prime_import = tegra_gem_prime_import, |
| 1028 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1029 | .dumb_create = tegra_bo_dumb_create, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1030 | |
| 1031 | .ioctls = tegra_drm_ioctls, |
| 1032 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), |
| 1033 | .fops = &tegra_drm_fops, |
| 1034 | |
| 1035 | .name = DRIVER_NAME, |
| 1036 | .desc = DRIVER_DESC, |
| 1037 | .date = DRIVER_DATE, |
| 1038 | .major = DRIVER_MAJOR, |
| 1039 | .minor = DRIVER_MINOR, |
| 1040 | .patchlevel = DRIVER_PATCHLEVEL, |
| 1041 | }; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1042 | |
| 1043 | int tegra_drm_register_client(struct tegra_drm *tegra, |
| 1044 | struct tegra_drm_client *client) |
| 1045 | { |
| 1046 | mutex_lock(&tegra->clients_lock); |
| 1047 | list_add_tail(&client->list, &tegra->clients); |
Thierry Reding | 8e5d19c | 2019-02-01 14:28:31 +0100 | [diff] [blame] | 1048 | client->drm = tegra; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1049 | mutex_unlock(&tegra->clients_lock); |
| 1050 | |
| 1051 | return 0; |
| 1052 | } |
| 1053 | |
| 1054 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
| 1055 | struct tegra_drm_client *client) |
| 1056 | { |
| 1057 | mutex_lock(&tegra->clients_lock); |
| 1058 | list_del_init(&client->list); |
Thierry Reding | 8e5d19c | 2019-02-01 14:28:31 +0100 | [diff] [blame] | 1059 | client->drm = NULL; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1060 | mutex_unlock(&tegra->clients_lock); |
| 1061 | |
| 1062 | return 0; |
| 1063 | } |
| 1064 | |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1065 | struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client, |
| 1066 | bool shared) |
| 1067 | { |
| 1068 | struct drm_device *drm = dev_get_drvdata(client->parent); |
| 1069 | struct tegra_drm *tegra = drm->dev_private; |
| 1070 | struct iommu_group *group = NULL; |
| 1071 | int err; |
| 1072 | |
| 1073 | if (tegra->domain) { |
| 1074 | group = iommu_group_get(client->dev); |
| 1075 | if (!group) { |
| 1076 | dev_err(client->dev, "failed to get IOMMU group\n"); |
| 1077 | return ERR_PTR(-ENODEV); |
| 1078 | } |
| 1079 | |
| 1080 | if (!shared || (shared && (group != tegra->group))) { |
Dmitry Osipenko | 5ac93f81 | 2018-08-19 17:24:20 +0300 | [diff] [blame] | 1081 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) |
| 1082 | if (client->dev->archdata.mapping) { |
| 1083 | struct dma_iommu_mapping *mapping = |
| 1084 | to_dma_iommu_mapping(client->dev); |
| 1085 | arm_iommu_detach_device(client->dev); |
| 1086 | arm_iommu_release_mapping(mapping); |
| 1087 | } |
| 1088 | #endif |
Thierry Reding | 0c407de | 2018-05-04 15:02:24 +0200 | [diff] [blame] | 1089 | err = iommu_attach_group(tegra->domain, group); |
| 1090 | if (err < 0) { |
| 1091 | iommu_group_put(group); |
| 1092 | return ERR_PTR(err); |
| 1093 | } |
| 1094 | |
| 1095 | if (shared && !tegra->group) |
| 1096 | tegra->group = group; |
| 1097 | } |
| 1098 | } |
| 1099 | |
| 1100 | return group; |
| 1101 | } |
| 1102 | |
| 1103 | void host1x_client_iommu_detach(struct host1x_client *client, |
| 1104 | struct iommu_group *group) |
| 1105 | { |
| 1106 | struct drm_device *drm = dev_get_drvdata(client->parent); |
| 1107 | struct tegra_drm *tegra = drm->dev_private; |
| 1108 | |
| 1109 | if (group) { |
| 1110 | if (group == tegra->group) { |
| 1111 | iommu_detach_group(tegra->domain, group); |
| 1112 | tegra->group = NULL; |
| 1113 | } |
| 1114 | |
| 1115 | iommu_group_put(group); |
| 1116 | } |
| 1117 | } |
| 1118 | |
Thierry Reding | 67485fb | 2017-11-09 13:17:11 +0100 | [diff] [blame] | 1119 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma) |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 1120 | { |
| 1121 | struct iova *alloc; |
| 1122 | void *virt; |
| 1123 | gfp_t gfp; |
| 1124 | int err; |
| 1125 | |
| 1126 | if (tegra->domain) |
| 1127 | size = iova_align(&tegra->carveout.domain, size); |
| 1128 | else |
| 1129 | size = PAGE_ALIGN(size); |
| 1130 | |
| 1131 | gfp = GFP_KERNEL | __GFP_ZERO; |
| 1132 | if (!tegra->domain) { |
| 1133 | /* |
| 1134 | * Many units only support 32-bit addresses, even on 64-bit |
| 1135 | * SoCs. If there is no IOMMU to translate into a 32-bit IO |
| 1136 | * virtual address space, force allocations to be in the |
| 1137 | * lower 32-bit range. |
| 1138 | */ |
| 1139 | gfp |= GFP_DMA; |
| 1140 | } |
| 1141 | |
| 1142 | virt = (void *)__get_free_pages(gfp, get_order(size)); |
| 1143 | if (!virt) |
| 1144 | return ERR_PTR(-ENOMEM); |
| 1145 | |
| 1146 | if (!tegra->domain) { |
| 1147 | /* |
| 1148 | * If IOMMU is disabled, devices address physical memory |
| 1149 | * directly. |
| 1150 | */ |
| 1151 | *dma = virt_to_phys(virt); |
| 1152 | return virt; |
| 1153 | } |
| 1154 | |
| 1155 | alloc = alloc_iova(&tegra->carveout.domain, |
| 1156 | size >> tegra->carveout.shift, |
| 1157 | tegra->carveout.limit, true); |
| 1158 | if (!alloc) { |
| 1159 | err = -EBUSY; |
| 1160 | goto free_pages; |
| 1161 | } |
| 1162 | |
| 1163 | *dma = iova_dma_addr(&tegra->carveout.domain, alloc); |
| 1164 | err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), |
| 1165 | size, IOMMU_READ | IOMMU_WRITE); |
| 1166 | if (err < 0) |
| 1167 | goto free_iova; |
| 1168 | |
| 1169 | return virt; |
| 1170 | |
| 1171 | free_iova: |
| 1172 | __free_iova(&tegra->carveout.domain, alloc); |
| 1173 | free_pages: |
| 1174 | free_pages((unsigned long)virt, get_order(size)); |
| 1175 | |
| 1176 | return ERR_PTR(err); |
| 1177 | } |
| 1178 | |
| 1179 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, |
| 1180 | dma_addr_t dma) |
| 1181 | { |
| 1182 | if (tegra->domain) |
| 1183 | size = iova_align(&tegra->carveout.domain, size); |
| 1184 | else |
| 1185 | size = PAGE_ALIGN(size); |
| 1186 | |
| 1187 | if (tegra->domain) { |
| 1188 | iommu_unmap(tegra->domain, dma, size); |
| 1189 | free_iova(&tegra->carveout.domain, |
| 1190 | iova_pfn(&tegra->carveout.domain, dma)); |
| 1191 | } |
| 1192 | |
| 1193 | free_pages((unsigned long)virt, get_order(size)); |
| 1194 | } |
| 1195 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1196 | static int host1x_drm_probe(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1197 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1198 | struct drm_driver *driver = &tegra_drm_driver; |
| 1199 | struct drm_device *drm; |
| 1200 | int err; |
| 1201 | |
| 1202 | drm = drm_dev_alloc(driver, &dev->dev); |
Tom Gundersen | 0f28860 | 2016-09-21 16:59:19 +0200 | [diff] [blame] | 1203 | if (IS_ERR(drm)) |
| 1204 | return PTR_ERR(drm); |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1205 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1206 | dev_set_drvdata(&dev->dev, drm); |
| 1207 | |
Michał Mirosław | 6e4228f | 2018-09-01 16:08:51 +0200 | [diff] [blame] | 1208 | err = drm_fb_helper_remove_conflicting_framebuffers(NULL, "tegradrmfb", false); |
| 1209 | if (err < 0) |
Thomas Zimmermann | 9c94209 | 2018-09-26 13:56:40 +0200 | [diff] [blame] | 1210 | goto put; |
Michał Mirosław | 6e4228f | 2018-09-01 16:08:51 +0200 | [diff] [blame] | 1211 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1212 | err = drm_dev_register(drm, 0); |
| 1213 | if (err < 0) |
Thomas Zimmermann | 9c94209 | 2018-09-26 13:56:40 +0200 | [diff] [blame] | 1214 | goto put; |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1215 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1216 | return 0; |
| 1217 | |
Thomas Zimmermann | 9c94209 | 2018-09-26 13:56:40 +0200 | [diff] [blame] | 1218 | put: |
| 1219 | drm_dev_put(drm); |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1220 | return err; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1221 | } |
| 1222 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1223 | static int host1x_drm_remove(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1224 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1225 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
| 1226 | |
| 1227 | drm_dev_unregister(drm); |
Thomas Zimmermann | 9c94209 | 2018-09-26 13:56:40 +0200 | [diff] [blame] | 1228 | drm_dev_put(drm); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1229 | |
| 1230 | return 0; |
| 1231 | } |
| 1232 | |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1233 | #ifdef CONFIG_PM_SLEEP |
| 1234 | static int host1x_drm_suspend(struct device *dev) |
| 1235 | { |
| 1236 | struct drm_device *drm = dev_get_drvdata(dev); |
| 1237 | |
Souptick Joarder | 53f1e06 | 2018-08-01 01:37:05 +0530 | [diff] [blame] | 1238 | return drm_mode_config_helper_suspend(drm); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1239 | } |
| 1240 | |
| 1241 | static int host1x_drm_resume(struct device *dev) |
| 1242 | { |
| 1243 | struct drm_device *drm = dev_get_drvdata(dev); |
| 1244 | |
Souptick Joarder | 53f1e06 | 2018-08-01 01:37:05 +0530 | [diff] [blame] | 1245 | return drm_mode_config_helper_resume(drm); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1246 | } |
| 1247 | #endif |
| 1248 | |
Thierry Reding | a13f1dc | 2015-08-11 13:22:44 +0200 | [diff] [blame] | 1249 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
| 1250 | host1x_drm_resume); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1251 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1252 | static const struct of_device_id host1x_drm_subdevs[] = { |
| 1253 | { .compatible = "nvidia,tegra20-dc", }, |
| 1254 | { .compatible = "nvidia,tegra20-hdmi", }, |
| 1255 | { .compatible = "nvidia,tegra20-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1256 | { .compatible = "nvidia,tegra20-gr3d", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1257 | { .compatible = "nvidia,tegra30-dc", }, |
| 1258 | { .compatible = "nvidia,tegra30-hdmi", }, |
| 1259 | { .compatible = "nvidia,tegra30-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1260 | { .compatible = "nvidia,tegra30-gr3d", }, |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 1261 | { .compatible = "nvidia,tegra114-dsi", }, |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1262 | { .compatible = "nvidia,tegra114-hdmi", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1263 | { .compatible = "nvidia,tegra114-gr3d", }, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1264 | { .compatible = "nvidia,tegra124-dc", }, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1265 | { .compatible = "nvidia,tegra124-sor", }, |
Thierry Reding | fb7be70 | 2013-11-15 16:07:32 +0100 | [diff] [blame] | 1266 | { .compatible = "nvidia,tegra124-hdmi", }, |
Thierry Reding | 7d33858 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1267 | { .compatible = "nvidia,tegra124-dsi", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1268 | { .compatible = "nvidia,tegra124-vic", }, |
Thierry Reding | c06c793 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1269 | { .compatible = "nvidia,tegra132-dsi", }, |
Thierry Reding | 5b4f516 | 2015-03-27 10:31:58 +0100 | [diff] [blame] | 1270 | { .compatible = "nvidia,tegra210-dc", }, |
Thierry Reding | ddfb406 | 2015-04-08 16:56:22 +0200 | [diff] [blame] | 1271 | { .compatible = "nvidia,tegra210-dsi", }, |
Thierry Reding | 3309ac8 | 2015-07-30 10:32:46 +0200 | [diff] [blame] | 1272 | { .compatible = "nvidia,tegra210-sor", }, |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1273 | { .compatible = "nvidia,tegra210-sor1", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1274 | { .compatible = "nvidia,tegra210-vic", }, |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 1275 | { .compatible = "nvidia,tegra186-display", }, |
Thierry Reding | 4730795 | 2017-08-30 17:42:54 +0200 | [diff] [blame] | 1276 | { .compatible = "nvidia,tegra186-dc", }, |
Thierry Reding | c57997b | 2017-10-12 19:12:57 +0200 | [diff] [blame] | 1277 | { .compatible = "nvidia,tegra186-sor", }, |
| 1278 | { .compatible = "nvidia,tegra186-sor1", }, |
Mikko Perttunen | 6e44b9a | 2017-09-05 11:43:06 +0300 | [diff] [blame] | 1279 | { .compatible = "nvidia,tegra186-vic", }, |
Thierry Reding | 5725daa | 2018-09-21 12:27:43 +0200 | [diff] [blame] | 1280 | { .compatible = "nvidia,tegra194-display", }, |
Thierry Reding | 4744319 | 2018-09-21 12:27:44 +0200 | [diff] [blame] | 1281 | { .compatible = "nvidia,tegra194-dc", }, |
Thierry Reding | 9b6c14b | 2018-09-21 12:27:46 +0200 | [diff] [blame] | 1282 | { .compatible = "nvidia,tegra194-sor", }, |
Thierry Reding | d6b9bc0 | 2018-10-26 10:59:38 +0200 | [diff] [blame] | 1283 | { .compatible = "nvidia,tegra194-vic", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1284 | { /* sentinel */ } |
| 1285 | }; |
| 1286 | |
| 1287 | static struct host1x_driver host1x_drm_driver = { |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1288 | .driver = { |
| 1289 | .name = "drm", |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1290 | .pm = &host1x_drm_pm_ops, |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1291 | }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1292 | .probe = host1x_drm_probe, |
| 1293 | .remove = host1x_drm_remove, |
| 1294 | .subdevs = host1x_drm_subdevs, |
| 1295 | }; |
| 1296 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1297 | static struct platform_driver * const drivers[] = { |
Thierry Reding | c4755fb | 2017-11-13 11:08:13 +0100 | [diff] [blame] | 1298 | &tegra_display_hub_driver, |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1299 | &tegra_dc_driver, |
| 1300 | &tegra_hdmi_driver, |
| 1301 | &tegra_dsi_driver, |
| 1302 | &tegra_dpaux_driver, |
| 1303 | &tegra_sor_driver, |
| 1304 | &tegra_gr2d_driver, |
| 1305 | &tegra_gr3d_driver, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1306 | &tegra_vic_driver, |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1307 | }; |
| 1308 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1309 | static int __init host1x_drm_init(void) |
| 1310 | { |
| 1311 | int err; |
| 1312 | |
| 1313 | err = host1x_driver_register(&host1x_drm_driver); |
| 1314 | if (err < 0) |
| 1315 | return err; |
| 1316 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1317 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1318 | if (err < 0) |
| 1319 | goto unregister_host1x; |
| 1320 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1321 | return 0; |
| 1322 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1323 | unregister_host1x: |
| 1324 | host1x_driver_unregister(&host1x_drm_driver); |
| 1325 | return err; |
| 1326 | } |
| 1327 | module_init(host1x_drm_init); |
| 1328 | |
| 1329 | static void __exit host1x_drm_exit(void) |
| 1330 | { |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1331 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1332 | host1x_driver_unregister(&host1x_drm_driver); |
| 1333 | } |
| 1334 | module_exit(host1x_drm_exit); |
| 1335 | |
| 1336 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); |
| 1337 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); |
| 1338 | MODULE_LICENSE("GPL v2"); |