blob: c52766a5b85f5ce8ac10bc104ac77354e1eb2885 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
Ralf Baechle36ccf1c2006-02-14 21:04:54 +00006 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +010011 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
Steven J. Hill2a0b24f2013-03-25 12:15:55 -050012 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
Markos Chandrasb08a9c92013-12-04 16:20:08 +000013 * Copyright (C) 2014, Imagination Technologies Ltd.
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 */
Maciej W. Rozyckied2d72c2015-04-03 23:27:06 +010015#include <linux/bitops.h>
Ralf Baechle8e8a52e2007-05-31 14:00:19 +010016#include <linux/bug.h>
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +010017#include <linux/compiler.h>
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +020018#include <linux/context_tracking.h>
James Hoganae4ce452014-03-04 10:20:43 +000019#include <linux/cpu_pm.h>
Ralf Baechle7aa1c8f2012-10-11 18:14:58 +020020#include <linux/kexec.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/init.h>
Nathan Lynch8742cd22011-09-30 13:49:35 -050022#include <linux/kernel.h>
Paul Gortmakerf9ded562012-02-28 19:24:46 -050023#include <linux/module.h>
Paul Gortmaker9f3b8082016-08-15 19:11:52 -040024#include <linux/extable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/mm.h>
Ingo Molnar68e21be2017-02-01 19:08:20 +010026#include <linux/sched/mm.h>
Ingo Molnarb17b0152017-02-08 18:51:35 +010027#include <linux/sched/debug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <linux/spinlock.h>
30#include <linux/kallsyms.h>
Mike Rapoportbcec54b2018-09-10 12:23:18 +030031#include <linux/memblock.h>
Maxime Bizond4fd1982006-07-20 18:52:02 +020032#include <linux/interrupt.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010033#include <linux/ptrace.h>
Jason Wessel88547002008-07-29 15:58:53 -050034#include <linux/kgdb.h>
35#include <linux/kdebug.h>
David Daneyc1bf2072010-08-03 11:22:20 -070036#include <linux/kprobes.h>
Ralf Baechle69f3a7d2009-11-24 01:24:58 +000037#include <linux/notifier.h>
Jason Wessel5dd11d52010-05-20 21:04:26 -050038#include <linux/kdb.h>
David Howellsca4d3e672010-10-07 14:08:54 +010039#include <linux/irq.h>
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +080040#include <linux/perf_event.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
Paul Burtona13c9962015-09-22 10:15:22 -070042#include <asm/addrspace.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#include <asm/bootinfo.h>
44#include <asm/branch.h>
45#include <asm/break.h>
Ralf Baechle69f3a7d2009-11-24 01:24:58 +000046#include <asm/cop2.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <asm/cpu.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020048#include <asm/cpu-type.h>
Ralf Baechlee50c0a82005-05-31 11:49:19 +000049#include <asm/dsp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#include <asm/fpu.h>
Ralf Baechleba3049e2008-10-28 17:38:42 +000051#include <asm/fpu_emulator.h>
Ralf Baechlebdc92d742013-05-21 16:59:19 +020052#include <asm/idle.h>
Paul Burtonb6d18e72018-11-09 20:08:36 +000053#include <asm/isa-rev.h>
Paul Burtone83f7e02017-08-12 19:49:41 -070054#include <asm/mips-cps.h>
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +000055#include <asm/mips-r2-to-r6-emul.h>
Ralf Baechle340ee4b2005-08-17 17:44:08 +000056#include <asm/mipsregs.h>
57#include <asm/mipsmtregs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070058#include <asm/module.h>
Paul Burton1db1af82014-01-27 15:23:11 +000059#include <asm/msa.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070060#include <asm/pgtable.h>
61#include <asm/ptrace.h>
62#include <asm/sections.h>
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +000063#include <asm/siginfo.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070064#include <asm/tlbdebug.h>
65#include <asm/traps.h>
Linus Torvalds7c0f6ba2016-12-24 11:46:01 -080066#include <linux/uaccess.h>
David Daneyb67b2b72008-09-23 00:08:45 -070067#include <asm/watch.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070068#include <asm/mmu_context.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070069#include <asm/types.h>
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +090070#include <asm/stacktrace.h>
Paul Burton4bcb4ad2018-08-10 16:03:31 -070071#include <asm/tlbex.h>
Florian Fainelli92bbe1b2010-01-28 15:22:37 +010072#include <asm/uasm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090074extern void check_wait(void);
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090075extern asmlinkage void rollback_handle_int(void);
Ralf Baechlee4ac58a2006-04-03 17:56:36 +010076extern asmlinkage void handle_int(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070077extern asmlinkage void handle_adel(void);
78extern asmlinkage void handle_ades(void);
79extern asmlinkage void handle_ibe(void);
80extern asmlinkage void handle_dbe(void);
81extern asmlinkage void handle_sys(void);
82extern asmlinkage void handle_bp(void);
83extern asmlinkage void handle_ri(void);
Huacai Chen5a341332017-03-16 21:00:26 +080084extern asmlinkage void handle_ri_rdhwr_tlbp(void);
Atsushi Nemoto5b104962006-09-11 17:50:29 +090085extern asmlinkage void handle_ri_rdhwr(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070086extern asmlinkage void handle_cpu(void);
87extern asmlinkage void handle_ov(void);
88extern asmlinkage void handle_tr(void);
Paul Burton2bcb3fb2014-01-27 15:23:12 +000089extern asmlinkage void handle_msa_fpe(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070090extern asmlinkage void handle_fpe(void);
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +000091extern asmlinkage void handle_ftlb(void);
Paul Burton1db1af82014-01-27 15:23:11 +000092extern asmlinkage void handle_msa(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070093extern asmlinkage void handle_mdmx(void);
94extern asmlinkage void handle_watch(void);
Ralf Baechle340ee4b2005-08-17 17:44:08 +000095extern asmlinkage void handle_mt(void);
Ralf Baechlee50c0a82005-05-31 11:49:19 +000096extern asmlinkage void handle_dsp(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070097extern asmlinkage void handle_mcheck(void);
98extern asmlinkage void handle_reserved(void);
Leonid Yegoshin5890f702014-07-15 14:09:56 +010099extern void tlb_do_page_fault_0(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101void (*board_be_init)(void);
102int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
Ralf Baechlee01402b2005-07-14 15:57:16 +0000103void (*board_nmi_handler_setup)(void);
104void (*board_ejtag_handler_setup)(void);
105void (*board_bind_eic_interrupt)(int irq, int regset);
Kevin Cernekee6fb97ef2011-11-16 01:25:45 +0000106void (*board_ebase_setup)(void);
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000107void(*board_cache_error_setup)(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200109static void show_raw_backtrace(unsigned long reg29)
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900110{
Ralf Baechle39b8d522008-04-28 17:14:26 +0100111 unsigned long *sp = (unsigned long *)(reg29 & ~3);
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900112 unsigned long addr;
113
114 printk("Call Trace:");
115#ifdef CONFIG_KALLSYMS
116 printk("\n");
117#endif
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200118 while (!kstack_end(sp)) {
119 unsigned long __user *p =
120 (unsigned long __user *)(unsigned long)sp++;
121 if (__get_user(addr, p)) {
122 printk(" (Bad stack address)");
123 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100124 }
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200125 if (__kernel_text_address(addr))
126 print_ip_sym(addr);
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900127 }
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200128 printk("\n");
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900129}
130
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900131#ifdef CONFIG_KALLSYMS
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +0900132int raw_show_trace;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900133static int __init set_raw_show_trace(char *str)
134{
135 raw_show_trace = 1;
136 return 1;
137}
138__setup("raw_show_trace", set_raw_show_trace);
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +0900139#endif
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200140
Ralf Baechleeae23f22007-10-14 23:27:21 +0100141static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900142{
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200143 unsigned long sp = regs->regs[29];
144 unsigned long ra = regs->regs[31];
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900145 unsigned long pc = regs->cp0_epc;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900146
Vincent Wene909be82012-07-19 09:11:16 +0200147 if (!task)
148 task = current;
149
James Hogan81a76d72015-12-04 22:25:02 +0000150 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200151 show_raw_backtrace(sp);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900152 return;
153 }
154 printk("Call Trace:\n");
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200155 do {
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200156 print_ip_sym(pc);
Atsushi Nemoto19246002006-09-29 18:02:51 +0900157 pc = unwind_stack(task, &sp, pc, &ra);
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200158 } while (pc);
Matt Redfearnbcf084d2016-10-19 14:33:20 +0100159 pr_cont("\n");
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900160}
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900161
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162/*
163 * This routine abuses get_user()/put_user() to reference pointers
164 * with at least a bit of error checking ...
165 */
Ralf Baechleeae23f22007-10-14 23:27:21 +0100166static void show_stacktrace(struct task_struct *task,
167 const struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168{
169 const int field = 2 * sizeof(unsigned long);
170 long stackdata;
171 int i;
Atsushi Nemoto5e0373b2007-07-13 23:02:42 +0900172 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173
174 printk("Stack :");
175 i = 0;
176 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100177 if (i && ((i % (64 / field)) == 0)) {
178 pr_cont("\n");
179 printk(" ");
180 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 if (i > 39) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100182 pr_cont(" ...");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 break;
184 }
185
186 if (__get_user(stackdata, sp++)) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100187 pr_cont(" (Bad stack address)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 break;
189 }
190
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100191 pr_cont(" %0*lx", field, stackdata);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 i++;
193 }
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100194 pr_cont("\n");
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200195 show_backtrace(task, regs);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900196}
197
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900198void show_stack(struct task_struct *task, unsigned long *sp)
199{
200 struct pt_regs regs;
James Hogan1e778632015-07-27 13:50:22 +0100201 mm_segment_t old_fs = get_fs();
James Hogan85423632017-06-29 15:05:04 +0100202
203 regs.cp0_status = KSU_KERNEL;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900204 if (sp) {
205 regs.regs[29] = (unsigned long)sp;
206 regs.regs[31] = 0;
207 regs.cp0_epc = 0;
208 } else {
209 if (task && task != current) {
210 regs.regs[29] = task->thread.reg29;
211 regs.regs[31] = 0;
212 regs.cp0_epc = task->thread.reg31;
Jason Wessel5dd11d52010-05-20 21:04:26 -0500213#ifdef CONFIG_KGDB_KDB
214 } else if (atomic_read(&kgdb_active) != -1 &&
215 kdb_current_regs) {
216 memcpy(&regs, kdb_current_regs, sizeof(regs));
217#endif /* CONFIG_KGDB_KDB */
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900218 } else {
219 prepare_frametrace(&regs);
220 }
221 }
James Hogan1e778632015-07-27 13:50:22 +0100222 /*
223 * show_stack() deals exclusively with kernel mode, so be sure to access
224 * the stack in the kernel (not user) address space.
225 */
226 set_fs(KERNEL_DS);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900227 show_stacktrace(task, &regs);
James Hogan1e778632015-07-27 13:50:22 +0100228 set_fs(old_fs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229}
230
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +0900231static void show_code(unsigned int __user *pc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232{
233 long i;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100234 unsigned short __user *pc16 = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235
Matt Redfearn41000c52016-10-19 14:33:22 +0100236 printk("Code:");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237
Ralf Baechle39b8d522008-04-28 17:14:26 +0100238 if ((unsigned long)pc & 1)
239 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 for(i = -3 ; i < 6 ; i++) {
241 unsigned int insn;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100242 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
Matt Redfearn41000c52016-10-19 14:33:22 +0100243 pr_cont(" (Bad address in epc)\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 break;
245 }
Matt Redfearn41000c52016-10-19 14:33:22 +0100246 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 }
Matt Redfearn41000c52016-10-19 14:33:22 +0100248 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249}
250
Ralf Baechleeae23f22007-10-14 23:27:21 +0100251static void __show_regs(const struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252{
253 const int field = 2 * sizeof(unsigned long);
254 unsigned int cause = regs->cp0_cause;
Petri Gynther37dd3812015-05-08 15:10:10 -0700255 unsigned int exccode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 int i;
257
Tejun Heoa43cb952013-04-30 15:27:17 -0700258 show_regs_print_info(KERN_DEFAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259
260 /*
261 * Saved main processor registers
262 */
263 for (i = 0; i < 32; ) {
264 if ((i % 4) == 0)
265 printk("$%2d :", i);
266 if (i == 0)
Paul Burton752f5492016-10-19 14:33:23 +0100267 pr_cont(" %0*lx", field, 0UL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 else if (i == 26 || i == 27)
Paul Burton752f5492016-10-19 14:33:23 +0100269 pr_cont(" %*s", field, "");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 else
Paul Burton752f5492016-10-19 14:33:23 +0100271 pr_cont(" %0*lx", field, regs->regs[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272
273 i++;
274 if ((i % 4) == 0)
Paul Burton752f5492016-10-19 14:33:23 +0100275 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 }
277
Franck Bui-Huu9693a852007-02-02 17:41:47 +0100278#ifdef CONFIG_CPU_HAS_SMARTMIPS
279 printk("Acx : %0*lx\n", field, regs->acx);
280#endif
Paul Burtonb6d18e72018-11-09 20:08:36 +0000281 if (MIPS_ISA_REV < 6) {
282 printk("Hi : %0*lx\n", field, regs->hi);
283 printk("Lo : %0*lx\n", field, regs->lo);
284 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285
286 /*
287 * Saved cp0 registers
288 */
Ralf Baechleb012cff2008-07-15 18:44:33 +0100289 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
290 (void *) regs->cp0_epc);
Ralf Baechleb012cff2008-07-15 18:44:33 +0100291 printk("ra : %0*lx %pS\n", field, regs->regs[31],
292 (void *) regs->regs[31]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293
Ralf Baechle70342282013-01-22 12:59:30 +0100294 printk("Status: %08x ", (uint32_t) regs->cp0_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295
Ralf Baechle1990e542013-06-26 17:06:34 +0200296 if (cpu_has_3kex) {
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000297 if (regs->cp0_status & ST0_KUO)
Paul Burton752f5492016-10-19 14:33:23 +0100298 pr_cont("KUo ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000299 if (regs->cp0_status & ST0_IEO)
Paul Burton752f5492016-10-19 14:33:23 +0100300 pr_cont("IEo ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000301 if (regs->cp0_status & ST0_KUP)
Paul Burton752f5492016-10-19 14:33:23 +0100302 pr_cont("KUp ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000303 if (regs->cp0_status & ST0_IEP)
Paul Burton752f5492016-10-19 14:33:23 +0100304 pr_cont("IEp ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000305 if (regs->cp0_status & ST0_KUC)
Paul Burton752f5492016-10-19 14:33:23 +0100306 pr_cont("KUc ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000307 if (regs->cp0_status & ST0_IEC)
Paul Burton752f5492016-10-19 14:33:23 +0100308 pr_cont("IEc ");
Ralf Baechle1990e542013-06-26 17:06:34 +0200309 } else if (cpu_has_4kex) {
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000310 if (regs->cp0_status & ST0_KX)
Paul Burton752f5492016-10-19 14:33:23 +0100311 pr_cont("KX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000312 if (regs->cp0_status & ST0_SX)
Paul Burton752f5492016-10-19 14:33:23 +0100313 pr_cont("SX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000314 if (regs->cp0_status & ST0_UX)
Paul Burton752f5492016-10-19 14:33:23 +0100315 pr_cont("UX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000316 switch (regs->cp0_status & ST0_KSU) {
317 case KSU_USER:
Paul Burton752f5492016-10-19 14:33:23 +0100318 pr_cont("USER ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000319 break;
320 case KSU_SUPERVISOR:
Paul Burton752f5492016-10-19 14:33:23 +0100321 pr_cont("SUPERVISOR ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000322 break;
323 case KSU_KERNEL:
Paul Burton752f5492016-10-19 14:33:23 +0100324 pr_cont("KERNEL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000325 break;
326 default:
Paul Burton752f5492016-10-19 14:33:23 +0100327 pr_cont("BAD_MODE ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000328 break;
329 }
330 if (regs->cp0_status & ST0_ERL)
Paul Burton752f5492016-10-19 14:33:23 +0100331 pr_cont("ERL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000332 if (regs->cp0_status & ST0_EXL)
Paul Burton752f5492016-10-19 14:33:23 +0100333 pr_cont("EXL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000334 if (regs->cp0_status & ST0_IE)
Paul Burton752f5492016-10-19 14:33:23 +0100335 pr_cont("IE ");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 }
Paul Burton752f5492016-10-19 14:33:23 +0100337 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
Petri Gynther37dd3812015-05-08 15:10:10 -0700339 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
340 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341
Petri Gynther37dd3812015-05-08 15:10:10 -0700342 if (1 <= exccode && exccode <= 5)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
344
Ralf Baechle9966db252007-10-11 23:46:17 +0100345 printk("PrId : %08x (%s)\n", read_c0_prid(),
346 cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347}
348
Ralf Baechleeae23f22007-10-14 23:27:21 +0100349/*
350 * FIXME: really the generic show_regs should take a const pointer argument.
351 */
352void show_regs(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353{
Paul Burton49881542018-08-31 11:49:20 -0700354 __show_regs(regs);
Paul Burton5a267832018-06-22 10:55:45 -0700355 dump_stack();
Ralf Baechleeae23f22007-10-14 23:27:21 +0100356}
357
David Daneyc1bf2072010-08-03 11:22:20 -0700358void show_registers(struct pt_regs *regs)
Ralf Baechleeae23f22007-10-14 23:27:21 +0100359{
Ralf Baechle39b8d522008-04-28 17:14:26 +0100360 const int field = 2 * sizeof(unsigned long);
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100361 mm_segment_t old_fs = get_fs();
Ralf Baechle39b8d522008-04-28 17:14:26 +0100362
Ralf Baechleeae23f22007-10-14 23:27:21 +0100363 __show_regs(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 print_modules();
Ralf Baechle39b8d522008-04-28 17:14:26 +0100365 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
366 current->comm, current->pid, current_thread_info(), current,
367 field, current_thread_info()->tp_value);
368 if (cpu_has_userlocal) {
369 unsigned long tls;
370
371 tls = read_c0_userlocal();
372 if (tls != current_thread_info()->tp_value)
373 printk("*HwTLS: %0*lx\n", field, tls);
374 }
375
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100376 if (!user_mode(regs))
377 /* Necessary for getting the correct stack content */
378 set_fs(KERNEL_DS);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900379 show_stacktrace(current, regs);
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +0900380 show_code((unsigned int __user *) regs->cp0_epc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 printk("\n");
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100382 set_fs(old_fs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383}
384
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000385static DEFINE_RAW_SPINLOCK(die_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386
David Daney70dc6f02010-08-03 15:44:43 -0700387void __noreturn die(const char *str, struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388{
389 static int die_counter;
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400390 int sig = SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391
Nathan Lynch8742cd22011-09-30 13:49:35 -0500392 oops_enter();
393
Ralf Baechlee3b28832015-07-28 20:37:43 +0200394 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200395 SIGSEGV) == NOTIFY_STOP)
Ralf Baechle10423c92011-05-13 10:33:28 +0100396 sig = 0;
Jason Wessel5dd11d52010-05-20 21:04:26 -0500397
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 console_verbose();
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000399 raw_spin_lock_irq(&die_lock);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100400 bust_spinlocks(1);
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400401
Ralf Baechle178086c2005-10-13 17:07:54 +0100402 printk("%s[#%d]:\n", str, ++die_counter);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 show_registers(regs);
Rusty Russell373d4d02013-01-21 17:17:39 +1030404 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000405 raw_spin_unlock_irq(&die_lock);
Maxime Bizond4fd1982006-07-20 18:52:02 +0200406
Nathan Lynch8742cd22011-09-30 13:49:35 -0500407 oops_exit();
408
Maxime Bizond4fd1982006-07-20 18:52:02 +0200409 if (in_interrupt())
410 panic("Fatal exception in interrupt");
411
Aaro Koskinen99a7a232016-03-09 22:08:42 +0200412 if (panic_on_oops)
Maxime Bizond4fd1982006-07-20 18:52:02 +0200413 panic("Fatal exception");
Maxime Bizond4fd1982006-07-20 18:52:02 +0200414
Ralf Baechle7aa1c8f2012-10-11 18:14:58 +0200415 if (regs && kexec_should_crash(current))
416 crash_kexec(regs);
417
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400418 do_exit(sig);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419}
420
Thomas Bogendoerfer05106172008-08-04 19:44:34 +0200421extern struct exception_table_entry __start___dbe_table[];
422extern struct exception_table_entry __stop___dbe_table[];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423
Ralf Baechleb6dcec92007-02-18 15:57:09 +0000424__asm__(
425" .section __dbe_table, \"a\"\n"
426" .previous \n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427
428/* Given an address, look for it in the exception tables. */
429static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
430{
431 const struct exception_table_entry *e;
432
Thomas Meyera94c33d2017-07-10 15:51:58 -0700433 e = search_extable(__start___dbe_table,
434 __stop___dbe_table - __start___dbe_table, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435 if (!e)
436 e = search_module_dbetables(addr);
437 return e;
438}
439
440asmlinkage void do_be(struct pt_regs *regs)
441{
442 const int field = 2 * sizeof(unsigned long);
443 const struct exception_table_entry *fixup = NULL;
444 int data = regs->cp0_cause & 4;
445 int action = MIPS_BE_FATAL;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200446 enum ctx_state prev_state;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200448 prev_state = exception_enter();
Ralf Baechle70342282013-01-22 12:59:30 +0100449 /* XXX For now. Fixme, this searches the wrong table ... */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 if (data && !user_mode(regs))
451 fixup = search_dbe_tables(exception_epc(regs));
452
453 if (fixup)
454 action = MIPS_BE_FIXUP;
455
456 if (board_be_handler)
Atsushi Nemoto28fc5822007-07-13 01:49:49 +0900457 action = board_be_handler(regs, fixup != NULL);
Paul Burtondabdc182016-10-05 18:18:17 +0100458 else
459 mips_cm_error_report();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460
461 switch (action) {
462 case MIPS_BE_DISCARD:
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200463 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 case MIPS_BE_FIXUP:
465 if (fixup) {
466 regs->cp0_epc = fixup->nextinsn;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200467 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 }
469 break;
470 default:
471 break;
472 }
473
474 /*
475 * Assume it would be too dangerous to continue ...
476 */
477 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
478 data ? "Data" : "Instruction",
479 field, regs->cp0_epc, field, regs->regs[31]);
Ralf Baechlee3b28832015-07-28 20:37:43 +0200480 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200481 SIGBUS) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200482 goto out;
Jason Wessel88547002008-07-29 15:58:53 -0500483
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 die_if_kernel("Oops", regs);
485 force_sig(SIGBUS, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200486
487out:
488 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489}
490
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491/*
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100492 * ll/sc, rdhwr, sync emulation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 */
494
495#define OPCODE 0xfc000000
496#define BASE 0x03e00000
497#define RT 0x001f0000
498#define OFFSET 0x0000ffff
499#define LL 0xc0000000
500#define SC 0xe0000000
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100501#define SPEC0 0x00000000
Ralf Baechle3c370262005-04-13 17:43:59 +0000502#define SPEC3 0x7c000000
503#define RD 0x0000f800
504#define FUNC 0x0000003f
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100505#define SYNC 0x0000000f
Ralf Baechle3c370262005-04-13 17:43:59 +0000506#define RDHWR 0x0000003b
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500508/* microMIPS definitions */
509#define MM_POOL32A_FUNC 0xfc00ffff
510#define MM_RDHWR 0x00006b3c
511#define MM_RS 0x001f0000
512#define MM_RT 0x03e00000
513
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514/*
515 * The ll_bit is cleared by r*_switch.S
516 */
517
Ralf Baechlef1e39a42009-09-17 02:25:05 +0200518unsigned int ll_bit;
519struct task_struct *ll_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100521static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522{
Ralf Baechlefe00f942005-03-01 19:22:29 +0000523 unsigned long value, __user *vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 long offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525
526 /*
527 * analyse the ll instruction that just caused a ri exception
528 * and put the referenced address to addr.
529 */
530
531 /* sign extend offset */
532 offset = opcode & OFFSET;
533 offset <<= 16;
534 offset >>= 16;
535
Ralf Baechlefe00f942005-03-01 19:22:29 +0000536 vaddr = (unsigned long __user *)
Steven J. Hillb9688312013-01-12 23:29:27 +0000537 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100539 if ((unsigned long)vaddr & 3)
540 return SIGBUS;
541 if (get_user(value, vaddr))
542 return SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543
544 preempt_disable();
545
546 if (ll_task == NULL || ll_task == current) {
547 ll_bit = 1;
548 } else {
549 ll_bit = 0;
550 }
551 ll_task = current;
552
553 preempt_enable();
554
555 regs->regs[(opcode & RT) >> 16] = value;
556
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100557 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558}
559
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100560static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561{
Ralf Baechlefe00f942005-03-01 19:22:29 +0000562 unsigned long __user *vaddr;
563 unsigned long reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564 long offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565
566 /*
567 * analyse the sc instruction that just caused a ri exception
568 * and put the referenced address to addr.
569 */
570
571 /* sign extend offset */
572 offset = opcode & OFFSET;
573 offset <<= 16;
574 offset >>= 16;
575
Ralf Baechlefe00f942005-03-01 19:22:29 +0000576 vaddr = (unsigned long __user *)
Steven J. Hillb9688312013-01-12 23:29:27 +0000577 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578 reg = (opcode & RT) >> 16;
579
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100580 if ((unsigned long)vaddr & 3)
581 return SIGBUS;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582
583 preempt_disable();
584
585 if (ll_bit == 0 || ll_task != current) {
586 regs->regs[reg] = 0;
587 preempt_enable();
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100588 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589 }
590
591 preempt_enable();
592
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100593 if (put_user(regs->regs[reg], vaddr))
594 return SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595
596 regs->regs[reg] = 1;
597
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100598 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599}
600
601/*
602 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
603 * opcodes are supposed to result in coprocessor unusable exceptions if
604 * executed on ll/sc-less processors. That's the theory. In practice a
605 * few processors such as NEC's VR4100 throw reserved instruction exceptions
606 * instead, so we're doing the emulation thing in both exception handlers.
607 */
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100608static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609{
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800610 if ((opcode & OPCODE) == LL) {
611 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200612 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100613 return simulate_ll(regs, opcode);
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800614 }
615 if ((opcode & OPCODE) == SC) {
616 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200617 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100618 return simulate_sc(regs, opcode);
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800619 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100621 return -1; /* Must be something else ... */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622}
623
Ralf Baechle3c370262005-04-13 17:43:59 +0000624/*
625 * Simulate trapping 'rdhwr' instructions to provide user accessible
Chris Dearman1f5826b2006-05-08 18:02:16 +0100626 * registers not implemented in hardware.
Ralf Baechle3c370262005-04-13 17:43:59 +0000627 */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500628static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
Ralf Baechle3c370262005-04-13 17:43:59 +0000629{
Al Virodc8f6022006-01-12 01:06:07 -0800630 struct thread_info *ti = task_thread_info(current);
Ralf Baechle3c370262005-04-13 17:43:59 +0000631
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500632 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
633 1, regs, 0);
634 switch (rd) {
James Hoganaff565a2016-06-15 19:29:52 +0100635 case MIPS_HWR_CPUNUM: /* CPU number */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500636 regs->regs[rt] = smp_processor_id();
637 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100638 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500639 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
640 current_cpu_data.icache.linesz);
641 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100642 case MIPS_HWR_CC: /* Read count register */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500643 regs->regs[rt] = read_c0_count();
644 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100645 case MIPS_HWR_CCRES: /* Count register resolution */
Ralf Baechle69f24d12013-09-17 10:25:47 +0200646 switch (current_cpu_type()) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500647 case CPU_20KC:
648 case CPU_25KF:
649 regs->regs[rt] = 1;
650 break;
651 default:
652 regs->regs[rt] = 2;
653 }
654 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100655 case MIPS_HWR_ULR: /* Read UserLocal register */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500656 regs->regs[rt] = ti->tp_value;
657 return 0;
658 default:
659 return -1;
660 }
661}
662
663static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
664{
Ralf Baechle3c370262005-04-13 17:43:59 +0000665 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
666 int rd = (opcode & RD) >> 11;
667 int rt = (opcode & RT) >> 16;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500668
669 simulate_rdhwr(regs, rd, rt);
670 return 0;
671 }
672
673 /* Not ours. */
674 return -1;
675}
676
Maciej W. Rozycki7aa70472016-01-30 09:08:28 +0000677static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500678{
679 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
680 int rd = (opcode & MM_RS) >> 16;
681 int rt = (opcode & MM_RT) >> 21;
682 simulate_rdhwr(regs, rd, rt);
683 return 0;
Ralf Baechle3c370262005-04-13 17:43:59 +0000684 }
685
Daniel Jacobowitz56ebd512005-11-26 22:34:41 -0500686 /* Not ours. */
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100687 return -1;
688}
Ralf Baechlee5679882006-11-30 01:14:47 +0000689
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100690static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
691{
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800692 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
693 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200694 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100695 return 0;
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800696 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100697
698 return -1; /* Must be something else ... */
Ralf Baechle3c370262005-04-13 17:43:59 +0000699}
700
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701asmlinkage void do_ov(struct pt_regs *regs)
702{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200703 enum ctx_state prev_state;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200705 prev_state = exception_enter();
Ralf Baechle36ccf1c2006-02-14 21:04:54 +0000706 die_if_kernel("Integer overflow", regs);
707
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500708 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200709 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710}
711
Paul Burton5328f742018-11-07 23:14:05 +0000712#ifdef CONFIG_MIPS_FP_SUPPORT
713
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100714/*
715 * Send SIGFPE according to FCSR Cause bits, which must have already
716 * been masked against Enable bits. This is impotant as Inexact can
717 * happen together with Overflow or Underflow, and `ptrace' can set
718 * any bits.
719 */
720void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
721 struct task_struct *tsk)
722{
Guenter Roeck0bb0a112018-05-15 06:50:47 -0700723 int si_code = FPE_FLTUNK;
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100724
725 if (fcr31 & FPU_CSR_INV_X)
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500726 si_code = FPE_FLTINV;
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100727 else if (fcr31 & FPU_CSR_DIV_X)
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500728 si_code = FPE_FLTDIV;
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100729 else if (fcr31 & FPU_CSR_OVF_X)
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500730 si_code = FPE_FLTOVF;
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100731 else if (fcr31 & FPU_CSR_UDF_X)
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500732 si_code = FPE_FLTUND;
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100733 else if (fcr31 & FPU_CSR_INE_X)
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500734 si_code = FPE_FLTRES;
Ralf Baechleb1237182017-08-07 21:14:18 +0200735
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500736 force_sig_fault(SIGFPE, si_code, fault_addr, tsk);
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100737}
738
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100739int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
David Daney515b0292010-10-21 16:32:26 -0700740{
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500741 int si_code;
Petar Jovanovicbcfc8f02016-07-13 15:23:37 +0200742 struct vm_area_struct *vma;
Paul Burtonad70c132015-01-30 12:09:35 +0000743
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100744 switch (sig) {
745 case 0:
746 return 0;
747
748 case SIGFPE:
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100749 force_fcr31_sig(fcr31, fault_addr, current);
David Daney515b0292010-10-21 16:32:26 -0700750 return 1;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100751
752 case SIGBUS:
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500753 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr, current);
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100754 return 1;
755
756 case SIGSEGV:
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100757 down_read(&current->mm->mmap_sem);
Petar Jovanovicbcfc8f02016-07-13 15:23:37 +0200758 vma = find_vma(current->mm, (unsigned long)fault_addr);
759 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500760 si_code = SEGV_ACCERR;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100761 else
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500762 si_code = SEGV_MAPERR;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100763 up_read(&current->mm->mmap_sem);
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500764 force_sig_fault(SIGSEGV, si_code, fault_addr, current);
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100765 return 1;
766
767 default:
David Daney515b0292010-10-21 16:32:26 -0700768 force_sig(sig, current);
769 return 1;
David Daney515b0292010-10-21 16:32:26 -0700770 }
771}
772
Paul Burton4227a2d2014-09-11 08:30:20 +0100773static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
774 unsigned long old_epc, unsigned long old_ra)
775{
776 union mips_instruction inst = { .word = opcode };
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100777 void __user *fault_addr;
778 unsigned long fcr31;
Paul Burton4227a2d2014-09-11 08:30:20 +0100779 int sig;
780
781 /* If it's obviously not an FP instruction, skip it */
782 switch (inst.i_format.opcode) {
783 case cop1_op:
784 case cop1x_op:
785 case lwc1_op:
786 case ldc1_op:
787 case swc1_op:
788 case sdc1_op:
789 break;
790
791 default:
792 return -1;
793 }
794
795 /*
796 * do_ri skipped over the instruction via compute_return_epc, undo
797 * that for the FPU emulator.
798 */
799 regs->cp0_epc = old_epc;
800 regs->regs[31] = old_ra;
801
Paul Burton4227a2d2014-09-11 08:30:20 +0100802 /* Run the emulator */
803 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
804 &fault_addr);
805
Maciej W. Rozycki443c4402015-04-03 23:27:10 +0100806 /*
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100807 * We can't allow the emulated instruction to leave any
808 * enabled Cause bits set in $fcr31.
Maciej W. Rozycki443c4402015-04-03 23:27:10 +0100809 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100810 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
811 current->thread.fpu.fcr31 &= ~fcr31;
Paul Burton4227a2d2014-09-11 08:30:20 +0100812
813 /* Restore the hardware register state */
814 own_fpu(1);
815
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100816 /* Send a signal if required. */
817 process_fpemu_return(sig, fault_addr, fcr31);
818
Paul Burton4227a2d2014-09-11 08:30:20 +0100819 return 0;
820}
821
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822/*
823 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
824 */
825asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
826{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200827 enum ctx_state prev_state;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100828 void __user *fault_addr;
829 int sig;
Thiemo Seufer948a34c2007-08-22 01:42:04 +0100830
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200831 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +0200832 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200833 SIGFPE) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200834 goto out;
James Hogan64bedff2014-12-02 13:44:13 +0000835
836 /* Clear FCSR.Cause before enabling interrupts */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100837 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
James Hogan64bedff2014-12-02 13:44:13 +0000838 local_irq_enable();
839
Chris Dearman57725f92006-06-30 23:35:28 +0100840 die_if_kernel("FP exception in kernel code", regs);
841
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 if (fcr31 & FPU_CSR_UNI_X) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 /*
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000844 * Unimplemented operation exception. If we've got the full
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 * software emulator on-board, let's use it...
846 *
847 * Force FPU to dump state into task/thread context. We're
848 * moving a lot of data here for what is probably a single
849 * instruction, but the alternative is to pre-decode the FP
850 * register operands before invoking the emulator, which seems
851 * a bit extreme for what should be an infrequent event.
852 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853
854 /* Run the emulator */
David Daney515b0292010-10-21 16:32:26 -0700855 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
856 &fault_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857
858 /*
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100859 * We can't allow the emulated instruction to leave any
860 * enabled Cause bits set in $fcr31.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100862 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
863 current->thread.fpu.fcr31 &= ~fcr31;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864
865 /* Restore the hardware register state */
Ralf Baechle70342282013-01-22 12:59:30 +0100866 own_fpu(1); /* Using the FPU again. */
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100867 } else {
868 sig = SIGFPE;
869 fault_addr = (void __user *) regs->cp0_epc;
Maciej W. Rozyckied2d72c2015-04-03 23:27:06 +0100870 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100872 /* Send a signal if required. */
873 process_fpemu_return(sig, fault_addr, fcr31);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200874
875out:
876 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877}
878
Paul Burton5328f742018-11-07 23:14:05 +0000879/*
880 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
881 * emulated more than some threshold number of instructions, force migration to
882 * a "CPU" that has FP support.
883 */
884static void mt_ase_fp_affinity(void)
885{
886#ifdef CONFIG_MIPS_MT_FPAFF
887 if (mt_fpemul_threshold > 0 &&
888 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
889 /*
890 * If there's no FPU present, or if the application has already
891 * restricted the allowed set to exclude any CPUs with FPUs,
892 * we'll skip the procedure.
893 */
894 if (cpumask_intersects(&current->cpus_allowed, &mt_fpu_cpumask)) {
895 cpumask_t tmask;
896
897 current->thread.user_cpus_allowed
898 = current->cpus_allowed;
899 cpumask_and(&tmask, &current->cpus_allowed,
900 &mt_fpu_cpumask);
901 set_cpus_allowed_ptr(current, &tmask);
902 set_thread_flag(TIF_FPUBOUND);
903 }
904 }
905#endif /* CONFIG_MIPS_MT_FPAFF */
906}
907
908#else /* !CONFIG_MIPS_FP_SUPPORT */
909
910static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
911 unsigned long old_epc, unsigned long old_ra)
912{
913 return -1;
914}
915
916#endif /* !CONFIG_MIPS_FP_SUPPORT */
917
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +0000918void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
Ralf Baechledf270052008-04-20 16:28:54 +0100919 const char *str)
920{
Ralf Baechledf270052008-04-20 16:28:54 +0100921 char b[40];
922
Jason Wessel5dd11d52010-05-20 21:04:26 -0500923#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
Ralf Baechlee3b28832015-07-28 20:37:43 +0200924 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
925 SIGTRAP) == NOTIFY_STOP)
Jason Wessel5dd11d52010-05-20 21:04:26 -0500926 return;
927#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
928
Ralf Baechlee3b28832015-07-28 20:37:43 +0200929 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200930 SIGTRAP) == NOTIFY_STOP)
Jason Wessel88547002008-07-29 15:58:53 -0500931 return;
932
Ralf Baechledf270052008-04-20 16:28:54 +0100933 /*
934 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
935 * insns, even for trap and break codes that indicate arithmetic
936 * failures. Weird ...
937 * But should we continue the brokenness??? --macro
938 */
939 switch (code) {
940 case BRK_OVERFLOW:
941 case BRK_DIVZERO:
942 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
943 die_if_kernel(b, regs);
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500944 force_sig_fault(SIGFPE,
945 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
946 (void __user *) regs->cp0_epc, current);
Ralf Baechledf270052008-04-20 16:28:54 +0100947 break;
948 case BRK_BUG:
949 die_if_kernel("Kernel bug detected", regs);
950 force_sig(SIGTRAP, current);
951 break;
Ralf Baechleba3049e2008-10-28 17:38:42 +0000952 case BRK_MEMU:
953 /*
Maciej W. Rozycki1f443772015-04-03 23:24:14 +0100954 * This breakpoint code is used by the FPU emulator to retake
955 * control of the CPU after executing the instruction from the
956 * delay slot of an emulated branch.
Ralf Baechleba3049e2008-10-28 17:38:42 +0000957 *
958 * Terminate if exception was recognized as a delay slot return
959 * otherwise handle as normal.
960 */
961 if (do_dsemulret(regs))
962 return;
963
964 die_if_kernel("Math emu break/trap", regs);
965 force_sig(SIGTRAP, current);
966 break;
Ralf Baechledf270052008-04-20 16:28:54 +0100967 default:
968 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
969 die_if_kernel(b, regs);
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +0000970 if (si_code) {
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -0500971 force_sig_fault(SIGTRAP, si_code, NULL, current);
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +0000972 } else {
973 force_sig(SIGTRAP, current);
974 }
Ralf Baechledf270052008-04-20 16:28:54 +0100975 }
976}
977
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978asmlinkage void do_bp(struct pt_regs *regs)
979{
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100980 unsigned long epc = msk_isa16_mode(exception_epc(regs));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 unsigned int opcode, bcode;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200982 enum ctx_state prev_state;
Leonid Yegoshin078dde52013-12-04 16:39:34 +0000983 mm_segment_t seg;
984
985 seg = get_fs();
986 if (!user_mode(regs))
987 set_fs(KERNEL_DS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200989 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +0200990 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500991 if (get_isa16_mode(regs->cp0_epc)) {
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100992 u16 instr[2];
993
994 if (__get_user(instr[0], (u16 __user *)epc))
995 goto out_sigsegv;
996
997 if (!cpu_has_mmips) {
998 /* MIPS16e mode */
999 bcode = (instr[0] >> 5) & 0x3f;
1000 } else if (mm_insn_16bit(instr[0])) {
1001 /* 16-bit microMIPS BREAK */
1002 bcode = instr[0] & 0xf;
1003 } else {
1004 /* 32-bit microMIPS BREAK */
1005 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001006 goto out_sigsegv;
Markos Chandrasb08a9c92013-12-04 16:20:08 +00001007 opcode = (instr[0] << 16) | instr[1];
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +01001008 bcode = (opcode >> 6) & ((1 << 20) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001009 }
1010 } else {
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +01001011 if (__get_user(opcode, (unsigned int __user *)epc))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001012 goto out_sigsegv;
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +01001013 bcode = (opcode >> 6) & ((1 << 20) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001014 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015
1016 /*
1017 * There is the ancient bug in the MIPS assemblers that the break
1018 * code starts left to bit 16 instead to bit 6 in the opcode.
1019 * Gas is bug-compatible, but not always, grrr...
1020 * We handle both cases with a simple heuristics. --macro
1021 */
Ralf Baechledf270052008-04-20 16:28:54 +01001022 if (bcode >= (1 << 10))
Maciej W. Rozyckic9875032015-04-03 23:26:32 +01001023 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024
David Daneyc1bf2072010-08-03 11:22:20 -07001025 /*
1026 * notify the kprobe handlers, if instruction is likely to
1027 * pertain to them.
1028 */
1029 switch (bcode) {
Ralf Baechle40e084a2015-07-29 22:44:53 +02001030 case BRK_UPROBE:
1031 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1032 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1033 goto out;
1034 else
1035 break;
1036 case BRK_UPROBE_XOL:
1037 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1038 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1039 goto out;
1040 else
1041 break;
David Daneyc1bf2072010-08-03 11:22:20 -07001042 case BRK_KPROBE_BP:
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001043 if (notify_die(DIE_BREAK, "debug", regs, bcode,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001044 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001045 goto out;
David Daneyc1bf2072010-08-03 11:22:20 -07001046 else
1047 break;
1048 case BRK_KPROBE_SSTEPBP:
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001049 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001050 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001051 goto out;
David Daneyc1bf2072010-08-03 11:22:20 -07001052 else
1053 break;
1054 default:
1055 break;
1056 }
1057
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001058 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001059
1060out:
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001061 set_fs(seg);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001062 exception_exit(prev_state);
Atsushi Nemoto90fccb12007-02-06 16:02:21 +09001063 return;
Ralf Baechlee5679882006-11-30 01:14:47 +00001064
1065out_sigsegv:
1066 force_sig(SIGSEGV, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001067 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068}
1069
1070asmlinkage void do_tr(struct pt_regs *regs)
1071{
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001072 u32 opcode, tcode = 0;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001073 enum ctx_state prev_state;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001074 u16 instr[2];
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001075 mm_segment_t seg;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001076 unsigned long epc = msk_isa16_mode(exception_epc(regs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001078 seg = get_fs();
1079 if (!user_mode(regs))
Linus Torvalds736706b2019-03-04 10:39:05 -08001080 set_fs(KERNEL_DS);
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001081
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001082 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001083 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001084 if (get_isa16_mode(regs->cp0_epc)) {
1085 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1086 __get_user(instr[1], (u16 __user *)(epc + 2)))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001087 goto out_sigsegv;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001088 opcode = (instr[0] << 16) | instr[1];
1089 /* Immediate versions don't provide a code. */
1090 if (!(opcode & OPCODE))
1091 tcode = (opcode >> 12) & ((1 << 4) - 1);
1092 } else {
1093 if (__get_user(opcode, (u32 __user *)epc))
1094 goto out_sigsegv;
1095 /* Immediate versions don't provide a code. */
1096 if (!(opcode & OPCODE))
1097 tcode = (opcode >> 6) & ((1 << 10) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001098 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001100 do_trap_or_bp(regs, tcode, 0, "Trap");
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001101
1102out:
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001103 set_fs(seg);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001104 exception_exit(prev_state);
Atsushi Nemoto90fccb12007-02-06 16:02:21 +09001105 return;
Ralf Baechlee5679882006-11-30 01:14:47 +00001106
1107out_sigsegv:
1108 force_sig(SIGSEGV, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001109 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110}
1111
1112asmlinkage void do_ri(struct pt_regs *regs)
1113{
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001114 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1115 unsigned long old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001116 unsigned long old31 = regs->regs[31];
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001117 enum ctx_state prev_state;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001118 unsigned int opcode = 0;
1119 int status = -1;
1120
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001121 /*
1122 * Avoid any kernel code. Just emulate the R2 instruction
1123 * as quickly as possible.
1124 */
1125 if (mipsr2_emulation && cpu_has_mips_r6 &&
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001126 likely(user_mode(regs)) &&
1127 likely(get_user(opcode, epc) >= 0)) {
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001128 unsigned long fcr31 = 0;
1129
1130 status = mipsr2_decoder(regs, opcode, &fcr31);
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001131 switch (status) {
1132 case 0:
1133 case SIGEMT:
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001134 return;
1135 case SIGILL:
1136 goto no_r2_instr;
1137 default:
1138 process_fpemu_return(status,
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001139 &current->thread.cp0_baduaddr,
1140 fcr31);
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001141 return;
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001142 }
1143 }
1144
1145no_r2_instr:
1146
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001147 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001148 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001149
Ralf Baechlee3b28832015-07-28 20:37:43 +02001150 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001151 SIGILL) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001152 goto out;
Jason Wessel88547002008-07-29 15:58:53 -05001153
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154 die_if_kernel("Reserved instruction in kernel code", regs);
1155
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001156 if (unlikely(compute_return_epc(regs) < 0))
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001157 goto out;
Ralf Baechle3c370262005-04-13 17:43:59 +00001158
Maciej W. Rozycki3d50a7f2016-01-30 09:08:43 +00001159 if (!get_isa16_mode(regs->cp0_epc)) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001160 if (unlikely(get_user(opcode, epc) < 0))
1161 status = SIGSEGV;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001162
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001163 if (!cpu_has_llsc && status < 0)
1164 status = simulate_llsc(regs, opcode);
1165
1166 if (status < 0)
1167 status = simulate_rdhwr_normal(regs, opcode);
1168
1169 if (status < 0)
1170 status = simulate_sync(regs, opcode);
Paul Burton4227a2d2014-09-11 08:30:20 +01001171
1172 if (status < 0)
1173 status = simulate_fp(regs, opcode, old_epc, old31);
Maciej W. Rozycki3d50a7f2016-01-30 09:08:43 +00001174 } else if (cpu_has_mmips) {
1175 unsigned short mmop[2] = { 0 };
1176
1177 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1178 status = SIGSEGV;
1179 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1180 status = SIGSEGV;
1181 opcode = mmop[0];
1182 opcode = (opcode << 16) | mmop[1];
1183
1184 if (status < 0)
1185 status = simulate_rdhwr_mm(regs, opcode);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001186 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001187
1188 if (status < 0)
1189 status = SIGILL;
1190
1191 if (unlikely(status > 0)) {
1192 regs->cp0_epc = old_epc; /* Undo skip-over. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001193 regs->regs[31] = old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001194 force_sig(status, current);
1195 }
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001196
1197out:
1198 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199}
1200
Ralf Baechled223a862007-07-10 17:33:02 +01001201/*
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001202 * No lock; only written during early bootup by CPU 0.
1203 */
1204static RAW_NOTIFIER_HEAD(cu2_chain);
1205
1206int __ref register_cu2_notifier(struct notifier_block *nb)
1207{
1208 return raw_notifier_chain_register(&cu2_chain, nb);
1209}
1210
1211int cu2_notifier_call_chain(unsigned long val, void *v)
1212{
1213 return raw_notifier_call_chain(&cu2_chain, val, v);
1214}
1215
1216static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
Ralf Baechle70342282013-01-22 12:59:30 +01001217 void *data)
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001218{
1219 struct pt_regs *regs = data;
1220
Jayachandran C83bee792013-06-10 06:30:01 +00001221 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001222 "instruction", regs);
Jayachandran C83bee792013-06-10 06:30:01 +00001223 force_sig(SIGILL, current);
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001224
1225 return NOTIFY_OK;
1226}
1227
Paul Burton5328f742018-11-07 23:14:05 +00001228#ifdef CONFIG_MIPS_FP_SUPPORT
1229
Paul Burton1db1af82014-01-27 15:23:11 +00001230static int enable_restore_fp_context(int msa)
1231{
Paul Burtonc9017752014-07-30 08:53:20 +01001232 int err, was_fpu_owner, prior_msa;
Paul Burtoncc97ab22018-11-07 23:13:59 +00001233 bool first_fp;
Paul Burton1db1af82014-01-27 15:23:11 +00001234
Paul Burtoncc97ab22018-11-07 23:13:59 +00001235 /* Initialize context if it hasn't been used already */
1236 first_fp = init_fp_ctx(current);
1237
1238 if (first_fp) {
Paul Burton762a1f42014-07-11 16:44:35 +01001239 preempt_disable();
Paul Burtoncc97ab22018-11-07 23:13:59 +00001240 err = own_fpu_inatomic(1);
Paul Burtonc9017752014-07-30 08:53:20 +01001241 if (msa && !err) {
Paul Burton1db1af82014-01-27 15:23:11 +00001242 enable_msa();
Paul Burton732c0c32014-07-31 14:53:16 +01001243 set_thread_flag(TIF_USEDMSA);
1244 set_thread_flag(TIF_MSA_CTX_LIVE);
Paul Burtonc9017752014-07-30 08:53:20 +01001245 }
Paul Burton762a1f42014-07-11 16:44:35 +01001246 preempt_enable();
Paul Burton1db1af82014-01-27 15:23:11 +00001247 return err;
1248 }
1249
1250 /*
1251 * This task has formerly used the FP context.
1252 *
1253 * If this thread has no live MSA vector context then we can simply
1254 * restore the scalar FP context. If it has live MSA vector context
1255 * (that is, it has or may have used MSA since last performing a
1256 * function call) then we'll need to restore the vector context. This
1257 * applies even if we're currently only executing a scalar FP
1258 * instruction. This is because if we were to later execute an MSA
1259 * instruction then we'd either have to:
1260 *
1261 * - Restore the vector context & clobber any registers modified by
1262 * scalar FP instructions between now & then.
1263 *
1264 * or
1265 *
1266 * - Not restore the vector context & lose the most significant bits
1267 * of all vector registers.
1268 *
1269 * Neither of those options is acceptable. We cannot restore the least
1270 * significant bits of the registers now & only restore the most
1271 * significant bits later because the most significant bits of any
1272 * vector registers whose aliased FP register is modified now will have
1273 * been zeroed. We'd have no way to know that when restoring the vector
1274 * context & thus may load an outdated value for the most significant
1275 * bits of a vector register.
1276 */
1277 if (!msa && !thread_msa_context_live())
1278 return own_fpu(1);
1279
1280 /*
1281 * This task is using or has previously used MSA. Thus we require
1282 * that Status.FR == 1.
1283 */
Paul Burton762a1f42014-07-11 16:44:35 +01001284 preempt_disable();
Paul Burton1db1af82014-01-27 15:23:11 +00001285 was_fpu_owner = is_fpu_owner();
Paul Burton762a1f42014-07-11 16:44:35 +01001286 err = own_fpu_inatomic(0);
Paul Burton1db1af82014-01-27 15:23:11 +00001287 if (err)
Paul Burton762a1f42014-07-11 16:44:35 +01001288 goto out;
Paul Burton1db1af82014-01-27 15:23:11 +00001289
1290 enable_msa();
1291 write_msa_csr(current->thread.fpu.msacsr);
1292 set_thread_flag(TIF_USEDMSA);
1293
1294 /*
1295 * If this is the first time that the task is using MSA and it has
1296 * previously used scalar FP in this time slice then we already nave
Paul Burtonc9017752014-07-30 08:53:20 +01001297 * FP context which we shouldn't clobber. We do however need to clear
1298 * the upper 64b of each vector register so that this task has no
1299 * opportunity to see data left behind by another.
Paul Burton1db1af82014-01-27 15:23:11 +00001300 */
Paul Burtonc9017752014-07-30 08:53:20 +01001301 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1302 if (!prior_msa && was_fpu_owner) {
Maciej W. Rozyckie49d3842016-05-17 06:12:27 +01001303 init_msa_upper();
Paul Burton762a1f42014-07-11 16:44:35 +01001304
1305 goto out;
Paul Burtonc9017752014-07-30 08:53:20 +01001306 }
Paul Burton1db1af82014-01-27 15:23:11 +00001307
Paul Burtonc9017752014-07-30 08:53:20 +01001308 if (!prior_msa) {
1309 /*
1310 * Restore the least significant 64b of each vector register
1311 * from the existing scalar FP context.
1312 */
1313 _restore_fp(current);
Paul Burtonb8340672014-07-11 16:44:29 +01001314
Paul Burtonc9017752014-07-30 08:53:20 +01001315 /*
1316 * The task has not formerly used MSA, so clear the upper 64b
1317 * of each vector register such that it cannot see data left
1318 * behind by another task.
1319 */
Maciej W. Rozyckie49d3842016-05-17 06:12:27 +01001320 init_msa_upper();
Paul Burtonc9017752014-07-30 08:53:20 +01001321 } else {
1322 /* We need to restore the vector context. */
1323 restore_msa(current);
Paul Burtonb8340672014-07-11 16:44:29 +01001324
Paul Burtonc9017752014-07-30 08:53:20 +01001325 /* Restore the scalar FP control & status register */
1326 if (!was_fpu_owner)
James Hogand76e9b92015-01-30 15:40:20 +00001327 write_32bit_cp1_register(CP1_STATUS,
1328 current->thread.fpu.fcr31);
Paul Burtonc9017752014-07-30 08:53:20 +01001329 }
Paul Burton762a1f42014-07-11 16:44:35 +01001330
1331out:
1332 preempt_enable();
1333
Paul Burton1db1af82014-01-27 15:23:11 +00001334 return 0;
1335}
1336
Paul Burton5328f742018-11-07 23:14:05 +00001337#else /* !CONFIG_MIPS_FP_SUPPORT */
1338
1339static int enable_restore_fp_context(int msa)
1340{
1341 return SIGILL;
1342}
1343
1344#endif /* CONFIG_MIPS_FP_SUPPORT */
1345
Linus Torvalds1da177e2005-04-16 15:20:36 -07001346asmlinkage void do_cpu(struct pt_regs *regs)
1347{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001348 enum ctx_state prev_state;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001349 unsigned int __user *epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001350 unsigned long old_epc, old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001351 unsigned int opcode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352 unsigned int cpid;
Paul Burton5328f742018-11-07 23:14:05 +00001353 int status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001355 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1357
Jayachandran C83bee792013-06-10 06:30:01 +00001358 if (cpid != 2)
1359 die_if_kernel("do_cpu invoked from kernel context!", regs);
1360
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361 switch (cpid) {
1362 case 0:
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001363 epc = (unsigned int __user *)exception_epc(regs);
1364 old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001365 old31 = regs->regs[31];
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001366 opcode = 0;
1367 status = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001369 if (unlikely(compute_return_epc(regs) < 0))
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001370 break;
Ralf Baechle3c370262005-04-13 17:43:59 +00001371
Maciej W. Rozycki10f6d99f2016-01-30 09:08:16 +00001372 if (!get_isa16_mode(regs->cp0_epc)) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001373 if (unlikely(get_user(opcode, epc) < 0))
1374 status = SIGSEGV;
1375
1376 if (!cpu_has_llsc && status < 0)
1377 status = simulate_llsc(regs, opcode);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001378 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001379
1380 if (status < 0)
1381 status = SIGILL;
1382
1383 if (unlikely(status > 0)) {
1384 regs->cp0_epc = old_epc; /* Undo skip-over. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001385 regs->regs[31] = old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001386 force_sig(status, current);
1387 }
1388
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001389 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390
Paul Burton5328f742018-11-07 23:14:05 +00001391#ifdef CONFIG_MIPS_FP_SUPPORT
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001392 case 3:
1393 /*
Maciej W. Rozycki2d83fea2015-04-03 23:26:49 +01001394 * The COP3 opcode space and consequently the CP0.Status.CU3
1395 * bit and the CP0.Cause.CE=3 encoding have been removed as
1396 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1397 * up the space has been reused for COP1X instructions, that
1398 * are enabled by the CP0.Status.CU1 bit and consequently
1399 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1400 * exceptions. Some FPU-less processors that implement one
1401 * of these ISAs however use this code erroneously for COP1X
1402 * instructions. Therefore we redirect this trap to the FP
1403 * emulator too.
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001404 */
Maciej W. Rozycki2d83fea2015-04-03 23:26:49 +01001405 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001406 force_sig(SIGILL, current);
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001407 break;
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001408 }
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001409 /* Fall through. */
1410
Paul Burton5328f742018-11-07 23:14:05 +00001411 case 1: {
1412 void __user *fault_addr;
1413 unsigned long fcr31;
1414 int err, sig;
1415
Paul Burton1db1af82014-01-27 15:23:11 +00001416 err = enable_restore_fp_context(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001418 if (raw_cpu_has_fpu && !err)
1419 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001420
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001421 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1422 &fault_addr);
Maciej W. Rozycki443c4402015-04-03 23:27:10 +01001423
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001424 /*
1425 * We can't allow the emulated instruction to leave
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +01001426 * any enabled Cause bits set in $fcr31.
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001427 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +01001428 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1429 current->thread.fpu.fcr31 &= ~fcr31;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001430
1431 /* Send a signal if required. */
1432 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1433 mt_ase_fp_affinity();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001434
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001435 break;
Paul Burton5328f742018-11-07 23:14:05 +00001436 }
1437#else /* CONFIG_MIPS_FP_SUPPORT */
1438 case 1:
1439 case 3:
1440 force_sig(SIGILL, current);
1441 break;
1442#endif /* CONFIG_MIPS_FP_SUPPORT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443
1444 case 2:
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001445 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001446 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447 }
1448
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001449 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450}
1451
James Hogan64bedff2014-12-02 13:44:13 +00001452asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001453{
1454 enum ctx_state prev_state;
1455
1456 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001457 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
James Hogan64bedff2014-12-02 13:44:13 +00001458 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001459 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
James Hogan64bedff2014-12-02 13:44:13 +00001460 goto out;
1461
1462 /* Clear MSACSR.Cause before enabling interrupts */
1463 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1464 local_irq_enable();
1465
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001466 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1467 force_sig(SIGFPE, current);
James Hogan64bedff2014-12-02 13:44:13 +00001468out:
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001469 exception_exit(prev_state);
1470}
1471
Paul Burton1db1af82014-01-27 15:23:11 +00001472asmlinkage void do_msa(struct pt_regs *regs)
1473{
1474 enum ctx_state prev_state;
1475 int err;
1476
1477 prev_state = exception_enter();
1478
1479 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1480 force_sig(SIGILL, current);
1481 goto out;
1482 }
1483
1484 die_if_kernel("do_msa invoked from kernel context!", regs);
1485
1486 err = enable_restore_fp_context(1);
1487 if (err)
1488 force_sig(SIGILL, current);
1489out:
1490 exception_exit(prev_state);
1491}
1492
Linus Torvalds1da177e2005-04-16 15:20:36 -07001493asmlinkage void do_mdmx(struct pt_regs *regs)
1494{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001495 enum ctx_state prev_state;
1496
1497 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498 force_sig(SIGILL, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001499 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500}
1501
David Daney8bc6d052009-01-05 15:29:58 -08001502/*
1503 * Called with interrupts disabled.
1504 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505asmlinkage void do_watch(struct pt_regs *regs)
1506{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001507 enum ctx_state prev_state;
David Daneyb67b2b72008-09-23 00:08:45 -07001508
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001509 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001510 /*
David Daneyb67b2b72008-09-23 00:08:45 -07001511 * Clear WP (bit 22) bit of cause register so we don't loop
1512 * forever.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001513 */
James Hogane233c732016-03-01 22:19:38 +00001514 clear_c0_cause(CAUSEF_WP);
David Daneyb67b2b72008-09-23 00:08:45 -07001515
1516 /*
1517 * If the current thread has the watch registers loaded, save
1518 * their values and send SIGTRAP. Otherwise another thread
1519 * left the registers set, clear them and continue.
1520 */
1521 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1522 mips_read_watch_registers();
David Daney8bc6d052009-01-05 15:29:58 -08001523 local_irq_enable();
Eric W. Biedermanf43a54a2018-04-15 21:11:06 -05001524 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL, current);
David Daney8bc6d052009-01-05 15:29:58 -08001525 } else {
David Daneyb67b2b72008-09-23 00:08:45 -07001526 mips_clear_watch_registers();
David Daney8bc6d052009-01-05 15:29:58 -08001527 local_irq_enable();
1528 }
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001529 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530}
1531
1532asmlinkage void do_mcheck(struct pt_regs *regs)
1533{
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001534 int multi_match = regs->cp0_status & ST0_TS;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001535 enum ctx_state prev_state;
James Hogan55c723e2015-07-27 13:50:21 +01001536 mm_segment_t old_fs = get_fs();
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001537
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001538 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001539 show_regs(regs);
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001540
1541 if (multi_match) {
James Hogan3c865dd2015-07-15 16:17:43 +01001542 dump_tlb_regs();
1543 pr_info("\n");
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001544 dump_tlb_all();
1545 }
1546
James Hogan55c723e2015-07-27 13:50:21 +01001547 if (!user_mode(regs))
1548 set_fs(KERNEL_DS);
1549
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +09001550 show_code((unsigned int __user *) regs->cp0_epc);
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001551
James Hogan55c723e2015-07-27 13:50:21 +01001552 set_fs(old_fs);
1553
Linus Torvalds1da177e2005-04-16 15:20:36 -07001554 /*
1555 * Some chips may have other causes of machine check (e.g. SB1
1556 * graduation timer)
1557 */
1558 panic("Caught Machine Check exception - %scaused by multiple "
1559 "matching entries in the TLB.",
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001560 (multi_match) ? "" : "not ");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561}
1562
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001563asmlinkage void do_mt(struct pt_regs *regs)
1564{
Ralf Baechle41c594a2006-04-05 09:45:45 +01001565 int subcode;
1566
Ralf Baechle41c594a2006-04-05 09:45:45 +01001567 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1568 >> VPECONTROL_EXCPT_SHIFT;
1569 switch (subcode) {
1570 case 0:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001571 printk(KERN_DEBUG "Thread Underflow\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001572 break;
1573 case 1:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001574 printk(KERN_DEBUG "Thread Overflow\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001575 break;
1576 case 2:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001577 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001578 break;
1579 case 3:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001580 printk(KERN_DEBUG "Gating Storage Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001581 break;
1582 case 4:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001583 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001584 break;
1585 case 5:
Masanari Iidaf232c7e2012-02-08 21:53:14 +09001586 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001587 break;
1588 default:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001589 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
Ralf Baechle41c594a2006-04-05 09:45:45 +01001590 subcode);
1591 break;
1592 }
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001593 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1594
1595 force_sig(SIGILL, current);
1596}
1597
1598
Ralf Baechlee50c0a82005-05-31 11:49:19 +00001599asmlinkage void do_dsp(struct pt_regs *regs)
1600{
1601 if (cpu_has_dsp)
Ralf Baechleab75dc02011-11-17 15:07:31 +00001602 panic("Unexpected DSP exception");
Ralf Baechlee50c0a82005-05-31 11:49:19 +00001603
1604 force_sig(SIGILL, current);
1605}
1606
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607asmlinkage void do_reserved(struct pt_regs *regs)
1608{
1609 /*
Ralf Baechle70342282013-01-22 12:59:30 +01001610 * Game over - no way to handle this if it ever occurs. Most probably
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 * caused by a new unknown cpu type or after another deadly
1612 * hard/software error.
1613 */
1614 show_regs(regs);
1615 panic("Caught reserved exception %ld - should not happen.",
1616 (regs->cp0_cause & 0x7f) >> 2);
1617}
1618
Ralf Baechle39b8d522008-04-28 17:14:26 +01001619static int __initdata l1parity = 1;
1620static int __init nol1parity(char *s)
1621{
1622 l1parity = 0;
1623 return 1;
1624}
1625__setup("nol1par", nol1parity);
1626static int __initdata l2parity = 1;
1627static int __init nol2parity(char *s)
1628{
1629 l2parity = 0;
1630 return 1;
1631}
1632__setup("nol2par", nol2parity);
1633
Linus Torvalds1da177e2005-04-16 15:20:36 -07001634/*
1635 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1636 * it different ways.
1637 */
1638static inline void parity_protection_init(void)
1639{
Paul Burton35e6de32016-10-17 16:01:07 +01001640#define ERRCTL_PE 0x80000000
1641#define ERRCTL_L2P 0x00800000
1642
1643 if (mips_cm_revision() >= CM_REV_CM3) {
1644 ulong gcr_ectl, cp0_ectl;
1645
1646 /*
1647 * With CM3 systems we need to ensure that the L1 & L2
1648 * parity enables are set to the same value, since this
1649 * is presumed by the hardware engineers.
1650 *
1651 * If the user disabled either of L1 or L2 ECC checking,
1652 * disable both.
1653 */
1654 l1parity &= l2parity;
1655 l2parity &= l1parity;
1656
1657 /* Probe L1 ECC support */
1658 cp0_ectl = read_c0_ecc();
1659 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1660 back_to_back_c0_hazard();
1661 cp0_ectl = read_c0_ecc();
1662
1663 /* Probe L2 ECC support */
1664 gcr_ectl = read_gcr_err_control();
1665
Paul Burton93c5bba52017-08-12 19:49:27 -07001666 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
Paul Burton35e6de32016-10-17 16:01:07 +01001667 !(cp0_ectl & ERRCTL_PE)) {
1668 /*
1669 * One of L1 or L2 ECC checking isn't supported,
1670 * so we cannot enable either.
1671 */
1672 l1parity = l2parity = 0;
1673 }
1674
1675 /* Configure L1 ECC checking */
1676 if (l1parity)
1677 cp0_ectl |= ERRCTL_PE;
1678 else
1679 cp0_ectl &= ~ERRCTL_PE;
1680 write_c0_ecc(cp0_ectl);
1681 back_to_back_c0_hazard();
1682 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1683
1684 /* Configure L2 ECC checking */
1685 if (l2parity)
Paul Burton93c5bba52017-08-12 19:49:27 -07001686 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
Paul Burton35e6de32016-10-17 16:01:07 +01001687 else
Paul Burton93c5bba52017-08-12 19:49:27 -07001688 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
Paul Burton35e6de32016-10-17 16:01:07 +01001689 write_gcr_err_control(gcr_ectl);
1690 gcr_ectl = read_gcr_err_control();
Paul Burton93c5bba52017-08-12 19:49:27 -07001691 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
Paul Burton35e6de32016-10-17 16:01:07 +01001692 WARN_ON(!!gcr_ectl != l2parity);
1693
1694 pr_info("Cache parity protection %sabled\n",
1695 l1parity ? "en" : "dis");
1696 return;
1697 }
1698
Ralf Baechle10cc3522007-10-11 23:46:15 +01001699 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001700 case CPU_24K:
Nigel Stephens98a41de2006-04-27 15:50:32 +01001701 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001702 case CPU_74K:
1703 case CPU_1004K:
Steven J. Hill442e14a2014-01-17 15:03:50 -06001704 case CPU_1074K:
Leonid Yegoshin26ab96d2013-11-27 10:07:53 +00001705 case CPU_INTERAPTIV:
Leonid Yegoshin708ac4b2013-11-14 16:12:27 +00001706 case CPU_PROAPTIV:
James Hoganaced4cb2014-01-22 16:19:38 +00001707 case CPU_P5600:
Leonid Yegoshin46950892014-11-24 12:59:01 +00001708 case CPU_QEMU_GENERIC:
Paul Burton1091bfa2016-02-03 03:26:38 +00001709 case CPU_P6600:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001710 {
Ralf Baechle39b8d522008-04-28 17:14:26 +01001711 unsigned long errctl;
1712 unsigned int l1parity_present, l2parity_present;
1713
1714 errctl = read_c0_ecc();
1715 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1716
1717 /* probe L1 parity support */
1718 write_c0_ecc(errctl | ERRCTL_PE);
1719 back_to_back_c0_hazard();
1720 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1721
1722 /* probe L2 parity support */
1723 write_c0_ecc(errctl|ERRCTL_L2P);
1724 back_to_back_c0_hazard();
1725 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1726
1727 if (l1parity_present && l2parity_present) {
1728 if (l1parity)
1729 errctl |= ERRCTL_PE;
1730 if (l1parity ^ l2parity)
1731 errctl |= ERRCTL_L2P;
1732 } else if (l1parity_present) {
1733 if (l1parity)
1734 errctl |= ERRCTL_PE;
1735 } else if (l2parity_present) {
1736 if (l2parity)
1737 errctl |= ERRCTL_L2P;
1738 } else {
1739 /* No parity available */
1740 }
1741
1742 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1743
1744 write_c0_ecc(errctl);
1745 back_to_back_c0_hazard();
1746 errctl = read_c0_ecc();
1747 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1748
1749 if (l1parity_present)
1750 printk(KERN_INFO "Cache parity protection %sabled\n",
1751 (errctl & ERRCTL_PE) ? "en" : "dis");
1752
1753 if (l2parity_present) {
1754 if (l1parity_present && l1parity)
1755 errctl ^= ERRCTL_L2P;
1756 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1757 (errctl & ERRCTL_L2P) ? "en" : "dis");
1758 }
1759 }
1760 break;
1761
Linus Torvalds1da177e2005-04-16 15:20:36 -07001762 case CPU_5KC:
Leonid Yegoshin78d48032012-07-06 21:56:01 +02001763 case CPU_5KE:
Kelvin Cheung2fa36392012-06-20 20:05:32 +01001764 case CPU_LOONGSON1:
Ralf Baechle14f18b72005-03-01 18:15:08 +00001765 write_c0_ecc(0x80000000);
1766 back_to_back_c0_hazard();
1767 /* Set the PE bit (bit 31) in the c0_errctl register. */
1768 printk(KERN_INFO "Cache parity protection %sabled\n",
1769 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770 break;
1771 case CPU_20KC:
1772 case CPU_25KF:
1773 /* Clear the DE bit (bit 16) in the c0_status register. */
1774 printk(KERN_INFO "Enable cache parity protection for "
1775 "MIPS 20KC/25KF CPUs.\n");
1776 clear_c0_status(ST0_DE);
1777 break;
1778 default:
1779 break;
1780 }
1781}
1782
1783asmlinkage void cache_parity_error(void)
1784{
1785 const int field = 2 * sizeof(unsigned long);
1786 unsigned int reg_val;
1787
1788 /* For the moment, report the problem and hang. */
1789 printk("Cache error exception:\n");
1790 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1791 reg_val = read_c0_cacheerr();
1792 printk("c0_cacheerr == %08x\n", reg_val);
1793
1794 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1795 reg_val & (1<<30) ? "secondary" : "primary",
1796 reg_val & (1<<31) ? "data" : "insn");
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00001797 if ((cpu_has_mips_r2_r6) &&
Markos Chandras721a9202014-05-21 12:35:00 +01001798 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
Leonid Yegoshin6de20452013-10-10 09:58:59 +01001799 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1800 reg_val & (1<<29) ? "ED " : "",
1801 reg_val & (1<<28) ? "ET " : "",
1802 reg_val & (1<<27) ? "ES " : "",
1803 reg_val & (1<<26) ? "EE " : "",
1804 reg_val & (1<<25) ? "EB " : "",
1805 reg_val & (1<<24) ? "EI " : "",
1806 reg_val & (1<<23) ? "E1 " : "",
1807 reg_val & (1<<22) ? "E0 " : "");
1808 } else {
1809 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1810 reg_val & (1<<29) ? "ED " : "",
1811 reg_val & (1<<28) ? "ET " : "",
1812 reg_val & (1<<26) ? "EE " : "",
1813 reg_val & (1<<25) ? "EB " : "",
1814 reg_val & (1<<24) ? "EI " : "",
1815 reg_val & (1<<23) ? "E1 " : "",
1816 reg_val & (1<<22) ? "E0 " : "");
1817 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001818 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1819
Ralf Baechleec917c2c2005-10-07 16:58:15 +01001820#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821 if (reg_val & (1<<22))
1822 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1823
1824 if (reg_val & (1<<23))
1825 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1826#endif
1827
1828 panic("Can't handle the cache error!");
1829}
1830
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +00001831asmlinkage void do_ftlb(void)
1832{
1833 const int field = 2 * sizeof(unsigned long);
1834 unsigned int reg_val;
1835
1836 /* For the moment, report the problem and hang. */
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00001837 if ((cpu_has_mips_r2_r6) &&
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001838 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1839 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +00001840 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1841 read_c0_ecc());
1842 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1843 reg_val = read_c0_cacheerr();
1844 pr_err("c0_cacheerr == %08x\n", reg_val);
1845
1846 if ((reg_val & 0xc0000000) == 0xc0000000) {
1847 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1848 } else {
1849 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1850 reg_val & (1<<30) ? "secondary" : "primary",
1851 reg_val & (1<<31) ? "data" : "insn");
1852 }
1853 } else {
1854 pr_err("FTLB error exception\n");
1855 }
1856 /* Just print the cacheerr bits for now */
1857 cache_parity_error();
1858}
1859
Linus Torvalds1da177e2005-04-16 15:20:36 -07001860/*
1861 * SDBBP EJTAG debug exception handler.
1862 * We skip the instruction and return to the next instruction.
1863 */
1864void ejtag_exception_handler(struct pt_regs *regs)
1865{
1866 const int field = 2 * sizeof(unsigned long);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001867 unsigned long depc, old_epc, old_ra;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001868 unsigned int debug;
1869
Chris Dearman70ae6122006-06-30 12:32:37 +01001870 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001871 depc = read_c0_depc();
1872 debug = read_c0_debug();
Chris Dearman70ae6122006-06-30 12:32:37 +01001873 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874 if (debug & 0x80000000) {
1875 /*
1876 * In branch delay slot.
1877 * We cheat a little bit here and use EPC to calculate the
1878 * debug return address (DEPC). EPC is restored after the
1879 * calculation.
1880 */
1881 old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001882 old_ra = regs->regs[31];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001883 regs->cp0_epc = depc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001884 compute_return_epc(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001885 depc = regs->cp0_epc;
1886 regs->cp0_epc = old_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001887 regs->regs[31] = old_ra;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001888 } else
1889 depc += 4;
1890 write_c0_depc(depc);
1891
1892#if 0
Chris Dearman70ae6122006-06-30 12:32:37 +01001893 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001894 write_c0_debug(debug | 0x100);
1895#endif
1896}
1897
1898/*
1899 * NMI exception handler.
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001900 * No lock; only written during early bootup by CPU 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901 */
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001902static RAW_NOTIFIER_HEAD(nmi_chain);
1903
1904int register_nmi_notifier(struct notifier_block *nb)
1905{
1906 return raw_notifier_chain_register(&nmi_chain, nb);
1907}
1908
Joe Perchesff2d8b12012-01-12 17:17:21 -08001909void __noreturn nmi_exception_handler(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910{
Leonid Yegoshin83e4da12013-10-08 12:39:31 +01001911 char str[100];
1912
Petri Gynther7963b3f2015-10-19 11:49:52 -07001913 nmi_enter();
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001914 raw_notifier_call_chain(&nmi_chain, 0, regs);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001915 bust_spinlocks(1);
Leonid Yegoshin83e4da12013-10-08 12:39:31 +01001916 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1917 smp_processor_id(), regs->cp0_epc);
1918 regs->cp0_epc = read_c0_errorepc();
1919 die(str, regs);
Petri Gynther7963b3f2015-10-19 11:49:52 -07001920 nmi_exit();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921}
1922
Ralf Baechlee01402b2005-07-14 15:57:16 +00001923#define VECTORSPACING 0x100 /* for EI/VI mode */
1924
1925unsigned long ebase;
James Hogan878edf02016-06-09 14:19:14 +01001926EXPORT_SYMBOL_GPL(ebase);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927unsigned long exception_handlers[32];
Ralf Baechlee01402b2005-07-14 15:57:16 +00001928unsigned long vi_handlers[64];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929
Florian Fainelli2d1b6e92010-01-28 15:21:42 +01001930void __init *set_except_vector(int n, void *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931{
1932 unsigned long handler = (unsigned long) addr;
Ralf Baechleb22d1b62013-05-09 17:57:30 +02001933 unsigned long old_handler;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001934
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001935#ifdef CONFIG_CPU_MICROMIPS
1936 /*
1937 * Only the TLB handlers are cache aligned with an even
1938 * address. All other handlers are on an odd address and
1939 * require no modification. Otherwise, MIPS32 mode will
1940 * be entered when handling any TLB exceptions. That
1941 * would be bad...since we must stay in microMIPS mode.
1942 */
1943 if (!(handler & 0x1))
1944 handler |= 1;
1945#endif
Ralf Baechleb22d1b62013-05-09 17:57:30 +02001946 old_handler = xchg(&exception_handlers[n], handler);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947
Linus Torvalds1da177e2005-04-16 15:20:36 -07001948 if (n == 0 && cpu_has_divec) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001949#ifdef CONFIG_CPU_MICROMIPS
1950 unsigned long jump_mask = ~((1 << 27) - 1);
1951#else
Florian Fainelli92bbe1b2010-01-28 15:22:37 +01001952 unsigned long jump_mask = ~((1 << 28) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001953#endif
Florian Fainelli92bbe1b2010-01-28 15:22:37 +01001954 u32 *buf = (u32 *)(ebase + 0x200);
1955 unsigned int k0 = 26;
1956 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1957 uasm_i_j(&buf, handler & ~jump_mask);
1958 uasm_i_nop(&buf);
1959 } else {
1960 UASM_i_LA(&buf, k0, handler);
1961 uasm_i_jr(&buf, k0);
1962 uasm_i_nop(&buf);
1963 }
1964 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001965 }
1966 return (void *)old_handler;
1967}
1968
Ralf Baechle86a17082013-02-08 01:21:34 +01001969static void do_default_vi(void)
Atsushi Nemoto6ba07e52007-05-21 23:45:38 +09001970{
1971 show_regs(get_irq_regs());
1972 panic("Caught unexpected vectored interrupt.");
1973}
1974
Ralf Baechleef300e42007-05-06 18:31:18 +01001975static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001976{
1977 unsigned long handler;
1978 unsigned long old_handler = vi_handlers[n];
Ralf Baechlef6771db2007-11-08 18:02:29 +00001979 int srssets = current_cpu_data.srsets;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001980 u16 *h;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001981 unsigned char *b;
1982
Ralf Baechleb72b7092009-03-30 14:49:44 +02001983 BUG_ON(!cpu_has_veic && !cpu_has_vint);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001984
1985 if (addr == NULL) {
1986 handler = (unsigned long) do_default_vi;
1987 srs = 0;
Ralf Baechle41c594a2006-04-05 09:45:45 +01001988 } else
Ralf Baechlee01402b2005-07-14 15:57:16 +00001989 handler = (unsigned long) addr;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001990 vi_handlers[n] = handler;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001991
1992 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1993
Ralf Baechlef6771db2007-11-08 18:02:29 +00001994 if (srs >= srssets)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001995 panic("Shadow register set %d not supported", srs);
1996
1997 if (cpu_has_veic) {
1998 if (board_bind_eic_interrupt)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01001999 board_bind_eic_interrupt(n, srs);
Ralf Baechle41c594a2006-04-05 09:45:45 +01002000 } else if (cpu_has_vint) {
Ralf Baechlee01402b2005-07-14 15:57:16 +00002001 /* SRSMap is only defined if shadow sets are implemented */
Ralf Baechlef6771db2007-11-08 18:02:29 +00002002 if (srssets > 1)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002003 change_c0_srsmap(0xf << n*4, srs << n*4);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002004 }
2005
2006 if (srs == 0) {
2007 /*
2008 * If no shadow set is selected then use the default handler
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002009 * that does normal register saving and standard interrupt exit
Ralf Baechlee01402b2005-07-14 15:57:16 +00002010 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002011 extern char except_vec_vi, except_vec_vi_lui;
2012 extern char except_vec_vi_ori, except_vec_vi_end;
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002013 extern char rollback_except_vec_vi;
Ralf Baechlef94d9a82013-05-21 17:30:36 +02002014 char *vec_start = using_rollback_handler() ?
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002015 &rollback_except_vec_vi : &except_vec_vi;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002016#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2017 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
2018 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
2019#else
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002020 const int lui_offset = &except_vec_vi_lui - vec_start;
2021 const int ori_offset = &except_vec_vi_ori - vec_start;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002022#endif
2023 const int handler_len = &except_vec_vi_end - vec_start;
Ralf Baechlee01402b2005-07-14 15:57:16 +00002024
2025 if (handler_len > VECTORSPACING) {
2026 /*
2027 * Sigh... panicing won't help as the console
2028 * is probably not configured :(
2029 */
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002030 panic("VECTORSPACING too small");
Ralf Baechlee01402b2005-07-14 15:57:16 +00002031 }
2032
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002033 set_handler(((unsigned long)b - ebase), vec_start,
2034#ifdef CONFIG_CPU_MICROMIPS
2035 (handler_len - 1));
2036#else
2037 handler_len);
2038#endif
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002039 h = (u16 *)(b + lui_offset);
2040 *h = (handler >> 16) & 0xffff;
2041 h = (u16 *)(b + ori_offset);
2042 *h = (handler & 0xffff);
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002043 local_flush_icache_range((unsigned long)b,
2044 (unsigned long)(b+handler_len));
Ralf Baechlee01402b2005-07-14 15:57:16 +00002045 }
2046 else {
2047 /*
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002048 * In other cases jump directly to the interrupt handler. It
2049 * is the handler's responsibility to save registers if required
2050 * (eg hi/lo) and return from the exception using "eret".
Ralf Baechlee01402b2005-07-14 15:57:16 +00002051 */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002052 u32 insn;
2053
2054 h = (u16 *)b;
2055 /* j handler */
2056#ifdef CONFIG_CPU_MICROMIPS
2057 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2058#else
2059 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2060#endif
2061 h[0] = (insn >> 16) & 0xffff;
2062 h[1] = insn & 0xffff;
2063 h[2] = 0;
2064 h[3] = 0;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002065 local_flush_icache_range((unsigned long)b,
2066 (unsigned long)(b+8));
Ralf Baechlee01402b2005-07-14 15:57:16 +00002067 }
2068
2069 return (void *)old_handler;
2070}
2071
Ralf Baechleef300e42007-05-06 18:31:18 +01002072void *set_vi_handler(int n, vi_handler_t addr)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002073{
Ralf Baechleff3eab22006-03-29 14:12:58 +01002074 return set_vi_srs_handler(n, addr, 0);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002075}
Ralf Baechlef41ae0b2006-06-05 17:24:46 +01002076
Linus Torvalds1da177e2005-04-16 15:20:36 -07002077extern void tlb_init(void);
2078
Ralf Baechle42f77542007-10-18 17:48:11 +01002079/*
2080 * Timer interrupt
2081 */
2082int cp0_compare_irq;
Ralf Baechle68b63522012-07-19 09:13:52 +02002083EXPORT_SYMBOL_GPL(cp0_compare_irq);
David VomLehn010c1082009-12-21 17:49:22 -08002084int cp0_compare_irq_shift;
Ralf Baechle42f77542007-10-18 17:48:11 +01002085
2086/*
2087 * Performance counter IRQ or -1 if shared with timer
2088 */
2089int cp0_perfcount_irq;
2090EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2091
James Hogan8f7ff022015-01-29 11:14:07 +00002092/*
2093 * Fast debug channel IRQ or -1 if not present
2094 */
2095int cp0_fdc_irq;
2096EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2097
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002098static int noulri;
Chris Dearmanbdc94eb2007-10-03 10:43:56 +01002099
2100static int __init ulri_disable(char *s)
2101{
2102 pr_info("Disabling ulri\n");
2103 noulri = 1;
2104
2105 return 1;
2106}
2107__setup("noulri", ulri_disable);
2108
James Hoganae4ce452014-03-04 10:20:43 +00002109/* configure STATUS register */
2110static void configure_status(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002111{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002112 /*
2113 * Disable coprocessors and select 32-bit or 64-bit addressing
2114 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2115 * flag that some firmware may have left set and the TS bit (for
2116 * IP27). Set XX for ISA IV code to work.
2117 */
James Hoganae4ce452014-03-04 10:20:43 +00002118 unsigned int status_set = ST0_CU0;
Ralf Baechle875d43e2005-09-03 15:56:16 -07002119#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07002120 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2121#endif
Deng-Cheng Zhuadb37892013-04-01 18:14:28 +00002122 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002123 status_set |= ST0_XX;
Chris Dearmanbbaf2382007-12-13 22:42:19 +00002124 if (cpu_has_dsp)
2125 status_set |= ST0_MX;
2126
Ralf Baechleb38c7392006-02-07 01:20:43 +00002127 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002128 status_set);
James Hoganae4ce452014-03-04 10:20:43 +00002129}
2130
James Hoganb937ff62016-06-15 19:29:53 +01002131unsigned int hwrena;
2132EXPORT_SYMBOL_GPL(hwrena);
2133
James Hoganae4ce452014-03-04 10:20:43 +00002134/* configure HWRENA register */
2135static void configure_hwrena(void)
2136{
James Hoganb937ff62016-06-15 19:29:53 +01002137 hwrena = cpu_hwrena_impl_bits;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002138
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00002139 if (cpu_has_mips_r2_r6)
James Hoganaff565a2016-06-15 19:29:52 +01002140 hwrena |= MIPS_HWRENA_CPUNUM |
2141 MIPS_HWRENA_SYNCISTEP |
2142 MIPS_HWRENA_CC |
2143 MIPS_HWRENA_CCRES;
Ralf Baechlea3692022007-07-10 17:33:02 +01002144
Kevin Cernekee18d693b2010-10-16 14:22:38 -07002145 if (!noulri && cpu_has_userlocal)
James Hoganaff565a2016-06-15 19:29:52 +01002146 hwrena |= MIPS_HWRENA_ULR;
Ralf Baechlea3692022007-07-10 17:33:02 +01002147
Kevin Cernekee18d693b2010-10-16 14:22:38 -07002148 if (hwrena)
2149 write_c0_hwrena(hwrena);
James Hoganae4ce452014-03-04 10:20:43 +00002150}
Ralf Baechlee01402b2005-07-14 15:57:16 +00002151
James Hoganae4ce452014-03-04 10:20:43 +00002152static void configure_exception_vector(void)
2153{
Paul Burtonde56d4c2019-04-30 22:53:31 +00002154 if (cpu_has_mips_r2_r6) {
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002155 unsigned long sr = set_c0_status(ST0_BEV);
Matt Redfearn4b22c692016-09-01 17:30:09 +01002156 /* If available, use WG to set top bits of EBASE */
2157 if (cpu_has_ebase_wg) {
2158#ifdef CONFIG_64BIT
2159 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2160#else
2161 write_c0_ebase(ebase | MIPS_EBASE_WG);
2162#endif
2163 }
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002164 write_c0_ebase(ebase);
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002165 write_c0_status(sr);
Paul Burtonde56d4c2019-04-30 22:53:31 +00002166 }
2167 if (cpu_has_veic || cpu_has_vint) {
Ralf Baechlee01402b2005-07-14 15:57:16 +00002168 /* Setting vector spacing enables EI/VI mode */
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002169 change_c0_intctl(0x3e0, VECTORSPACING);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002170 }
Ralf Baechled03d0a52005-08-17 13:44:26 +00002171 if (cpu_has_divec) {
2172 if (cpu_has_mipsmt) {
2173 unsigned int vpflags = dvpe();
2174 set_c0_cause(CAUSEF_IV);
2175 evpe(vpflags);
2176 } else
2177 set_c0_cause(CAUSEF_IV);
2178 }
James Hoganae4ce452014-03-04 10:20:43 +00002179}
2180
2181void per_cpu_trap_init(bool is_boot_cpu)
2182{
2183 unsigned int cpu = smp_processor_id();
James Hoganae4ce452014-03-04 10:20:43 +00002184
2185 configure_status();
2186 configure_hwrena();
2187
James Hoganae4ce452014-03-04 10:20:43 +00002188 configure_exception_vector();
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002189
2190 /*
2191 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2192 *
2193 * o read IntCtl.IPTI to determine the timer interrupt
2194 * o read IntCtl.IPPCI to determine the performance counter interrupt
James Hogan8f7ff022015-01-29 11:14:07 +00002195 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002196 */
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00002197 if (cpu_has_mips_r2_r6) {
David VomLehn010c1082009-12-21 17:49:22 -08002198 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2199 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2200 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
James Hogan8f7ff022015-01-29 11:14:07 +00002201 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2202 if (!cp0_fdc_irq)
2203 cp0_fdc_irq = -1;
2204
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002205 } else {
2206 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
Ralf Baechlec6a4ebb2012-07-06 23:56:00 +02002207 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
Chris Dearmanc3e838a2007-06-21 12:59:57 +01002208 cp0_perfcount_irq = -1;
James Hogan8f7ff022015-01-29 11:14:07 +00002209 cp0_fdc_irq = -1;
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002210 }
2211
Paul Burtonc8790d62019-02-02 01:43:28 +00002212 if (cpu_has_mmid)
2213 cpu_data[cpu].asid_cache = 0;
2214 else if (!cpu_data[cpu].asid_cache)
Paul Burton4edf00a2016-05-06 14:36:23 +01002215 cpu_data[cpu].asid_cache = asid_first_version(cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002216
Vegard Nossumf1f10072017-02-27 14:30:07 -08002217 mmgrab(&init_mm);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002218 current->active_mm = &init_mm;
2219 BUG_ON(current->mm);
2220 enter_lazy_tlb(&init_mm, current);
2221
Markos Chandras761b4492015-06-24 09:29:20 +01002222 /* Boot CPU's cache setup in setup_arch(). */
2223 if (!is_boot_cpu)
2224 cpu_cache_init();
2225 tlb_init();
David Daney3d8bfdd2010-12-21 14:19:11 -08002226 TLBMISS_HANDLER_SETUP();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002227}
2228
Ralf Baechlee01402b2005-07-14 15:57:16 +00002229/* Install CPU exception handler */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002230void set_handler(unsigned long offset, void *addr, unsigned long size)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002231{
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002232#ifdef CONFIG_CPU_MICROMIPS
2233 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2234#else
Ralf Baechlee01402b2005-07-14 15:57:16 +00002235 memcpy((void *)(ebase + offset), addr, size);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002236#endif
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002237 local_flush_icache_range(ebase + offset, ebase + offset + size);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002238}
2239
Kees Cook06324662017-05-08 15:59:05 -07002240static const char panic_null_cerr[] =
2241 "Trying to set NULL cache error exception handler\n";
Ralf Baechle641e97f2007-10-11 23:46:05 +01002242
Ralf Baechle42fe7ee2009-01-28 18:48:23 +00002243/*
2244 * Install uncached CPU exception handler.
2245 * This is suitable only for the cache error exception which is the only
2246 * exception handler that is being run uncached.
2247 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002248void set_uncached_handler(unsigned long offset, void *addr,
Ralf Baechle234fcd12008-03-08 09:56:28 +00002249 unsigned long size)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002250{
Sebastian Andrzej Siewior4f81b012010-04-27 22:53:30 +02002251 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002252
Ralf Baechle641e97f2007-10-11 23:46:05 +01002253 if (!addr)
2254 panic(panic_null_cerr);
2255
Ralf Baechlee01402b2005-07-14 15:57:16 +00002256 memcpy((void *)(uncached_ebase + offset), addr, size);
2257}
2258
Atsushi Nemoto5b104962006-09-11 17:50:29 +09002259static int __initdata rdhwr_noopt;
2260static int __init set_rdhwr_noopt(char *str)
2261{
2262 rdhwr_noopt = 1;
2263 return 1;
2264}
2265
2266__setup("rdhwr_noopt", set_rdhwr_noopt);
2267
Linus Torvalds1da177e2005-04-16 15:20:36 -07002268void __init trap_init(void)
2269{
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002270 extern char except_vec3_generic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002271 extern char except_vec4;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002272 extern char except_vec3_r4000;
Paul Burton172dcd92019-04-30 22:53:30 +00002273 unsigned long i, vec_size;
2274 phys_addr_t ebase_pa;
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002275
2276 check_wait();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002277
Paul Burton172dcd92019-04-30 22:53:30 +00002278 if (!cpu_has_mips_r2_r6) {
2279 ebase = CAC_BASE;
2280 ebase_pa = virt_to_phys((void *)ebase);
2281 vec_size = 0x400;
James Hoganc195e072016-09-01 17:30:08 +01002282
Paul Burton172dcd92019-04-30 22:53:30 +00002283 memblock_reserve(ebase_pa, vec_size);
2284 } else {
2285 if (cpu_has_veic || cpu_has_vint)
2286 vec_size = 0x200 + VECTORSPACING*64;
2287 else
2288 vec_size = PAGE_SIZE;
2289
2290 ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
Paul Burtonf995adb2019-04-30 22:53:30 +00002291 if (!ebase_pa)
Mike Rapoport8a7f97b2019-03-11 23:30:31 -07002292 panic("%s: Failed to allocate %lu bytes align=0x%x\n",
Paul Burton172dcd92019-04-30 22:53:30 +00002293 __func__, vec_size, 1 << fls(vec_size));
James Hoganc195e072016-09-01 17:30:08 +01002294
2295 /*
2296 * Try to ensure ebase resides in KSeg0 if possible.
2297 *
2298 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2299 * hitting a poorly defined exception base for Cache Errors.
2300 * The allocation is likely to be in the low 512MB of physical,
2301 * in which case we should be able to convert to KSeg0.
2302 *
2303 * EVA is special though as it allows segments to be rearranged
2304 * and to become uncached during cache error handling.
2305 */
James Hoganc195e072016-09-01 17:30:08 +01002306 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2307 ebase = CKSEG0ADDR(ebase_pa);
Paul Burtonf995adb2019-04-30 22:53:30 +00002308 else
2309 ebase = (unsigned long)phys_to_virt(ebase_pa);
David Daney566f74f2008-10-23 17:56:35 -07002310 }
Ralf Baechlee01402b2005-07-14 15:57:16 +00002311
Steven J. Hillc6213c62013-06-05 21:25:17 +00002312 if (cpu_has_mmips) {
2313 unsigned int config3 = read_c0_config3();
2314
2315 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2316 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2317 else
2318 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2319 }
2320
Kevin Cernekee6fb97ef2011-11-16 01:25:45 +00002321 if (board_ebase_setup)
2322 board_ebase_setup();
David Daney6650df32012-05-15 00:04:50 -07002323 per_cpu_trap_init(true);
Huacai Chen25517ed2018-11-10 11:50:14 +08002324 memblock_set_bottom_up(false);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002325
2326 /*
2327 * Copy the generic exception handlers to their final destination.
Adam Buchbinder92a76f62016-02-25 00:44:58 -08002328 * This will be overridden later as suitable for a particular
Linus Torvalds1da177e2005-04-16 15:20:36 -07002329 * configuration.
2330 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002331 set_handler(0x180, &except_vec3_generic, 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002332
2333 /*
2334 * Setup default vectors
2335 */
2336 for (i = 0; i <= 31; i++)
2337 set_except_vector(i, handle_reserved);
2338
2339 /*
2340 * Copy the EJTAG debug exception vector handler code to it's final
2341 * destination.
2342 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002343 if (cpu_has_ejtag && board_ejtag_handler_setup)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002344 board_ejtag_handler_setup();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002345
2346 /*
2347 * Only some CPUs have the watch exceptions.
2348 */
2349 if (cpu_has_watch)
James Hogan1b505de2015-12-16 23:49:35 +00002350 set_except_vector(EXCCODE_WATCH, handle_watch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002351
2352 /*
Ralf Baechlee01402b2005-07-14 15:57:16 +00002353 * Initialise interrupt handlers
Linus Torvalds1da177e2005-04-16 15:20:36 -07002354 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002355 if (cpu_has_veic || cpu_has_vint) {
2356 int nvec = cpu_has_veic ? 64 : 8;
2357 for (i = 0; i < nvec; i++)
Ralf Baechleff3eab22006-03-29 14:12:58 +01002358 set_vi_handler(i, NULL);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002359 }
2360 else if (cpu_has_divec)
2361 set_handler(0x200, &except_vec4, 0x8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002362
2363 /*
2364 * Some CPUs can enable/disable for cache parity detection, but does
2365 * it different ways.
2366 */
2367 parity_protection_init();
2368
2369 /*
2370 * The Data Bus Errors / Instruction Bus Errors are signaled
2371 * by external hardware. Therefore these two exceptions
2372 * may have board specific handlers.
2373 */
2374 if (board_be_init)
2375 board_be_init();
2376
James Hogan1b505de2015-12-16 23:49:35 +00002377 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2378 rollback_handle_int : handle_int);
2379 set_except_vector(EXCCODE_MOD, handle_tlbm);
2380 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2381 set_except_vector(EXCCODE_TLBS, handle_tlbs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002382
James Hogan1b505de2015-12-16 23:49:35 +00002383 set_except_vector(EXCCODE_ADEL, handle_adel);
2384 set_except_vector(EXCCODE_ADES, handle_ades);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002385
James Hogan1b505de2015-12-16 23:49:35 +00002386 set_except_vector(EXCCODE_IBE, handle_ibe);
2387 set_except_vector(EXCCODE_DBE, handle_dbe);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002388
James Hogan1b505de2015-12-16 23:49:35 +00002389 set_except_vector(EXCCODE_SYS, handle_sys);
2390 set_except_vector(EXCCODE_BP, handle_bp);
Huacai Chen5a341332017-03-16 21:00:26 +08002391
2392 if (rdhwr_noopt)
2393 set_except_vector(EXCCODE_RI, handle_ri);
2394 else {
2395 if (cpu_has_vtag_icache)
2396 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2397 else if (current_cpu_type() == CPU_LOONGSON3)
2398 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2399 else
2400 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2401 }
2402
James Hogan1b505de2015-12-16 23:49:35 +00002403 set_except_vector(EXCCODE_CPU, handle_cpu);
2404 set_except_vector(EXCCODE_OV, handle_ov);
2405 set_except_vector(EXCCODE_TR, handle_tr);
2406 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002407
Ralf Baechlee01402b2005-07-14 15:57:16 +00002408 if (board_nmi_handler_setup)
2409 board_nmi_handler_setup();
2410
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002411 if (cpu_has_fpu && !cpu_has_nofpuex)
James Hogan1b505de2015-12-16 23:49:35 +00002412 set_except_vector(EXCCODE_FPE, handle_fpe);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002413
James Hogan1b505de2015-12-16 23:49:35 +00002414 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
Leonid Yegoshin5890f702014-07-15 14:09:56 +01002415
2416 if (cpu_has_rixiex) {
James Hogan1b505de2015-12-16 23:49:35 +00002417 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2418 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
Leonid Yegoshin5890f702014-07-15 14:09:56 +01002419 }
2420
James Hogan1b505de2015-12-16 23:49:35 +00002421 set_except_vector(EXCCODE_MSADIS, handle_msa);
2422 set_except_vector(EXCCODE_MDMX, handle_mdmx);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002423
2424 if (cpu_has_mcheck)
James Hogan1b505de2015-12-16 23:49:35 +00002425 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002426
Ralf Baechle340ee4b2005-08-17 17:44:08 +00002427 if (cpu_has_mipsmt)
James Hogan1b505de2015-12-16 23:49:35 +00002428 set_except_vector(EXCCODE_THREAD, handle_mt);
Ralf Baechle340ee4b2005-08-17 17:44:08 +00002429
James Hogan1b505de2015-12-16 23:49:35 +00002430 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002431
David Daneyfcbf1df2012-05-15 00:04:46 -07002432 if (board_cache_error_setup)
2433 board_cache_error_setup();
2434
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002435 if (cpu_has_vce)
2436 /* Special exception: R4[04]00 uses also the divec space. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002437 set_handler(0x180, &except_vec3_r4000, 0x100);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002438 else if (cpu_has_4kex)
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002439 set_handler(0x180, &except_vec3_generic, 0x80);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002440 else
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002441 set_handler(0x080, &except_vec3_generic, 0x80);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002442
Paul Burton783454e2019-04-30 22:53:31 +00002443 local_flush_icache_range(ebase, ebase + vec_size);
Thomas Bogendoerfer05106172008-08-04 19:44:34 +02002444
2445 sort_extable(__start___dbe_table, __stop___dbe_table);
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00002446
Ralf Baechle4483b152010-08-05 13:25:59 +01002447 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002448}
James Hoganae4ce452014-03-04 10:20:43 +00002449
2450static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2451 void *v)
2452{
2453 switch (cmd) {
2454 case CPU_PM_ENTER_FAILED:
2455 case CPU_PM_EXIT:
2456 configure_status();
2457 configure_hwrena();
2458 configure_exception_vector();
2459
2460 /* Restore register with CPU number for TLB handlers */
2461 TLBMISS_HANDLER_RESTORE();
2462
2463 break;
2464 }
2465
2466 return NOTIFY_OK;
2467}
2468
2469static struct notifier_block trap_pm_notifier_block = {
2470 .notifier_call = trap_pm_notifier,
2471};
2472
2473static int __init trap_pm_init(void)
2474{
2475 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2476}
2477arch_initcall(trap_pm_init);