blob: 49c6df20672a9dca6575cd0771bf72867ddfd869 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
Ralf Baechle36ccf1c2006-02-14 21:04:54 +00006 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +010011 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
Steven J. Hill2a0b24f2013-03-25 12:15:55 -050012 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
Markos Chandrasb08a9c92013-12-04 16:20:08 +000013 * Copyright (C) 2014, Imagination Technologies Ltd.
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 */
Maciej W. Rozyckied2d72c2015-04-03 23:27:06 +010015#include <linux/bitops.h>
Ralf Baechle8e8a52e2007-05-31 14:00:19 +010016#include <linux/bug.h>
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +010017#include <linux/compiler.h>
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +020018#include <linux/context_tracking.h>
James Hoganae4ce452014-03-04 10:20:43 +000019#include <linux/cpu_pm.h>
Ralf Baechle7aa1c8f2012-10-11 18:14:58 +020020#include <linux/kexec.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/init.h>
Nathan Lynch8742cd22011-09-30 13:49:35 -050022#include <linux/kernel.h>
Paul Gortmakerf9ded562012-02-28 19:24:46 -050023#include <linux/module.h>
Paul Gortmaker9f3b8082016-08-15 19:11:52 -040024#include <linux/extable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <linux/sched.h>
27#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/spinlock.h>
29#include <linux/kallsyms.h>
Ralf Baechlee01402b2005-07-14 15:57:16 +000030#include <linux/bootmem.h>
Maxime Bizond4fd1982006-07-20 18:52:02 +020031#include <linux/interrupt.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010032#include <linux/ptrace.h>
Jason Wessel88547002008-07-29 15:58:53 -050033#include <linux/kgdb.h>
34#include <linux/kdebug.h>
David Daneyc1bf2072010-08-03 11:22:20 -070035#include <linux/kprobes.h>
Ralf Baechle69f3a7d2009-11-24 01:24:58 +000036#include <linux/notifier.h>
Jason Wessel5dd11d52010-05-20 21:04:26 -050037#include <linux/kdb.h>
David Howellsca4d3e672010-10-07 14:08:54 +010038#include <linux/irq.h>
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +080039#include <linux/perf_event.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040
Paul Burtona13c9962015-09-22 10:15:22 -070041#include <asm/addrspace.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <asm/bootinfo.h>
43#include <asm/branch.h>
44#include <asm/break.h>
Ralf Baechle69f3a7d2009-11-24 01:24:58 +000045#include <asm/cop2.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <asm/cpu.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020047#include <asm/cpu-type.h>
Ralf Baechlee50c0a82005-05-31 11:49:19 +000048#include <asm/dsp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include <asm/fpu.h>
Ralf Baechleba3049e2008-10-28 17:38:42 +000050#include <asm/fpu_emulator.h>
Ralf Baechlebdc92d742013-05-21 16:59:19 +020051#include <asm/idle.h>
Paul Burtondabdc182016-10-05 18:18:17 +010052#include <asm/mips-cm.h>
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +000053#include <asm/mips-r2-to-r6-emul.h>
Paul Burton35e6de32016-10-17 16:01:07 +010054#include <asm/mips-cm.h>
Ralf Baechle340ee4b2005-08-17 17:44:08 +000055#include <asm/mipsregs.h>
56#include <asm/mipsmtregs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#include <asm/module.h>
Paul Burton1db1af82014-01-27 15:23:11 +000058#include <asm/msa.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070059#include <asm/pgtable.h>
60#include <asm/ptrace.h>
61#include <asm/sections.h>
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +000062#include <asm/siginfo.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070063#include <asm/tlbdebug.h>
64#include <asm/traps.h>
Linus Torvalds7c0f6ba2016-12-24 11:46:01 -080065#include <linux/uaccess.h>
David Daneyb67b2b72008-09-23 00:08:45 -070066#include <asm/watch.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070067#include <asm/mmu_context.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070068#include <asm/types.h>
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +090069#include <asm/stacktrace.h>
Florian Fainelli92bbe1b2010-01-28 15:22:37 +010070#include <asm/uasm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090072extern void check_wait(void);
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090073extern asmlinkage void rollback_handle_int(void);
Ralf Baechlee4ac58a2006-04-03 17:56:36 +010074extern asmlinkage void handle_int(void);
Ralf Baechle86a17082013-02-08 01:21:34 +010075extern u32 handle_tlbl[];
76extern u32 handle_tlbs[];
77extern u32 handle_tlbm[];
Linus Torvalds1da177e2005-04-16 15:20:36 -070078extern asmlinkage void handle_adel(void);
79extern asmlinkage void handle_ades(void);
80extern asmlinkage void handle_ibe(void);
81extern asmlinkage void handle_dbe(void);
82extern asmlinkage void handle_sys(void);
83extern asmlinkage void handle_bp(void);
84extern asmlinkage void handle_ri(void);
Atsushi Nemoto5b104962006-09-11 17:50:29 +090085extern asmlinkage void handle_ri_rdhwr_vivt(void);
86extern asmlinkage void handle_ri_rdhwr(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070087extern asmlinkage void handle_cpu(void);
88extern asmlinkage void handle_ov(void);
89extern asmlinkage void handle_tr(void);
Paul Burton2bcb3fb2014-01-27 15:23:12 +000090extern asmlinkage void handle_msa_fpe(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070091extern asmlinkage void handle_fpe(void);
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +000092extern asmlinkage void handle_ftlb(void);
Paul Burton1db1af82014-01-27 15:23:11 +000093extern asmlinkage void handle_msa(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070094extern asmlinkage void handle_mdmx(void);
95extern asmlinkage void handle_watch(void);
Ralf Baechle340ee4b2005-08-17 17:44:08 +000096extern asmlinkage void handle_mt(void);
Ralf Baechlee50c0a82005-05-31 11:49:19 +000097extern asmlinkage void handle_dsp(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070098extern asmlinkage void handle_mcheck(void);
99extern asmlinkage void handle_reserved(void);
Leonid Yegoshin5890f702014-07-15 14:09:56 +0100100extern void tlb_do_page_fault_0(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102void (*board_be_init)(void);
103int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
Ralf Baechlee01402b2005-07-14 15:57:16 +0000104void (*board_nmi_handler_setup)(void);
105void (*board_ejtag_handler_setup)(void);
106void (*board_bind_eic_interrupt)(int irq, int regset);
Kevin Cernekee6fb97ef2011-11-16 01:25:45 +0000107void (*board_ebase_setup)(void);
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000108void(*board_cache_error_setup)(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200110static void show_raw_backtrace(unsigned long reg29)
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900111{
Ralf Baechle39b8d522008-04-28 17:14:26 +0100112 unsigned long *sp = (unsigned long *)(reg29 & ~3);
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900113 unsigned long addr;
114
115 printk("Call Trace:");
116#ifdef CONFIG_KALLSYMS
117 printk("\n");
118#endif
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200119 while (!kstack_end(sp)) {
120 unsigned long __user *p =
121 (unsigned long __user *)(unsigned long)sp++;
122 if (__get_user(addr, p)) {
123 printk(" (Bad stack address)");
124 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100125 }
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200126 if (__kernel_text_address(addr))
127 print_ip_sym(addr);
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900128 }
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200129 printk("\n");
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900130}
131
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900132#ifdef CONFIG_KALLSYMS
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +0900133int raw_show_trace;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900134static int __init set_raw_show_trace(char *str)
135{
136 raw_show_trace = 1;
137 return 1;
138}
139__setup("raw_show_trace", set_raw_show_trace);
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +0900140#endif
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200141
Ralf Baechleeae23f22007-10-14 23:27:21 +0100142static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900143{
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200144 unsigned long sp = regs->regs[29];
145 unsigned long ra = regs->regs[31];
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900146 unsigned long pc = regs->cp0_epc;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900147
Vincent Wene909be82012-07-19 09:11:16 +0200148 if (!task)
149 task = current;
150
James Hogan81a76d72015-12-04 22:25:02 +0000151 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200152 show_raw_backtrace(sp);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900153 return;
154 }
155 printk("Call Trace:\n");
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200156 do {
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200157 print_ip_sym(pc);
Atsushi Nemoto19246002006-09-29 18:02:51 +0900158 pc = unwind_stack(task, &sp, pc, &ra);
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200159 } while (pc);
Matt Redfearnbcf084d2016-10-19 14:33:20 +0100160 pr_cont("\n");
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900161}
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900162
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163/*
164 * This routine abuses get_user()/put_user() to reference pointers
165 * with at least a bit of error checking ...
166 */
Ralf Baechleeae23f22007-10-14 23:27:21 +0100167static void show_stacktrace(struct task_struct *task,
168 const struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169{
170 const int field = 2 * sizeof(unsigned long);
171 long stackdata;
172 int i;
Atsushi Nemoto5e0373b2007-07-13 23:02:42 +0900173 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174
175 printk("Stack :");
176 i = 0;
177 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100178 if (i && ((i % (64 / field)) == 0)) {
179 pr_cont("\n");
180 printk(" ");
181 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 if (i > 39) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100183 pr_cont(" ...");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 break;
185 }
186
187 if (__get_user(stackdata, sp++)) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100188 pr_cont(" (Bad stack address)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 break;
190 }
191
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100192 pr_cont(" %0*lx", field, stackdata);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 i++;
194 }
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100195 pr_cont("\n");
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200196 show_backtrace(task, regs);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900197}
198
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900199void show_stack(struct task_struct *task, unsigned long *sp)
200{
201 struct pt_regs regs;
James Hogan1e778632015-07-27 13:50:22 +0100202 mm_segment_t old_fs = get_fs();
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900203 if (sp) {
204 regs.regs[29] = (unsigned long)sp;
205 regs.regs[31] = 0;
206 regs.cp0_epc = 0;
207 } else {
208 if (task && task != current) {
209 regs.regs[29] = task->thread.reg29;
210 regs.regs[31] = 0;
211 regs.cp0_epc = task->thread.reg31;
Jason Wessel5dd11d52010-05-20 21:04:26 -0500212#ifdef CONFIG_KGDB_KDB
213 } else if (atomic_read(&kgdb_active) != -1 &&
214 kdb_current_regs) {
215 memcpy(&regs, kdb_current_regs, sizeof(regs));
216#endif /* CONFIG_KGDB_KDB */
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900217 } else {
218 prepare_frametrace(&regs);
219 }
220 }
James Hogan1e778632015-07-27 13:50:22 +0100221 /*
222 * show_stack() deals exclusively with kernel mode, so be sure to access
223 * the stack in the kernel (not user) address space.
224 */
225 set_fs(KERNEL_DS);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900226 show_stacktrace(task, &regs);
James Hogan1e778632015-07-27 13:50:22 +0100227 set_fs(old_fs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228}
229
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +0900230static void show_code(unsigned int __user *pc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231{
232 long i;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100233 unsigned short __user *pc16 = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234
Matt Redfearn41000c52016-10-19 14:33:22 +0100235 printk("Code:");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
Ralf Baechle39b8d522008-04-28 17:14:26 +0100237 if ((unsigned long)pc & 1)
238 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 for(i = -3 ; i < 6 ; i++) {
240 unsigned int insn;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100241 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
Matt Redfearn41000c52016-10-19 14:33:22 +0100242 pr_cont(" (Bad address in epc)\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243 break;
244 }
Matt Redfearn41000c52016-10-19 14:33:22 +0100245 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 }
Matt Redfearn41000c52016-10-19 14:33:22 +0100247 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248}
249
Ralf Baechleeae23f22007-10-14 23:27:21 +0100250static void __show_regs(const struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251{
252 const int field = 2 * sizeof(unsigned long);
253 unsigned int cause = regs->cp0_cause;
Petri Gynther37dd3812015-05-08 15:10:10 -0700254 unsigned int exccode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 int i;
256
Tejun Heoa43cb952013-04-30 15:27:17 -0700257 show_regs_print_info(KERN_DEFAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258
259 /*
260 * Saved main processor registers
261 */
262 for (i = 0; i < 32; ) {
263 if ((i % 4) == 0)
264 printk("$%2d :", i);
265 if (i == 0)
Paul Burton752f5492016-10-19 14:33:23 +0100266 pr_cont(" %0*lx", field, 0UL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 else if (i == 26 || i == 27)
Paul Burton752f5492016-10-19 14:33:23 +0100268 pr_cont(" %*s", field, "");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 else
Paul Burton752f5492016-10-19 14:33:23 +0100270 pr_cont(" %0*lx", field, regs->regs[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271
272 i++;
273 if ((i % 4) == 0)
Paul Burton752f5492016-10-19 14:33:23 +0100274 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 }
276
Franck Bui-Huu9693a852007-02-02 17:41:47 +0100277#ifdef CONFIG_CPU_HAS_SMARTMIPS
278 printk("Acx : %0*lx\n", field, regs->acx);
279#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 printk("Hi : %0*lx\n", field, regs->hi);
281 printk("Lo : %0*lx\n", field, regs->lo);
282
283 /*
284 * Saved cp0 registers
285 */
Ralf Baechleb012cff2008-07-15 18:44:33 +0100286 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
287 (void *) regs->cp0_epc);
Ralf Baechleb012cff2008-07-15 18:44:33 +0100288 printk("ra : %0*lx %pS\n", field, regs->regs[31],
289 (void *) regs->regs[31]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290
Ralf Baechle70342282013-01-22 12:59:30 +0100291 printk("Status: %08x ", (uint32_t) regs->cp0_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
Ralf Baechle1990e542013-06-26 17:06:34 +0200293 if (cpu_has_3kex) {
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000294 if (regs->cp0_status & ST0_KUO)
Paul Burton752f5492016-10-19 14:33:23 +0100295 pr_cont("KUo ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000296 if (regs->cp0_status & ST0_IEO)
Paul Burton752f5492016-10-19 14:33:23 +0100297 pr_cont("IEo ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000298 if (regs->cp0_status & ST0_KUP)
Paul Burton752f5492016-10-19 14:33:23 +0100299 pr_cont("KUp ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000300 if (regs->cp0_status & ST0_IEP)
Paul Burton752f5492016-10-19 14:33:23 +0100301 pr_cont("IEp ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000302 if (regs->cp0_status & ST0_KUC)
Paul Burton752f5492016-10-19 14:33:23 +0100303 pr_cont("KUc ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000304 if (regs->cp0_status & ST0_IEC)
Paul Burton752f5492016-10-19 14:33:23 +0100305 pr_cont("IEc ");
Ralf Baechle1990e542013-06-26 17:06:34 +0200306 } else if (cpu_has_4kex) {
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000307 if (regs->cp0_status & ST0_KX)
Paul Burton752f5492016-10-19 14:33:23 +0100308 pr_cont("KX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000309 if (regs->cp0_status & ST0_SX)
Paul Burton752f5492016-10-19 14:33:23 +0100310 pr_cont("SX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000311 if (regs->cp0_status & ST0_UX)
Paul Burton752f5492016-10-19 14:33:23 +0100312 pr_cont("UX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000313 switch (regs->cp0_status & ST0_KSU) {
314 case KSU_USER:
Paul Burton752f5492016-10-19 14:33:23 +0100315 pr_cont("USER ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000316 break;
317 case KSU_SUPERVISOR:
Paul Burton752f5492016-10-19 14:33:23 +0100318 pr_cont("SUPERVISOR ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000319 break;
320 case KSU_KERNEL:
Paul Burton752f5492016-10-19 14:33:23 +0100321 pr_cont("KERNEL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000322 break;
323 default:
Paul Burton752f5492016-10-19 14:33:23 +0100324 pr_cont("BAD_MODE ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000325 break;
326 }
327 if (regs->cp0_status & ST0_ERL)
Paul Burton752f5492016-10-19 14:33:23 +0100328 pr_cont("ERL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000329 if (regs->cp0_status & ST0_EXL)
Paul Burton752f5492016-10-19 14:33:23 +0100330 pr_cont("EXL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000331 if (regs->cp0_status & ST0_IE)
Paul Burton752f5492016-10-19 14:33:23 +0100332 pr_cont("IE ");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 }
Paul Burton752f5492016-10-19 14:33:23 +0100334 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335
Petri Gynther37dd3812015-05-08 15:10:10 -0700336 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
337 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
Petri Gynther37dd3812015-05-08 15:10:10 -0700339 if (1 <= exccode && exccode <= 5)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
341
Ralf Baechle9966db252007-10-11 23:46:17 +0100342 printk("PrId : %08x (%s)\n", read_c0_prid(),
343 cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344}
345
Ralf Baechleeae23f22007-10-14 23:27:21 +0100346/*
347 * FIXME: really the generic show_regs should take a const pointer argument.
348 */
349void show_regs(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350{
Ralf Baechleeae23f22007-10-14 23:27:21 +0100351 __show_regs((struct pt_regs *)regs);
352}
353
David Daneyc1bf2072010-08-03 11:22:20 -0700354void show_registers(struct pt_regs *regs)
Ralf Baechleeae23f22007-10-14 23:27:21 +0100355{
Ralf Baechle39b8d522008-04-28 17:14:26 +0100356 const int field = 2 * sizeof(unsigned long);
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100357 mm_segment_t old_fs = get_fs();
Ralf Baechle39b8d522008-04-28 17:14:26 +0100358
Ralf Baechleeae23f22007-10-14 23:27:21 +0100359 __show_regs(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 print_modules();
Ralf Baechle39b8d522008-04-28 17:14:26 +0100361 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
362 current->comm, current->pid, current_thread_info(), current,
363 field, current_thread_info()->tp_value);
364 if (cpu_has_userlocal) {
365 unsigned long tls;
366
367 tls = read_c0_userlocal();
368 if (tls != current_thread_info()->tp_value)
369 printk("*HwTLS: %0*lx\n", field, tls);
370 }
371
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100372 if (!user_mode(regs))
373 /* Necessary for getting the correct stack content */
374 set_fs(KERNEL_DS);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900375 show_stacktrace(current, regs);
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +0900376 show_code((unsigned int __user *) regs->cp0_epc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 printk("\n");
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100378 set_fs(old_fs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379}
380
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000381static DEFINE_RAW_SPINLOCK(die_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382
David Daney70dc6f02010-08-03 15:44:43 -0700383void __noreturn die(const char *str, struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384{
385 static int die_counter;
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400386 int sig = SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387
Nathan Lynch8742cd22011-09-30 13:49:35 -0500388 oops_enter();
389
Ralf Baechlee3b28832015-07-28 20:37:43 +0200390 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200391 SIGSEGV) == NOTIFY_STOP)
Ralf Baechle10423c92011-05-13 10:33:28 +0100392 sig = 0;
Jason Wessel5dd11d52010-05-20 21:04:26 -0500393
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 console_verbose();
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000395 raw_spin_lock_irq(&die_lock);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100396 bust_spinlocks(1);
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400397
Ralf Baechle178086c2005-10-13 17:07:54 +0100398 printk("%s[#%d]:\n", str, ++die_counter);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 show_registers(regs);
Rusty Russell373d4d02013-01-21 17:17:39 +1030400 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000401 raw_spin_unlock_irq(&die_lock);
Maxime Bizond4fd1982006-07-20 18:52:02 +0200402
Nathan Lynch8742cd22011-09-30 13:49:35 -0500403 oops_exit();
404
Maxime Bizond4fd1982006-07-20 18:52:02 +0200405 if (in_interrupt())
406 panic("Fatal exception in interrupt");
407
Aaro Koskinen99a7a232016-03-09 22:08:42 +0200408 if (panic_on_oops)
Maxime Bizond4fd1982006-07-20 18:52:02 +0200409 panic("Fatal exception");
Maxime Bizond4fd1982006-07-20 18:52:02 +0200410
Ralf Baechle7aa1c8f2012-10-11 18:14:58 +0200411 if (regs && kexec_should_crash(current))
412 crash_kexec(regs);
413
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400414 do_exit(sig);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415}
416
Thomas Bogendoerfer05106172008-08-04 19:44:34 +0200417extern struct exception_table_entry __start___dbe_table[];
418extern struct exception_table_entry __stop___dbe_table[];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419
Ralf Baechleb6dcec92007-02-18 15:57:09 +0000420__asm__(
421" .section __dbe_table, \"a\"\n"
422" .previous \n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423
424/* Given an address, look for it in the exception tables. */
425static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
426{
427 const struct exception_table_entry *e;
428
429 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
430 if (!e)
431 e = search_module_dbetables(addr);
432 return e;
433}
434
435asmlinkage void do_be(struct pt_regs *regs)
436{
437 const int field = 2 * sizeof(unsigned long);
438 const struct exception_table_entry *fixup = NULL;
439 int data = regs->cp0_cause & 4;
440 int action = MIPS_BE_FATAL;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200441 enum ctx_state prev_state;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200443 prev_state = exception_enter();
Ralf Baechle70342282013-01-22 12:59:30 +0100444 /* XXX For now. Fixme, this searches the wrong table ... */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 if (data && !user_mode(regs))
446 fixup = search_dbe_tables(exception_epc(regs));
447
448 if (fixup)
449 action = MIPS_BE_FIXUP;
450
451 if (board_be_handler)
Atsushi Nemoto28fc5822007-07-13 01:49:49 +0900452 action = board_be_handler(regs, fixup != NULL);
Paul Burtondabdc182016-10-05 18:18:17 +0100453 else
454 mips_cm_error_report();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455
456 switch (action) {
457 case MIPS_BE_DISCARD:
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200458 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 case MIPS_BE_FIXUP:
460 if (fixup) {
461 regs->cp0_epc = fixup->nextinsn;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200462 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463 }
464 break;
465 default:
466 break;
467 }
468
469 /*
470 * Assume it would be too dangerous to continue ...
471 */
472 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
473 data ? "Data" : "Instruction",
474 field, regs->cp0_epc, field, regs->regs[31]);
Ralf Baechlee3b28832015-07-28 20:37:43 +0200475 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200476 SIGBUS) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200477 goto out;
Jason Wessel88547002008-07-29 15:58:53 -0500478
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 die_if_kernel("Oops", regs);
480 force_sig(SIGBUS, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200481
482out:
483 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484}
485
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486/*
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100487 * ll/sc, rdhwr, sync emulation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 */
489
490#define OPCODE 0xfc000000
491#define BASE 0x03e00000
492#define RT 0x001f0000
493#define OFFSET 0x0000ffff
494#define LL 0xc0000000
495#define SC 0xe0000000
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100496#define SPEC0 0x00000000
Ralf Baechle3c370262005-04-13 17:43:59 +0000497#define SPEC3 0x7c000000
498#define RD 0x0000f800
499#define FUNC 0x0000003f
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100500#define SYNC 0x0000000f
Ralf Baechle3c370262005-04-13 17:43:59 +0000501#define RDHWR 0x0000003b
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500503/* microMIPS definitions */
504#define MM_POOL32A_FUNC 0xfc00ffff
505#define MM_RDHWR 0x00006b3c
506#define MM_RS 0x001f0000
507#define MM_RT 0x03e00000
508
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509/*
510 * The ll_bit is cleared by r*_switch.S
511 */
512
Ralf Baechlef1e39a42009-09-17 02:25:05 +0200513unsigned int ll_bit;
514struct task_struct *ll_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100516static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517{
Ralf Baechlefe00f942005-03-01 19:22:29 +0000518 unsigned long value, __user *vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 long offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520
521 /*
522 * analyse the ll instruction that just caused a ri exception
523 * and put the referenced address to addr.
524 */
525
526 /* sign extend offset */
527 offset = opcode & OFFSET;
528 offset <<= 16;
529 offset >>= 16;
530
Ralf Baechlefe00f942005-03-01 19:22:29 +0000531 vaddr = (unsigned long __user *)
Steven J. Hillb9688312013-01-12 23:29:27 +0000532 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100534 if ((unsigned long)vaddr & 3)
535 return SIGBUS;
536 if (get_user(value, vaddr))
537 return SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
539 preempt_disable();
540
541 if (ll_task == NULL || ll_task == current) {
542 ll_bit = 1;
543 } else {
544 ll_bit = 0;
545 }
546 ll_task = current;
547
548 preempt_enable();
549
550 regs->regs[(opcode & RT) >> 16] = value;
551
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100552 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553}
554
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100555static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556{
Ralf Baechlefe00f942005-03-01 19:22:29 +0000557 unsigned long __user *vaddr;
558 unsigned long reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 long offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560
561 /*
562 * analyse the sc instruction that just caused a ri exception
563 * and put the referenced address to addr.
564 */
565
566 /* sign extend offset */
567 offset = opcode & OFFSET;
568 offset <<= 16;
569 offset >>= 16;
570
Ralf Baechlefe00f942005-03-01 19:22:29 +0000571 vaddr = (unsigned long __user *)
Steven J. Hillb9688312013-01-12 23:29:27 +0000572 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 reg = (opcode & RT) >> 16;
574
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100575 if ((unsigned long)vaddr & 3)
576 return SIGBUS;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577
578 preempt_disable();
579
580 if (ll_bit == 0 || ll_task != current) {
581 regs->regs[reg] = 0;
582 preempt_enable();
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100583 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 }
585
586 preempt_enable();
587
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100588 if (put_user(regs->regs[reg], vaddr))
589 return SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590
591 regs->regs[reg] = 1;
592
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100593 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594}
595
596/*
597 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
598 * opcodes are supposed to result in coprocessor unusable exceptions if
599 * executed on ll/sc-less processors. That's the theory. In practice a
600 * few processors such as NEC's VR4100 throw reserved instruction exceptions
601 * instead, so we're doing the emulation thing in both exception handlers.
602 */
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100603static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604{
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800605 if ((opcode & OPCODE) == LL) {
606 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200607 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100608 return simulate_ll(regs, opcode);
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800609 }
610 if ((opcode & OPCODE) == SC) {
611 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200612 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100613 return simulate_sc(regs, opcode);
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800614 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100616 return -1; /* Must be something else ... */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617}
618
Ralf Baechle3c370262005-04-13 17:43:59 +0000619/*
620 * Simulate trapping 'rdhwr' instructions to provide user accessible
Chris Dearman1f5826b2006-05-08 18:02:16 +0100621 * registers not implemented in hardware.
Ralf Baechle3c370262005-04-13 17:43:59 +0000622 */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500623static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
Ralf Baechle3c370262005-04-13 17:43:59 +0000624{
Al Virodc8f6022006-01-12 01:06:07 -0800625 struct thread_info *ti = task_thread_info(current);
Ralf Baechle3c370262005-04-13 17:43:59 +0000626
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500627 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
628 1, regs, 0);
629 switch (rd) {
James Hoganaff565a2016-06-15 19:29:52 +0100630 case MIPS_HWR_CPUNUM: /* CPU number */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500631 regs->regs[rt] = smp_processor_id();
632 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100633 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500634 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
635 current_cpu_data.icache.linesz);
636 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100637 case MIPS_HWR_CC: /* Read count register */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500638 regs->regs[rt] = read_c0_count();
639 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100640 case MIPS_HWR_CCRES: /* Count register resolution */
Ralf Baechle69f24d12013-09-17 10:25:47 +0200641 switch (current_cpu_type()) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500642 case CPU_20KC:
643 case CPU_25KF:
644 regs->regs[rt] = 1;
645 break;
646 default:
647 regs->regs[rt] = 2;
648 }
649 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100650 case MIPS_HWR_ULR: /* Read UserLocal register */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500651 regs->regs[rt] = ti->tp_value;
652 return 0;
653 default:
654 return -1;
655 }
656}
657
658static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
659{
Ralf Baechle3c370262005-04-13 17:43:59 +0000660 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
661 int rd = (opcode & RD) >> 11;
662 int rt = (opcode & RT) >> 16;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500663
664 simulate_rdhwr(regs, rd, rt);
665 return 0;
666 }
667
668 /* Not ours. */
669 return -1;
670}
671
Maciej W. Rozycki7aa70472016-01-30 09:08:28 +0000672static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500673{
674 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
675 int rd = (opcode & MM_RS) >> 16;
676 int rt = (opcode & MM_RT) >> 21;
677 simulate_rdhwr(regs, rd, rt);
678 return 0;
Ralf Baechle3c370262005-04-13 17:43:59 +0000679 }
680
Daniel Jacobowitz56ebd512005-11-26 22:34:41 -0500681 /* Not ours. */
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100682 return -1;
683}
Ralf Baechlee5679882006-11-30 01:14:47 +0000684
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100685static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
686{
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800687 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
688 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200689 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100690 return 0;
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800691 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100692
693 return -1; /* Must be something else ... */
Ralf Baechle3c370262005-04-13 17:43:59 +0000694}
695
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696asmlinkage void do_ov(struct pt_regs *regs)
697{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200698 enum ctx_state prev_state;
Maciej W. Rozyckie723e3f2016-03-04 01:42:49 +0000699 siginfo_t info = {
700 .si_signo = SIGFPE,
701 .si_code = FPE_INTOVF,
702 .si_addr = (void __user *)regs->cp0_epc,
703 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200705 prev_state = exception_enter();
Ralf Baechle36ccf1c2006-02-14 21:04:54 +0000706 die_if_kernel("Integer overflow", regs);
707
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708 force_sig_info(SIGFPE, &info, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200709 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710}
711
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100712/*
713 * Send SIGFPE according to FCSR Cause bits, which must have already
714 * been masked against Enable bits. This is impotant as Inexact can
715 * happen together with Overflow or Underflow, and `ptrace' can set
716 * any bits.
717 */
718void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
719 struct task_struct *tsk)
720{
721 struct siginfo si = { .si_addr = fault_addr, .si_signo = SIGFPE };
722
723 if (fcr31 & FPU_CSR_INV_X)
724 si.si_code = FPE_FLTINV;
725 else if (fcr31 & FPU_CSR_DIV_X)
726 si.si_code = FPE_FLTDIV;
727 else if (fcr31 & FPU_CSR_OVF_X)
728 si.si_code = FPE_FLTOVF;
729 else if (fcr31 & FPU_CSR_UDF_X)
730 si.si_code = FPE_FLTUND;
731 else if (fcr31 & FPU_CSR_INE_X)
732 si.si_code = FPE_FLTRES;
733 else
734 si.si_code = __SI_FAULT;
735 force_sig_info(SIGFPE, &si, tsk);
736}
737
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100738int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
David Daney515b0292010-10-21 16:32:26 -0700739{
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100740 struct siginfo si = { 0 };
Petar Jovanovicbcfc8f02016-07-13 15:23:37 +0200741 struct vm_area_struct *vma;
Paul Burtonad70c132015-01-30 12:09:35 +0000742
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100743 switch (sig) {
744 case 0:
745 return 0;
746
747 case SIGFPE:
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100748 force_fcr31_sig(fcr31, fault_addr, current);
David Daney515b0292010-10-21 16:32:26 -0700749 return 1;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100750
751 case SIGBUS:
752 si.si_addr = fault_addr;
753 si.si_signo = sig;
754 si.si_code = BUS_ADRERR;
755 force_sig_info(sig, &si, current);
756 return 1;
757
758 case SIGSEGV:
759 si.si_addr = fault_addr;
760 si.si_signo = sig;
761 down_read(&current->mm->mmap_sem);
Petar Jovanovicbcfc8f02016-07-13 15:23:37 +0200762 vma = find_vma(current->mm, (unsigned long)fault_addr);
763 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100764 si.si_code = SEGV_ACCERR;
765 else
766 si.si_code = SEGV_MAPERR;
767 up_read(&current->mm->mmap_sem);
768 force_sig_info(sig, &si, current);
769 return 1;
770
771 default:
David Daney515b0292010-10-21 16:32:26 -0700772 force_sig(sig, current);
773 return 1;
David Daney515b0292010-10-21 16:32:26 -0700774 }
775}
776
Paul Burton4227a2d2014-09-11 08:30:20 +0100777static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
778 unsigned long old_epc, unsigned long old_ra)
779{
780 union mips_instruction inst = { .word = opcode };
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100781 void __user *fault_addr;
782 unsigned long fcr31;
Paul Burton4227a2d2014-09-11 08:30:20 +0100783 int sig;
784
785 /* If it's obviously not an FP instruction, skip it */
786 switch (inst.i_format.opcode) {
787 case cop1_op:
788 case cop1x_op:
789 case lwc1_op:
790 case ldc1_op:
791 case swc1_op:
792 case sdc1_op:
793 break;
794
795 default:
796 return -1;
797 }
798
799 /*
800 * do_ri skipped over the instruction via compute_return_epc, undo
801 * that for the FPU emulator.
802 */
803 regs->cp0_epc = old_epc;
804 regs->regs[31] = old_ra;
805
806 /* Save the FP context to struct thread_struct */
807 lose_fpu(1);
808
809 /* Run the emulator */
810 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
811 &fault_addr);
812
Maciej W. Rozycki443c4402015-04-03 23:27:10 +0100813 /*
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100814 * We can't allow the emulated instruction to leave any
815 * enabled Cause bits set in $fcr31.
Maciej W. Rozycki443c4402015-04-03 23:27:10 +0100816 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100817 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
818 current->thread.fpu.fcr31 &= ~fcr31;
Paul Burton4227a2d2014-09-11 08:30:20 +0100819
820 /* Restore the hardware register state */
821 own_fpu(1);
822
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100823 /* Send a signal if required. */
824 process_fpemu_return(sig, fault_addr, fcr31);
825
Paul Burton4227a2d2014-09-11 08:30:20 +0100826 return 0;
827}
828
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829/*
830 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
831 */
832asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
833{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200834 enum ctx_state prev_state;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100835 void __user *fault_addr;
836 int sig;
Thiemo Seufer948a34c2007-08-22 01:42:04 +0100837
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200838 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +0200839 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200840 SIGFPE) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200841 goto out;
James Hogan64bedff2014-12-02 13:44:13 +0000842
843 /* Clear FCSR.Cause before enabling interrupts */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100844 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
James Hogan64bedff2014-12-02 13:44:13 +0000845 local_irq_enable();
846
Chris Dearman57725f92006-06-30 23:35:28 +0100847 die_if_kernel("FP exception in kernel code", regs);
848
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849 if (fcr31 & FPU_CSR_UNI_X) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 /*
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000851 * Unimplemented operation exception. If we've got the full
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 * software emulator on-board, let's use it...
853 *
854 * Force FPU to dump state into task/thread context. We're
855 * moving a lot of data here for what is probably a single
856 * instruction, but the alternative is to pre-decode the FP
857 * register operands before invoking the emulator, which seems
858 * a bit extreme for what should be an infrequent event.
859 */
Ralf Baechlecd21dfc2005-04-28 13:39:10 +0000860 /* Ensure 'resume' not overwrite saved fp context again. */
Atsushi Nemoto53dc8022007-03-10 01:07:45 +0900861 lose_fpu(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862
863 /* Run the emulator */
David Daney515b0292010-10-21 16:32:26 -0700864 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
865 &fault_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866
867 /*
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100868 * We can't allow the emulated instruction to leave any
869 * enabled Cause bits set in $fcr31.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100871 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
872 current->thread.fpu.fcr31 &= ~fcr31;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873
874 /* Restore the hardware register state */
Ralf Baechle70342282013-01-22 12:59:30 +0100875 own_fpu(1); /* Using the FPU again. */
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100876 } else {
877 sig = SIGFPE;
878 fault_addr = (void __user *) regs->cp0_epc;
Maciej W. Rozyckied2d72c2015-04-03 23:27:06 +0100879 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700880
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100881 /* Send a signal if required. */
882 process_fpemu_return(sig, fault_addr, fcr31);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200883
884out:
885 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886}
887
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +0000888void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
Ralf Baechledf270052008-04-20 16:28:54 +0100889 const char *str)
890{
Maciej W. Rozyckie723e3f2016-03-04 01:42:49 +0000891 siginfo_t info = { 0 };
Ralf Baechledf270052008-04-20 16:28:54 +0100892 char b[40];
893
Jason Wessel5dd11d52010-05-20 21:04:26 -0500894#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
Ralf Baechlee3b28832015-07-28 20:37:43 +0200895 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
896 SIGTRAP) == NOTIFY_STOP)
Jason Wessel5dd11d52010-05-20 21:04:26 -0500897 return;
898#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
899
Ralf Baechlee3b28832015-07-28 20:37:43 +0200900 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200901 SIGTRAP) == NOTIFY_STOP)
Jason Wessel88547002008-07-29 15:58:53 -0500902 return;
903
Ralf Baechledf270052008-04-20 16:28:54 +0100904 /*
905 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
906 * insns, even for trap and break codes that indicate arithmetic
907 * failures. Weird ...
908 * But should we continue the brokenness??? --macro
909 */
910 switch (code) {
911 case BRK_OVERFLOW:
912 case BRK_DIVZERO:
913 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
914 die_if_kernel(b, regs);
915 if (code == BRK_DIVZERO)
916 info.si_code = FPE_INTDIV;
917 else
918 info.si_code = FPE_INTOVF;
919 info.si_signo = SIGFPE;
Ralf Baechledf270052008-04-20 16:28:54 +0100920 info.si_addr = (void __user *) regs->cp0_epc;
921 force_sig_info(SIGFPE, &info, current);
922 break;
923 case BRK_BUG:
924 die_if_kernel("Kernel bug detected", regs);
925 force_sig(SIGTRAP, current);
926 break;
Ralf Baechleba3049e2008-10-28 17:38:42 +0000927 case BRK_MEMU:
928 /*
Maciej W. Rozycki1f443772015-04-03 23:24:14 +0100929 * This breakpoint code is used by the FPU emulator to retake
930 * control of the CPU after executing the instruction from the
931 * delay slot of an emulated branch.
Ralf Baechleba3049e2008-10-28 17:38:42 +0000932 *
933 * Terminate if exception was recognized as a delay slot return
934 * otherwise handle as normal.
935 */
936 if (do_dsemulret(regs))
937 return;
938
939 die_if_kernel("Math emu break/trap", regs);
940 force_sig(SIGTRAP, current);
941 break;
Ralf Baechledf270052008-04-20 16:28:54 +0100942 default:
943 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
944 die_if_kernel(b, regs);
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +0000945 if (si_code) {
946 info.si_signo = SIGTRAP;
947 info.si_code = si_code;
948 force_sig_info(SIGTRAP, &info, current);
949 } else {
950 force_sig(SIGTRAP, current);
951 }
Ralf Baechledf270052008-04-20 16:28:54 +0100952 }
953}
954
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955asmlinkage void do_bp(struct pt_regs *regs)
956{
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100957 unsigned long epc = msk_isa16_mode(exception_epc(regs));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958 unsigned int opcode, bcode;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200959 enum ctx_state prev_state;
Leonid Yegoshin078dde52013-12-04 16:39:34 +0000960 mm_segment_t seg;
961
962 seg = get_fs();
963 if (!user_mode(regs))
964 set_fs(KERNEL_DS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200966 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +0200967 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500968 if (get_isa16_mode(regs->cp0_epc)) {
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100969 u16 instr[2];
970
971 if (__get_user(instr[0], (u16 __user *)epc))
972 goto out_sigsegv;
973
974 if (!cpu_has_mmips) {
975 /* MIPS16e mode */
976 bcode = (instr[0] >> 5) & 0x3f;
977 } else if (mm_insn_16bit(instr[0])) {
978 /* 16-bit microMIPS BREAK */
979 bcode = instr[0] & 0xf;
980 } else {
981 /* 32-bit microMIPS BREAK */
982 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500983 goto out_sigsegv;
Markos Chandrasb08a9c92013-12-04 16:20:08 +0000984 opcode = (instr[0] << 16) | instr[1];
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100985 bcode = (opcode >> 6) & ((1 << 20) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500986 }
987 } else {
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100988 if (__get_user(opcode, (unsigned int __user *)epc))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500989 goto out_sigsegv;
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100990 bcode = (opcode >> 6) & ((1 << 20) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500991 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992
993 /*
994 * There is the ancient bug in the MIPS assemblers that the break
995 * code starts left to bit 16 instead to bit 6 in the opcode.
996 * Gas is bug-compatible, but not always, grrr...
997 * We handle both cases with a simple heuristics. --macro
998 */
Ralf Baechledf270052008-04-20 16:28:54 +0100999 if (bcode >= (1 << 10))
Maciej W. Rozyckic9875032015-04-03 23:26:32 +01001000 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001
David Daneyc1bf2072010-08-03 11:22:20 -07001002 /*
1003 * notify the kprobe handlers, if instruction is likely to
1004 * pertain to them.
1005 */
1006 switch (bcode) {
Ralf Baechle40e084a2015-07-29 22:44:53 +02001007 case BRK_UPROBE:
1008 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1009 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1010 goto out;
1011 else
1012 break;
1013 case BRK_UPROBE_XOL:
1014 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1015 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1016 goto out;
1017 else
1018 break;
David Daneyc1bf2072010-08-03 11:22:20 -07001019 case BRK_KPROBE_BP:
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001020 if (notify_die(DIE_BREAK, "debug", regs, bcode,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001021 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001022 goto out;
David Daneyc1bf2072010-08-03 11:22:20 -07001023 else
1024 break;
1025 case BRK_KPROBE_SSTEPBP:
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001026 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001027 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001028 goto out;
David Daneyc1bf2072010-08-03 11:22:20 -07001029 else
1030 break;
1031 default:
1032 break;
1033 }
1034
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001035 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001036
1037out:
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001038 set_fs(seg);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001039 exception_exit(prev_state);
Atsushi Nemoto90fccb12007-02-06 16:02:21 +09001040 return;
Ralf Baechlee5679882006-11-30 01:14:47 +00001041
1042out_sigsegv:
1043 force_sig(SIGSEGV, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001044 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045}
1046
1047asmlinkage void do_tr(struct pt_regs *regs)
1048{
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001049 u32 opcode, tcode = 0;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001050 enum ctx_state prev_state;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001051 u16 instr[2];
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001052 mm_segment_t seg;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001053 unsigned long epc = msk_isa16_mode(exception_epc(regs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001055 seg = get_fs();
1056 if (!user_mode(regs))
1057 set_fs(get_ds());
1058
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001059 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001060 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001061 if (get_isa16_mode(regs->cp0_epc)) {
1062 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1063 __get_user(instr[1], (u16 __user *)(epc + 2)))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001064 goto out_sigsegv;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001065 opcode = (instr[0] << 16) | instr[1];
1066 /* Immediate versions don't provide a code. */
1067 if (!(opcode & OPCODE))
1068 tcode = (opcode >> 12) & ((1 << 4) - 1);
1069 } else {
1070 if (__get_user(opcode, (u32 __user *)epc))
1071 goto out_sigsegv;
1072 /* Immediate versions don't provide a code. */
1073 if (!(opcode & OPCODE))
1074 tcode = (opcode >> 6) & ((1 << 10) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001075 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001077 do_trap_or_bp(regs, tcode, 0, "Trap");
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001078
1079out:
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001080 set_fs(seg);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001081 exception_exit(prev_state);
Atsushi Nemoto90fccb12007-02-06 16:02:21 +09001082 return;
Ralf Baechlee5679882006-11-30 01:14:47 +00001083
1084out_sigsegv:
1085 force_sig(SIGSEGV, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001086 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087}
1088
1089asmlinkage void do_ri(struct pt_regs *regs)
1090{
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001091 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1092 unsigned long old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001093 unsigned long old31 = regs->regs[31];
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001094 enum ctx_state prev_state;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001095 unsigned int opcode = 0;
1096 int status = -1;
1097
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001098 /*
1099 * Avoid any kernel code. Just emulate the R2 instruction
1100 * as quickly as possible.
1101 */
1102 if (mipsr2_emulation && cpu_has_mips_r6 &&
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001103 likely(user_mode(regs)) &&
1104 likely(get_user(opcode, epc) >= 0)) {
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001105 unsigned long fcr31 = 0;
1106
1107 status = mipsr2_decoder(regs, opcode, &fcr31);
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001108 switch (status) {
1109 case 0:
1110 case SIGEMT:
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001111 return;
1112 case SIGILL:
1113 goto no_r2_instr;
1114 default:
1115 process_fpemu_return(status,
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001116 &current->thread.cp0_baduaddr,
1117 fcr31);
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001118 return;
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001119 }
1120 }
1121
1122no_r2_instr:
1123
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001124 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001125 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001126
Ralf Baechlee3b28832015-07-28 20:37:43 +02001127 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001128 SIGILL) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001129 goto out;
Jason Wessel88547002008-07-29 15:58:53 -05001130
Linus Torvalds1da177e2005-04-16 15:20:36 -07001131 die_if_kernel("Reserved instruction in kernel code", regs);
1132
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001133 if (unlikely(compute_return_epc(regs) < 0))
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001134 goto out;
Ralf Baechle3c370262005-04-13 17:43:59 +00001135
Maciej W. Rozycki3d50a7f2016-01-30 09:08:43 +00001136 if (!get_isa16_mode(regs->cp0_epc)) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001137 if (unlikely(get_user(opcode, epc) < 0))
1138 status = SIGSEGV;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001139
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001140 if (!cpu_has_llsc && status < 0)
1141 status = simulate_llsc(regs, opcode);
1142
1143 if (status < 0)
1144 status = simulate_rdhwr_normal(regs, opcode);
1145
1146 if (status < 0)
1147 status = simulate_sync(regs, opcode);
Paul Burton4227a2d2014-09-11 08:30:20 +01001148
1149 if (status < 0)
1150 status = simulate_fp(regs, opcode, old_epc, old31);
Maciej W. Rozycki3d50a7f2016-01-30 09:08:43 +00001151 } else if (cpu_has_mmips) {
1152 unsigned short mmop[2] = { 0 };
1153
1154 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1155 status = SIGSEGV;
1156 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1157 status = SIGSEGV;
1158 opcode = mmop[0];
1159 opcode = (opcode << 16) | mmop[1];
1160
1161 if (status < 0)
1162 status = simulate_rdhwr_mm(regs, opcode);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001163 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001164
1165 if (status < 0)
1166 status = SIGILL;
1167
1168 if (unlikely(status > 0)) {
1169 regs->cp0_epc = old_epc; /* Undo skip-over. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001170 regs->regs[31] = old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001171 force_sig(status, current);
1172 }
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001173
1174out:
1175 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176}
1177
Ralf Baechled223a862007-07-10 17:33:02 +01001178/*
1179 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1180 * emulated more than some threshold number of instructions, force migration to
1181 * a "CPU" that has FP support.
1182 */
1183static void mt_ase_fp_affinity(void)
1184{
1185#ifdef CONFIG_MIPS_MT_FPAFF
1186 if (mt_fpemul_threshold > 0 &&
1187 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1188 /*
1189 * If there's no FPU present, or if the application has already
1190 * restricted the allowed set to exclude any CPUs with FPUs,
1191 * we'll skip the procedure.
1192 */
Rusty Russell8dd92892015-03-05 10:49:17 +10301193 if (cpumask_intersects(&current->cpus_allowed, &mt_fpu_cpumask)) {
Ralf Baechled223a862007-07-10 17:33:02 +01001194 cpumask_t tmask;
1195
Kevin D. Kissell9cc12362008-09-09 21:33:36 +02001196 current->thread.user_cpus_allowed
1197 = current->cpus_allowed;
Rusty Russell8dd92892015-03-05 10:49:17 +10301198 cpumask_and(&tmask, &current->cpus_allowed,
1199 &mt_fpu_cpumask);
Julia Lawalled1bbde2010-03-26 23:03:07 +01001200 set_cpus_allowed_ptr(current, &tmask);
Ralf Baechle293c5bd2007-07-25 16:19:33 +01001201 set_thread_flag(TIF_FPUBOUND);
Ralf Baechled223a862007-07-10 17:33:02 +01001202 }
1203 }
1204#endif /* CONFIG_MIPS_MT_FPAFF */
1205}
1206
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001207/*
1208 * No lock; only written during early bootup by CPU 0.
1209 */
1210static RAW_NOTIFIER_HEAD(cu2_chain);
1211
1212int __ref register_cu2_notifier(struct notifier_block *nb)
1213{
1214 return raw_notifier_chain_register(&cu2_chain, nb);
1215}
1216
1217int cu2_notifier_call_chain(unsigned long val, void *v)
1218{
1219 return raw_notifier_call_chain(&cu2_chain, val, v);
1220}
1221
1222static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
Ralf Baechle70342282013-01-22 12:59:30 +01001223 void *data)
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001224{
1225 struct pt_regs *regs = data;
1226
Jayachandran C83bee792013-06-10 06:30:01 +00001227 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001228 "instruction", regs);
Jayachandran C83bee792013-06-10 06:30:01 +00001229 force_sig(SIGILL, current);
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001230
1231 return NOTIFY_OK;
1232}
1233
Paul Burton97915542015-01-08 12:17:37 +00001234static int wait_on_fp_mode_switch(atomic_t *p)
1235{
1236 /*
1237 * The FP mode for this task is currently being switched. That may
1238 * involve modifications to the format of this tasks FP context which
1239 * make it unsafe to proceed with execution for the moment. Instead,
1240 * schedule some other task.
1241 */
1242 schedule();
1243 return 0;
1244}
1245
Paul Burton1db1af82014-01-27 15:23:11 +00001246static int enable_restore_fp_context(int msa)
1247{
Paul Burtonc9017752014-07-30 08:53:20 +01001248 int err, was_fpu_owner, prior_msa;
Paul Burton1db1af82014-01-27 15:23:11 +00001249
Paul Burton97915542015-01-08 12:17:37 +00001250 /*
1251 * If an FP mode switch is currently underway, wait for it to
1252 * complete before proceeding.
1253 */
1254 wait_on_atomic_t(&current->mm->context.fp_mode_switching,
1255 wait_on_fp_mode_switch, TASK_KILLABLE);
1256
Paul Burton1db1af82014-01-27 15:23:11 +00001257 if (!used_math()) {
1258 /* First time FP context user. */
Paul Burton762a1f42014-07-11 16:44:35 +01001259 preempt_disable();
Paul Burton1db1af82014-01-27 15:23:11 +00001260 err = init_fpu();
Paul Burtonc9017752014-07-30 08:53:20 +01001261 if (msa && !err) {
Paul Burton1db1af82014-01-27 15:23:11 +00001262 enable_msa();
Maciej W. Rozyckie49d3842016-05-17 06:12:27 +01001263 init_msa_upper();
Paul Burton732c0c32014-07-31 14:53:16 +01001264 set_thread_flag(TIF_USEDMSA);
1265 set_thread_flag(TIF_MSA_CTX_LIVE);
Paul Burtonc9017752014-07-30 08:53:20 +01001266 }
Paul Burton762a1f42014-07-11 16:44:35 +01001267 preempt_enable();
Paul Burton1db1af82014-01-27 15:23:11 +00001268 if (!err)
1269 set_used_math();
1270 return err;
1271 }
1272
1273 /*
1274 * This task has formerly used the FP context.
1275 *
1276 * If this thread has no live MSA vector context then we can simply
1277 * restore the scalar FP context. If it has live MSA vector context
1278 * (that is, it has or may have used MSA since last performing a
1279 * function call) then we'll need to restore the vector context. This
1280 * applies even if we're currently only executing a scalar FP
1281 * instruction. This is because if we were to later execute an MSA
1282 * instruction then we'd either have to:
1283 *
1284 * - Restore the vector context & clobber any registers modified by
1285 * scalar FP instructions between now & then.
1286 *
1287 * or
1288 *
1289 * - Not restore the vector context & lose the most significant bits
1290 * of all vector registers.
1291 *
1292 * Neither of those options is acceptable. We cannot restore the least
1293 * significant bits of the registers now & only restore the most
1294 * significant bits later because the most significant bits of any
1295 * vector registers whose aliased FP register is modified now will have
1296 * been zeroed. We'd have no way to know that when restoring the vector
1297 * context & thus may load an outdated value for the most significant
1298 * bits of a vector register.
1299 */
1300 if (!msa && !thread_msa_context_live())
1301 return own_fpu(1);
1302
1303 /*
1304 * This task is using or has previously used MSA. Thus we require
1305 * that Status.FR == 1.
1306 */
Paul Burton762a1f42014-07-11 16:44:35 +01001307 preempt_disable();
Paul Burton1db1af82014-01-27 15:23:11 +00001308 was_fpu_owner = is_fpu_owner();
Paul Burton762a1f42014-07-11 16:44:35 +01001309 err = own_fpu_inatomic(0);
Paul Burton1db1af82014-01-27 15:23:11 +00001310 if (err)
Paul Burton762a1f42014-07-11 16:44:35 +01001311 goto out;
Paul Burton1db1af82014-01-27 15:23:11 +00001312
1313 enable_msa();
1314 write_msa_csr(current->thread.fpu.msacsr);
1315 set_thread_flag(TIF_USEDMSA);
1316
1317 /*
1318 * If this is the first time that the task is using MSA and it has
1319 * previously used scalar FP in this time slice then we already nave
Paul Burtonc9017752014-07-30 08:53:20 +01001320 * FP context which we shouldn't clobber. We do however need to clear
1321 * the upper 64b of each vector register so that this task has no
1322 * opportunity to see data left behind by another.
Paul Burton1db1af82014-01-27 15:23:11 +00001323 */
Paul Burtonc9017752014-07-30 08:53:20 +01001324 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1325 if (!prior_msa && was_fpu_owner) {
Maciej W. Rozyckie49d3842016-05-17 06:12:27 +01001326 init_msa_upper();
Paul Burton762a1f42014-07-11 16:44:35 +01001327
1328 goto out;
Paul Burtonc9017752014-07-30 08:53:20 +01001329 }
Paul Burton1db1af82014-01-27 15:23:11 +00001330
Paul Burtonc9017752014-07-30 08:53:20 +01001331 if (!prior_msa) {
1332 /*
1333 * Restore the least significant 64b of each vector register
1334 * from the existing scalar FP context.
1335 */
1336 _restore_fp(current);
Paul Burtonb8340672014-07-11 16:44:29 +01001337
Paul Burtonc9017752014-07-30 08:53:20 +01001338 /*
1339 * The task has not formerly used MSA, so clear the upper 64b
1340 * of each vector register such that it cannot see data left
1341 * behind by another task.
1342 */
Maciej W. Rozyckie49d3842016-05-17 06:12:27 +01001343 init_msa_upper();
Paul Burtonc9017752014-07-30 08:53:20 +01001344 } else {
1345 /* We need to restore the vector context. */
1346 restore_msa(current);
Paul Burtonb8340672014-07-11 16:44:29 +01001347
Paul Burtonc9017752014-07-30 08:53:20 +01001348 /* Restore the scalar FP control & status register */
1349 if (!was_fpu_owner)
James Hogand76e9b92015-01-30 15:40:20 +00001350 write_32bit_cp1_register(CP1_STATUS,
1351 current->thread.fpu.fcr31);
Paul Burtonc9017752014-07-30 08:53:20 +01001352 }
Paul Burton762a1f42014-07-11 16:44:35 +01001353
1354out:
1355 preempt_enable();
1356
Paul Burton1db1af82014-01-27 15:23:11 +00001357 return 0;
1358}
1359
Linus Torvalds1da177e2005-04-16 15:20:36 -07001360asmlinkage void do_cpu(struct pt_regs *regs)
1361{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001362 enum ctx_state prev_state;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001363 unsigned int __user *epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001364 unsigned long old_epc, old31;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001365 void __user *fault_addr;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001366 unsigned int opcode;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001367 unsigned long fcr31;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368 unsigned int cpid;
Paul Burton597ce172013-11-22 13:12:07 +00001369 int status, err;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001370 int sig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001372 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1374
Jayachandran C83bee792013-06-10 06:30:01 +00001375 if (cpid != 2)
1376 die_if_kernel("do_cpu invoked from kernel context!", regs);
1377
Linus Torvalds1da177e2005-04-16 15:20:36 -07001378 switch (cpid) {
1379 case 0:
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001380 epc = (unsigned int __user *)exception_epc(regs);
1381 old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001382 old31 = regs->regs[31];
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001383 opcode = 0;
1384 status = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001386 if (unlikely(compute_return_epc(regs) < 0))
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001387 break;
Ralf Baechle3c370262005-04-13 17:43:59 +00001388
Maciej W. Rozycki10f6d99f2016-01-30 09:08:16 +00001389 if (!get_isa16_mode(regs->cp0_epc)) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001390 if (unlikely(get_user(opcode, epc) < 0))
1391 status = SIGSEGV;
1392
1393 if (!cpu_has_llsc && status < 0)
1394 status = simulate_llsc(regs, opcode);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001395 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001396
1397 if (status < 0)
1398 status = SIGILL;
1399
1400 if (unlikely(status > 0)) {
1401 regs->cp0_epc = old_epc; /* Undo skip-over. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001402 regs->regs[31] = old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001403 force_sig(status, current);
1404 }
1405
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001406 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001408 case 3:
1409 /*
Maciej W. Rozycki2d83fea2015-04-03 23:26:49 +01001410 * The COP3 opcode space and consequently the CP0.Status.CU3
1411 * bit and the CP0.Cause.CE=3 encoding have been removed as
1412 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1413 * up the space has been reused for COP1X instructions, that
1414 * are enabled by the CP0.Status.CU1 bit and consequently
1415 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1416 * exceptions. Some FPU-less processors that implement one
1417 * of these ISAs however use this code erroneously for COP1X
1418 * instructions. Therefore we redirect this trap to the FP
1419 * emulator too.
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001420 */
Maciej W. Rozycki2d83fea2015-04-03 23:26:49 +01001421 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001422 force_sig(SIGILL, current);
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001423 break;
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001424 }
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001425 /* Fall through. */
1426
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427 case 1:
Paul Burton1db1af82014-01-27 15:23:11 +00001428 err = enable_restore_fp_context(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001430 if (raw_cpu_has_fpu && !err)
1431 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001433 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1434 &fault_addr);
Maciej W. Rozycki443c4402015-04-03 23:27:10 +01001435
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001436 /*
1437 * We can't allow the emulated instruction to leave
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +01001438 * any enabled Cause bits set in $fcr31.
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001439 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +01001440 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1441 current->thread.fpu.fcr31 &= ~fcr31;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001442
1443 /* Send a signal if required. */
1444 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1445 mt_ase_fp_affinity();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001447 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448
1449 case 2:
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001450 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001451 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452 }
1453
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001454 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455}
1456
James Hogan64bedff2014-12-02 13:44:13 +00001457asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001458{
1459 enum ctx_state prev_state;
1460
1461 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001462 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
James Hogan64bedff2014-12-02 13:44:13 +00001463 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001464 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
James Hogan64bedff2014-12-02 13:44:13 +00001465 goto out;
1466
1467 /* Clear MSACSR.Cause before enabling interrupts */
1468 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1469 local_irq_enable();
1470
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001471 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1472 force_sig(SIGFPE, current);
James Hogan64bedff2014-12-02 13:44:13 +00001473out:
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001474 exception_exit(prev_state);
1475}
1476
Paul Burton1db1af82014-01-27 15:23:11 +00001477asmlinkage void do_msa(struct pt_regs *regs)
1478{
1479 enum ctx_state prev_state;
1480 int err;
1481
1482 prev_state = exception_enter();
1483
1484 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1485 force_sig(SIGILL, current);
1486 goto out;
1487 }
1488
1489 die_if_kernel("do_msa invoked from kernel context!", regs);
1490
1491 err = enable_restore_fp_context(1);
1492 if (err)
1493 force_sig(SIGILL, current);
1494out:
1495 exception_exit(prev_state);
1496}
1497
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498asmlinkage void do_mdmx(struct pt_regs *regs)
1499{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001500 enum ctx_state prev_state;
1501
1502 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001503 force_sig(SIGILL, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001504 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505}
1506
David Daney8bc6d052009-01-05 15:29:58 -08001507/*
1508 * Called with interrupts disabled.
1509 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001510asmlinkage void do_watch(struct pt_regs *regs)
1511{
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001512 siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001513 enum ctx_state prev_state;
David Daneyb67b2b72008-09-23 00:08:45 -07001514
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001515 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516 /*
David Daneyb67b2b72008-09-23 00:08:45 -07001517 * Clear WP (bit 22) bit of cause register so we don't loop
1518 * forever.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519 */
James Hogane233c732016-03-01 22:19:38 +00001520 clear_c0_cause(CAUSEF_WP);
David Daneyb67b2b72008-09-23 00:08:45 -07001521
1522 /*
1523 * If the current thread has the watch registers loaded, save
1524 * their values and send SIGTRAP. Otherwise another thread
1525 * left the registers set, clear them and continue.
1526 */
1527 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1528 mips_read_watch_registers();
David Daney8bc6d052009-01-05 15:29:58 -08001529 local_irq_enable();
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001530 force_sig_info(SIGTRAP, &info, current);
David Daney8bc6d052009-01-05 15:29:58 -08001531 } else {
David Daneyb67b2b72008-09-23 00:08:45 -07001532 mips_clear_watch_registers();
David Daney8bc6d052009-01-05 15:29:58 -08001533 local_irq_enable();
1534 }
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001535 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536}
1537
1538asmlinkage void do_mcheck(struct pt_regs *regs)
1539{
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001540 int multi_match = regs->cp0_status & ST0_TS;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001541 enum ctx_state prev_state;
James Hogan55c723e2015-07-27 13:50:21 +01001542 mm_segment_t old_fs = get_fs();
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001543
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001544 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545 show_regs(regs);
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001546
1547 if (multi_match) {
James Hogan3c865dd2015-07-15 16:17:43 +01001548 dump_tlb_regs();
1549 pr_info("\n");
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001550 dump_tlb_all();
1551 }
1552
James Hogan55c723e2015-07-27 13:50:21 +01001553 if (!user_mode(regs))
1554 set_fs(KERNEL_DS);
1555
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +09001556 show_code((unsigned int __user *) regs->cp0_epc);
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001557
James Hogan55c723e2015-07-27 13:50:21 +01001558 set_fs(old_fs);
1559
Linus Torvalds1da177e2005-04-16 15:20:36 -07001560 /*
1561 * Some chips may have other causes of machine check (e.g. SB1
1562 * graduation timer)
1563 */
1564 panic("Caught Machine Check exception - %scaused by multiple "
1565 "matching entries in the TLB.",
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001566 (multi_match) ? "" : "not ");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001567}
1568
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001569asmlinkage void do_mt(struct pt_regs *regs)
1570{
Ralf Baechle41c594a2006-04-05 09:45:45 +01001571 int subcode;
1572
Ralf Baechle41c594a2006-04-05 09:45:45 +01001573 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1574 >> VPECONTROL_EXCPT_SHIFT;
1575 switch (subcode) {
1576 case 0:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001577 printk(KERN_DEBUG "Thread Underflow\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001578 break;
1579 case 1:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001580 printk(KERN_DEBUG "Thread Overflow\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001581 break;
1582 case 2:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001583 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001584 break;
1585 case 3:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001586 printk(KERN_DEBUG "Gating Storage Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001587 break;
1588 case 4:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001589 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001590 break;
1591 case 5:
Masanari Iidaf232c7e2012-02-08 21:53:14 +09001592 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001593 break;
1594 default:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001595 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
Ralf Baechle41c594a2006-04-05 09:45:45 +01001596 subcode);
1597 break;
1598 }
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001599 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1600
1601 force_sig(SIGILL, current);
1602}
1603
1604
Ralf Baechlee50c0a82005-05-31 11:49:19 +00001605asmlinkage void do_dsp(struct pt_regs *regs)
1606{
1607 if (cpu_has_dsp)
Ralf Baechleab75dc02011-11-17 15:07:31 +00001608 panic("Unexpected DSP exception");
Ralf Baechlee50c0a82005-05-31 11:49:19 +00001609
1610 force_sig(SIGILL, current);
1611}
1612
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613asmlinkage void do_reserved(struct pt_regs *regs)
1614{
1615 /*
Ralf Baechle70342282013-01-22 12:59:30 +01001616 * Game over - no way to handle this if it ever occurs. Most probably
Linus Torvalds1da177e2005-04-16 15:20:36 -07001617 * caused by a new unknown cpu type or after another deadly
1618 * hard/software error.
1619 */
1620 show_regs(regs);
1621 panic("Caught reserved exception %ld - should not happen.",
1622 (regs->cp0_cause & 0x7f) >> 2);
1623}
1624
Ralf Baechle39b8d522008-04-28 17:14:26 +01001625static int __initdata l1parity = 1;
1626static int __init nol1parity(char *s)
1627{
1628 l1parity = 0;
1629 return 1;
1630}
1631__setup("nol1par", nol1parity);
1632static int __initdata l2parity = 1;
1633static int __init nol2parity(char *s)
1634{
1635 l2parity = 0;
1636 return 1;
1637}
1638__setup("nol2par", nol2parity);
1639
Linus Torvalds1da177e2005-04-16 15:20:36 -07001640/*
1641 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1642 * it different ways.
1643 */
1644static inline void parity_protection_init(void)
1645{
Paul Burton35e6de32016-10-17 16:01:07 +01001646#define ERRCTL_PE 0x80000000
1647#define ERRCTL_L2P 0x00800000
1648
1649 if (mips_cm_revision() >= CM_REV_CM3) {
1650 ulong gcr_ectl, cp0_ectl;
1651
1652 /*
1653 * With CM3 systems we need to ensure that the L1 & L2
1654 * parity enables are set to the same value, since this
1655 * is presumed by the hardware engineers.
1656 *
1657 * If the user disabled either of L1 or L2 ECC checking,
1658 * disable both.
1659 */
1660 l1parity &= l2parity;
1661 l2parity &= l1parity;
1662
1663 /* Probe L1 ECC support */
1664 cp0_ectl = read_c0_ecc();
1665 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1666 back_to_back_c0_hazard();
1667 cp0_ectl = read_c0_ecc();
1668
1669 /* Probe L2 ECC support */
1670 gcr_ectl = read_gcr_err_control();
1671
1672 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_MSK) ||
1673 !(cp0_ectl & ERRCTL_PE)) {
1674 /*
1675 * One of L1 or L2 ECC checking isn't supported,
1676 * so we cannot enable either.
1677 */
1678 l1parity = l2parity = 0;
1679 }
1680
1681 /* Configure L1 ECC checking */
1682 if (l1parity)
1683 cp0_ectl |= ERRCTL_PE;
1684 else
1685 cp0_ectl &= ~ERRCTL_PE;
1686 write_c0_ecc(cp0_ectl);
1687 back_to_back_c0_hazard();
1688 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1689
1690 /* Configure L2 ECC checking */
1691 if (l2parity)
1692 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1693 else
1694 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1695 write_gcr_err_control(gcr_ectl);
1696 gcr_ectl = read_gcr_err_control();
1697 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
1698 WARN_ON(!!gcr_ectl != l2parity);
1699
1700 pr_info("Cache parity protection %sabled\n",
1701 l1parity ? "en" : "dis");
1702 return;
1703 }
1704
Ralf Baechle10cc3522007-10-11 23:46:15 +01001705 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001706 case CPU_24K:
Nigel Stephens98a41de2006-04-27 15:50:32 +01001707 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001708 case CPU_74K:
1709 case CPU_1004K:
Steven J. Hill442e14a2014-01-17 15:03:50 -06001710 case CPU_1074K:
Leonid Yegoshin26ab96d2013-11-27 10:07:53 +00001711 case CPU_INTERAPTIV:
Leonid Yegoshin708ac4b2013-11-14 16:12:27 +00001712 case CPU_PROAPTIV:
James Hoganaced4cb2014-01-22 16:19:38 +00001713 case CPU_P5600:
Leonid Yegoshin46950892014-11-24 12:59:01 +00001714 case CPU_QEMU_GENERIC:
Paul Burton1091bfa2016-02-03 03:26:38 +00001715 case CPU_P6600:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001716 {
Ralf Baechle39b8d522008-04-28 17:14:26 +01001717 unsigned long errctl;
1718 unsigned int l1parity_present, l2parity_present;
1719
1720 errctl = read_c0_ecc();
1721 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1722
1723 /* probe L1 parity support */
1724 write_c0_ecc(errctl | ERRCTL_PE);
1725 back_to_back_c0_hazard();
1726 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1727
1728 /* probe L2 parity support */
1729 write_c0_ecc(errctl|ERRCTL_L2P);
1730 back_to_back_c0_hazard();
1731 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1732
1733 if (l1parity_present && l2parity_present) {
1734 if (l1parity)
1735 errctl |= ERRCTL_PE;
1736 if (l1parity ^ l2parity)
1737 errctl |= ERRCTL_L2P;
1738 } else if (l1parity_present) {
1739 if (l1parity)
1740 errctl |= ERRCTL_PE;
1741 } else if (l2parity_present) {
1742 if (l2parity)
1743 errctl |= ERRCTL_L2P;
1744 } else {
1745 /* No parity available */
1746 }
1747
1748 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1749
1750 write_c0_ecc(errctl);
1751 back_to_back_c0_hazard();
1752 errctl = read_c0_ecc();
1753 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1754
1755 if (l1parity_present)
1756 printk(KERN_INFO "Cache parity protection %sabled\n",
1757 (errctl & ERRCTL_PE) ? "en" : "dis");
1758
1759 if (l2parity_present) {
1760 if (l1parity_present && l1parity)
1761 errctl ^= ERRCTL_L2P;
1762 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1763 (errctl & ERRCTL_L2P) ? "en" : "dis");
1764 }
1765 }
1766 break;
1767
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768 case CPU_5KC:
Leonid Yegoshin78d48032012-07-06 21:56:01 +02001769 case CPU_5KE:
Kelvin Cheung2fa36392012-06-20 20:05:32 +01001770 case CPU_LOONGSON1:
Ralf Baechle14f18b72005-03-01 18:15:08 +00001771 write_c0_ecc(0x80000000);
1772 back_to_back_c0_hazard();
1773 /* Set the PE bit (bit 31) in the c0_errctl register. */
1774 printk(KERN_INFO "Cache parity protection %sabled\n",
1775 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001776 break;
1777 case CPU_20KC:
1778 case CPU_25KF:
1779 /* Clear the DE bit (bit 16) in the c0_status register. */
1780 printk(KERN_INFO "Enable cache parity protection for "
1781 "MIPS 20KC/25KF CPUs.\n");
1782 clear_c0_status(ST0_DE);
1783 break;
1784 default:
1785 break;
1786 }
1787}
1788
1789asmlinkage void cache_parity_error(void)
1790{
1791 const int field = 2 * sizeof(unsigned long);
1792 unsigned int reg_val;
1793
1794 /* For the moment, report the problem and hang. */
1795 printk("Cache error exception:\n");
1796 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1797 reg_val = read_c0_cacheerr();
1798 printk("c0_cacheerr == %08x\n", reg_val);
1799
1800 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1801 reg_val & (1<<30) ? "secondary" : "primary",
1802 reg_val & (1<<31) ? "data" : "insn");
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00001803 if ((cpu_has_mips_r2_r6) &&
Markos Chandras721a9202014-05-21 12:35:00 +01001804 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
Leonid Yegoshin6de20452013-10-10 09:58:59 +01001805 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1806 reg_val & (1<<29) ? "ED " : "",
1807 reg_val & (1<<28) ? "ET " : "",
1808 reg_val & (1<<27) ? "ES " : "",
1809 reg_val & (1<<26) ? "EE " : "",
1810 reg_val & (1<<25) ? "EB " : "",
1811 reg_val & (1<<24) ? "EI " : "",
1812 reg_val & (1<<23) ? "E1 " : "",
1813 reg_val & (1<<22) ? "E0 " : "");
1814 } else {
1815 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1816 reg_val & (1<<29) ? "ED " : "",
1817 reg_val & (1<<28) ? "ET " : "",
1818 reg_val & (1<<26) ? "EE " : "",
1819 reg_val & (1<<25) ? "EB " : "",
1820 reg_val & (1<<24) ? "EI " : "",
1821 reg_val & (1<<23) ? "E1 " : "",
1822 reg_val & (1<<22) ? "E0 " : "");
1823 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001824 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1825
Ralf Baechleec917c2c2005-10-07 16:58:15 +01001826#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001827 if (reg_val & (1<<22))
1828 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1829
1830 if (reg_val & (1<<23))
1831 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1832#endif
1833
1834 panic("Can't handle the cache error!");
1835}
1836
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +00001837asmlinkage void do_ftlb(void)
1838{
1839 const int field = 2 * sizeof(unsigned long);
1840 unsigned int reg_val;
1841
1842 /* For the moment, report the problem and hang. */
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00001843 if ((cpu_has_mips_r2_r6) &&
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001844 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1845 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +00001846 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1847 read_c0_ecc());
1848 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1849 reg_val = read_c0_cacheerr();
1850 pr_err("c0_cacheerr == %08x\n", reg_val);
1851
1852 if ((reg_val & 0xc0000000) == 0xc0000000) {
1853 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1854 } else {
1855 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1856 reg_val & (1<<30) ? "secondary" : "primary",
1857 reg_val & (1<<31) ? "data" : "insn");
1858 }
1859 } else {
1860 pr_err("FTLB error exception\n");
1861 }
1862 /* Just print the cacheerr bits for now */
1863 cache_parity_error();
1864}
1865
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866/*
1867 * SDBBP EJTAG debug exception handler.
1868 * We skip the instruction and return to the next instruction.
1869 */
1870void ejtag_exception_handler(struct pt_regs *regs)
1871{
1872 const int field = 2 * sizeof(unsigned long);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001873 unsigned long depc, old_epc, old_ra;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874 unsigned int debug;
1875
Chris Dearman70ae6122006-06-30 12:32:37 +01001876 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001877 depc = read_c0_depc();
1878 debug = read_c0_debug();
Chris Dearman70ae6122006-06-30 12:32:37 +01001879 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880 if (debug & 0x80000000) {
1881 /*
1882 * In branch delay slot.
1883 * We cheat a little bit here and use EPC to calculate the
1884 * debug return address (DEPC). EPC is restored after the
1885 * calculation.
1886 */
1887 old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001888 old_ra = regs->regs[31];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889 regs->cp0_epc = depc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001890 compute_return_epc(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891 depc = regs->cp0_epc;
1892 regs->cp0_epc = old_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001893 regs->regs[31] = old_ra;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001894 } else
1895 depc += 4;
1896 write_c0_depc(depc);
1897
1898#if 0
Chris Dearman70ae6122006-06-30 12:32:37 +01001899 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001900 write_c0_debug(debug | 0x100);
1901#endif
1902}
1903
1904/*
1905 * NMI exception handler.
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001906 * No lock; only written during early bootup by CPU 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001907 */
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001908static RAW_NOTIFIER_HEAD(nmi_chain);
1909
1910int register_nmi_notifier(struct notifier_block *nb)
1911{
1912 return raw_notifier_chain_register(&nmi_chain, nb);
1913}
1914
Joe Perchesff2d8b12012-01-12 17:17:21 -08001915void __noreturn nmi_exception_handler(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001916{
Leonid Yegoshin83e4da12013-10-08 12:39:31 +01001917 char str[100];
1918
Petri Gynther7963b3f2015-10-19 11:49:52 -07001919 nmi_enter();
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001920 raw_notifier_call_chain(&nmi_chain, 0, regs);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001921 bust_spinlocks(1);
Leonid Yegoshin83e4da12013-10-08 12:39:31 +01001922 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1923 smp_processor_id(), regs->cp0_epc);
1924 regs->cp0_epc = read_c0_errorepc();
1925 die(str, regs);
Petri Gynther7963b3f2015-10-19 11:49:52 -07001926 nmi_exit();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927}
1928
Ralf Baechlee01402b2005-07-14 15:57:16 +00001929#define VECTORSPACING 0x100 /* for EI/VI mode */
1930
1931unsigned long ebase;
James Hogan878edf02016-06-09 14:19:14 +01001932EXPORT_SYMBOL_GPL(ebase);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001933unsigned long exception_handlers[32];
Ralf Baechlee01402b2005-07-14 15:57:16 +00001934unsigned long vi_handlers[64];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935
Florian Fainelli2d1b6e92010-01-28 15:21:42 +01001936void __init *set_except_vector(int n, void *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001937{
1938 unsigned long handler = (unsigned long) addr;
Ralf Baechleb22d1b62013-05-09 17:57:30 +02001939 unsigned long old_handler;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001940
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001941#ifdef CONFIG_CPU_MICROMIPS
1942 /*
1943 * Only the TLB handlers are cache aligned with an even
1944 * address. All other handlers are on an odd address and
1945 * require no modification. Otherwise, MIPS32 mode will
1946 * be entered when handling any TLB exceptions. That
1947 * would be bad...since we must stay in microMIPS mode.
1948 */
1949 if (!(handler & 0x1))
1950 handler |= 1;
1951#endif
Ralf Baechleb22d1b62013-05-09 17:57:30 +02001952 old_handler = xchg(&exception_handlers[n], handler);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001953
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954 if (n == 0 && cpu_has_divec) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001955#ifdef CONFIG_CPU_MICROMIPS
1956 unsigned long jump_mask = ~((1 << 27) - 1);
1957#else
Florian Fainelli92bbe1b2010-01-28 15:22:37 +01001958 unsigned long jump_mask = ~((1 << 28) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001959#endif
Florian Fainelli92bbe1b2010-01-28 15:22:37 +01001960 u32 *buf = (u32 *)(ebase + 0x200);
1961 unsigned int k0 = 26;
1962 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1963 uasm_i_j(&buf, handler & ~jump_mask);
1964 uasm_i_nop(&buf);
1965 } else {
1966 UASM_i_LA(&buf, k0, handler);
1967 uasm_i_jr(&buf, k0);
1968 uasm_i_nop(&buf);
1969 }
1970 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001971 }
1972 return (void *)old_handler;
1973}
1974
Ralf Baechle86a17082013-02-08 01:21:34 +01001975static void do_default_vi(void)
Atsushi Nemoto6ba07e52007-05-21 23:45:38 +09001976{
1977 show_regs(get_irq_regs());
1978 panic("Caught unexpected vectored interrupt.");
1979}
1980
Ralf Baechleef300e42007-05-06 18:31:18 +01001981static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001982{
1983 unsigned long handler;
1984 unsigned long old_handler = vi_handlers[n];
Ralf Baechlef6771db2007-11-08 18:02:29 +00001985 int srssets = current_cpu_data.srsets;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001986 u16 *h;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001987 unsigned char *b;
1988
Ralf Baechleb72b7092009-03-30 14:49:44 +02001989 BUG_ON(!cpu_has_veic && !cpu_has_vint);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001990
1991 if (addr == NULL) {
1992 handler = (unsigned long) do_default_vi;
1993 srs = 0;
Ralf Baechle41c594a2006-04-05 09:45:45 +01001994 } else
Ralf Baechlee01402b2005-07-14 15:57:16 +00001995 handler = (unsigned long) addr;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001996 vi_handlers[n] = handler;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001997
1998 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1999
Ralf Baechlef6771db2007-11-08 18:02:29 +00002000 if (srs >= srssets)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002001 panic("Shadow register set %d not supported", srs);
2002
2003 if (cpu_has_veic) {
2004 if (board_bind_eic_interrupt)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002005 board_bind_eic_interrupt(n, srs);
Ralf Baechle41c594a2006-04-05 09:45:45 +01002006 } else if (cpu_has_vint) {
Ralf Baechlee01402b2005-07-14 15:57:16 +00002007 /* SRSMap is only defined if shadow sets are implemented */
Ralf Baechlef6771db2007-11-08 18:02:29 +00002008 if (srssets > 1)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002009 change_c0_srsmap(0xf << n*4, srs << n*4);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002010 }
2011
2012 if (srs == 0) {
2013 /*
2014 * If no shadow set is selected then use the default handler
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002015 * that does normal register saving and standard interrupt exit
Ralf Baechlee01402b2005-07-14 15:57:16 +00002016 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002017 extern char except_vec_vi, except_vec_vi_lui;
2018 extern char except_vec_vi_ori, except_vec_vi_end;
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002019 extern char rollback_except_vec_vi;
Ralf Baechlef94d9a82013-05-21 17:30:36 +02002020 char *vec_start = using_rollback_handler() ?
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002021 &rollback_except_vec_vi : &except_vec_vi;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002022#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2023 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
2024 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
2025#else
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002026 const int lui_offset = &except_vec_vi_lui - vec_start;
2027 const int ori_offset = &except_vec_vi_ori - vec_start;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002028#endif
2029 const int handler_len = &except_vec_vi_end - vec_start;
Ralf Baechlee01402b2005-07-14 15:57:16 +00002030
2031 if (handler_len > VECTORSPACING) {
2032 /*
2033 * Sigh... panicing won't help as the console
2034 * is probably not configured :(
2035 */
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002036 panic("VECTORSPACING too small");
Ralf Baechlee01402b2005-07-14 15:57:16 +00002037 }
2038
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002039 set_handler(((unsigned long)b - ebase), vec_start,
2040#ifdef CONFIG_CPU_MICROMIPS
2041 (handler_len - 1));
2042#else
2043 handler_len);
2044#endif
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002045 h = (u16 *)(b + lui_offset);
2046 *h = (handler >> 16) & 0xffff;
2047 h = (u16 *)(b + ori_offset);
2048 *h = (handler & 0xffff);
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002049 local_flush_icache_range((unsigned long)b,
2050 (unsigned long)(b+handler_len));
Ralf Baechlee01402b2005-07-14 15:57:16 +00002051 }
2052 else {
2053 /*
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002054 * In other cases jump directly to the interrupt handler. It
2055 * is the handler's responsibility to save registers if required
2056 * (eg hi/lo) and return from the exception using "eret".
Ralf Baechlee01402b2005-07-14 15:57:16 +00002057 */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002058 u32 insn;
2059
2060 h = (u16 *)b;
2061 /* j handler */
2062#ifdef CONFIG_CPU_MICROMIPS
2063 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2064#else
2065 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2066#endif
2067 h[0] = (insn >> 16) & 0xffff;
2068 h[1] = insn & 0xffff;
2069 h[2] = 0;
2070 h[3] = 0;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002071 local_flush_icache_range((unsigned long)b,
2072 (unsigned long)(b+8));
Ralf Baechlee01402b2005-07-14 15:57:16 +00002073 }
2074
2075 return (void *)old_handler;
2076}
2077
Ralf Baechleef300e42007-05-06 18:31:18 +01002078void *set_vi_handler(int n, vi_handler_t addr)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002079{
Ralf Baechleff3eab22006-03-29 14:12:58 +01002080 return set_vi_srs_handler(n, addr, 0);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002081}
Ralf Baechlef41ae0b2006-06-05 17:24:46 +01002082
Linus Torvalds1da177e2005-04-16 15:20:36 -07002083extern void tlb_init(void);
2084
Ralf Baechle42f77542007-10-18 17:48:11 +01002085/*
2086 * Timer interrupt
2087 */
2088int cp0_compare_irq;
Ralf Baechle68b63522012-07-19 09:13:52 +02002089EXPORT_SYMBOL_GPL(cp0_compare_irq);
David VomLehn010c1082009-12-21 17:49:22 -08002090int cp0_compare_irq_shift;
Ralf Baechle42f77542007-10-18 17:48:11 +01002091
2092/*
2093 * Performance counter IRQ or -1 if shared with timer
2094 */
2095int cp0_perfcount_irq;
2096EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2097
James Hogan8f7ff022015-01-29 11:14:07 +00002098/*
2099 * Fast debug channel IRQ or -1 if not present
2100 */
2101int cp0_fdc_irq;
2102EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2103
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002104static int noulri;
Chris Dearmanbdc94eb2007-10-03 10:43:56 +01002105
2106static int __init ulri_disable(char *s)
2107{
2108 pr_info("Disabling ulri\n");
2109 noulri = 1;
2110
2111 return 1;
2112}
2113__setup("noulri", ulri_disable);
2114
James Hoganae4ce452014-03-04 10:20:43 +00002115/* configure STATUS register */
2116static void configure_status(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002117{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002118 /*
2119 * Disable coprocessors and select 32-bit or 64-bit addressing
2120 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2121 * flag that some firmware may have left set and the TS bit (for
2122 * IP27). Set XX for ISA IV code to work.
2123 */
James Hoganae4ce452014-03-04 10:20:43 +00002124 unsigned int status_set = ST0_CU0;
Ralf Baechle875d43e2005-09-03 15:56:16 -07002125#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07002126 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2127#endif
Deng-Cheng Zhuadb37892013-04-01 18:14:28 +00002128 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002129 status_set |= ST0_XX;
Chris Dearmanbbaf2382007-12-13 22:42:19 +00002130 if (cpu_has_dsp)
2131 status_set |= ST0_MX;
2132
Ralf Baechleb38c7392006-02-07 01:20:43 +00002133 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002134 status_set);
James Hoganae4ce452014-03-04 10:20:43 +00002135}
2136
James Hoganb937ff62016-06-15 19:29:53 +01002137unsigned int hwrena;
2138EXPORT_SYMBOL_GPL(hwrena);
2139
James Hoganae4ce452014-03-04 10:20:43 +00002140/* configure HWRENA register */
2141static void configure_hwrena(void)
2142{
James Hoganb937ff62016-06-15 19:29:53 +01002143 hwrena = cpu_hwrena_impl_bits;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002144
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00002145 if (cpu_has_mips_r2_r6)
James Hoganaff565a2016-06-15 19:29:52 +01002146 hwrena |= MIPS_HWRENA_CPUNUM |
2147 MIPS_HWRENA_SYNCISTEP |
2148 MIPS_HWRENA_CC |
2149 MIPS_HWRENA_CCRES;
Ralf Baechlea3692022007-07-10 17:33:02 +01002150
Kevin Cernekee18d693b2010-10-16 14:22:38 -07002151 if (!noulri && cpu_has_userlocal)
James Hoganaff565a2016-06-15 19:29:52 +01002152 hwrena |= MIPS_HWRENA_ULR;
Ralf Baechlea3692022007-07-10 17:33:02 +01002153
Kevin Cernekee18d693b2010-10-16 14:22:38 -07002154 if (hwrena)
2155 write_c0_hwrena(hwrena);
James Hoganae4ce452014-03-04 10:20:43 +00002156}
Ralf Baechlee01402b2005-07-14 15:57:16 +00002157
James Hoganae4ce452014-03-04 10:20:43 +00002158static void configure_exception_vector(void)
2159{
Ralf Baechlee01402b2005-07-14 15:57:16 +00002160 if (cpu_has_veic || cpu_has_vint) {
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002161 unsigned long sr = set_c0_status(ST0_BEV);
Matt Redfearn4b22c692016-09-01 17:30:09 +01002162 /* If available, use WG to set top bits of EBASE */
2163 if (cpu_has_ebase_wg) {
2164#ifdef CONFIG_64BIT
2165 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2166#else
2167 write_c0_ebase(ebase | MIPS_EBASE_WG);
2168#endif
2169 }
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002170 write_c0_ebase(ebase);
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002171 write_c0_status(sr);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002172 /* Setting vector spacing enables EI/VI mode */
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002173 change_c0_intctl(0x3e0, VECTORSPACING);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002174 }
Ralf Baechled03d0a52005-08-17 13:44:26 +00002175 if (cpu_has_divec) {
2176 if (cpu_has_mipsmt) {
2177 unsigned int vpflags = dvpe();
2178 set_c0_cause(CAUSEF_IV);
2179 evpe(vpflags);
2180 } else
2181 set_c0_cause(CAUSEF_IV);
2182 }
James Hoganae4ce452014-03-04 10:20:43 +00002183}
2184
2185void per_cpu_trap_init(bool is_boot_cpu)
2186{
2187 unsigned int cpu = smp_processor_id();
James Hoganae4ce452014-03-04 10:20:43 +00002188
2189 configure_status();
2190 configure_hwrena();
2191
James Hoganae4ce452014-03-04 10:20:43 +00002192 configure_exception_vector();
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002193
2194 /*
2195 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2196 *
2197 * o read IntCtl.IPTI to determine the timer interrupt
2198 * o read IntCtl.IPPCI to determine the performance counter interrupt
James Hogan8f7ff022015-01-29 11:14:07 +00002199 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002200 */
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00002201 if (cpu_has_mips_r2_r6) {
Markos Chandras04d83f92016-02-03 03:15:22 +00002202 /*
2203 * We shouldn't trust a secondary core has a sane EBASE register
2204 * so use the one calculated by the boot CPU.
2205 */
Matt Redfearn4b22c692016-09-01 17:30:09 +01002206 if (!is_boot_cpu) {
2207 /* If available, use WG to set top bits of EBASE */
2208 if (cpu_has_ebase_wg) {
2209#ifdef CONFIG_64BIT
2210 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2211#else
2212 write_c0_ebase(ebase | MIPS_EBASE_WG);
2213#endif
2214 }
Markos Chandras04d83f92016-02-03 03:15:22 +00002215 write_c0_ebase(ebase);
Matt Redfearn4b22c692016-09-01 17:30:09 +01002216 }
Markos Chandras04d83f92016-02-03 03:15:22 +00002217
David VomLehn010c1082009-12-21 17:49:22 -08002218 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2219 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2220 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
James Hogan8f7ff022015-01-29 11:14:07 +00002221 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2222 if (!cp0_fdc_irq)
2223 cp0_fdc_irq = -1;
2224
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002225 } else {
2226 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
Ralf Baechlec6a4ebb2012-07-06 23:56:00 +02002227 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
Chris Dearmanc3e838a2007-06-21 12:59:57 +01002228 cp0_perfcount_irq = -1;
James Hogan8f7ff022015-01-29 11:14:07 +00002229 cp0_fdc_irq = -1;
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002230 }
2231
David Daney48c4ac92013-05-13 13:56:44 -07002232 if (!cpu_data[cpu].asid_cache)
Paul Burton4edf00a2016-05-06 14:36:23 +01002233 cpu_data[cpu].asid_cache = asid_first_version(cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002234
Vegard Nossumf1f10072017-02-27 14:30:07 -08002235 mmgrab(&init_mm);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002236 current->active_mm = &init_mm;
2237 BUG_ON(current->mm);
2238 enter_lazy_tlb(&init_mm, current);
2239
Markos Chandras761b4492015-06-24 09:29:20 +01002240 /* Boot CPU's cache setup in setup_arch(). */
2241 if (!is_boot_cpu)
2242 cpu_cache_init();
2243 tlb_init();
David Daney3d8bfdd2010-12-21 14:19:11 -08002244 TLBMISS_HANDLER_SETUP();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245}
2246
Ralf Baechlee01402b2005-07-14 15:57:16 +00002247/* Install CPU exception handler */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002248void set_handler(unsigned long offset, void *addr, unsigned long size)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002249{
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002250#ifdef CONFIG_CPU_MICROMIPS
2251 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2252#else
Ralf Baechlee01402b2005-07-14 15:57:16 +00002253 memcpy((void *)(ebase + offset), addr, size);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002254#endif
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002255 local_flush_icache_range(ebase + offset, ebase + offset + size);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002256}
2257
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002258static char panic_null_cerr[] =
Ralf Baechle641e97f2007-10-11 23:46:05 +01002259 "Trying to set NULL cache error exception handler";
2260
Ralf Baechle42fe7ee2009-01-28 18:48:23 +00002261/*
2262 * Install uncached CPU exception handler.
2263 * This is suitable only for the cache error exception which is the only
2264 * exception handler that is being run uncached.
2265 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002266void set_uncached_handler(unsigned long offset, void *addr,
Ralf Baechle234fcd12008-03-08 09:56:28 +00002267 unsigned long size)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002268{
Sebastian Andrzej Siewior4f81b012010-04-27 22:53:30 +02002269 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002270
Ralf Baechle641e97f2007-10-11 23:46:05 +01002271 if (!addr)
2272 panic(panic_null_cerr);
2273
Ralf Baechlee01402b2005-07-14 15:57:16 +00002274 memcpy((void *)(uncached_ebase + offset), addr, size);
2275}
2276
Atsushi Nemoto5b104962006-09-11 17:50:29 +09002277static int __initdata rdhwr_noopt;
2278static int __init set_rdhwr_noopt(char *str)
2279{
2280 rdhwr_noopt = 1;
2281 return 1;
2282}
2283
2284__setup("rdhwr_noopt", set_rdhwr_noopt);
2285
Linus Torvalds1da177e2005-04-16 15:20:36 -07002286void __init trap_init(void)
2287{
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002288 extern char except_vec3_generic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002289 extern char except_vec4;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002290 extern char except_vec3_r4000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002291 unsigned long i;
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002292
2293 check_wait();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002294
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002295 if (cpu_has_veic || cpu_has_vint) {
2296 unsigned long size = 0x200 + VECTORSPACING*64;
James Hoganc195e072016-09-01 17:30:08 +01002297 phys_addr_t ebase_pa;
2298
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002299 ebase = (unsigned long)
2300 __alloc_bootmem(size, 1 << fls(size), 0);
James Hoganc195e072016-09-01 17:30:08 +01002301
2302 /*
2303 * Try to ensure ebase resides in KSeg0 if possible.
2304 *
2305 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2306 * hitting a poorly defined exception base for Cache Errors.
2307 * The allocation is likely to be in the low 512MB of physical,
2308 * in which case we should be able to convert to KSeg0.
2309 *
2310 * EVA is special though as it allows segments to be rearranged
2311 * and to become uncached during cache error handling.
2312 */
2313 ebase_pa = __pa(ebase);
2314 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2315 ebase = CKSEG0ADDR(ebase_pa);
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002316 } else {
Paul Burtona13c9962015-09-22 10:15:22 -07002317 ebase = CAC_BASE;
2318
James Hogan18022892016-09-01 17:30:07 +01002319 if (cpu_has_mips_r2_r6) {
2320 if (cpu_has_ebase_wg) {
2321#ifdef CONFIG_64BIT
2322 ebase = (read_c0_ebase_64() & ~0xfff);
2323#else
2324 ebase = (read_c0_ebase() & ~0xfff);
2325#endif
2326 } else {
2327 ebase += (read_c0_ebase() & 0x3ffff000);
2328 }
2329 }
David Daney566f74f2008-10-23 17:56:35 -07002330 }
Ralf Baechlee01402b2005-07-14 15:57:16 +00002331
Steven J. Hillc6213c62013-06-05 21:25:17 +00002332 if (cpu_has_mmips) {
2333 unsigned int config3 = read_c0_config3();
2334
2335 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2336 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2337 else
2338 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2339 }
2340
Kevin Cernekee6fb97ef2011-11-16 01:25:45 +00002341 if (board_ebase_setup)
2342 board_ebase_setup();
David Daney6650df32012-05-15 00:04:50 -07002343 per_cpu_trap_init(true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002344
2345 /*
2346 * Copy the generic exception handlers to their final destination.
Adam Buchbinder92a76f62016-02-25 00:44:58 -08002347 * This will be overridden later as suitable for a particular
Linus Torvalds1da177e2005-04-16 15:20:36 -07002348 * configuration.
2349 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002350 set_handler(0x180, &except_vec3_generic, 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002351
2352 /*
2353 * Setup default vectors
2354 */
2355 for (i = 0; i <= 31; i++)
2356 set_except_vector(i, handle_reserved);
2357
2358 /*
2359 * Copy the EJTAG debug exception vector handler code to it's final
2360 * destination.
2361 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002362 if (cpu_has_ejtag && board_ejtag_handler_setup)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002363 board_ejtag_handler_setup();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002364
2365 /*
2366 * Only some CPUs have the watch exceptions.
2367 */
2368 if (cpu_has_watch)
James Hogan1b505de2015-12-16 23:49:35 +00002369 set_except_vector(EXCCODE_WATCH, handle_watch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002370
2371 /*
Ralf Baechlee01402b2005-07-14 15:57:16 +00002372 * Initialise interrupt handlers
Linus Torvalds1da177e2005-04-16 15:20:36 -07002373 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002374 if (cpu_has_veic || cpu_has_vint) {
2375 int nvec = cpu_has_veic ? 64 : 8;
2376 for (i = 0; i < nvec; i++)
Ralf Baechleff3eab22006-03-29 14:12:58 +01002377 set_vi_handler(i, NULL);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002378 }
2379 else if (cpu_has_divec)
2380 set_handler(0x200, &except_vec4, 0x8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002381
2382 /*
2383 * Some CPUs can enable/disable for cache parity detection, but does
2384 * it different ways.
2385 */
2386 parity_protection_init();
2387
2388 /*
2389 * The Data Bus Errors / Instruction Bus Errors are signaled
2390 * by external hardware. Therefore these two exceptions
2391 * may have board specific handlers.
2392 */
2393 if (board_be_init)
2394 board_be_init();
2395
James Hogan1b505de2015-12-16 23:49:35 +00002396 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2397 rollback_handle_int : handle_int);
2398 set_except_vector(EXCCODE_MOD, handle_tlbm);
2399 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2400 set_except_vector(EXCCODE_TLBS, handle_tlbs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401
James Hogan1b505de2015-12-16 23:49:35 +00002402 set_except_vector(EXCCODE_ADEL, handle_adel);
2403 set_except_vector(EXCCODE_ADES, handle_ades);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002404
James Hogan1b505de2015-12-16 23:49:35 +00002405 set_except_vector(EXCCODE_IBE, handle_ibe);
2406 set_except_vector(EXCCODE_DBE, handle_dbe);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002407
James Hogan1b505de2015-12-16 23:49:35 +00002408 set_except_vector(EXCCODE_SYS, handle_sys);
2409 set_except_vector(EXCCODE_BP, handle_bp);
2410 set_except_vector(EXCCODE_RI, rdhwr_noopt ? handle_ri :
Atsushi Nemoto5b104962006-09-11 17:50:29 +09002411 (cpu_has_vtag_icache ?
2412 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
James Hogan1b505de2015-12-16 23:49:35 +00002413 set_except_vector(EXCCODE_CPU, handle_cpu);
2414 set_except_vector(EXCCODE_OV, handle_ov);
2415 set_except_vector(EXCCODE_TR, handle_tr);
2416 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002417
Ralf Baechle10cc3522007-10-11 23:46:15 +01002418 if (current_cpu_type() == CPU_R6000 ||
2419 current_cpu_type() == CPU_R6000A) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002420 /*
2421 * The R6000 is the only R-series CPU that features a machine
2422 * check exception (similar to the R4000 cache error) and
2423 * unaligned ldc1/sdc1 exception. The handlers have not been
Ralf Baechle70342282013-01-22 12:59:30 +01002424 * written yet. Well, anyway there is no R6000 machine on the
Linus Torvalds1da177e2005-04-16 15:20:36 -07002425 * current list of targets for Linux/MIPS.
2426 * (Duh, crap, there is someone with a triple R6k machine)
2427 */
2428 //set_except_vector(14, handle_mc);
2429 //set_except_vector(15, handle_ndc);
2430 }
2431
Ralf Baechlee01402b2005-07-14 15:57:16 +00002432
2433 if (board_nmi_handler_setup)
2434 board_nmi_handler_setup();
2435
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002436 if (cpu_has_fpu && !cpu_has_nofpuex)
James Hogan1b505de2015-12-16 23:49:35 +00002437 set_except_vector(EXCCODE_FPE, handle_fpe);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002438
James Hogan1b505de2015-12-16 23:49:35 +00002439 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
Leonid Yegoshin5890f702014-07-15 14:09:56 +01002440
2441 if (cpu_has_rixiex) {
James Hogan1b505de2015-12-16 23:49:35 +00002442 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2443 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
Leonid Yegoshin5890f702014-07-15 14:09:56 +01002444 }
2445
James Hogan1b505de2015-12-16 23:49:35 +00002446 set_except_vector(EXCCODE_MSADIS, handle_msa);
2447 set_except_vector(EXCCODE_MDMX, handle_mdmx);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002448
2449 if (cpu_has_mcheck)
James Hogan1b505de2015-12-16 23:49:35 +00002450 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002451
Ralf Baechle340ee4b2005-08-17 17:44:08 +00002452 if (cpu_has_mipsmt)
James Hogan1b505de2015-12-16 23:49:35 +00002453 set_except_vector(EXCCODE_THREAD, handle_mt);
Ralf Baechle340ee4b2005-08-17 17:44:08 +00002454
James Hogan1b505de2015-12-16 23:49:35 +00002455 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002456
David Daneyfcbf1df2012-05-15 00:04:46 -07002457 if (board_cache_error_setup)
2458 board_cache_error_setup();
2459
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002460 if (cpu_has_vce)
2461 /* Special exception: R4[04]00 uses also the divec space. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002462 set_handler(0x180, &except_vec3_r4000, 0x100);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002463 else if (cpu_has_4kex)
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002464 set_handler(0x180, &except_vec3_generic, 0x80);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002465 else
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002466 set_handler(0x080, &except_vec3_generic, 0x80);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002467
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002468 local_flush_icache_range(ebase, ebase + 0x400);
Thomas Bogendoerfer05106172008-08-04 19:44:34 +02002469
2470 sort_extable(__start___dbe_table, __stop___dbe_table);
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00002471
Ralf Baechle4483b152010-08-05 13:25:59 +01002472 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473}
James Hoganae4ce452014-03-04 10:20:43 +00002474
2475static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2476 void *v)
2477{
2478 switch (cmd) {
2479 case CPU_PM_ENTER_FAILED:
2480 case CPU_PM_EXIT:
2481 configure_status();
2482 configure_hwrena();
2483 configure_exception_vector();
2484
2485 /* Restore register with CPU number for TLB handlers */
2486 TLBMISS_HANDLER_RESTORE();
2487
2488 break;
2489 }
2490
2491 return NOTIFY_OK;
2492}
2493
2494static struct notifier_block trap_pm_notifier_block = {
2495 .notifier_call = trap_pm_notifier,
2496};
2497
2498static int __init trap_pm_init(void)
2499{
2500 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2501}
2502arch_initcall(trap_pm_init);