blob: 70e40aaf37d2d1ab2ae6da852b954a6fac1fc68f [file] [log] [blame]
Daniel Scheller4771d832018-06-19 14:50:09 -04001/* SPDX-License-Identifier: GPL-2.0 */
Ralph Metzlerccad04572011-07-03 18:23:11 -03002/*
3 * ddbridge.h: Digital Devices PCIe bridge driver
4 *
Daniel Scheller22e74382017-08-12 07:55:52 -04005 * Copyright (C) 2010-2017 Digital Devices GmbH
6 * Ralph Metzler <rmetzler@digitaldevices.de>
Ralph Metzlerccad04572011-07-03 18:23:11 -03007 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 only, as published by the Free Software Foundation.
11 *
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
Sakari Ailusbcb63312016-10-28 09:31:20 -020018 * To obtain the license, point your browser to
19 * http://www.gnu.org/copyleft/gpl.html
Ralph Metzlerccad04572011-07-03 18:23:11 -030020 */
21
22#ifndef _DDBRIDGE_H_
23#define _DDBRIDGE_H_
24
Daniel Scheller22e74382017-08-12 07:55:52 -040025#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/slab.h>
30#include <linux/poll.h>
31#include <linux/io.h>
32#include <linux/pci.h>
33#include <linux/timer.h>
34#include <linux/i2c.h>
35#include <linux/swab.h>
36#include <linux/vmalloc.h>
37#include <linux/workqueue.h>
38#include <linux/kthread.h>
39#include <linux/platform_device.h>
40#include <linux/clk.h>
41#include <linux/spi/spi.h>
42#include <linux/gpio.h>
43#include <linux/completion.h>
44
Ralph Metzlerccad04572011-07-03 18:23:11 -030045#include <linux/types.h>
46#include <linux/sched.h>
47#include <linux/interrupt.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030048#include <linux/mutex.h>
49#include <asm/dma.h>
Daniel Scheller22e74382017-08-12 07:55:52 -040050#include <asm/irq.h>
51#include <linux/io.h>
52#include <linux/uaccess.h>
53
Ralph Metzlerccad04572011-07-03 18:23:11 -030054#include <linux/dvb/ca.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030055#include <linux/socket.h>
Daniel Scheller22e74382017-08-12 07:55:52 -040056#include <linux/device.h>
57#include <linux/io.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030058
Mauro Carvalho Chehabfada1932017-12-28 13:03:51 -050059#include <media/dmxdev.h>
60#include <media/dvbdev.h>
61#include <media/dvb_demux.h>
62#include <media/dvb_frontend.h>
63#include <media/dvb_ringbuffer.h>
64#include <media/dvb_ca_en50221.h>
65#include <media/dvb_net.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030066
Daniel Schelleredcc3082018-04-09 12:47:52 -040067#define DDBRIDGE_VERSION "0.9.33-integrated"
Daniel Schellera96e5ab2017-07-29 07:28:36 -040068
Daniel Scheller22e74382017-08-12 07:55:52 -040069#define DDB_MAX_I2C 32
70#define DDB_MAX_PORT 32
71#define DDB_MAX_INPUT 64
72#define DDB_MAX_OUTPUT 32
Daniel Scheller1b58a5a2017-04-09 16:38:25 -030073#define DDB_MAX_LINK 4
74#define DDB_LINK_SHIFT 28
75
76#define DDB_LINK_TAG(_x) (_x << DDB_LINK_SHIFT)
Ralph Metzlerccad04572011-07-03 18:23:11 -030077
Daniel Scheller22e74382017-08-12 07:55:52 -040078struct ddb_regset {
79 u32 base;
80 u32 num;
81 u32 size;
82};
83
84struct ddb_regmap {
85 u32 irq_base_i2c;
86 u32 irq_base_idma;
87 u32 irq_base_odma;
88
Daniel Scheller0937e7e2017-08-20 06:41:13 -040089 const struct ddb_regset *i2c;
90 const struct ddb_regset *i2c_buf;
91 const struct ddb_regset *idma;
92 const struct ddb_regset *idma_buf;
93 const struct ddb_regset *odma;
94 const struct ddb_regset *odma_buf;
Daniel Scheller22e74382017-08-12 07:55:52 -040095
Daniel Scheller0937e7e2017-08-20 06:41:13 -040096 const struct ddb_regset *input;
97 const struct ddb_regset *output;
Daniel Scheller22e74382017-08-12 07:55:52 -040098
Daniel Scheller0937e7e2017-08-20 06:41:13 -040099 const struct ddb_regset *channel;
Daniel Scheller22e74382017-08-12 07:55:52 -0400100};
101
102struct ddb_ids {
103 u16 vendor;
104 u16 device;
105 u16 subvendor;
106 u16 subdevice;
107
108 u32 hwid;
109 u32 regmapid;
110 u32 devid;
111 u32 mac;
112};
Daniel Schellere933a6f2017-04-09 16:38:26 -0300113
Ralph Metzlerccad04572011-07-03 18:23:11 -0300114struct ddb_info {
115 int type;
Daniel Schellerc3eda332018-04-09 12:47:50 -0400116#define DDB_NONE 0
117#define DDB_OCTOPUS 1
118#define DDB_OCTOPUS_CI 2
119#define DDB_OCTOPUS_MAX 5
Daniel Scheller22e74382017-08-12 07:55:52 -0400120#define DDB_OCTOPUS_MAX_CT 6
Daniel Schellerc3eda332018-04-09 12:47:50 -0400121#define DDB_OCTOPUS_MCI 9
Ralph Metzlerccad04572011-07-03 18:23:11 -0300122 char *name;
Daniel Scheller22e74382017-08-12 07:55:52 -0400123 u32 i2c_mask;
Daniel Scheller07b12de2018-06-23 11:36:09 -0400124 u32 board_control;
125 u32 board_control_2;
126
Daniel Scheller22e74382017-08-12 07:55:52 -0400127 u8 port_num;
128 u8 led_num;
129 u8 fan_num;
130 u8 temp_num;
131 u8 temp_bus;
Daniel Scheller22e74382017-08-12 07:55:52 -0400132 u8 con_clock; /* use a continuous clock */
Daniel Scheller1b58a5a2017-04-09 16:38:25 -0300133 u8 ts_quirks;
134#define TS_QUIRK_SERIAL 1
135#define TS_QUIRK_REVERSED 2
136#define TS_QUIRK_ALT_OSC 8
Daniel Scheller07b12de2018-06-23 11:36:09 -0400137 u8 mci_ports;
138 u8 mci_type;
139
Daniel Scheller22e74382017-08-12 07:55:52 -0400140 u32 tempmon_irq;
Daniel Scheller0937e7e2017-08-20 06:41:13 -0400141 const struct ddb_regmap *regmap;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300142};
143
Daniel Scheller22e74382017-08-12 07:55:52 -0400144#define DMA_MAX_BUFS 32 /* hardware table limit */
145
Ralph Metzlerccad04572011-07-03 18:23:11 -0300146struct ddb;
147struct ddb_port;
148
Daniel Scheller22e74382017-08-12 07:55:52 -0400149struct ddb_dma {
150 void *io;
151 u32 regs;
152 u32 bufregs;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300153
Daniel Scheller22e74382017-08-12 07:55:52 -0400154 dma_addr_t pbuf[DMA_MAX_BUFS];
155 u8 *vbuf[DMA_MAX_BUFS];
156 u32 num;
157 u32 size;
158 u32 div;
159 u32 bufval;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300160
Daniel Scheller22e74382017-08-12 07:55:52 -0400161 struct work_struct work;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400162 spinlock_t lock; /* DMA lock */
Ralph Metzlerccad04572011-07-03 18:23:11 -0300163 wait_queue_head_t wq;
164 int running;
165 u32 stat;
Daniel Scheller22e74382017-08-12 07:55:52 -0400166 u32 ctrl;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300167 u32 cbuf;
168 u32 coff;
Daniel Scheller22e74382017-08-12 07:55:52 -0400169};
Ralph Metzlerccad04572011-07-03 18:23:11 -0300170
Daniel Scheller22e74382017-08-12 07:55:52 -0400171struct ddb_dvb {
172 struct dvb_adapter *adap;
173 int adap_registered;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300174 struct dvb_device *dev;
Daniel Scheller05da9432017-03-29 13:43:13 -0300175 struct i2c_client *i2c_client[1];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300176 struct dvb_frontend *fe;
177 struct dvb_frontend *fe2;
178 struct dmxdev dmxdev;
179 struct dvb_demux demux;
180 struct dvb_net dvbnet;
181 struct dmx_frontend hw_frontend;
182 struct dmx_frontend mem_frontend;
183 int users;
Daniel Scheller22e74382017-08-12 07:55:52 -0400184 u32 attached;
185 u8 input;
186
187 enum fe_sec_tone_mode tone;
188 enum fe_sec_voltage voltage;
189
190 int (*i2c_gate_ctrl)(struct dvb_frontend *, int);
191 int (*set_voltage)(struct dvb_frontend *fe,
Daniel Scheller757d78d2017-10-15 16:51:51 -0400192 enum fe_sec_voltage voltage);
Daniel Scheller22e74382017-08-12 07:55:52 -0400193 int (*set_input)(struct dvb_frontend *fe, int input);
194 int (*diseqc_send_master_cmd)(struct dvb_frontend *fe,
Daniel Scheller757d78d2017-10-15 16:51:51 -0400195 struct dvb_diseqc_master_cmd *cmd);
Ralph Metzlerccad04572011-07-03 18:23:11 -0300196};
197
Daniel Scheller22e74382017-08-12 07:55:52 -0400198struct ddb_ci {
199 struct dvb_ca_en50221 en;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300200 struct ddb_port *port;
201 u32 nr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300202};
203
Daniel Scheller22e74382017-08-12 07:55:52 -0400204struct ddb_io {
205 struct ddb_port *port;
206 u32 nr;
207 u32 regs;
208 struct ddb_dma *dma;
209 struct ddb_io *redo;
210 struct ddb_io *redi;
211};
212
213#define ddb_output ddb_io
214#define ddb_input ddb_io
215
Ralph Metzlerccad04572011-07-03 18:23:11 -0300216struct ddb_i2c {
217 struct ddb *dev;
218 u32 nr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300219 u32 regs;
Daniel Scheller22e74382017-08-12 07:55:52 -0400220 u32 link;
221 struct i2c_adapter adap;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300222 u32 rbuf;
223 u32 wbuf;
Daniel Scheller22e74382017-08-12 07:55:52 -0400224 u32 bsize;
225 struct completion completion;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300226};
227
228struct ddb_port {
229 struct ddb *dev;
230 u32 nr;
Daniel Scheller22e74382017-08-12 07:55:52 -0400231 u32 pnr;
232 u32 regs;
233 u32 lnr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300234 struct ddb_i2c *i2c;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400235 struct mutex i2c_gate_lock; /* I2C access lock */
Ralph Metzlerccad04572011-07-03 18:23:11 -0300236 u32 class;
237#define DDB_PORT_NONE 0
238#define DDB_PORT_CI 1
239#define DDB_PORT_TUNER 2
Daniel Scheller22e74382017-08-12 07:55:52 -0400240#define DDB_PORT_LOOP 3
241 char *name;
242 char *type_name;
243 u32 type;
Daniel Schellerab123972018-04-09 12:47:47 -0400244#define DDB_TUNER_DUMMY 0xffffffff
Daniel Scheller22e74382017-08-12 07:55:52 -0400245#define DDB_TUNER_NONE 0
246#define DDB_TUNER_DVBS_ST 1
247#define DDB_TUNER_DVBS_ST_AA 2
248#define DDB_TUNER_DVBCT_TR 3
249#define DDB_TUNER_DVBCT_ST 4
250#define DDB_CI_INTERNAL 5
251#define DDB_CI_EXTERNAL_SONY 6
252#define DDB_TUNER_DVBCT2_SONY_P 7
253#define DDB_TUNER_DVBC2T2_SONY_P 8
254#define DDB_TUNER_ISDBT_SONY_P 9
255#define DDB_TUNER_DVBS_STV0910_P 10
256#define DDB_TUNER_MXL5XX 11
257#define DDB_CI_EXTERNAL_XO2 12
258#define DDB_CI_EXTERNAL_XO2_B 13
259#define DDB_TUNER_DVBS_STV0910_PR 14
260#define DDB_TUNER_DVBC2T2I_SONY_P 15
Daniel Schellere933a6f2017-04-09 16:38:26 -0300261
Daniel Scheller22e74382017-08-12 07:55:52 -0400262#define DDB_TUNER_XO2 32
263#define DDB_TUNER_DVBS_STV0910 (DDB_TUNER_XO2 + 0)
264#define DDB_TUNER_DVBCT2_SONY (DDB_TUNER_XO2 + 1)
265#define DDB_TUNER_ISDBT_SONY (DDB_TUNER_XO2 + 2)
266#define DDB_TUNER_DVBC2T2_SONY (DDB_TUNER_XO2 + 3)
267#define DDB_TUNER_ATSC_ST (DDB_TUNER_XO2 + 4)
268#define DDB_TUNER_DVBC2T2I_SONY (DDB_TUNER_XO2 + 5)
Ralph Metzlerccad04572011-07-03 18:23:11 -0300269
Daniel Scheller9f269f12018-06-23 11:36:04 -0400270#define DDB_TUNER_MCI 48
271#define DDB_TUNER_MCI_SX8 (DDB_TUNER_MCI + 0)
272
Ralph Metzlerccad04572011-07-03 18:23:11 -0300273 struct ddb_input *input[2];
274 struct ddb_output *output;
275 struct dvb_ca_en50221 *en;
Daniel Schellere5eaf6f2018-03-06 11:39:10 -0500276 u8 en_freedata;
Daniel Scheller22e74382017-08-12 07:55:52 -0400277 struct ddb_dvb dvb[2];
278 u32 gap;
279 u32 obr;
280 u8 creg;
281};
282
283#define CM_STARTUP_DELAY 2
284#define CM_AVERAGE 20
285#define CM_GAIN 10
286
287#define HW_LSB_SHIFT 12
288#define HW_LSB_MASK 0x1000
289
290#define CM_IDLE 0
291#define CM_STARTUP 1
292#define CM_ADJUST 2
293
294#define TS_CAPTURE_LEN (4096)
295
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400296struct ddb_lnb {
Daniel Scheller757d78d2017-10-15 16:51:51 -0400297 struct mutex lock; /* lock lnb access */
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400298 u32 tone;
299 enum fe_sec_voltage oldvoltage[4];
300 u32 voltage[4];
301 u32 voltages;
302 u32 fmode;
303};
304
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400305struct ddb_irq {
306 void (*handler)(void *);
307 void *data;
308};
309
Daniel Scheller22e74382017-08-12 07:55:52 -0400310struct ddb_link {
311 struct ddb *dev;
Daniel Scheller66cc3d92017-08-20 06:41:11 -0400312 const struct ddb_info *info;
Daniel Scheller22e74382017-08-12 07:55:52 -0400313 u32 nr;
314 u32 regs;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400315 spinlock_t lock; /* lock link access */
316 struct mutex flash_mutex; /* lock flash access */
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400317 struct ddb_lnb lnb;
Daniel Scheller22e74382017-08-12 07:55:52 -0400318 struct tasklet_struct tasklet;
319 struct ddb_ids ids;
320
Daniel Scheller757d78d2017-10-15 16:51:51 -0400321 spinlock_t temp_lock; /* lock temp chip access */
Daniel Scheller22e74382017-08-12 07:55:52 -0400322 int overtemperature_error;
323 u8 temp_tab[11];
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400324 struct ddb_irq irq[256];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300325};
326
327struct ddb {
Daniel Scheller757d78d2017-10-15 16:51:51 -0400328 struct pci_dev *pdev;
329 struct platform_device *pfdev;
330 struct device *dev;
Daniel Scheller22e74382017-08-12 07:55:52 -0400331
Daniel Scheller757d78d2017-10-15 16:51:51 -0400332 int msi;
Daniel Scheller22e74382017-08-12 07:55:52 -0400333 struct workqueue_struct *wq;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400334 u32 has_dma;
Daniel Scheller22e74382017-08-12 07:55:52 -0400335
Daniel Scheller757d78d2017-10-15 16:51:51 -0400336 struct ddb_link link[DDB_MAX_LINK];
337 unsigned char __iomem *regs;
338 u32 regs_len;
339 u32 port_num;
340 struct ddb_port port[DDB_MAX_PORT];
341 u32 i2c_num;
342 struct ddb_i2c i2c[DDB_MAX_I2C];
343 struct ddb_input input[DDB_MAX_INPUT];
344 struct ddb_output output[DDB_MAX_OUTPUT];
345 struct dvb_adapter adap[DDB_MAX_INPUT];
346 struct ddb_dma idma[DDB_MAX_INPUT];
347 struct ddb_dma odma[DDB_MAX_OUTPUT];
Daniel Scheller22e74382017-08-12 07:55:52 -0400348
Daniel Scheller757d78d2017-10-15 16:51:51 -0400349 struct device *ddb_dev;
350 u32 ddb_dev_users;
351 u32 nr;
352 u8 iobuf[1028];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300353
Daniel Scheller757d78d2017-10-15 16:51:51 -0400354 u8 leds;
355 u32 ts_irq;
356 u32 i2c_irq;
Daniel Scheller22e74382017-08-12 07:55:52 -0400357
Daniel Scheller757d78d2017-10-15 16:51:51 -0400358 struct mutex mutex; /* lock access to global ddb array */
Daniel Scheller22e74382017-08-12 07:55:52 -0400359
Daniel Scheller757d78d2017-10-15 16:51:51 -0400360 u8 tsbuf[TS_CAPTURE_LEN];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300361};
362
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400363/****************************************************************************/
Daniel Scheller22e74382017-08-12 07:55:52 -0400364/****************************************************************************/
365/****************************************************************************/
366
367int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);
368
369/****************************************************************************/
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400370
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400371/* ddbridge-core.c */
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400372struct ddb_irq *ddb_irq_set(struct ddb *dev, u32 link, u32 nr,
373 void (*handler)(void *), void *data);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400374void ddb_ports_detach(struct ddb *dev);
375void ddb_ports_release(struct ddb *dev);
376void ddb_buffers_free(struct ddb *dev);
377void ddb_device_destroy(struct ddb *dev);
Daniel Scheller22e74382017-08-12 07:55:52 -0400378irqreturn_t ddb_irq_handler0(int irq, void *dev_id);
379irqreturn_t ddb_irq_handler1(int irq, void *dev_id);
380irqreturn_t ddb_irq_handler(int irq, void *dev_id);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400381void ddb_ports_init(struct ddb *dev);
382int ddb_buffers_alloc(struct ddb *dev);
383int ddb_ports_attach(struct ddb *dev);
384int ddb_device_create(struct ddb *dev);
Daniel Scheller22e74382017-08-12 07:55:52 -0400385int ddb_init(struct ddb *dev);
Daniel Scheller8e4eef22017-08-20 06:41:10 -0400386void ddb_unmap(struct ddb *dev);
Daniel Scheller05ed62d2018-04-09 12:47:37 -0400387int ddb_exit_ddbridge(int stage, int error);
388int ddb_init_ddbridge(void);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400389
Daniel Scheller22e74382017-08-12 07:55:52 -0400390#endif /* DDBRIDGE_H */