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Ralph Metzlerccad04572011-07-03 18:23:11 -03001/*
2 * ddbridge.h: Digital Devices PCIe bridge driver
3 *
Daniel Scheller22e74382017-08-12 07:55:52 -04004 * Copyright (C) 2010-2017 Digital Devices GmbH
5 * Ralph Metzler <rmetzler@digitaldevices.de>
Ralph Metzlerccad04572011-07-03 18:23:11 -03006 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 only, as published by the Free Software Foundation.
10 *
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
Sakari Ailusbcb63312016-10-28 09:31:20 -020017 * To obtain the license, point your browser to
18 * http://www.gnu.org/copyleft/gpl.html
Ralph Metzlerccad04572011-07-03 18:23:11 -030019 */
20
21#ifndef _DDBRIDGE_H_
22#define _DDBRIDGE_H_
23
Daniel Scheller22e74382017-08-12 07:55:52 -040024#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/poll.h>
30#include <linux/io.h>
31#include <linux/pci.h>
32#include <linux/timer.h>
33#include <linux/i2c.h>
34#include <linux/swab.h>
35#include <linux/vmalloc.h>
36#include <linux/workqueue.h>
37#include <linux/kthread.h>
38#include <linux/platform_device.h>
39#include <linux/clk.h>
40#include <linux/spi/spi.h>
41#include <linux/gpio.h>
42#include <linux/completion.h>
43
Ralph Metzlerccad04572011-07-03 18:23:11 -030044#include <linux/types.h>
45#include <linux/sched.h>
46#include <linux/interrupt.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030047#include <linux/mutex.h>
48#include <asm/dma.h>
Daniel Scheller22e74382017-08-12 07:55:52 -040049#include <asm/irq.h>
50#include <linux/io.h>
51#include <linux/uaccess.h>
52
Ralph Metzlerccad04572011-07-03 18:23:11 -030053#include <linux/dvb/ca.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030054#include <linux/socket.h>
Daniel Scheller22e74382017-08-12 07:55:52 -040055#include <linux/device.h>
56#include <linux/io.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030057
Mauro Carvalho Chehabfada1932017-12-28 13:03:51 -050058#include <media/dmxdev.h>
59#include <media/dvbdev.h>
60#include <media/dvb_demux.h>
61#include <media/dvb_frontend.h>
62#include <media/dvb_ringbuffer.h>
63#include <media/dvb_ca_en50221.h>
64#include <media/dvb_net.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030065
Daniel Scheller40f80612017-10-15 16:51:57 -040066#define DDBRIDGE_VERSION "0.9.32-integrated"
Daniel Schellera96e5ab2017-07-29 07:28:36 -040067
Daniel Scheller22e74382017-08-12 07:55:52 -040068#define DDB_MAX_I2C 32
69#define DDB_MAX_PORT 32
70#define DDB_MAX_INPUT 64
71#define DDB_MAX_OUTPUT 32
Daniel Scheller1b58a5a2017-04-09 16:38:25 -030072#define DDB_MAX_LINK 4
73#define DDB_LINK_SHIFT 28
74
75#define DDB_LINK_TAG(_x) (_x << DDB_LINK_SHIFT)
Ralph Metzlerccad04572011-07-03 18:23:11 -030076
Daniel Scheller22e74382017-08-12 07:55:52 -040077struct ddb_regset {
78 u32 base;
79 u32 num;
80 u32 size;
81};
82
83struct ddb_regmap {
84 u32 irq_base_i2c;
85 u32 irq_base_idma;
86 u32 irq_base_odma;
87
Daniel Scheller0937e7e2017-08-20 06:41:13 -040088 const struct ddb_regset *i2c;
89 const struct ddb_regset *i2c_buf;
90 const struct ddb_regset *idma;
91 const struct ddb_regset *idma_buf;
92 const struct ddb_regset *odma;
93 const struct ddb_regset *odma_buf;
Daniel Scheller22e74382017-08-12 07:55:52 -040094
Daniel Scheller0937e7e2017-08-20 06:41:13 -040095 const struct ddb_regset *input;
96 const struct ddb_regset *output;
Daniel Scheller22e74382017-08-12 07:55:52 -040097
Daniel Scheller0937e7e2017-08-20 06:41:13 -040098 const struct ddb_regset *channel;
Daniel Scheller22e74382017-08-12 07:55:52 -040099};
100
101struct ddb_ids {
102 u16 vendor;
103 u16 device;
104 u16 subvendor;
105 u16 subdevice;
106
107 u32 hwid;
108 u32 regmapid;
109 u32 devid;
110 u32 mac;
111};
Daniel Schellere933a6f2017-04-09 16:38:26 -0300112
Ralph Metzlerccad04572011-07-03 18:23:11 -0300113struct ddb_info {
114 int type;
Daniel Scheller22e74382017-08-12 07:55:52 -0400115#define DDB_NONE 0
116#define DDB_OCTOPUS 1
117#define DDB_OCTOPUS_CI 2
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400118#define DDB_OCTOPUS_MAX 5
Daniel Scheller22e74382017-08-12 07:55:52 -0400119#define DDB_OCTOPUS_MAX_CT 6
Ralph Metzlerccad04572011-07-03 18:23:11 -0300120 char *name;
Daniel Scheller22e74382017-08-12 07:55:52 -0400121 u32 i2c_mask;
122 u8 port_num;
123 u8 led_num;
124 u8 fan_num;
125 u8 temp_num;
126 u8 temp_bus;
Daniel Scheller1b58a5a2017-04-09 16:38:25 -0300127 u32 board_control;
128 u32 board_control_2;
Daniel Scheller22e74382017-08-12 07:55:52 -0400129 u8 mdio_num;
130 u8 con_clock; /* use a continuous clock */
Daniel Scheller1b58a5a2017-04-09 16:38:25 -0300131 u8 ts_quirks;
132#define TS_QUIRK_SERIAL 1
133#define TS_QUIRK_REVERSED 2
134#define TS_QUIRK_ALT_OSC 8
Daniel Scheller22e74382017-08-12 07:55:52 -0400135 u32 tempmon_irq;
Daniel Scheller0937e7e2017-08-20 06:41:13 -0400136 const struct ddb_regmap *regmap;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300137};
138
Daniel Scheller22e74382017-08-12 07:55:52 -0400139#define DMA_MAX_BUFS 32 /* hardware table limit */
140
Ralph Metzlerccad04572011-07-03 18:23:11 -0300141struct ddb;
142struct ddb_port;
143
Daniel Scheller22e74382017-08-12 07:55:52 -0400144struct ddb_dma {
145 void *io;
146 u32 regs;
147 u32 bufregs;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300148
Daniel Scheller22e74382017-08-12 07:55:52 -0400149 dma_addr_t pbuf[DMA_MAX_BUFS];
150 u8 *vbuf[DMA_MAX_BUFS];
151 u32 num;
152 u32 size;
153 u32 div;
154 u32 bufval;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300155
Daniel Scheller22e74382017-08-12 07:55:52 -0400156 struct work_struct work;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400157 spinlock_t lock; /* DMA lock */
Ralph Metzlerccad04572011-07-03 18:23:11 -0300158 wait_queue_head_t wq;
159 int running;
160 u32 stat;
Daniel Scheller22e74382017-08-12 07:55:52 -0400161 u32 ctrl;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300162 u32 cbuf;
163 u32 coff;
Daniel Scheller22e74382017-08-12 07:55:52 -0400164};
Ralph Metzlerccad04572011-07-03 18:23:11 -0300165
Daniel Scheller22e74382017-08-12 07:55:52 -0400166struct ddb_dvb {
167 struct dvb_adapter *adap;
168 int adap_registered;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300169 struct dvb_device *dev;
Daniel Scheller05da9432017-03-29 13:43:13 -0300170 struct i2c_client *i2c_client[1];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300171 struct dvb_frontend *fe;
172 struct dvb_frontend *fe2;
173 struct dmxdev dmxdev;
174 struct dvb_demux demux;
175 struct dvb_net dvbnet;
176 struct dmx_frontend hw_frontend;
177 struct dmx_frontend mem_frontend;
178 int users;
Daniel Scheller22e74382017-08-12 07:55:52 -0400179 u32 attached;
180 u8 input;
181
182 enum fe_sec_tone_mode tone;
183 enum fe_sec_voltage voltage;
184
185 int (*i2c_gate_ctrl)(struct dvb_frontend *, int);
186 int (*set_voltage)(struct dvb_frontend *fe,
Daniel Scheller757d78d2017-10-15 16:51:51 -0400187 enum fe_sec_voltage voltage);
Daniel Scheller22e74382017-08-12 07:55:52 -0400188 int (*set_input)(struct dvb_frontend *fe, int input);
189 int (*diseqc_send_master_cmd)(struct dvb_frontend *fe,
Daniel Scheller757d78d2017-10-15 16:51:51 -0400190 struct dvb_diseqc_master_cmd *cmd);
Ralph Metzlerccad04572011-07-03 18:23:11 -0300191};
192
Daniel Scheller22e74382017-08-12 07:55:52 -0400193struct ddb_ci {
194 struct dvb_ca_en50221 en;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300195 struct ddb_port *port;
196 u32 nr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300197};
198
Daniel Scheller22e74382017-08-12 07:55:52 -0400199struct ddb_io {
200 struct ddb_port *port;
201 u32 nr;
202 u32 regs;
203 struct ddb_dma *dma;
204 struct ddb_io *redo;
205 struct ddb_io *redi;
206};
207
208#define ddb_output ddb_io
209#define ddb_input ddb_io
210
Ralph Metzlerccad04572011-07-03 18:23:11 -0300211struct ddb_i2c {
212 struct ddb *dev;
213 u32 nr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300214 u32 regs;
Daniel Scheller22e74382017-08-12 07:55:52 -0400215 u32 link;
216 struct i2c_adapter adap;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300217 u32 rbuf;
218 u32 wbuf;
Daniel Scheller22e74382017-08-12 07:55:52 -0400219 u32 bsize;
220 struct completion completion;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300221};
222
223struct ddb_port {
224 struct ddb *dev;
225 u32 nr;
Daniel Scheller22e74382017-08-12 07:55:52 -0400226 u32 pnr;
227 u32 regs;
228 u32 lnr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300229 struct ddb_i2c *i2c;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400230 struct mutex i2c_gate_lock; /* I2C access lock */
Ralph Metzlerccad04572011-07-03 18:23:11 -0300231 u32 class;
232#define DDB_PORT_NONE 0
233#define DDB_PORT_CI 1
234#define DDB_PORT_TUNER 2
Daniel Scheller22e74382017-08-12 07:55:52 -0400235#define DDB_PORT_LOOP 3
236 char *name;
237 char *type_name;
238 u32 type;
Daniel Schellerab123972018-04-09 12:47:47 -0400239#define DDB_TUNER_DUMMY 0xffffffff
Daniel Scheller22e74382017-08-12 07:55:52 -0400240#define DDB_TUNER_NONE 0
241#define DDB_TUNER_DVBS_ST 1
242#define DDB_TUNER_DVBS_ST_AA 2
243#define DDB_TUNER_DVBCT_TR 3
244#define DDB_TUNER_DVBCT_ST 4
245#define DDB_CI_INTERNAL 5
246#define DDB_CI_EXTERNAL_SONY 6
247#define DDB_TUNER_DVBCT2_SONY_P 7
248#define DDB_TUNER_DVBC2T2_SONY_P 8
249#define DDB_TUNER_ISDBT_SONY_P 9
250#define DDB_TUNER_DVBS_STV0910_P 10
251#define DDB_TUNER_MXL5XX 11
252#define DDB_CI_EXTERNAL_XO2 12
253#define DDB_CI_EXTERNAL_XO2_B 13
254#define DDB_TUNER_DVBS_STV0910_PR 14
255#define DDB_TUNER_DVBC2T2I_SONY_P 15
Daniel Schellere933a6f2017-04-09 16:38:26 -0300256
Daniel Scheller22e74382017-08-12 07:55:52 -0400257#define DDB_TUNER_XO2 32
258#define DDB_TUNER_DVBS_STV0910 (DDB_TUNER_XO2 + 0)
259#define DDB_TUNER_DVBCT2_SONY (DDB_TUNER_XO2 + 1)
260#define DDB_TUNER_ISDBT_SONY (DDB_TUNER_XO2 + 2)
261#define DDB_TUNER_DVBC2T2_SONY (DDB_TUNER_XO2 + 3)
262#define DDB_TUNER_ATSC_ST (DDB_TUNER_XO2 + 4)
263#define DDB_TUNER_DVBC2T2I_SONY (DDB_TUNER_XO2 + 5)
Ralph Metzlerccad04572011-07-03 18:23:11 -0300264
265 struct ddb_input *input[2];
266 struct ddb_output *output;
267 struct dvb_ca_en50221 *en;
Daniel Schellere5eaf6f2018-03-06 11:39:10 -0500268 u8 en_freedata;
Daniel Scheller22e74382017-08-12 07:55:52 -0400269 struct ddb_dvb dvb[2];
270 u32 gap;
271 u32 obr;
272 u8 creg;
273};
274
275#define CM_STARTUP_DELAY 2
276#define CM_AVERAGE 20
277#define CM_GAIN 10
278
279#define HW_LSB_SHIFT 12
280#define HW_LSB_MASK 0x1000
281
282#define CM_IDLE 0
283#define CM_STARTUP 1
284#define CM_ADJUST 2
285
286#define TS_CAPTURE_LEN (4096)
287
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400288struct ddb_lnb {
Daniel Scheller757d78d2017-10-15 16:51:51 -0400289 struct mutex lock; /* lock lnb access */
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400290 u32 tone;
291 enum fe_sec_voltage oldvoltage[4];
292 u32 voltage[4];
293 u32 voltages;
294 u32 fmode;
295};
296
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400297struct ddb_irq {
298 void (*handler)(void *);
299 void *data;
300};
301
Daniel Scheller22e74382017-08-12 07:55:52 -0400302struct ddb_link {
303 struct ddb *dev;
Daniel Scheller66cc3d92017-08-20 06:41:11 -0400304 const struct ddb_info *info;
Daniel Scheller22e74382017-08-12 07:55:52 -0400305 u32 nr;
306 u32 regs;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400307 spinlock_t lock; /* lock link access */
308 struct mutex flash_mutex; /* lock flash access */
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400309 struct ddb_lnb lnb;
Daniel Scheller22e74382017-08-12 07:55:52 -0400310 struct tasklet_struct tasklet;
311 struct ddb_ids ids;
312
Daniel Scheller757d78d2017-10-15 16:51:51 -0400313 spinlock_t temp_lock; /* lock temp chip access */
Daniel Scheller22e74382017-08-12 07:55:52 -0400314 int overtemperature_error;
315 u8 temp_tab[11];
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400316 struct ddb_irq irq[256];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300317};
318
319struct ddb {
Daniel Scheller757d78d2017-10-15 16:51:51 -0400320 struct pci_dev *pdev;
321 struct platform_device *pfdev;
322 struct device *dev;
Daniel Scheller22e74382017-08-12 07:55:52 -0400323
Daniel Scheller757d78d2017-10-15 16:51:51 -0400324 int msi;
Daniel Scheller22e74382017-08-12 07:55:52 -0400325 struct workqueue_struct *wq;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400326 u32 has_dma;
Daniel Scheller22e74382017-08-12 07:55:52 -0400327
Daniel Scheller757d78d2017-10-15 16:51:51 -0400328 struct ddb_link link[DDB_MAX_LINK];
329 unsigned char __iomem *regs;
330 u32 regs_len;
331 u32 port_num;
332 struct ddb_port port[DDB_MAX_PORT];
333 u32 i2c_num;
334 struct ddb_i2c i2c[DDB_MAX_I2C];
335 struct ddb_input input[DDB_MAX_INPUT];
336 struct ddb_output output[DDB_MAX_OUTPUT];
337 struct dvb_adapter adap[DDB_MAX_INPUT];
338 struct ddb_dma idma[DDB_MAX_INPUT];
339 struct ddb_dma odma[DDB_MAX_OUTPUT];
Daniel Scheller22e74382017-08-12 07:55:52 -0400340
Daniel Scheller757d78d2017-10-15 16:51:51 -0400341 struct device *ddb_dev;
342 u32 ddb_dev_users;
343 u32 nr;
344 u8 iobuf[1028];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300345
Daniel Scheller757d78d2017-10-15 16:51:51 -0400346 u8 leds;
347 u32 ts_irq;
348 u32 i2c_irq;
Daniel Scheller22e74382017-08-12 07:55:52 -0400349
Daniel Scheller757d78d2017-10-15 16:51:51 -0400350 struct mutex mutex; /* lock access to global ddb array */
Daniel Scheller22e74382017-08-12 07:55:52 -0400351
Daniel Scheller757d78d2017-10-15 16:51:51 -0400352 u8 tsbuf[TS_CAPTURE_LEN];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300353};
354
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400355/****************************************************************************/
Daniel Scheller22e74382017-08-12 07:55:52 -0400356/****************************************************************************/
357/****************************************************************************/
358
359int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);
360
361/****************************************************************************/
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400362
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400363/* ddbridge-core.c */
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400364struct ddb_irq *ddb_irq_set(struct ddb *dev, u32 link, u32 nr,
365 void (*handler)(void *), void *data);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400366void ddb_ports_detach(struct ddb *dev);
367void ddb_ports_release(struct ddb *dev);
368void ddb_buffers_free(struct ddb *dev);
369void ddb_device_destroy(struct ddb *dev);
Daniel Scheller22e74382017-08-12 07:55:52 -0400370irqreturn_t ddb_irq_handler0(int irq, void *dev_id);
371irqreturn_t ddb_irq_handler1(int irq, void *dev_id);
372irqreturn_t ddb_irq_handler(int irq, void *dev_id);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400373void ddb_ports_init(struct ddb *dev);
374int ddb_buffers_alloc(struct ddb *dev);
375int ddb_ports_attach(struct ddb *dev);
376int ddb_device_create(struct ddb *dev);
Daniel Scheller22e74382017-08-12 07:55:52 -0400377int ddb_init(struct ddb *dev);
Daniel Scheller8e4eef22017-08-20 06:41:10 -0400378void ddb_unmap(struct ddb *dev);
Daniel Scheller05ed62d2018-04-09 12:47:37 -0400379int ddb_exit_ddbridge(int stage, int error);
380int ddb_init_ddbridge(void);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400381
Daniel Scheller22e74382017-08-12 07:55:52 -0400382#endif /* DDBRIDGE_H */