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Ralph Metzlerccad04572011-07-03 18:23:11 -03001/*
2 * ddbridge.h: Digital Devices PCIe bridge driver
3 *
Daniel Scheller22e74382017-08-12 07:55:52 -04004 * Copyright (C) 2010-2017 Digital Devices GmbH
5 * Ralph Metzler <rmetzler@digitaldevices.de>
Ralph Metzlerccad04572011-07-03 18:23:11 -03006 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 only, as published by the Free Software Foundation.
10 *
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
Sakari Ailusbcb63312016-10-28 09:31:20 -020017 * To obtain the license, point your browser to
18 * http://www.gnu.org/copyleft/gpl.html
Ralph Metzlerccad04572011-07-03 18:23:11 -030019 */
20
21#ifndef _DDBRIDGE_H_
22#define _DDBRIDGE_H_
23
Daniel Scheller22e74382017-08-12 07:55:52 -040024#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/poll.h>
30#include <linux/io.h>
31#include <linux/pci.h>
32#include <linux/timer.h>
33#include <linux/i2c.h>
34#include <linux/swab.h>
35#include <linux/vmalloc.h>
36#include <linux/workqueue.h>
37#include <linux/kthread.h>
38#include <linux/platform_device.h>
39#include <linux/clk.h>
40#include <linux/spi/spi.h>
41#include <linux/gpio.h>
42#include <linux/completion.h>
43
Ralph Metzlerccad04572011-07-03 18:23:11 -030044#include <linux/types.h>
45#include <linux/sched.h>
46#include <linux/interrupt.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030047#include <linux/mutex.h>
48#include <asm/dma.h>
Daniel Scheller22e74382017-08-12 07:55:52 -040049#include <asm/irq.h>
50#include <linux/io.h>
51#include <linux/uaccess.h>
52
Ralph Metzlerccad04572011-07-03 18:23:11 -030053#include <linux/dvb/ca.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030054#include <linux/socket.h>
Daniel Scheller22e74382017-08-12 07:55:52 -040055#include <linux/device.h>
56#include <linux/io.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030057
Mauro Carvalho Chehabfada1932017-12-28 13:03:51 -050058#include <media/dmxdev.h>
59#include <media/dvbdev.h>
60#include <media/dvb_demux.h>
61#include <media/dvb_frontend.h>
62#include <media/dvb_ringbuffer.h>
63#include <media/dvb_ca_en50221.h>
64#include <media/dvb_net.h>
Ralph Metzlerccad04572011-07-03 18:23:11 -030065
Daniel Scheller40f80612017-10-15 16:51:57 -040066#define DDBRIDGE_VERSION "0.9.32-integrated"
Daniel Schellera96e5ab2017-07-29 07:28:36 -040067
Daniel Scheller22e74382017-08-12 07:55:52 -040068#define DDB_MAX_I2C 32
69#define DDB_MAX_PORT 32
70#define DDB_MAX_INPUT 64
71#define DDB_MAX_OUTPUT 32
Daniel Scheller1b58a5a2017-04-09 16:38:25 -030072#define DDB_MAX_LINK 4
73#define DDB_LINK_SHIFT 28
74
75#define DDB_LINK_TAG(_x) (_x << DDB_LINK_SHIFT)
Ralph Metzlerccad04572011-07-03 18:23:11 -030076
Daniel Scheller22e74382017-08-12 07:55:52 -040077struct ddb_regset {
78 u32 base;
79 u32 num;
80 u32 size;
81};
82
83struct ddb_regmap {
84 u32 irq_base_i2c;
85 u32 irq_base_idma;
86 u32 irq_base_odma;
87
Daniel Scheller0937e7e2017-08-20 06:41:13 -040088 const struct ddb_regset *i2c;
89 const struct ddb_regset *i2c_buf;
90 const struct ddb_regset *idma;
91 const struct ddb_regset *idma_buf;
92 const struct ddb_regset *odma;
93 const struct ddb_regset *odma_buf;
Daniel Scheller22e74382017-08-12 07:55:52 -040094
Daniel Scheller0937e7e2017-08-20 06:41:13 -040095 const struct ddb_regset *input;
96 const struct ddb_regset *output;
Daniel Scheller22e74382017-08-12 07:55:52 -040097
Daniel Scheller0937e7e2017-08-20 06:41:13 -040098 const struct ddb_regset *channel;
Daniel Scheller22e74382017-08-12 07:55:52 -040099};
100
101struct ddb_ids {
102 u16 vendor;
103 u16 device;
104 u16 subvendor;
105 u16 subdevice;
106
107 u32 hwid;
108 u32 regmapid;
109 u32 devid;
110 u32 mac;
111};
Daniel Schellere933a6f2017-04-09 16:38:26 -0300112
Ralph Metzlerccad04572011-07-03 18:23:11 -0300113struct ddb_info {
114 int type;
Daniel Schellerc3eda332018-04-09 12:47:50 -0400115#define DDB_NONE 0
116#define DDB_OCTOPUS 1
117#define DDB_OCTOPUS_CI 2
118#define DDB_OCTOPUS_MAX 5
Daniel Scheller22e74382017-08-12 07:55:52 -0400119#define DDB_OCTOPUS_MAX_CT 6
Daniel Schellerc3eda332018-04-09 12:47:50 -0400120#define DDB_OCTOPUS_MCI 9
Ralph Metzlerccad04572011-07-03 18:23:11 -0300121 char *name;
Daniel Scheller22e74382017-08-12 07:55:52 -0400122 u32 i2c_mask;
123 u8 port_num;
124 u8 led_num;
125 u8 fan_num;
126 u8 temp_num;
127 u8 temp_bus;
Daniel Scheller1b58a5a2017-04-09 16:38:25 -0300128 u32 board_control;
129 u32 board_control_2;
Daniel Scheller22e74382017-08-12 07:55:52 -0400130 u8 mdio_num;
131 u8 con_clock; /* use a continuous clock */
Daniel Scheller1b58a5a2017-04-09 16:38:25 -0300132 u8 ts_quirks;
133#define TS_QUIRK_SERIAL 1
134#define TS_QUIRK_REVERSED 2
135#define TS_QUIRK_ALT_OSC 8
Daniel Scheller22e74382017-08-12 07:55:52 -0400136 u32 tempmon_irq;
Daniel Schellerc3eda332018-04-09 12:47:50 -0400137 u8 mci;
Daniel Scheller0937e7e2017-08-20 06:41:13 -0400138 const struct ddb_regmap *regmap;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300139};
140
Daniel Scheller22e74382017-08-12 07:55:52 -0400141#define DMA_MAX_BUFS 32 /* hardware table limit */
142
Ralph Metzlerccad04572011-07-03 18:23:11 -0300143struct ddb;
144struct ddb_port;
145
Daniel Scheller22e74382017-08-12 07:55:52 -0400146struct ddb_dma {
147 void *io;
148 u32 regs;
149 u32 bufregs;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300150
Daniel Scheller22e74382017-08-12 07:55:52 -0400151 dma_addr_t pbuf[DMA_MAX_BUFS];
152 u8 *vbuf[DMA_MAX_BUFS];
153 u32 num;
154 u32 size;
155 u32 div;
156 u32 bufval;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300157
Daniel Scheller22e74382017-08-12 07:55:52 -0400158 struct work_struct work;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400159 spinlock_t lock; /* DMA lock */
Ralph Metzlerccad04572011-07-03 18:23:11 -0300160 wait_queue_head_t wq;
161 int running;
162 u32 stat;
Daniel Scheller22e74382017-08-12 07:55:52 -0400163 u32 ctrl;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300164 u32 cbuf;
165 u32 coff;
Daniel Scheller22e74382017-08-12 07:55:52 -0400166};
Ralph Metzlerccad04572011-07-03 18:23:11 -0300167
Daniel Scheller22e74382017-08-12 07:55:52 -0400168struct ddb_dvb {
169 struct dvb_adapter *adap;
170 int adap_registered;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300171 struct dvb_device *dev;
Daniel Scheller05da9432017-03-29 13:43:13 -0300172 struct i2c_client *i2c_client[1];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300173 struct dvb_frontend *fe;
174 struct dvb_frontend *fe2;
175 struct dmxdev dmxdev;
176 struct dvb_demux demux;
177 struct dvb_net dvbnet;
178 struct dmx_frontend hw_frontend;
179 struct dmx_frontend mem_frontend;
180 int users;
Daniel Scheller22e74382017-08-12 07:55:52 -0400181 u32 attached;
182 u8 input;
183
184 enum fe_sec_tone_mode tone;
185 enum fe_sec_voltage voltage;
186
187 int (*i2c_gate_ctrl)(struct dvb_frontend *, int);
188 int (*set_voltage)(struct dvb_frontend *fe,
Daniel Scheller757d78d2017-10-15 16:51:51 -0400189 enum fe_sec_voltage voltage);
Daniel Scheller22e74382017-08-12 07:55:52 -0400190 int (*set_input)(struct dvb_frontend *fe, int input);
191 int (*diseqc_send_master_cmd)(struct dvb_frontend *fe,
Daniel Scheller757d78d2017-10-15 16:51:51 -0400192 struct dvb_diseqc_master_cmd *cmd);
Ralph Metzlerccad04572011-07-03 18:23:11 -0300193};
194
Daniel Scheller22e74382017-08-12 07:55:52 -0400195struct ddb_ci {
196 struct dvb_ca_en50221 en;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300197 struct ddb_port *port;
198 u32 nr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300199};
200
Daniel Scheller22e74382017-08-12 07:55:52 -0400201struct ddb_io {
202 struct ddb_port *port;
203 u32 nr;
204 u32 regs;
205 struct ddb_dma *dma;
206 struct ddb_io *redo;
207 struct ddb_io *redi;
208};
209
210#define ddb_output ddb_io
211#define ddb_input ddb_io
212
Ralph Metzlerccad04572011-07-03 18:23:11 -0300213struct ddb_i2c {
214 struct ddb *dev;
215 u32 nr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300216 u32 regs;
Daniel Scheller22e74382017-08-12 07:55:52 -0400217 u32 link;
218 struct i2c_adapter adap;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300219 u32 rbuf;
220 u32 wbuf;
Daniel Scheller22e74382017-08-12 07:55:52 -0400221 u32 bsize;
222 struct completion completion;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300223};
224
225struct ddb_port {
226 struct ddb *dev;
227 u32 nr;
Daniel Scheller22e74382017-08-12 07:55:52 -0400228 u32 pnr;
229 u32 regs;
230 u32 lnr;
Ralph Metzlerccad04572011-07-03 18:23:11 -0300231 struct ddb_i2c *i2c;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400232 struct mutex i2c_gate_lock; /* I2C access lock */
Ralph Metzlerccad04572011-07-03 18:23:11 -0300233 u32 class;
234#define DDB_PORT_NONE 0
235#define DDB_PORT_CI 1
236#define DDB_PORT_TUNER 2
Daniel Scheller22e74382017-08-12 07:55:52 -0400237#define DDB_PORT_LOOP 3
238 char *name;
239 char *type_name;
240 u32 type;
Daniel Schellerab123972018-04-09 12:47:47 -0400241#define DDB_TUNER_DUMMY 0xffffffff
Daniel Scheller22e74382017-08-12 07:55:52 -0400242#define DDB_TUNER_NONE 0
243#define DDB_TUNER_DVBS_ST 1
244#define DDB_TUNER_DVBS_ST_AA 2
245#define DDB_TUNER_DVBCT_TR 3
246#define DDB_TUNER_DVBCT_ST 4
247#define DDB_CI_INTERNAL 5
248#define DDB_CI_EXTERNAL_SONY 6
249#define DDB_TUNER_DVBCT2_SONY_P 7
250#define DDB_TUNER_DVBC2T2_SONY_P 8
251#define DDB_TUNER_ISDBT_SONY_P 9
252#define DDB_TUNER_DVBS_STV0910_P 10
253#define DDB_TUNER_MXL5XX 11
254#define DDB_CI_EXTERNAL_XO2 12
255#define DDB_CI_EXTERNAL_XO2_B 13
256#define DDB_TUNER_DVBS_STV0910_PR 14
257#define DDB_TUNER_DVBC2T2I_SONY_P 15
Daniel Schellerc3eda332018-04-09 12:47:50 -0400258#define DDB_TUNER_MCI 16
Daniel Schellere933a6f2017-04-09 16:38:26 -0300259
Daniel Scheller22e74382017-08-12 07:55:52 -0400260#define DDB_TUNER_XO2 32
261#define DDB_TUNER_DVBS_STV0910 (DDB_TUNER_XO2 + 0)
262#define DDB_TUNER_DVBCT2_SONY (DDB_TUNER_XO2 + 1)
263#define DDB_TUNER_ISDBT_SONY (DDB_TUNER_XO2 + 2)
264#define DDB_TUNER_DVBC2T2_SONY (DDB_TUNER_XO2 + 3)
265#define DDB_TUNER_ATSC_ST (DDB_TUNER_XO2 + 4)
266#define DDB_TUNER_DVBC2T2I_SONY (DDB_TUNER_XO2 + 5)
Ralph Metzlerccad04572011-07-03 18:23:11 -0300267
268 struct ddb_input *input[2];
269 struct ddb_output *output;
270 struct dvb_ca_en50221 *en;
Daniel Schellere5eaf6f2018-03-06 11:39:10 -0500271 u8 en_freedata;
Daniel Scheller22e74382017-08-12 07:55:52 -0400272 struct ddb_dvb dvb[2];
273 u32 gap;
274 u32 obr;
275 u8 creg;
276};
277
278#define CM_STARTUP_DELAY 2
279#define CM_AVERAGE 20
280#define CM_GAIN 10
281
282#define HW_LSB_SHIFT 12
283#define HW_LSB_MASK 0x1000
284
285#define CM_IDLE 0
286#define CM_STARTUP 1
287#define CM_ADJUST 2
288
289#define TS_CAPTURE_LEN (4096)
290
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400291struct ddb_lnb {
Daniel Scheller757d78d2017-10-15 16:51:51 -0400292 struct mutex lock; /* lock lnb access */
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400293 u32 tone;
294 enum fe_sec_voltage oldvoltage[4];
295 u32 voltage[4];
296 u32 voltages;
297 u32 fmode;
298};
299
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400300struct ddb_irq {
301 void (*handler)(void *);
302 void *data;
303};
304
Daniel Scheller22e74382017-08-12 07:55:52 -0400305struct ddb_link {
306 struct ddb *dev;
Daniel Scheller66cc3d92017-08-20 06:41:11 -0400307 const struct ddb_info *info;
Daniel Scheller22e74382017-08-12 07:55:52 -0400308 u32 nr;
309 u32 regs;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400310 spinlock_t lock; /* lock link access */
311 struct mutex flash_mutex; /* lock flash access */
Daniel Schellerbb4cec92017-07-09 15:42:44 -0400312 struct ddb_lnb lnb;
Daniel Scheller22e74382017-08-12 07:55:52 -0400313 struct tasklet_struct tasklet;
314 struct ddb_ids ids;
315
Daniel Scheller757d78d2017-10-15 16:51:51 -0400316 spinlock_t temp_lock; /* lock temp chip access */
Daniel Scheller22e74382017-08-12 07:55:52 -0400317 int overtemperature_error;
318 u8 temp_tab[11];
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400319 struct ddb_irq irq[256];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300320};
321
322struct ddb {
Daniel Scheller757d78d2017-10-15 16:51:51 -0400323 struct pci_dev *pdev;
324 struct platform_device *pfdev;
325 struct device *dev;
Daniel Scheller22e74382017-08-12 07:55:52 -0400326
Daniel Scheller757d78d2017-10-15 16:51:51 -0400327 int msi;
Daniel Scheller22e74382017-08-12 07:55:52 -0400328 struct workqueue_struct *wq;
Daniel Scheller757d78d2017-10-15 16:51:51 -0400329 u32 has_dma;
Daniel Scheller22e74382017-08-12 07:55:52 -0400330
Daniel Scheller757d78d2017-10-15 16:51:51 -0400331 struct ddb_link link[DDB_MAX_LINK];
332 unsigned char __iomem *regs;
333 u32 regs_len;
334 u32 port_num;
335 struct ddb_port port[DDB_MAX_PORT];
336 u32 i2c_num;
337 struct ddb_i2c i2c[DDB_MAX_I2C];
338 struct ddb_input input[DDB_MAX_INPUT];
339 struct ddb_output output[DDB_MAX_OUTPUT];
340 struct dvb_adapter adap[DDB_MAX_INPUT];
341 struct ddb_dma idma[DDB_MAX_INPUT];
342 struct ddb_dma odma[DDB_MAX_OUTPUT];
Daniel Scheller22e74382017-08-12 07:55:52 -0400343
Daniel Scheller757d78d2017-10-15 16:51:51 -0400344 struct device *ddb_dev;
345 u32 ddb_dev_users;
346 u32 nr;
347 u8 iobuf[1028];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300348
Daniel Scheller757d78d2017-10-15 16:51:51 -0400349 u8 leds;
350 u32 ts_irq;
351 u32 i2c_irq;
Daniel Scheller22e74382017-08-12 07:55:52 -0400352
Daniel Scheller757d78d2017-10-15 16:51:51 -0400353 struct mutex mutex; /* lock access to global ddb array */
Daniel Scheller22e74382017-08-12 07:55:52 -0400354
Daniel Scheller757d78d2017-10-15 16:51:51 -0400355 u8 tsbuf[TS_CAPTURE_LEN];
Ralph Metzlerccad04572011-07-03 18:23:11 -0300356};
357
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400358/****************************************************************************/
Daniel Scheller22e74382017-08-12 07:55:52 -0400359/****************************************************************************/
360/****************************************************************************/
361
362int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);
363
364/****************************************************************************/
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400365
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400366/* ddbridge-core.c */
Daniel Scheller1dda87a2018-04-09 12:47:40 -0400367struct ddb_irq *ddb_irq_set(struct ddb *dev, u32 link, u32 nr,
368 void (*handler)(void *), void *data);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400369void ddb_ports_detach(struct ddb *dev);
370void ddb_ports_release(struct ddb *dev);
371void ddb_buffers_free(struct ddb *dev);
372void ddb_device_destroy(struct ddb *dev);
Daniel Scheller22e74382017-08-12 07:55:52 -0400373irqreturn_t ddb_irq_handler0(int irq, void *dev_id);
374irqreturn_t ddb_irq_handler1(int irq, void *dev_id);
375irqreturn_t ddb_irq_handler(int irq, void *dev_id);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400376void ddb_ports_init(struct ddb *dev);
377int ddb_buffers_alloc(struct ddb *dev);
378int ddb_ports_attach(struct ddb *dev);
379int ddb_device_create(struct ddb *dev);
Daniel Scheller22e74382017-08-12 07:55:52 -0400380int ddb_init(struct ddb *dev);
Daniel Scheller8e4eef22017-08-20 06:41:10 -0400381void ddb_unmap(struct ddb *dev);
Daniel Scheller05ed62d2018-04-09 12:47:37 -0400382int ddb_exit_ddbridge(int stage, int error);
383int ddb_init_ddbridge(void);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400384
Daniel Scheller22e74382017-08-12 07:55:52 -0400385#endif /* DDBRIDGE_H */