blob: d50bddb2e4474e456b8105d6b90b47488ff21263 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Redingab7d3f52017-12-14 13:46:20 +010036static int tegra_atomic_check(struct drm_device *drm,
37 struct drm_atomic_state *state)
Thierry Reding1503ca42014-11-24 17:41:23 +010038{
Thierry Reding1503ca42014-11-24 17:41:23 +010039 int err;
40
Thierry Redingab7d3f52017-12-14 13:46:20 +010041 err = drm_atomic_helper_check_modeset(drm, state);
42 if (err < 0)
Thierry Reding1503ca42014-11-24 17:41:23 +010043 return err;
44
Thierry Redingab7d3f52017-12-14 13:46:20 +010045 err = drm_atomic_normalize_zpos(drm, state);
46 if (err < 0)
Maarten Lankhorst424624e2017-07-11 16:33:10 +020047 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010048
Thierry Redingab7d3f52017-12-14 13:46:20 +010049 err = drm_atomic_helper_check_planes(drm, state);
50 if (err < 0)
51 return err;
Thierry Reding1503ca42014-11-24 17:41:23 +010052
Thierry Redingab7d3f52017-12-14 13:46:20 +010053 if (state->legacy_cursor_update)
54 state->async_update = !drm_atomic_helper_async_check(drm, state);
55
Thierry Reding1503ca42014-11-24 17:41:23 +010056 return 0;
57}
58
Thierry Redingc4755fb2017-11-13 11:08:13 +010059static struct drm_atomic_state *
60tegra_atomic_state_alloc(struct drm_device *drm)
61{
62 struct tegra_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
63
64 if (!state || drm_atomic_state_init(drm, &state->base) < 0) {
65 kfree(state);
66 return NULL;
67 }
68
69 return &state->base;
70}
71
72static void tegra_atomic_state_clear(struct drm_atomic_state *state)
73{
74 struct tegra_atomic_state *tegra = to_tegra_atomic_state(state);
75
76 drm_atomic_state_default_clear(state);
77 tegra->clk_disp = NULL;
78 tegra->dc = NULL;
79 tegra->rate = 0;
80}
81
82static void tegra_atomic_state_free(struct drm_atomic_state *state)
83{
84 drm_atomic_state_default_release(state);
85 kfree(state);
86}
87
Thierry Reding31b02ca2017-10-12 17:40:46 +020088static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
Thierry Redingf9914212014-11-26 13:03:57 +010089 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +053090#ifdef CONFIG_DRM_FBDEV_EMULATION
Noralf Trønnesc94beda2017-12-05 19:25:04 +010091 .output_poll_changed = drm_fb_helper_output_poll_changed,
Thierry Redingf9914212014-11-26 13:03:57 +010092#endif
Thierry Redingab7d3f52017-12-14 13:46:20 +010093 .atomic_check = tegra_atomic_check,
Thierry Reding31b02ca2017-10-12 17:40:46 +020094 .atomic_commit = drm_atomic_helper_commit,
Thierry Redingc4755fb2017-11-13 11:08:13 +010095 .atomic_state_alloc = tegra_atomic_state_alloc,
96 .atomic_state_clear = tegra_atomic_state_clear,
97 .atomic_state_free = tegra_atomic_state_free,
Thierry Reding31b02ca2017-10-12 17:40:46 +020098};
99
Thierry Redingc4755fb2017-11-13 11:08:13 +0100100static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
101{
102 struct drm_device *drm = old_state->dev;
103 struct tegra_drm *tegra = drm->dev_private;
104
105 if (tegra->hub) {
106 drm_atomic_helper_commit_modeset_disables(drm, old_state);
107 tegra_display_hub_atomic_commit(drm, old_state);
108 drm_atomic_helper_commit_planes(drm, old_state, 0);
109 drm_atomic_helper_commit_modeset_enables(drm, old_state);
110 drm_atomic_helper_commit_hw_done(old_state);
111 drm_atomic_helper_wait_for_vblanks(drm, old_state);
112 drm_atomic_helper_cleanup_planes(drm, old_state);
113 } else {
114 drm_atomic_helper_commit_tail_rpm(old_state);
115 }
116}
117
Thierry Reding31b02ca2017-10-12 17:40:46 +0200118static const struct drm_mode_config_helper_funcs
119tegra_drm_mode_config_helpers = {
Thierry Redingc4755fb2017-11-13 11:08:13 +0100120 .atomic_commit_tail = tegra_atomic_commit_tail,
Thierry Redingf9914212014-11-26 13:03:57 +0100121};
122
Thierry Reding776dc382013-10-14 14:43:22 +0200123static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000124{
Thierry Reding776dc382013-10-14 14:43:22 +0200125 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200126 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000127 int err;
128
Thierry Reding776dc382013-10-14 14:43:22 +0200129 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200130 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200131 return -ENOMEM;
132
Thierry Redingdf06b752014-06-26 21:41:53 +0200133 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200134 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100135 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200136 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100137
Thierry Redingdf06b752014-06-26 21:41:53 +0200138 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300139 if (!tegra->domain) {
140 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200141 goto free;
142 }
143
Thierry Reding4553f732015-01-19 16:15:04 +0100144 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200145 gem_start = geometry->aperture_start;
146 gem_end = geometry->aperture_end - CARVEOUT_SZ;
147 carveout_start = gem_end + 1;
148 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100149
Mikko Perttunenad926012016-12-14 13:16:11 +0200150 order = __ffs(tegra->domain->pgsize_bitmap);
151 init_iova_domain(&tegra->carveout.domain, 1UL << order,
Zhen Leiaa3ac942017-09-21 16:52:45 +0100152 carveout_start >> order);
Mikko Perttunenad926012016-12-14 13:16:11 +0200153
154 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
155 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
156
157 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100158 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200159
160 DRM_DEBUG("IOMMU apertures:\n");
161 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
162 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
163 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200164 }
165
Thierry Reding386a2a72013-09-24 13:22:17 +0200166 mutex_init(&tegra->clients_lock);
167 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100168
Thierry Reding386a2a72013-09-24 13:22:17 +0200169 drm->dev_private = tegra;
170 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000171
172 drm_mode_config_init(drm);
173
Thierry Redingf9914212014-11-26 13:03:57 +0100174 drm->mode_config.min_width = 0;
175 drm->mode_config.min_height = 0;
176
177 drm->mode_config.max_width = 4096;
178 drm->mode_config.max_height = 4096;
179
Alexandre Courbot5e911442016-11-08 16:50:42 +0900180 drm->mode_config.allow_fb_modifiers = true;
181
Thierry Reding31b02ca2017-10-12 17:40:46 +0200182 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
183 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
Thierry Redingf9914212014-11-26 13:03:57 +0100184
Thierry Redinge2215322014-06-27 17:19:25 +0200185 err = tegra_drm_fb_prepare(drm);
186 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100187 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200188
189 drm_kms_helper_poll_init(drm);
190
Thierry Reding776dc382013-10-14 14:43:22 +0200191 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000192 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100193 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000194
Thierry Redingc4755fb2017-11-13 11:08:13 +0100195 if (tegra->hub) {
196 err = tegra_display_hub_prepare(tegra->hub);
197 if (err < 0)
198 goto device;
199 }
200
Thierry Reding603f0cc2013-04-22 21:22:14 +0200201 /*
202 * We don't use the drm_irq_install() helpers provided by the DRM
203 * core, so we need to set this manually in order to allow the
204 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
205 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300206 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200207
Thierry Reding42e9ce02015-01-28 14:43:05 +0100208 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100209 drm->max_vblank_count = 0xffffffff;
210
Thierry Reding6e5ff992012-11-28 11:45:47 +0100211 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
212 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100213 goto hub;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100214
Thierry Reding31930d42015-07-02 17:04:06 +0200215 drm_mode_config_reset(drm);
216
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000217 err = tegra_drm_fb_init(drm);
218 if (err < 0)
Thierry Redingc4755fb2017-11-13 11:08:13 +0100219 goto hub;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000220
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000221 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100222
Thierry Redingc4755fb2017-11-13 11:08:13 +0100223hub:
224 if (tegra->hub)
225 tegra_display_hub_cleanup(tegra->hub);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100226device:
227 host1x_device_exit(device);
228fbdev:
229 drm_kms_helper_poll_fini(drm);
230 tegra_drm_fb_free(drm);
231config:
232 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200233
234 if (tegra->domain) {
235 iommu_domain_free(tegra->domain);
236 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100237 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200238 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200239 }
240free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100241 kfree(tegra);
242 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000243}
244
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200245static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000246{
Thierry Reding776dc382013-10-14 14:43:22 +0200247 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200248 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200249 int err;
250
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000251 drm_kms_helper_poll_fini(drm);
252 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200253 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000254
Thierry Reding776dc382013-10-14 14:43:22 +0200255 err = host1x_device_exit(device);
256 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200257 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200258
Thierry Redingdf06b752014-06-26 21:41:53 +0200259 if (tegra->domain) {
260 iommu_domain_free(tegra->domain);
261 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100262 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200263 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200264 }
265
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100266 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000267}
268
269static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
270{
Thierry Reding08943e62013-09-26 16:08:18 +0200271 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200272
273 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
274 if (!fpriv)
275 return -ENOMEM;
276
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100277 idr_init(&fpriv->contexts);
278 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200279 filp->driver_priv = fpriv;
280
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000281 return 0;
282}
283
Thierry Redingc88c3632013-09-26 16:08:22 +0200284static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200285{
286 context->client->ops->close_channel(context);
287 kfree(context);
288}
289
Thierry Redingc40f0f12013-10-10 11:00:33 +0200290static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100291host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200292{
293 struct drm_gem_object *gem;
294 struct tegra_bo *bo;
295
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100296 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200297 if (!gem)
298 return NULL;
299
Thierry Redingc40f0f12013-10-10 11:00:33 +0200300 bo = to_tegra_bo(gem);
301 return &bo->base;
302}
303
Thierry Reding961e3be2014-06-10 10:25:00 +0200304static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
305 struct drm_tegra_reloc __user *src,
306 struct drm_device *drm,
307 struct drm_file *file)
308{
309 u32 cmdbuf, target;
310 int err;
311
312 err = get_user(cmdbuf, &src->cmdbuf.handle);
313 if (err < 0)
314 return err;
315
316 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
317 if (err < 0)
318 return err;
319
320 err = get_user(target, &src->target.handle);
321 if (err < 0)
322 return err;
323
David Ung31f40f82015-01-20 18:37:35 -0800324 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200325 if (err < 0)
326 return err;
327
328 err = get_user(dest->shift, &src->shift);
329 if (err < 0)
330 return err;
331
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100332 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200333 if (!dest->cmdbuf.bo)
334 return -ENOENT;
335
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100336 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200337 if (!dest->target.bo)
338 return -ENOENT;
339
340 return 0;
341}
342
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300343static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
344 struct drm_tegra_waitchk __user *src,
345 struct drm_file *file)
346{
347 u32 cmdbuf;
348 int err;
349
350 err = get_user(cmdbuf, &src->handle);
351 if (err < 0)
352 return err;
353
354 err = get_user(dest->offset, &src->offset);
355 if (err < 0)
356 return err;
357
358 err = get_user(dest->syncpt_id, &src->syncpt);
359 if (err < 0)
360 return err;
361
362 err = get_user(dest->thresh, &src->thresh);
363 if (err < 0)
364 return err;
365
366 dest->bo = host1x_bo_lookup(file, cmdbuf);
367 if (!dest->bo)
368 return -ENOENT;
369
370 return 0;
371}
372
Thierry Redingc40f0f12013-10-10 11:00:33 +0200373int tegra_drm_submit(struct tegra_drm_context *context,
374 struct drm_tegra_submit *args, struct drm_device *drm,
375 struct drm_file *file)
376{
377 unsigned int num_cmdbufs = args->num_cmdbufs;
378 unsigned int num_relocs = args->num_relocs;
379 unsigned int num_waitchks = args->num_waitchks;
Mikko Perttunena176c672017-09-28 15:50:44 +0300380 struct drm_tegra_cmdbuf __user *user_cmdbufs;
381 struct drm_tegra_reloc __user *user_relocs;
382 struct drm_tegra_waitchk __user *user_waitchks;
383 struct drm_tegra_syncpt __user *user_syncpt;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200384 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300385 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200386 struct drm_gem_object **refs;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300387 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200388 struct host1x_job *job;
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200389 unsigned int num_refs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200390 int err;
391
Mikko Perttunena176c672017-09-28 15:50:44 +0300392 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
393 user_relocs = u64_to_user_ptr(args->relocs);
394 user_waitchks = u64_to_user_ptr(args->waitchks);
395 user_syncpt = u64_to_user_ptr(args->syncpts);
396
Thierry Redingc40f0f12013-10-10 11:00:33 +0200397 /* We don't yet support other than one syncpt_incr struct per submit */
398 if (args->num_syncpts != 1)
399 return -EINVAL;
400
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300401 /* We don't yet support waitchks */
402 if (args->num_waitchks != 0)
403 return -EINVAL;
404
Thierry Redingc40f0f12013-10-10 11:00:33 +0200405 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
406 args->num_relocs, args->num_waitchks);
407 if (!job)
408 return -ENOMEM;
409
410 job->num_relocs = args->num_relocs;
411 job->num_waitchk = args->num_waitchks;
412 job->client = (u32)args->context;
413 job->class = context->client->base.class;
414 job->serialize = true;
415
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200416 /*
417 * Track referenced BOs so that they can be unreferenced after the
418 * submission is complete.
419 */
420 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
421
422 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
423 if (!refs) {
424 err = -ENOMEM;
425 goto put;
426 }
427
428 /* reuse as an iterator later */
429 num_refs = 0;
430
Thierry Redingc40f0f12013-10-10 11:00:33 +0200431 while (num_cmdbufs) {
432 struct drm_tegra_cmdbuf cmdbuf;
433 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300434 struct tegra_bo *obj;
435 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200436
Mikko Perttunena176c672017-09-28 15:50:44 +0300437 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300438 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200439 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300440 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200441
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300442 /*
443 * The maximum number of CDMA gather fetches is 16383, a higher
444 * value means the words count is malformed.
445 */
446 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
447 err = -EINVAL;
448 goto fail;
449 }
450
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100451 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200452 if (!bo) {
453 err = -ENOENT;
454 goto fail;
455 }
456
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300457 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
458 obj = host1x_to_tegra_bo(bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200459 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300460
461 /*
462 * Gather buffer base address must be 4-bytes aligned,
463 * unaligned offset is malformed and cause commands stream
464 * corruption on the buffer address relocation.
465 */
466 if (offset & 3 || offset >= obj->gem.size) {
467 err = -EINVAL;
468 goto fail;
469 }
470
Thierry Redingc40f0f12013-10-10 11:00:33 +0200471 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
472 num_cmdbufs--;
Mikko Perttunena176c672017-09-28 15:50:44 +0300473 user_cmdbufs++;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200474 }
475
Thierry Reding961e3be2014-06-10 10:25:00 +0200476 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200477 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300478 struct host1x_reloc *reloc;
479 struct tegra_bo *obj;
480
Thierry Reding961e3be2014-06-10 10:25:00 +0200481 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
Mikko Perttunena176c672017-09-28 15:50:44 +0300482 &user_relocs[num_relocs], drm,
Thierry Reding961e3be2014-06-10 10:25:00 +0200483 file);
484 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200485 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300486
487 reloc = &job->relocarray[num_relocs];
488 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200489 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300490
491 /*
492 * The unaligned cmdbuf offset will cause an unaligned write
493 * during of the relocations patching, corrupting the commands
494 * stream.
495 */
496 if (reloc->cmdbuf.offset & 3 ||
497 reloc->cmdbuf.offset >= obj->gem.size) {
498 err = -EINVAL;
499 goto fail;
500 }
501
502 obj = host1x_to_tegra_bo(reloc->target.bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200503 refs[num_refs++] = &obj->gem;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300504
505 if (reloc->target.offset >= obj->gem.size) {
506 err = -EINVAL;
507 goto fail;
508 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200509 }
510
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300511 /* copy and resolve waitchks from submit */
512 while (num_waitchks--) {
513 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
514 struct tegra_bo *obj;
515
Mikko Perttunena176c672017-09-28 15:50:44 +0300516 err = host1x_waitchk_copy_from_user(
517 wait, &user_waitchks[num_waitchks], file);
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300518 if (err < 0)
519 goto fail;
520
521 obj = host1x_to_tegra_bo(wait->bo);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200522 refs[num_refs++] = &obj->gem;
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300523
524 /*
525 * The unaligned offset will cause an unaligned write during
526 * of the waitchks patching, corrupting the commands stream.
527 */
528 if (wait->offset & 3 ||
529 wait->offset >= obj->gem.size) {
530 err = -EINVAL;
531 goto fail;
532 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300533 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200534
Mikko Perttunena176c672017-09-28 15:50:44 +0300535 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
Dan Carpenter9a991602013-11-08 13:07:37 +0300536 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200537 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300538 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200539
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300540 /* check whether syncpoint ID is valid */
541 sp = host1x_syncpt_get(host1x, syncpt.id);
542 if (!sp) {
543 err = -ENOENT;
544 goto fail;
545 }
546
Thierry Redingc40f0f12013-10-10 11:00:33 +0200547 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300548 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200549 job->syncpt_incrs = syncpt.incrs;
550 job->syncpt_id = syncpt.id;
551 job->timeout = 10000;
552
553 if (args->timeout && args->timeout < 10000)
554 job->timeout = args->timeout;
555
556 err = host1x_job_pin(job, context->client->base.dev);
557 if (err)
558 goto fail;
559
560 err = host1x_job_submit(job);
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200561 if (err) {
562 host1x_job_unpin(job);
563 goto fail;
564 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200565
566 args->fence = job->syncpt_end;
567
Thierry Redingc40f0f12013-10-10 11:00:33 +0200568fail:
Dmitry Osipenkoec73c4c2017-08-11 19:54:56 +0200569 while (num_refs--)
570 drm_gem_object_put_unlocked(refs[num_refs]);
571
572 kfree(refs);
573
574put:
Thierry Redingc40f0f12013-10-10 11:00:33 +0200575 host1x_job_put(job);
576 return err;
577}
578
579
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200580#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200581static int tegra_gem_create(struct drm_device *drm, void *data,
582 struct drm_file *file)
583{
584 struct drm_tegra_gem_create *args = data;
585 struct tegra_bo *bo;
586
Thierry Reding773af772013-10-04 22:34:01 +0200587 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200588 &args->handle);
589 if (IS_ERR(bo))
590 return PTR_ERR(bo);
591
592 return 0;
593}
594
595static int tegra_gem_mmap(struct drm_device *drm, void *data,
596 struct drm_file *file)
597{
598 struct drm_tegra_gem_mmap *args = data;
599 struct drm_gem_object *gem;
600 struct tegra_bo *bo;
601
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100602 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200603 if (!gem)
604 return -EINVAL;
605
606 bo = to_tegra_bo(gem);
607
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200608 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200609
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300610 drm_gem_object_put_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200611
612 return 0;
613}
614
615static int tegra_syncpt_read(struct drm_device *drm, void *data,
616 struct drm_file *file)
617{
Thierry Reding776dc382013-10-14 14:43:22 +0200618 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200619 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200620 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200621
Thierry Reding776dc382013-10-14 14:43:22 +0200622 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200623 if (!sp)
624 return -EINVAL;
625
626 args->value = host1x_syncpt_read_min(sp);
627 return 0;
628}
629
630static int tegra_syncpt_incr(struct drm_device *drm, void *data,
631 struct drm_file *file)
632{
Thierry Reding776dc382013-10-14 14:43:22 +0200633 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200634 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200635 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200636
Thierry Reding776dc382013-10-14 14:43:22 +0200637 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200638 if (!sp)
639 return -EINVAL;
640
Arto Merilainenebae30b2013-05-29 13:26:08 +0300641 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200642}
643
644static int tegra_syncpt_wait(struct drm_device *drm, void *data,
645 struct drm_file *file)
646{
Thierry Reding776dc382013-10-14 14:43:22 +0200647 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200648 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200649 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200650
Thierry Reding776dc382013-10-14 14:43:22 +0200651 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200652 if (!sp)
653 return -EINVAL;
654
Dmitry Osipenko4c69ac122017-12-20 18:46:14 +0300655 return host1x_syncpt_wait(sp, args->thresh,
656 msecs_to_jiffies(args->timeout),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200657 &args->value);
658}
659
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100660static int tegra_client_open(struct tegra_drm_file *fpriv,
661 struct tegra_drm_client *client,
662 struct tegra_drm_context *context)
663{
664 int err;
665
666 err = client->ops->open_channel(client, context);
667 if (err < 0)
668 return err;
669
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300670 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100671 if (err < 0) {
672 client->ops->close_channel(context);
673 return err;
674 }
675
676 context->client = client;
677 context->id = err;
678
679 return 0;
680}
681
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200682static int tegra_open_channel(struct drm_device *drm, void *data,
683 struct drm_file *file)
684{
Thierry Reding08943e62013-09-26 16:08:18 +0200685 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200686 struct tegra_drm *tegra = drm->dev_private;
687 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200688 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200689 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200690 int err = -ENODEV;
691
692 context = kzalloc(sizeof(*context), GFP_KERNEL);
693 if (!context)
694 return -ENOMEM;
695
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100696 mutex_lock(&fpriv->lock);
697
Thierry Reding776dc382013-10-14 14:43:22 +0200698 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200699 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100700 err = tegra_client_open(fpriv, client, context);
701 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200702 break;
703
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100704 args->context = context->id;
705 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200706 }
707
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100708 if (err < 0)
709 kfree(context);
710
711 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200712 return err;
713}
714
715static int tegra_close_channel(struct drm_device *drm, void *data,
716 struct drm_file *file)
717{
Thierry Reding08943e62013-09-26 16:08:18 +0200718 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200719 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200720 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100721 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200722
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100723 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200724
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300725 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100726 if (!context) {
727 err = -EINVAL;
728 goto unlock;
729 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200730
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100731 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200732 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200733
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100734unlock:
735 mutex_unlock(&fpriv->lock);
736 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200737}
738
739static int tegra_get_syncpt(struct drm_device *drm, void *data,
740 struct drm_file *file)
741{
Thierry Reding08943e62013-09-26 16:08:18 +0200742 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200743 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200744 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200745 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100746 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200747
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100748 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200749
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300750 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100751 if (!context) {
752 err = -ENODEV;
753 goto unlock;
754 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200755
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100756 if (args->index >= context->client->base.num_syncpts) {
757 err = -EINVAL;
758 goto unlock;
759 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200760
Thierry Reding53fa7f72013-09-24 15:35:40 +0200761 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200762 args->id = host1x_syncpt_id(syncpt);
763
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100764unlock:
765 mutex_unlock(&fpriv->lock);
766 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200767}
768
769static int tegra_submit(struct drm_device *drm, void *data,
770 struct drm_file *file)
771{
Thierry Reding08943e62013-09-26 16:08:18 +0200772 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200773 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200774 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100775 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200776
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100777 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200778
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300779 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100780 if (!context) {
781 err = -ENODEV;
782 goto unlock;
783 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200784
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100785 err = context->client->ops->submit(context, args, drm, file);
786
787unlock:
788 mutex_unlock(&fpriv->lock);
789 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200790}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300791
792static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
793 struct drm_file *file)
794{
795 struct tegra_drm_file *fpriv = file->driver_priv;
796 struct drm_tegra_get_syncpt_base *args = data;
797 struct tegra_drm_context *context;
798 struct host1x_syncpt_base *base;
799 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100800 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300801
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100802 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300803
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300804 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100805 if (!context) {
806 err = -ENODEV;
807 goto unlock;
808 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300809
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100810 if (args->syncpt >= context->client->base.num_syncpts) {
811 err = -EINVAL;
812 goto unlock;
813 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300814
815 syncpt = context->client->base.syncpts[args->syncpt];
816
817 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100818 if (!base) {
819 err = -ENXIO;
820 goto unlock;
821 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300822
823 args->id = host1x_syncpt_base_id(base);
824
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100825unlock:
826 mutex_unlock(&fpriv->lock);
827 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300828}
Thierry Reding7678d712014-06-03 14:56:57 +0200829
830static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
831 struct drm_file *file)
832{
833 struct drm_tegra_gem_set_tiling *args = data;
834 enum tegra_bo_tiling_mode mode;
835 struct drm_gem_object *gem;
836 unsigned long value = 0;
837 struct tegra_bo *bo;
838
839 switch (args->mode) {
840 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
841 mode = TEGRA_BO_TILING_MODE_PITCH;
842
843 if (args->value != 0)
844 return -EINVAL;
845
846 break;
847
848 case DRM_TEGRA_GEM_TILING_MODE_TILED:
849 mode = TEGRA_BO_TILING_MODE_TILED;
850
851 if (args->value != 0)
852 return -EINVAL;
853
854 break;
855
856 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
857 mode = TEGRA_BO_TILING_MODE_BLOCK;
858
859 if (args->value > 5)
860 return -EINVAL;
861
862 value = args->value;
863 break;
864
865 default:
866 return -EINVAL;
867 }
868
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100869 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200870 if (!gem)
871 return -ENOENT;
872
873 bo = to_tegra_bo(gem);
874
875 bo->tiling.mode = mode;
876 bo->tiling.value = value;
877
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300878 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200879
880 return 0;
881}
882
883static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
884 struct drm_file *file)
885{
886 struct drm_tegra_gem_get_tiling *args = data;
887 struct drm_gem_object *gem;
888 struct tegra_bo *bo;
889 int err = 0;
890
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100891 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200892 if (!gem)
893 return -ENOENT;
894
895 bo = to_tegra_bo(gem);
896
897 switch (bo->tiling.mode) {
898 case TEGRA_BO_TILING_MODE_PITCH:
899 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
900 args->value = 0;
901 break;
902
903 case TEGRA_BO_TILING_MODE_TILED:
904 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
905 args->value = 0;
906 break;
907
908 case TEGRA_BO_TILING_MODE_BLOCK:
909 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
910 args->value = bo->tiling.value;
911 break;
912
913 default:
914 err = -EINVAL;
915 break;
916 }
917
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300918 drm_gem_object_put_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200919
920 return err;
921}
Thierry Reding7b129082014-06-10 12:04:03 +0200922
923static int tegra_gem_set_flags(struct drm_device *drm, void *data,
924 struct drm_file *file)
925{
926 struct drm_tegra_gem_set_flags *args = data;
927 struct drm_gem_object *gem;
928 struct tegra_bo *bo;
929
930 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
931 return -EINVAL;
932
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100933 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200934 if (!gem)
935 return -ENOENT;
936
937 bo = to_tegra_bo(gem);
938 bo->flags = 0;
939
940 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
941 bo->flags |= TEGRA_BO_BOTTOM_UP;
942
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300943 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200944
945 return 0;
946}
947
948static int tegra_gem_get_flags(struct drm_device *drm, void *data,
949 struct drm_file *file)
950{
951 struct drm_tegra_gem_get_flags *args = data;
952 struct drm_gem_object *gem;
953 struct tegra_bo *bo;
954
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100955 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200956 if (!gem)
957 return -ENOENT;
958
959 bo = to_tegra_bo(gem);
960 args->flags = 0;
961
962 if (bo->flags & TEGRA_BO_BOTTOM_UP)
963 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
964
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300965 drm_gem_object_put_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200966
967 return 0;
968}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200969#endif
970
Rob Clarkbaa70942013-08-02 13:27:49 -0400971static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200972#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Reding6c68b712017-08-15 15:42:39 +0200973 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
974 DRM_UNLOCKED | DRM_RENDER_ALLOW),
975 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
976 DRM_UNLOCKED | DRM_RENDER_ALLOW),
977 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
978 DRM_UNLOCKED | DRM_RENDER_ALLOW),
979 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
980 DRM_UNLOCKED | DRM_RENDER_ALLOW),
981 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
982 DRM_UNLOCKED | DRM_RENDER_ALLOW),
983 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
984 DRM_UNLOCKED | DRM_RENDER_ALLOW),
985 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
986 DRM_UNLOCKED | DRM_RENDER_ALLOW),
987 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
988 DRM_UNLOCKED | DRM_RENDER_ALLOW),
989 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
990 DRM_UNLOCKED | DRM_RENDER_ALLOW),
991 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
992 DRM_UNLOCKED | DRM_RENDER_ALLOW),
993 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
994 DRM_UNLOCKED | DRM_RENDER_ALLOW),
995 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
996 DRM_UNLOCKED | DRM_RENDER_ALLOW),
997 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
998 DRM_UNLOCKED | DRM_RENDER_ALLOW),
999 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
1000 DRM_UNLOCKED | DRM_RENDER_ALLOW),
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001001#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001002};
1003
1004static const struct file_operations tegra_drm_fops = {
1005 .owner = THIS_MODULE,
1006 .open = drm_open,
1007 .release = drm_release,
1008 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +02001009 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001010 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001011 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001012 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001013 .llseek = noop_llseek,
1014};
1015
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001016static int tegra_drm_context_cleanup(int id, void *p, void *data)
1017{
1018 struct tegra_drm_context *context = p;
1019
1020 tegra_drm_context_free(context);
1021
1022 return 0;
1023}
1024
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001025static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +01001026{
Thierry Reding08943e62013-09-26 16:08:18 +02001027 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +01001028
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001029 mutex_lock(&fpriv->lock);
1030 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1031 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001032
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001033 idr_destroy(&fpriv->contexts);
1034 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001035 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001036}
1037
Thierry Redinge450fcc2013-02-13 16:13:16 +01001038#ifdef CONFIG_DEBUG_FS
1039static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1040{
1041 struct drm_info_node *node = (struct drm_info_node *)s->private;
1042 struct drm_device *drm = node->minor->dev;
1043 struct drm_framebuffer *fb;
1044
1045 mutex_lock(&drm->mode_config.fb_lock);
1046
1047 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1048 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001049 fb->base.id, fb->width, fb->height,
1050 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001051 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001052 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001053 }
1054
1055 mutex_unlock(&drm->mode_config.fb_lock);
1056
1057 return 0;
1058}
1059
Thierry Reding28c23372015-01-23 09:16:03 +01001060static int tegra_debugfs_iova(struct seq_file *s, void *data)
1061{
1062 struct drm_info_node *node = (struct drm_info_node *)s->private;
1063 struct drm_device *drm = node->minor->dev;
1064 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001065 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001066
Michał Mirosław68d890a2017-08-14 23:53:45 +02001067 if (tegra->domain) {
1068 mutex_lock(&tegra->mm_lock);
1069 drm_mm_print(&tegra->mm, &p);
1070 mutex_unlock(&tegra->mm_lock);
1071 }
Daniel Vetterb5c37142016-12-29 12:09:24 +01001072
1073 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001074}
1075
Thierry Redinge450fcc2013-02-13 16:13:16 +01001076static struct drm_info_list tegra_debugfs_list[] = {
1077 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001078 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001079};
1080
1081static int tegra_debugfs_init(struct drm_minor *minor)
1082{
1083 return drm_debugfs_create_files(tegra_debugfs_list,
1084 ARRAY_SIZE(tegra_debugfs_list),
1085 minor->debugfs_root, minor);
1086}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001087#endif
1088
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001089static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001090 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
Thierry Reding6c68b712017-08-15 15:42:39 +02001091 DRIVER_ATOMIC | DRIVER_RENDER,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001092 .load = tegra_drm_load,
1093 .unload = tegra_drm_unload,
1094 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001095 .postclose = tegra_drm_postclose,
Noralf Trønnesc94beda2017-12-05 19:25:04 +01001096 .lastclose = drm_fb_helper_lastclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001097
Thierry Redinge450fcc2013-02-13 16:13:16 +01001098#if defined(CONFIG_DEBUG_FS)
1099 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001100#endif
1101
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001102 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001103 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001104
1105 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1106 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1107 .gem_prime_export = tegra_gem_prime_export,
1108 .gem_prime_import = tegra_gem_prime_import,
1109
Arto Merilainende2ba662013-03-22 16:34:08 +02001110 .dumb_create = tegra_bo_dumb_create,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001111
1112 .ioctls = tegra_drm_ioctls,
1113 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1114 .fops = &tegra_drm_fops,
1115
1116 .name = DRIVER_NAME,
1117 .desc = DRIVER_DESC,
1118 .date = DRIVER_DATE,
1119 .major = DRIVER_MAJOR,
1120 .minor = DRIVER_MINOR,
1121 .patchlevel = DRIVER_PATCHLEVEL,
1122};
Thierry Reding776dc382013-10-14 14:43:22 +02001123
1124int tegra_drm_register_client(struct tegra_drm *tegra,
1125 struct tegra_drm_client *client)
1126{
1127 mutex_lock(&tegra->clients_lock);
1128 list_add_tail(&client->list, &tegra->clients);
1129 mutex_unlock(&tegra->clients_lock);
1130
1131 return 0;
1132}
1133
1134int tegra_drm_unregister_client(struct tegra_drm *tegra,
1135 struct tegra_drm_client *client)
1136{
1137 mutex_lock(&tegra->clients_lock);
1138 list_del_init(&client->list);
1139 mutex_unlock(&tegra->clients_lock);
1140
1141 return 0;
1142}
1143
Thierry Reding67485fb2017-11-09 13:17:11 +01001144void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
Mikko Perttunenad926012016-12-14 13:16:11 +02001145{
1146 struct iova *alloc;
1147 void *virt;
1148 gfp_t gfp;
1149 int err;
1150
1151 if (tegra->domain)
1152 size = iova_align(&tegra->carveout.domain, size);
1153 else
1154 size = PAGE_ALIGN(size);
1155
1156 gfp = GFP_KERNEL | __GFP_ZERO;
1157 if (!tegra->domain) {
1158 /*
1159 * Many units only support 32-bit addresses, even on 64-bit
1160 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1161 * virtual address space, force allocations to be in the
1162 * lower 32-bit range.
1163 */
1164 gfp |= GFP_DMA;
1165 }
1166
1167 virt = (void *)__get_free_pages(gfp, get_order(size));
1168 if (!virt)
1169 return ERR_PTR(-ENOMEM);
1170
1171 if (!tegra->domain) {
1172 /*
1173 * If IOMMU is disabled, devices address physical memory
1174 * directly.
1175 */
1176 *dma = virt_to_phys(virt);
1177 return virt;
1178 }
1179
1180 alloc = alloc_iova(&tegra->carveout.domain,
1181 size >> tegra->carveout.shift,
1182 tegra->carveout.limit, true);
1183 if (!alloc) {
1184 err = -EBUSY;
1185 goto free_pages;
1186 }
1187
1188 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1189 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1190 size, IOMMU_READ | IOMMU_WRITE);
1191 if (err < 0)
1192 goto free_iova;
1193
1194 return virt;
1195
1196free_iova:
1197 __free_iova(&tegra->carveout.domain, alloc);
1198free_pages:
1199 free_pages((unsigned long)virt, get_order(size));
1200
1201 return ERR_PTR(err);
1202}
1203
1204void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1205 dma_addr_t dma)
1206{
1207 if (tegra->domain)
1208 size = iova_align(&tegra->carveout.domain, size);
1209 else
1210 size = PAGE_ALIGN(size);
1211
1212 if (tegra->domain) {
1213 iommu_unmap(tegra->domain, dma, size);
1214 free_iova(&tegra->carveout.domain,
1215 iova_pfn(&tegra->carveout.domain, dma));
1216 }
1217
1218 free_pages((unsigned long)virt, get_order(size));
1219}
1220
Thierry Reding9910f5c2014-05-22 09:57:15 +02001221static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001222{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001223 struct drm_driver *driver = &tegra_drm_driver;
1224 struct drm_device *drm;
1225 int err;
1226
1227 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001228 if (IS_ERR(drm))
1229 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001230
Thierry Reding9910f5c2014-05-22 09:57:15 +02001231 dev_set_drvdata(&dev->dev, drm);
1232
1233 err = drm_dev_register(drm, 0);
1234 if (err < 0)
1235 goto unref;
1236
Thierry Reding9910f5c2014-05-22 09:57:15 +02001237 return 0;
1238
1239unref:
1240 drm_dev_unref(drm);
1241 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001242}
1243
Thierry Reding9910f5c2014-05-22 09:57:15 +02001244static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001245{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001246 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1247
1248 drm_dev_unregister(drm);
1249 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001250
1251 return 0;
1252}
1253
Thierry Reding359ae682014-12-18 17:15:25 +01001254#ifdef CONFIG_PM_SLEEP
1255static int host1x_drm_suspend(struct device *dev)
1256{
1257 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001258 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001259
1260 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001261 tegra_drm_fb_suspend(drm);
1262
1263 tegra->state = drm_atomic_helper_suspend(drm);
1264 if (IS_ERR(tegra->state)) {
1265 tegra_drm_fb_resume(drm);
1266 drm_kms_helper_poll_enable(drm);
1267 return PTR_ERR(tegra->state);
1268 }
Thierry Reding359ae682014-12-18 17:15:25 +01001269
1270 return 0;
1271}
1272
1273static int host1x_drm_resume(struct device *dev)
1274{
1275 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001276 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001277
Thierry Reding986c58d2015-08-11 13:11:49 +02001278 drm_atomic_helper_resume(drm, tegra->state);
1279 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001280 drm_kms_helper_poll_enable(drm);
1281
1282 return 0;
1283}
1284#endif
1285
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001286static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1287 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001288
Thierry Reding776dc382013-10-14 14:43:22 +02001289static const struct of_device_id host1x_drm_subdevs[] = {
1290 { .compatible = "nvidia,tegra20-dc", },
1291 { .compatible = "nvidia,tegra20-hdmi", },
1292 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001293 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001294 { .compatible = "nvidia,tegra30-dc", },
1295 { .compatible = "nvidia,tegra30-hdmi", },
1296 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001297 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001298 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001299 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001300 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001301 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001302 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001303 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001304 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001305 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001306 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001307 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001308 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001309 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001310 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001311 { .compatible = "nvidia,tegra210-vic", },
Thierry Redingc4755fb2017-11-13 11:08:13 +01001312 { .compatible = "nvidia,tegra186-display", },
Thierry Reding47307952017-08-30 17:42:54 +02001313 { .compatible = "nvidia,tegra186-dc", },
Thierry Redingc57997b2017-10-12 19:12:57 +02001314 { .compatible = "nvidia,tegra186-sor", },
1315 { .compatible = "nvidia,tegra186-sor1", },
Mikko Perttunen6e44b9a2017-09-05 11:43:06 +03001316 { .compatible = "nvidia,tegra186-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001317 { /* sentinel */ }
1318};
1319
1320static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001321 .driver = {
1322 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001323 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001324 },
Thierry Reding776dc382013-10-14 14:43:22 +02001325 .probe = host1x_drm_probe,
1326 .remove = host1x_drm_remove,
1327 .subdevs = host1x_drm_subdevs,
1328};
1329
Thierry Reding473112e2015-09-10 16:07:14 +02001330static struct platform_driver * const drivers[] = {
Thierry Redingc4755fb2017-11-13 11:08:13 +01001331 &tegra_display_hub_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001332 &tegra_dc_driver,
1333 &tegra_hdmi_driver,
1334 &tegra_dsi_driver,
1335 &tegra_dpaux_driver,
1336 &tegra_sor_driver,
1337 &tegra_gr2d_driver,
1338 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001339 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001340};
1341
Thierry Reding776dc382013-10-14 14:43:22 +02001342static int __init host1x_drm_init(void)
1343{
1344 int err;
1345
1346 err = host1x_driver_register(&host1x_drm_driver);
1347 if (err < 0)
1348 return err;
1349
Thierry Reding473112e2015-09-10 16:07:14 +02001350 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001351 if (err < 0)
1352 goto unregister_host1x;
1353
Thierry Reding776dc382013-10-14 14:43:22 +02001354 return 0;
1355
Thierry Reding776dc382013-10-14 14:43:22 +02001356unregister_host1x:
1357 host1x_driver_unregister(&host1x_drm_driver);
1358 return err;
1359}
1360module_init(host1x_drm_init);
1361
1362static void __exit host1x_drm_exit(void)
1363{
Thierry Reding473112e2015-09-10 16:07:14 +02001364 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001365 host1x_driver_unregister(&host1x_drm_driver);
1366}
1367module_exit(host1x_drm_exit);
1368
1369MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1370MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1371MODULE_LICENSE("GPL v2");