blob: 967e9e4e795e7b808e1129c6db923bd85e366499 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
Ralf Baechle36ccf1c2006-02-14 21:04:54 +00006 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +010011 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
Steven J. Hill2a0b24f2013-03-25 12:15:55 -050012 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
Markos Chandrasb08a9c92013-12-04 16:20:08 +000013 * Copyright (C) 2014, Imagination Technologies Ltd.
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 */
Maciej W. Rozyckied2d72c2015-04-03 23:27:06 +010015#include <linux/bitops.h>
Ralf Baechle8e8a52e2007-05-31 14:00:19 +010016#include <linux/bug.h>
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +010017#include <linux/compiler.h>
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +020018#include <linux/context_tracking.h>
James Hoganae4ce452014-03-04 10:20:43 +000019#include <linux/cpu_pm.h>
Ralf Baechle7aa1c8f2012-10-11 18:14:58 +020020#include <linux/kexec.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/init.h>
Nathan Lynch8742cd22011-09-30 13:49:35 -050022#include <linux/kernel.h>
Paul Gortmakerf9ded562012-02-28 19:24:46 -050023#include <linux/module.h>
Paul Gortmaker9f3b8082016-08-15 19:11:52 -040024#include <linux/extable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/mm.h>
Ingo Molnar68e21be2017-02-01 19:08:20 +010026#include <linux/sched/mm.h>
Ingo Molnarb17b0152017-02-08 18:51:35 +010027#include <linux/sched/debug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <linux/spinlock.h>
30#include <linux/kallsyms.h>
Ralf Baechlee01402b2005-07-14 15:57:16 +000031#include <linux/bootmem.h>
Maxime Bizond4fd1982006-07-20 18:52:02 +020032#include <linux/interrupt.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010033#include <linux/ptrace.h>
Jason Wessel88547002008-07-29 15:58:53 -050034#include <linux/kgdb.h>
35#include <linux/kdebug.h>
David Daneyc1bf2072010-08-03 11:22:20 -070036#include <linux/kprobes.h>
Ralf Baechle69f3a7d2009-11-24 01:24:58 +000037#include <linux/notifier.h>
Jason Wessel5dd11d52010-05-20 21:04:26 -050038#include <linux/kdb.h>
David Howellsca4d3e672010-10-07 14:08:54 +010039#include <linux/irq.h>
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +080040#include <linux/perf_event.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
Paul Burtona13c9962015-09-22 10:15:22 -070042#include <asm/addrspace.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#include <asm/bootinfo.h>
44#include <asm/branch.h>
45#include <asm/break.h>
Ralf Baechle69f3a7d2009-11-24 01:24:58 +000046#include <asm/cop2.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <asm/cpu.h>
Ralf Baechle69f24d12013-09-17 10:25:47 +020048#include <asm/cpu-type.h>
Ralf Baechlee50c0a82005-05-31 11:49:19 +000049#include <asm/dsp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#include <asm/fpu.h>
Ralf Baechleba3049e2008-10-28 17:38:42 +000051#include <asm/fpu_emulator.h>
Ralf Baechlebdc92d742013-05-21 16:59:19 +020052#include <asm/idle.h>
Paul Burtone83f7e02017-08-12 19:49:41 -070053#include <asm/mips-cps.h>
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +000054#include <asm/mips-r2-to-r6-emul.h>
Ralf Baechle340ee4b2005-08-17 17:44:08 +000055#include <asm/mipsregs.h>
56#include <asm/mipsmtregs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#include <asm/module.h>
Paul Burton1db1af82014-01-27 15:23:11 +000058#include <asm/msa.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070059#include <asm/pgtable.h>
60#include <asm/ptrace.h>
61#include <asm/sections.h>
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +000062#include <asm/siginfo.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070063#include <asm/tlbdebug.h>
64#include <asm/traps.h>
Linus Torvalds7c0f6ba2016-12-24 11:46:01 -080065#include <linux/uaccess.h>
David Daneyb67b2b72008-09-23 00:08:45 -070066#include <asm/watch.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070067#include <asm/mmu_context.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070068#include <asm/types.h>
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +090069#include <asm/stacktrace.h>
Florian Fainelli92bbe1b2010-01-28 15:22:37 +010070#include <asm/uasm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090072extern void check_wait(void);
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090073extern asmlinkage void rollback_handle_int(void);
Ralf Baechlee4ac58a2006-04-03 17:56:36 +010074extern asmlinkage void handle_int(void);
Ralf Baechle86a17082013-02-08 01:21:34 +010075extern u32 handle_tlbl[];
76extern u32 handle_tlbs[];
77extern u32 handle_tlbm[];
Linus Torvalds1da177e2005-04-16 15:20:36 -070078extern asmlinkage void handle_adel(void);
79extern asmlinkage void handle_ades(void);
80extern asmlinkage void handle_ibe(void);
81extern asmlinkage void handle_dbe(void);
82extern asmlinkage void handle_sys(void);
83extern asmlinkage void handle_bp(void);
84extern asmlinkage void handle_ri(void);
Huacai Chen5a341332017-03-16 21:00:26 +080085extern asmlinkage void handle_ri_rdhwr_tlbp(void);
Atsushi Nemoto5b104962006-09-11 17:50:29 +090086extern asmlinkage void handle_ri_rdhwr(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070087extern asmlinkage void handle_cpu(void);
88extern asmlinkage void handle_ov(void);
89extern asmlinkage void handle_tr(void);
Paul Burton2bcb3fb2014-01-27 15:23:12 +000090extern asmlinkage void handle_msa_fpe(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070091extern asmlinkage void handle_fpe(void);
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +000092extern asmlinkage void handle_ftlb(void);
Paul Burton1db1af82014-01-27 15:23:11 +000093extern asmlinkage void handle_msa(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070094extern asmlinkage void handle_mdmx(void);
95extern asmlinkage void handle_watch(void);
Ralf Baechle340ee4b2005-08-17 17:44:08 +000096extern asmlinkage void handle_mt(void);
Ralf Baechlee50c0a82005-05-31 11:49:19 +000097extern asmlinkage void handle_dsp(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070098extern asmlinkage void handle_mcheck(void);
99extern asmlinkage void handle_reserved(void);
Leonid Yegoshin5890f702014-07-15 14:09:56 +0100100extern void tlb_do_page_fault_0(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102void (*board_be_init)(void);
103int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
Ralf Baechlee01402b2005-07-14 15:57:16 +0000104void (*board_nmi_handler_setup)(void);
105void (*board_ejtag_handler_setup)(void);
106void (*board_bind_eic_interrupt)(int irq, int regset);
Kevin Cernekee6fb97ef2011-11-16 01:25:45 +0000107void (*board_ebase_setup)(void);
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000108void(*board_cache_error_setup)(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200110static void show_raw_backtrace(unsigned long reg29)
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900111{
Ralf Baechle39b8d522008-04-28 17:14:26 +0100112 unsigned long *sp = (unsigned long *)(reg29 & ~3);
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900113 unsigned long addr;
114
115 printk("Call Trace:");
116#ifdef CONFIG_KALLSYMS
117 printk("\n");
118#endif
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200119 while (!kstack_end(sp)) {
120 unsigned long __user *p =
121 (unsigned long __user *)(unsigned long)sp++;
122 if (__get_user(addr, p)) {
123 printk(" (Bad stack address)");
124 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100125 }
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200126 if (__kernel_text_address(addr))
127 print_ip_sym(addr);
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900128 }
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200129 printk("\n");
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900130}
131
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900132#ifdef CONFIG_KALLSYMS
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +0900133int raw_show_trace;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900134static int __init set_raw_show_trace(char *str)
135{
136 raw_show_trace = 1;
137 return 1;
138}
139__setup("raw_show_trace", set_raw_show_trace);
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +0900140#endif
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200141
Ralf Baechleeae23f22007-10-14 23:27:21 +0100142static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900143{
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200144 unsigned long sp = regs->regs[29];
145 unsigned long ra = regs->regs[31];
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900146 unsigned long pc = regs->cp0_epc;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900147
Vincent Wene909be82012-07-19 09:11:16 +0200148 if (!task)
149 task = current;
150
James Hogan81a76d72015-12-04 22:25:02 +0000151 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200152 show_raw_backtrace(sp);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900153 return;
154 }
155 printk("Call Trace:\n");
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200156 do {
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200157 print_ip_sym(pc);
Atsushi Nemoto19246002006-09-29 18:02:51 +0900158 pc = unwind_stack(task, &sp, pc, &ra);
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200159 } while (pc);
Matt Redfearnbcf084d2016-10-19 14:33:20 +0100160 pr_cont("\n");
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900161}
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900162
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163/*
164 * This routine abuses get_user()/put_user() to reference pointers
165 * with at least a bit of error checking ...
166 */
Ralf Baechleeae23f22007-10-14 23:27:21 +0100167static void show_stacktrace(struct task_struct *task,
168 const struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169{
170 const int field = 2 * sizeof(unsigned long);
171 long stackdata;
172 int i;
Atsushi Nemoto5e0373b2007-07-13 23:02:42 +0900173 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174
175 printk("Stack :");
176 i = 0;
177 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100178 if (i && ((i % (64 / field)) == 0)) {
179 pr_cont("\n");
180 printk(" ");
181 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 if (i > 39) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100183 pr_cont(" ...");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 break;
185 }
186
187 if (__get_user(stackdata, sp++)) {
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100188 pr_cont(" (Bad stack address)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 break;
190 }
191
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100192 pr_cont(" %0*lx", field, stackdata);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 i++;
194 }
Matt Redfearnfe4e09e2016-10-19 14:33:21 +0100195 pr_cont("\n");
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200196 show_backtrace(task, regs);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900197}
198
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900199void show_stack(struct task_struct *task, unsigned long *sp)
200{
201 struct pt_regs regs;
James Hogan1e778632015-07-27 13:50:22 +0100202 mm_segment_t old_fs = get_fs();
James Hogan85423632017-06-29 15:05:04 +0100203
204 regs.cp0_status = KSU_KERNEL;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900205 if (sp) {
206 regs.regs[29] = (unsigned long)sp;
207 regs.regs[31] = 0;
208 regs.cp0_epc = 0;
209 } else {
210 if (task && task != current) {
211 regs.regs[29] = task->thread.reg29;
212 regs.regs[31] = 0;
213 regs.cp0_epc = task->thread.reg31;
Jason Wessel5dd11d52010-05-20 21:04:26 -0500214#ifdef CONFIG_KGDB_KDB
215 } else if (atomic_read(&kgdb_active) != -1 &&
216 kdb_current_regs) {
217 memcpy(&regs, kdb_current_regs, sizeof(regs));
218#endif /* CONFIG_KGDB_KDB */
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900219 } else {
220 prepare_frametrace(&regs);
221 }
222 }
James Hogan1e778632015-07-27 13:50:22 +0100223 /*
224 * show_stack() deals exclusively with kernel mode, so be sure to access
225 * the stack in the kernel (not user) address space.
226 */
227 set_fs(KERNEL_DS);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900228 show_stacktrace(task, &regs);
James Hogan1e778632015-07-27 13:50:22 +0100229 set_fs(old_fs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230}
231
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +0900232static void show_code(unsigned int __user *pc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233{
234 long i;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100235 unsigned short __user *pc16 = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
Matt Redfearn41000c52016-10-19 14:33:22 +0100237 printk("Code:");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238
Ralf Baechle39b8d522008-04-28 17:14:26 +0100239 if ((unsigned long)pc & 1)
240 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 for(i = -3 ; i < 6 ; i++) {
242 unsigned int insn;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100243 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
Matt Redfearn41000c52016-10-19 14:33:22 +0100244 pr_cont(" (Bad address in epc)\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 break;
246 }
Matt Redfearn41000c52016-10-19 14:33:22 +0100247 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 }
Matt Redfearn41000c52016-10-19 14:33:22 +0100249 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250}
251
Ralf Baechleeae23f22007-10-14 23:27:21 +0100252static void __show_regs(const struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253{
254 const int field = 2 * sizeof(unsigned long);
255 unsigned int cause = regs->cp0_cause;
Petri Gynther37dd3812015-05-08 15:10:10 -0700256 unsigned int exccode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 int i;
258
Tejun Heoa43cb952013-04-30 15:27:17 -0700259 show_regs_print_info(KERN_DEFAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260
261 /*
262 * Saved main processor registers
263 */
264 for (i = 0; i < 32; ) {
265 if ((i % 4) == 0)
266 printk("$%2d :", i);
267 if (i == 0)
Paul Burton752f5492016-10-19 14:33:23 +0100268 pr_cont(" %0*lx", field, 0UL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 else if (i == 26 || i == 27)
Paul Burton752f5492016-10-19 14:33:23 +0100270 pr_cont(" %*s", field, "");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 else
Paul Burton752f5492016-10-19 14:33:23 +0100272 pr_cont(" %0*lx", field, regs->regs[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273
274 i++;
275 if ((i % 4) == 0)
Paul Burton752f5492016-10-19 14:33:23 +0100276 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 }
278
Franck Bui-Huu9693a852007-02-02 17:41:47 +0100279#ifdef CONFIG_CPU_HAS_SMARTMIPS
280 printk("Acx : %0*lx\n", field, regs->acx);
281#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 printk("Hi : %0*lx\n", field, regs->hi);
283 printk("Lo : %0*lx\n", field, regs->lo);
284
285 /*
286 * Saved cp0 registers
287 */
Ralf Baechleb012cff2008-07-15 18:44:33 +0100288 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
289 (void *) regs->cp0_epc);
Ralf Baechleb012cff2008-07-15 18:44:33 +0100290 printk("ra : %0*lx %pS\n", field, regs->regs[31],
291 (void *) regs->regs[31]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
Ralf Baechle70342282013-01-22 12:59:30 +0100293 printk("Status: %08x ", (uint32_t) regs->cp0_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294
Ralf Baechle1990e542013-06-26 17:06:34 +0200295 if (cpu_has_3kex) {
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000296 if (regs->cp0_status & ST0_KUO)
Paul Burton752f5492016-10-19 14:33:23 +0100297 pr_cont("KUo ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000298 if (regs->cp0_status & ST0_IEO)
Paul Burton752f5492016-10-19 14:33:23 +0100299 pr_cont("IEo ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000300 if (regs->cp0_status & ST0_KUP)
Paul Burton752f5492016-10-19 14:33:23 +0100301 pr_cont("KUp ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000302 if (regs->cp0_status & ST0_IEP)
Paul Burton752f5492016-10-19 14:33:23 +0100303 pr_cont("IEp ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000304 if (regs->cp0_status & ST0_KUC)
Paul Burton752f5492016-10-19 14:33:23 +0100305 pr_cont("KUc ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000306 if (regs->cp0_status & ST0_IEC)
Paul Burton752f5492016-10-19 14:33:23 +0100307 pr_cont("IEc ");
Ralf Baechle1990e542013-06-26 17:06:34 +0200308 } else if (cpu_has_4kex) {
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000309 if (regs->cp0_status & ST0_KX)
Paul Burton752f5492016-10-19 14:33:23 +0100310 pr_cont("KX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000311 if (regs->cp0_status & ST0_SX)
Paul Burton752f5492016-10-19 14:33:23 +0100312 pr_cont("SX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000313 if (regs->cp0_status & ST0_UX)
Paul Burton752f5492016-10-19 14:33:23 +0100314 pr_cont("UX ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000315 switch (regs->cp0_status & ST0_KSU) {
316 case KSU_USER:
Paul Burton752f5492016-10-19 14:33:23 +0100317 pr_cont("USER ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000318 break;
319 case KSU_SUPERVISOR:
Paul Burton752f5492016-10-19 14:33:23 +0100320 pr_cont("SUPERVISOR ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000321 break;
322 case KSU_KERNEL:
Paul Burton752f5492016-10-19 14:33:23 +0100323 pr_cont("KERNEL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000324 break;
325 default:
Paul Burton752f5492016-10-19 14:33:23 +0100326 pr_cont("BAD_MODE ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000327 break;
328 }
329 if (regs->cp0_status & ST0_ERL)
Paul Burton752f5492016-10-19 14:33:23 +0100330 pr_cont("ERL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000331 if (regs->cp0_status & ST0_EXL)
Paul Burton752f5492016-10-19 14:33:23 +0100332 pr_cont("EXL ");
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000333 if (regs->cp0_status & ST0_IE)
Paul Burton752f5492016-10-19 14:33:23 +0100334 pr_cont("IE ");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 }
Paul Burton752f5492016-10-19 14:33:23 +0100336 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337
Petri Gynther37dd3812015-05-08 15:10:10 -0700338 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
339 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340
Petri Gynther37dd3812015-05-08 15:10:10 -0700341 if (1 <= exccode && exccode <= 5)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
343
Ralf Baechle9966db252007-10-11 23:46:17 +0100344 printk("PrId : %08x (%s)\n", read_c0_prid(),
345 cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346}
347
Ralf Baechleeae23f22007-10-14 23:27:21 +0100348/*
349 * FIXME: really the generic show_regs should take a const pointer argument.
350 */
351void show_regs(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352{
Ralf Baechleeae23f22007-10-14 23:27:21 +0100353 __show_regs((struct pt_regs *)regs);
354}
355
David Daneyc1bf2072010-08-03 11:22:20 -0700356void show_registers(struct pt_regs *regs)
Ralf Baechleeae23f22007-10-14 23:27:21 +0100357{
Ralf Baechle39b8d522008-04-28 17:14:26 +0100358 const int field = 2 * sizeof(unsigned long);
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100359 mm_segment_t old_fs = get_fs();
Ralf Baechle39b8d522008-04-28 17:14:26 +0100360
Ralf Baechleeae23f22007-10-14 23:27:21 +0100361 __show_regs(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 print_modules();
Ralf Baechle39b8d522008-04-28 17:14:26 +0100363 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
364 current->comm, current->pid, current_thread_info(), current,
365 field, current_thread_info()->tp_value);
366 if (cpu_has_userlocal) {
367 unsigned long tls;
368
369 tls = read_c0_userlocal();
370 if (tls != current_thread_info()->tp_value)
371 printk("*HwTLS: %0*lx\n", field, tls);
372 }
373
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100374 if (!user_mode(regs))
375 /* Necessary for getting the correct stack content */
376 set_fs(KERNEL_DS);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900377 show_stacktrace(current, regs);
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +0900378 show_code((unsigned int __user *) regs->cp0_epc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 printk("\n");
Leonid Yegoshin83e4da12013-10-08 12:39:31 +0100380 set_fs(old_fs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381}
382
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000383static DEFINE_RAW_SPINLOCK(die_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384
David Daney70dc6f02010-08-03 15:44:43 -0700385void __noreturn die(const char *str, struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386{
387 static int die_counter;
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400388 int sig = SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389
Nathan Lynch8742cd22011-09-30 13:49:35 -0500390 oops_enter();
391
Ralf Baechlee3b28832015-07-28 20:37:43 +0200392 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200393 SIGSEGV) == NOTIFY_STOP)
Ralf Baechle10423c92011-05-13 10:33:28 +0100394 sig = 0;
Jason Wessel5dd11d52010-05-20 21:04:26 -0500395
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 console_verbose();
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000397 raw_spin_lock_irq(&die_lock);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100398 bust_spinlocks(1);
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400399
Ralf Baechle178086c2005-10-13 17:07:54 +0100400 printk("%s[#%d]:\n", str, ++die_counter);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 show_registers(regs);
Rusty Russell373d4d02013-01-21 17:17:39 +1030402 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000403 raw_spin_unlock_irq(&die_lock);
Maxime Bizond4fd1982006-07-20 18:52:02 +0200404
Nathan Lynch8742cd22011-09-30 13:49:35 -0500405 oops_exit();
406
Maxime Bizond4fd1982006-07-20 18:52:02 +0200407 if (in_interrupt())
408 panic("Fatal exception in interrupt");
409
Aaro Koskinen99a7a232016-03-09 22:08:42 +0200410 if (panic_on_oops)
Maxime Bizond4fd1982006-07-20 18:52:02 +0200411 panic("Fatal exception");
Maxime Bizond4fd1982006-07-20 18:52:02 +0200412
Ralf Baechle7aa1c8f2012-10-11 18:14:58 +0200413 if (regs && kexec_should_crash(current))
414 crash_kexec(regs);
415
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400416 do_exit(sig);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417}
418
Thomas Bogendoerfer05106172008-08-04 19:44:34 +0200419extern struct exception_table_entry __start___dbe_table[];
420extern struct exception_table_entry __stop___dbe_table[];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421
Ralf Baechleb6dcec92007-02-18 15:57:09 +0000422__asm__(
423" .section __dbe_table, \"a\"\n"
424" .previous \n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425
426/* Given an address, look for it in the exception tables. */
427static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
428{
429 const struct exception_table_entry *e;
430
Thomas Meyera94c33d2017-07-10 15:51:58 -0700431 e = search_extable(__start___dbe_table,
432 __stop___dbe_table - __start___dbe_table, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433 if (!e)
434 e = search_module_dbetables(addr);
435 return e;
436}
437
438asmlinkage void do_be(struct pt_regs *regs)
439{
440 const int field = 2 * sizeof(unsigned long);
441 const struct exception_table_entry *fixup = NULL;
442 int data = regs->cp0_cause & 4;
443 int action = MIPS_BE_FATAL;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200444 enum ctx_state prev_state;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200446 prev_state = exception_enter();
Ralf Baechle70342282013-01-22 12:59:30 +0100447 /* XXX For now. Fixme, this searches the wrong table ... */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 if (data && !user_mode(regs))
449 fixup = search_dbe_tables(exception_epc(regs));
450
451 if (fixup)
452 action = MIPS_BE_FIXUP;
453
454 if (board_be_handler)
Atsushi Nemoto28fc5822007-07-13 01:49:49 +0900455 action = board_be_handler(regs, fixup != NULL);
Paul Burtondabdc182016-10-05 18:18:17 +0100456 else
457 mips_cm_error_report();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458
459 switch (action) {
460 case MIPS_BE_DISCARD:
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200461 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 case MIPS_BE_FIXUP:
463 if (fixup) {
464 regs->cp0_epc = fixup->nextinsn;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200465 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 }
467 break;
468 default:
469 break;
470 }
471
472 /*
473 * Assume it would be too dangerous to continue ...
474 */
475 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
476 data ? "Data" : "Instruction",
477 field, regs->cp0_epc, field, regs->regs[31]);
Ralf Baechlee3b28832015-07-28 20:37:43 +0200478 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200479 SIGBUS) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200480 goto out;
Jason Wessel88547002008-07-29 15:58:53 -0500481
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482 die_if_kernel("Oops", regs);
483 force_sig(SIGBUS, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200484
485out:
486 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487}
488
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489/*
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100490 * ll/sc, rdhwr, sync emulation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491 */
492
493#define OPCODE 0xfc000000
494#define BASE 0x03e00000
495#define RT 0x001f0000
496#define OFFSET 0x0000ffff
497#define LL 0xc0000000
498#define SC 0xe0000000
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100499#define SPEC0 0x00000000
Ralf Baechle3c370262005-04-13 17:43:59 +0000500#define SPEC3 0x7c000000
501#define RD 0x0000f800
502#define FUNC 0x0000003f
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100503#define SYNC 0x0000000f
Ralf Baechle3c370262005-04-13 17:43:59 +0000504#define RDHWR 0x0000003b
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500506/* microMIPS definitions */
507#define MM_POOL32A_FUNC 0xfc00ffff
508#define MM_RDHWR 0x00006b3c
509#define MM_RS 0x001f0000
510#define MM_RT 0x03e00000
511
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512/*
513 * The ll_bit is cleared by r*_switch.S
514 */
515
Ralf Baechlef1e39a42009-09-17 02:25:05 +0200516unsigned int ll_bit;
517struct task_struct *ll_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100519static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520{
Ralf Baechlefe00f942005-03-01 19:22:29 +0000521 unsigned long value, __user *vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522 long offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523
524 /*
525 * analyse the ll instruction that just caused a ri exception
526 * and put the referenced address to addr.
527 */
528
529 /* sign extend offset */
530 offset = opcode & OFFSET;
531 offset <<= 16;
532 offset >>= 16;
533
Ralf Baechlefe00f942005-03-01 19:22:29 +0000534 vaddr = (unsigned long __user *)
Steven J. Hillb9688312013-01-12 23:29:27 +0000535 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100537 if ((unsigned long)vaddr & 3)
538 return SIGBUS;
539 if (get_user(value, vaddr))
540 return SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541
542 preempt_disable();
543
544 if (ll_task == NULL || ll_task == current) {
545 ll_bit = 1;
546 } else {
547 ll_bit = 0;
548 }
549 ll_task = current;
550
551 preempt_enable();
552
553 regs->regs[(opcode & RT) >> 16] = value;
554
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100555 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556}
557
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100558static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559{
Ralf Baechlefe00f942005-03-01 19:22:29 +0000560 unsigned long __user *vaddr;
561 unsigned long reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562 long offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563
564 /*
565 * analyse the sc instruction that just caused a ri exception
566 * and put the referenced address to addr.
567 */
568
569 /* sign extend offset */
570 offset = opcode & OFFSET;
571 offset <<= 16;
572 offset >>= 16;
573
Ralf Baechlefe00f942005-03-01 19:22:29 +0000574 vaddr = (unsigned long __user *)
Steven J. Hillb9688312013-01-12 23:29:27 +0000575 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576 reg = (opcode & RT) >> 16;
577
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100578 if ((unsigned long)vaddr & 3)
579 return SIGBUS;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580
581 preempt_disable();
582
583 if (ll_bit == 0 || ll_task != current) {
584 regs->regs[reg] = 0;
585 preempt_enable();
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100586 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587 }
588
589 preempt_enable();
590
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100591 if (put_user(regs->regs[reg], vaddr))
592 return SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593
594 regs->regs[reg] = 1;
595
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100596 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597}
598
599/*
600 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
601 * opcodes are supposed to result in coprocessor unusable exceptions if
602 * executed on ll/sc-less processors. That's the theory. In practice a
603 * few processors such as NEC's VR4100 throw reserved instruction exceptions
604 * instead, so we're doing the emulation thing in both exception handlers.
605 */
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100606static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607{
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800608 if ((opcode & OPCODE) == LL) {
609 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200610 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100611 return simulate_ll(regs, opcode);
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800612 }
613 if ((opcode & OPCODE) == SC) {
614 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200615 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100616 return simulate_sc(regs, opcode);
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800617 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100619 return -1; /* Must be something else ... */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620}
621
Ralf Baechle3c370262005-04-13 17:43:59 +0000622/*
623 * Simulate trapping 'rdhwr' instructions to provide user accessible
Chris Dearman1f5826b2006-05-08 18:02:16 +0100624 * registers not implemented in hardware.
Ralf Baechle3c370262005-04-13 17:43:59 +0000625 */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500626static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
Ralf Baechle3c370262005-04-13 17:43:59 +0000627{
Al Virodc8f6022006-01-12 01:06:07 -0800628 struct thread_info *ti = task_thread_info(current);
Ralf Baechle3c370262005-04-13 17:43:59 +0000629
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500630 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
631 1, regs, 0);
632 switch (rd) {
James Hoganaff565a2016-06-15 19:29:52 +0100633 case MIPS_HWR_CPUNUM: /* CPU number */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500634 regs->regs[rt] = smp_processor_id();
635 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100636 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500637 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
638 current_cpu_data.icache.linesz);
639 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100640 case MIPS_HWR_CC: /* Read count register */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500641 regs->regs[rt] = read_c0_count();
642 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100643 case MIPS_HWR_CCRES: /* Count register resolution */
Ralf Baechle69f24d12013-09-17 10:25:47 +0200644 switch (current_cpu_type()) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500645 case CPU_20KC:
646 case CPU_25KF:
647 regs->regs[rt] = 1;
648 break;
649 default:
650 regs->regs[rt] = 2;
651 }
652 return 0;
James Hoganaff565a2016-06-15 19:29:52 +0100653 case MIPS_HWR_ULR: /* Read UserLocal register */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500654 regs->regs[rt] = ti->tp_value;
655 return 0;
656 default:
657 return -1;
658 }
659}
660
661static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
662{
Ralf Baechle3c370262005-04-13 17:43:59 +0000663 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
664 int rd = (opcode & RD) >> 11;
665 int rt = (opcode & RT) >> 16;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500666
667 simulate_rdhwr(regs, rd, rt);
668 return 0;
669 }
670
671 /* Not ours. */
672 return -1;
673}
674
Maciej W. Rozycki7aa70472016-01-30 09:08:28 +0000675static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500676{
677 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
678 int rd = (opcode & MM_RS) >> 16;
679 int rt = (opcode & MM_RT) >> 21;
680 simulate_rdhwr(regs, rd, rt);
681 return 0;
Ralf Baechle3c370262005-04-13 17:43:59 +0000682 }
683
Daniel Jacobowitz56ebd512005-11-26 22:34:41 -0500684 /* Not ours. */
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100685 return -1;
686}
Ralf Baechlee5679882006-11-30 01:14:47 +0000687
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100688static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
689{
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800690 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
691 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200692 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100693 return 0;
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800694 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100695
696 return -1; /* Must be something else ... */
Ralf Baechle3c370262005-04-13 17:43:59 +0000697}
698
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699asmlinkage void do_ov(struct pt_regs *regs)
700{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200701 enum ctx_state prev_state;
Eric W. Biederman5f749722018-01-22 14:58:57 -0600702 siginfo_t info;
703
704 clear_siginfo(&info);
705 info.si_signo = SIGFPE;
706 info.si_code = FPE_INTOVF;
707 info.si_addr = (void __user *)regs->cp0_epc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200709 prev_state = exception_enter();
Ralf Baechle36ccf1c2006-02-14 21:04:54 +0000710 die_if_kernel("Integer overflow", regs);
711
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712 force_sig_info(SIGFPE, &info, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200713 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714}
715
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100716/*
717 * Send SIGFPE according to FCSR Cause bits, which must have already
718 * been masked against Enable bits. This is impotant as Inexact can
719 * happen together with Overflow or Underflow, and `ptrace' can set
720 * any bits.
721 */
722void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
723 struct task_struct *tsk)
724{
Eric W. Biederman5f749722018-01-22 14:58:57 -0600725 struct siginfo si;
726
727 clear_siginfo(&si);
728 si.si_addr = fault_addr;
729 si.si_signo = SIGFPE;
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100730
731 if (fcr31 & FPU_CSR_INV_X)
732 si.si_code = FPE_FLTINV;
733 else if (fcr31 & FPU_CSR_DIV_X)
734 si.si_code = FPE_FLTDIV;
735 else if (fcr31 & FPU_CSR_OVF_X)
736 si.si_code = FPE_FLTOVF;
737 else if (fcr31 & FPU_CSR_UDF_X)
738 si.si_code = FPE_FLTUND;
739 else if (fcr31 & FPU_CSR_INE_X)
740 si.si_code = FPE_FLTRES;
Ralf Baechleb1237182017-08-07 21:14:18 +0200741
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100742 force_sig_info(SIGFPE, &si, tsk);
743}
744
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100745int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
David Daney515b0292010-10-21 16:32:26 -0700746{
Eric W. Biederman5f749722018-01-22 14:58:57 -0600747 struct siginfo si;
Petar Jovanovicbcfc8f02016-07-13 15:23:37 +0200748 struct vm_area_struct *vma;
Paul Burtonad70c132015-01-30 12:09:35 +0000749
Eric W. Biederman5f749722018-01-22 14:58:57 -0600750 clear_siginfo(&si);
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100751 switch (sig) {
752 case 0:
753 return 0;
754
755 case SIGFPE:
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100756 force_fcr31_sig(fcr31, fault_addr, current);
David Daney515b0292010-10-21 16:32:26 -0700757 return 1;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100758
759 case SIGBUS:
760 si.si_addr = fault_addr;
761 si.si_signo = sig;
762 si.si_code = BUS_ADRERR;
763 force_sig_info(sig, &si, current);
764 return 1;
765
766 case SIGSEGV:
767 si.si_addr = fault_addr;
768 si.si_signo = sig;
769 down_read(&current->mm->mmap_sem);
Petar Jovanovicbcfc8f02016-07-13 15:23:37 +0200770 vma = find_vma(current->mm, (unsigned long)fault_addr);
771 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100772 si.si_code = SEGV_ACCERR;
773 else
774 si.si_code = SEGV_MAPERR;
775 up_read(&current->mm->mmap_sem);
776 force_sig_info(sig, &si, current);
777 return 1;
778
779 default:
David Daney515b0292010-10-21 16:32:26 -0700780 force_sig(sig, current);
781 return 1;
David Daney515b0292010-10-21 16:32:26 -0700782 }
783}
784
Paul Burton4227a2d2014-09-11 08:30:20 +0100785static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
786 unsigned long old_epc, unsigned long old_ra)
787{
788 union mips_instruction inst = { .word = opcode };
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100789 void __user *fault_addr;
790 unsigned long fcr31;
Paul Burton4227a2d2014-09-11 08:30:20 +0100791 int sig;
792
793 /* If it's obviously not an FP instruction, skip it */
794 switch (inst.i_format.opcode) {
795 case cop1_op:
796 case cop1x_op:
797 case lwc1_op:
798 case ldc1_op:
799 case swc1_op:
800 case sdc1_op:
801 break;
802
803 default:
804 return -1;
805 }
806
807 /*
808 * do_ri skipped over the instruction via compute_return_epc, undo
809 * that for the FPU emulator.
810 */
811 regs->cp0_epc = old_epc;
812 regs->regs[31] = old_ra;
813
814 /* Save the FP context to struct thread_struct */
815 lose_fpu(1);
816
817 /* Run the emulator */
818 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
819 &fault_addr);
820
Maciej W. Rozycki443c4402015-04-03 23:27:10 +0100821 /*
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100822 * We can't allow the emulated instruction to leave any
823 * enabled Cause bits set in $fcr31.
Maciej W. Rozycki443c4402015-04-03 23:27:10 +0100824 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100825 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
826 current->thread.fpu.fcr31 &= ~fcr31;
Paul Burton4227a2d2014-09-11 08:30:20 +0100827
828 /* Restore the hardware register state */
829 own_fpu(1);
830
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100831 /* Send a signal if required. */
832 process_fpemu_return(sig, fault_addr, fcr31);
833
Paul Burton4227a2d2014-09-11 08:30:20 +0100834 return 0;
835}
836
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837/*
838 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
839 */
840asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
841{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200842 enum ctx_state prev_state;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100843 void __user *fault_addr;
844 int sig;
Thiemo Seufer948a34c2007-08-22 01:42:04 +0100845
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200846 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +0200847 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200848 SIGFPE) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200849 goto out;
James Hogan64bedff2014-12-02 13:44:13 +0000850
851 /* Clear FCSR.Cause before enabling interrupts */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100852 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
James Hogan64bedff2014-12-02 13:44:13 +0000853 local_irq_enable();
854
Chris Dearman57725f92006-06-30 23:35:28 +0100855 die_if_kernel("FP exception in kernel code", regs);
856
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 if (fcr31 & FPU_CSR_UNI_X) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 /*
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000859 * Unimplemented operation exception. If we've got the full
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 * software emulator on-board, let's use it...
861 *
862 * Force FPU to dump state into task/thread context. We're
863 * moving a lot of data here for what is probably a single
864 * instruction, but the alternative is to pre-decode the FP
865 * register operands before invoking the emulator, which seems
866 * a bit extreme for what should be an infrequent event.
867 */
Ralf Baechlecd21dfc2005-04-28 13:39:10 +0000868 /* Ensure 'resume' not overwrite saved fp context again. */
Atsushi Nemoto53dc8022007-03-10 01:07:45 +0900869 lose_fpu(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870
871 /* Run the emulator */
David Daney515b0292010-10-21 16:32:26 -0700872 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
873 &fault_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874
875 /*
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100876 * We can't allow the emulated instruction to leave any
877 * enabled Cause bits set in $fcr31.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +0100879 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
880 current->thread.fpu.fcr31 &= ~fcr31;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881
882 /* Restore the hardware register state */
Ralf Baechle70342282013-01-22 12:59:30 +0100883 own_fpu(1); /* Using the FPU again. */
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100884 } else {
885 sig = SIGFPE;
886 fault_addr = (void __user *) regs->cp0_epc;
Maciej W. Rozyckied2d72c2015-04-03 23:27:06 +0100887 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888
Maciej W. Rozycki304acb72015-04-03 23:27:15 +0100889 /* Send a signal if required. */
890 process_fpemu_return(sig, fault_addr, fcr31);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200891
892out:
893 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894}
895
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +0000896void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
Ralf Baechledf270052008-04-20 16:28:54 +0100897 const char *str)
898{
Eric W. Biederman5f749722018-01-22 14:58:57 -0600899 siginfo_t info;
Ralf Baechledf270052008-04-20 16:28:54 +0100900 char b[40];
901
Eric W. Biederman5f749722018-01-22 14:58:57 -0600902 clear_siginfo(&info);
Jason Wessel5dd11d52010-05-20 21:04:26 -0500903#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
Ralf Baechlee3b28832015-07-28 20:37:43 +0200904 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
905 SIGTRAP) == NOTIFY_STOP)
Jason Wessel5dd11d52010-05-20 21:04:26 -0500906 return;
907#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
908
Ralf Baechlee3b28832015-07-28 20:37:43 +0200909 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +0200910 SIGTRAP) == NOTIFY_STOP)
Jason Wessel88547002008-07-29 15:58:53 -0500911 return;
912
Ralf Baechledf270052008-04-20 16:28:54 +0100913 /*
914 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
915 * insns, even for trap and break codes that indicate arithmetic
916 * failures. Weird ...
917 * But should we continue the brokenness??? --macro
918 */
919 switch (code) {
920 case BRK_OVERFLOW:
921 case BRK_DIVZERO:
922 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
923 die_if_kernel(b, regs);
924 if (code == BRK_DIVZERO)
925 info.si_code = FPE_INTDIV;
926 else
927 info.si_code = FPE_INTOVF;
928 info.si_signo = SIGFPE;
Ralf Baechledf270052008-04-20 16:28:54 +0100929 info.si_addr = (void __user *) regs->cp0_epc;
930 force_sig_info(SIGFPE, &info, current);
931 break;
932 case BRK_BUG:
933 die_if_kernel("Kernel bug detected", regs);
934 force_sig(SIGTRAP, current);
935 break;
Ralf Baechleba3049e2008-10-28 17:38:42 +0000936 case BRK_MEMU:
937 /*
Maciej W. Rozycki1f443772015-04-03 23:24:14 +0100938 * This breakpoint code is used by the FPU emulator to retake
939 * control of the CPU after executing the instruction from the
940 * delay slot of an emulated branch.
Ralf Baechleba3049e2008-10-28 17:38:42 +0000941 *
942 * Terminate if exception was recognized as a delay slot return
943 * otherwise handle as normal.
944 */
945 if (do_dsemulret(regs))
946 return;
947
948 die_if_kernel("Math emu break/trap", regs);
949 force_sig(SIGTRAP, current);
950 break;
Ralf Baechledf270052008-04-20 16:28:54 +0100951 default:
952 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
953 die_if_kernel(b, regs);
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +0000954 if (si_code) {
955 info.si_signo = SIGTRAP;
956 info.si_code = si_code;
957 force_sig_info(SIGTRAP, &info, current);
958 } else {
959 force_sig(SIGTRAP, current);
960 }
Ralf Baechledf270052008-04-20 16:28:54 +0100961 }
962}
963
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964asmlinkage void do_bp(struct pt_regs *regs)
965{
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100966 unsigned long epc = msk_isa16_mode(exception_epc(regs));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967 unsigned int opcode, bcode;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200968 enum ctx_state prev_state;
Leonid Yegoshin078dde52013-12-04 16:39:34 +0000969 mm_segment_t seg;
970
971 seg = get_fs();
972 if (!user_mode(regs))
973 set_fs(KERNEL_DS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +0200975 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +0200976 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500977 if (get_isa16_mode(regs->cp0_epc)) {
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100978 u16 instr[2];
979
980 if (__get_user(instr[0], (u16 __user *)epc))
981 goto out_sigsegv;
982
983 if (!cpu_has_mmips) {
984 /* MIPS16e mode */
985 bcode = (instr[0] >> 5) & 0x3f;
986 } else if (mm_insn_16bit(instr[0])) {
987 /* 16-bit microMIPS BREAK */
988 bcode = instr[0] & 0xf;
989 } else {
990 /* 32-bit microMIPS BREAK */
991 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500992 goto out_sigsegv;
Markos Chandrasb08a9c92013-12-04 16:20:08 +0000993 opcode = (instr[0] << 16) | instr[1];
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100994 bcode = (opcode >> 6) & ((1 << 20) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500995 }
996 } else {
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100997 if (__get_user(opcode, (unsigned int __user *)epc))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500998 goto out_sigsegv;
Maciej W. Rozyckif6a31da2015-04-03 23:26:27 +0100999 bcode = (opcode >> 6) & ((1 << 20) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001000 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001
1002 /*
1003 * There is the ancient bug in the MIPS assemblers that the break
1004 * code starts left to bit 16 instead to bit 6 in the opcode.
1005 * Gas is bug-compatible, but not always, grrr...
1006 * We handle both cases with a simple heuristics. --macro
1007 */
Ralf Baechledf270052008-04-20 16:28:54 +01001008 if (bcode >= (1 << 10))
Maciej W. Rozyckic9875032015-04-03 23:26:32 +01001009 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010
David Daneyc1bf2072010-08-03 11:22:20 -07001011 /*
1012 * notify the kprobe handlers, if instruction is likely to
1013 * pertain to them.
1014 */
1015 switch (bcode) {
Ralf Baechle40e084a2015-07-29 22:44:53 +02001016 case BRK_UPROBE:
1017 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1018 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1019 goto out;
1020 else
1021 break;
1022 case BRK_UPROBE_XOL:
1023 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1024 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1025 goto out;
1026 else
1027 break;
David Daneyc1bf2072010-08-03 11:22:20 -07001028 case BRK_KPROBE_BP:
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001029 if (notify_die(DIE_BREAK, "debug", regs, bcode,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001030 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001031 goto out;
David Daneyc1bf2072010-08-03 11:22:20 -07001032 else
1033 break;
1034 case BRK_KPROBE_SSTEPBP:
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001035 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001036 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001037 goto out;
David Daneyc1bf2072010-08-03 11:22:20 -07001038 else
1039 break;
1040 default:
1041 break;
1042 }
1043
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001044 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001045
1046out:
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001047 set_fs(seg);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001048 exception_exit(prev_state);
Atsushi Nemoto90fccb12007-02-06 16:02:21 +09001049 return;
Ralf Baechlee5679882006-11-30 01:14:47 +00001050
1051out_sigsegv:
1052 force_sig(SIGSEGV, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001053 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054}
1055
1056asmlinkage void do_tr(struct pt_regs *regs)
1057{
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001058 u32 opcode, tcode = 0;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001059 enum ctx_state prev_state;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001060 u16 instr[2];
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001061 mm_segment_t seg;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001062 unsigned long epc = msk_isa16_mode(exception_epc(regs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001064 seg = get_fs();
1065 if (!user_mode(regs))
1066 set_fs(get_ds());
1067
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001068 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001069 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001070 if (get_isa16_mode(regs->cp0_epc)) {
1071 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1072 __get_user(instr[1], (u16 __user *)(epc + 2)))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001073 goto out_sigsegv;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +00001074 opcode = (instr[0] << 16) | instr[1];
1075 /* Immediate versions don't provide a code. */
1076 if (!(opcode & OPCODE))
1077 tcode = (opcode >> 12) & ((1 << 4) - 1);
1078 } else {
1079 if (__get_user(opcode, (u32 __user *)epc))
1080 goto out_sigsegv;
1081 /* Immediate versions don't provide a code. */
1082 if (!(opcode & OPCODE))
1083 tcode = (opcode >> 6) & ((1 << 10) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001084 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001086 do_trap_or_bp(regs, tcode, 0, "Trap");
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001087
1088out:
Leonid Yegoshin078dde52013-12-04 16:39:34 +00001089 set_fs(seg);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001090 exception_exit(prev_state);
Atsushi Nemoto90fccb12007-02-06 16:02:21 +09001091 return;
Ralf Baechlee5679882006-11-30 01:14:47 +00001092
1093out_sigsegv:
1094 force_sig(SIGSEGV, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001095 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096}
1097
1098asmlinkage void do_ri(struct pt_regs *regs)
1099{
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001100 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1101 unsigned long old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001102 unsigned long old31 = regs->regs[31];
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001103 enum ctx_state prev_state;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001104 unsigned int opcode = 0;
1105 int status = -1;
1106
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001107 /*
1108 * Avoid any kernel code. Just emulate the R2 instruction
1109 * as quickly as possible.
1110 */
1111 if (mipsr2_emulation && cpu_has_mips_r6 &&
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001112 likely(user_mode(regs)) &&
1113 likely(get_user(opcode, epc) >= 0)) {
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001114 unsigned long fcr31 = 0;
1115
1116 status = mipsr2_decoder(regs, opcode, &fcr31);
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001117 switch (status) {
1118 case 0:
1119 case SIGEMT:
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001120 return;
1121 case SIGILL:
1122 goto no_r2_instr;
1123 default:
1124 process_fpemu_return(status,
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001125 &current->thread.cp0_baduaddr,
1126 fcr31);
Maciej W. Rozycki4a7c2372015-04-03 23:24:51 +01001127 return;
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001128 }
1129 }
1130
1131no_r2_instr:
1132
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001133 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001134 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
Leonid Yegoshinb0a668f2014-12-03 15:47:03 +00001135
Ralf Baechlee3b28832015-07-28 20:37:43 +02001136 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
Ralf Baechledc73e4c2013-10-09 08:54:15 +02001137 SIGILL) == NOTIFY_STOP)
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001138 goto out;
Jason Wessel88547002008-07-29 15:58:53 -05001139
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 die_if_kernel("Reserved instruction in kernel code", regs);
1141
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001142 if (unlikely(compute_return_epc(regs) < 0))
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001143 goto out;
Ralf Baechle3c370262005-04-13 17:43:59 +00001144
Maciej W. Rozycki3d50a7f2016-01-30 09:08:43 +00001145 if (!get_isa16_mode(regs->cp0_epc)) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001146 if (unlikely(get_user(opcode, epc) < 0))
1147 status = SIGSEGV;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001148
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001149 if (!cpu_has_llsc && status < 0)
1150 status = simulate_llsc(regs, opcode);
1151
1152 if (status < 0)
1153 status = simulate_rdhwr_normal(regs, opcode);
1154
1155 if (status < 0)
1156 status = simulate_sync(regs, opcode);
Paul Burton4227a2d2014-09-11 08:30:20 +01001157
1158 if (status < 0)
1159 status = simulate_fp(regs, opcode, old_epc, old31);
Maciej W. Rozycki3d50a7f2016-01-30 09:08:43 +00001160 } else if (cpu_has_mmips) {
1161 unsigned short mmop[2] = { 0 };
1162
1163 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1164 status = SIGSEGV;
1165 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1166 status = SIGSEGV;
1167 opcode = mmop[0];
1168 opcode = (opcode << 16) | mmop[1];
1169
1170 if (status < 0)
1171 status = simulate_rdhwr_mm(regs, opcode);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001172 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001173
1174 if (status < 0)
1175 status = SIGILL;
1176
1177 if (unlikely(status > 0)) {
1178 regs->cp0_epc = old_epc; /* Undo skip-over. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001179 regs->regs[31] = old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001180 force_sig(status, current);
1181 }
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001182
1183out:
1184 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185}
1186
Ralf Baechled223a862007-07-10 17:33:02 +01001187/*
1188 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1189 * emulated more than some threshold number of instructions, force migration to
1190 * a "CPU" that has FP support.
1191 */
1192static void mt_ase_fp_affinity(void)
1193{
1194#ifdef CONFIG_MIPS_MT_FPAFF
1195 if (mt_fpemul_threshold > 0 &&
1196 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1197 /*
1198 * If there's no FPU present, or if the application has already
1199 * restricted the allowed set to exclude any CPUs with FPUs,
1200 * we'll skip the procedure.
1201 */
Rusty Russell8dd92892015-03-05 10:49:17 +10301202 if (cpumask_intersects(&current->cpus_allowed, &mt_fpu_cpumask)) {
Ralf Baechled223a862007-07-10 17:33:02 +01001203 cpumask_t tmask;
1204
Kevin D. Kissell9cc12362008-09-09 21:33:36 +02001205 current->thread.user_cpus_allowed
1206 = current->cpus_allowed;
Rusty Russell8dd92892015-03-05 10:49:17 +10301207 cpumask_and(&tmask, &current->cpus_allowed,
1208 &mt_fpu_cpumask);
Julia Lawalled1bbde2010-03-26 23:03:07 +01001209 set_cpus_allowed_ptr(current, &tmask);
Ralf Baechle293c5bd2007-07-25 16:19:33 +01001210 set_thread_flag(TIF_FPUBOUND);
Ralf Baechled223a862007-07-10 17:33:02 +01001211 }
1212 }
1213#endif /* CONFIG_MIPS_MT_FPAFF */
1214}
1215
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001216/*
1217 * No lock; only written during early bootup by CPU 0.
1218 */
1219static RAW_NOTIFIER_HEAD(cu2_chain);
1220
1221int __ref register_cu2_notifier(struct notifier_block *nb)
1222{
1223 return raw_notifier_chain_register(&cu2_chain, nb);
1224}
1225
1226int cu2_notifier_call_chain(unsigned long val, void *v)
1227{
1228 return raw_notifier_call_chain(&cu2_chain, val, v);
1229}
1230
1231static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
Ralf Baechle70342282013-01-22 12:59:30 +01001232 void *data)
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001233{
1234 struct pt_regs *regs = data;
1235
Jayachandran C83bee792013-06-10 06:30:01 +00001236 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001237 "instruction", regs);
Jayachandran C83bee792013-06-10 06:30:01 +00001238 force_sig(SIGILL, current);
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001239
1240 return NOTIFY_OK;
1241}
1242
Paul Burton1db1af82014-01-27 15:23:11 +00001243static int enable_restore_fp_context(int msa)
1244{
Paul Burtonc9017752014-07-30 08:53:20 +01001245 int err, was_fpu_owner, prior_msa;
Paul Burton1db1af82014-01-27 15:23:11 +00001246
Paul Burton97915542015-01-08 12:17:37 +00001247 /*
1248 * If an FP mode switch is currently underway, wait for it to
1249 * complete before proceeding.
1250 */
Peter Zijlstra6887a562018-03-15 11:45:44 +01001251 wait_var_event(&current->mm->context.fp_mode_switching,
1252 !atomic_read(&current->mm->context.fp_mode_switching));
Paul Burton97915542015-01-08 12:17:37 +00001253
Paul Burton1db1af82014-01-27 15:23:11 +00001254 if (!used_math()) {
1255 /* First time FP context user. */
Paul Burton762a1f42014-07-11 16:44:35 +01001256 preempt_disable();
Paul Burton1db1af82014-01-27 15:23:11 +00001257 err = init_fpu();
Paul Burtonc9017752014-07-30 08:53:20 +01001258 if (msa && !err) {
Paul Burton1db1af82014-01-27 15:23:11 +00001259 enable_msa();
Maciej W. Rozyckie49d3842016-05-17 06:12:27 +01001260 init_msa_upper();
Paul Burton732c0c32014-07-31 14:53:16 +01001261 set_thread_flag(TIF_USEDMSA);
1262 set_thread_flag(TIF_MSA_CTX_LIVE);
Paul Burtonc9017752014-07-30 08:53:20 +01001263 }
Paul Burton762a1f42014-07-11 16:44:35 +01001264 preempt_enable();
Paul Burton1db1af82014-01-27 15:23:11 +00001265 if (!err)
1266 set_used_math();
1267 return err;
1268 }
1269
1270 /*
1271 * This task has formerly used the FP context.
1272 *
1273 * If this thread has no live MSA vector context then we can simply
1274 * restore the scalar FP context. If it has live MSA vector context
1275 * (that is, it has or may have used MSA since last performing a
1276 * function call) then we'll need to restore the vector context. This
1277 * applies even if we're currently only executing a scalar FP
1278 * instruction. This is because if we were to later execute an MSA
1279 * instruction then we'd either have to:
1280 *
1281 * - Restore the vector context & clobber any registers modified by
1282 * scalar FP instructions between now & then.
1283 *
1284 * or
1285 *
1286 * - Not restore the vector context & lose the most significant bits
1287 * of all vector registers.
1288 *
1289 * Neither of those options is acceptable. We cannot restore the least
1290 * significant bits of the registers now & only restore the most
1291 * significant bits later because the most significant bits of any
1292 * vector registers whose aliased FP register is modified now will have
1293 * been zeroed. We'd have no way to know that when restoring the vector
1294 * context & thus may load an outdated value for the most significant
1295 * bits of a vector register.
1296 */
1297 if (!msa && !thread_msa_context_live())
1298 return own_fpu(1);
1299
1300 /*
1301 * This task is using or has previously used MSA. Thus we require
1302 * that Status.FR == 1.
1303 */
Paul Burton762a1f42014-07-11 16:44:35 +01001304 preempt_disable();
Paul Burton1db1af82014-01-27 15:23:11 +00001305 was_fpu_owner = is_fpu_owner();
Paul Burton762a1f42014-07-11 16:44:35 +01001306 err = own_fpu_inatomic(0);
Paul Burton1db1af82014-01-27 15:23:11 +00001307 if (err)
Paul Burton762a1f42014-07-11 16:44:35 +01001308 goto out;
Paul Burton1db1af82014-01-27 15:23:11 +00001309
1310 enable_msa();
1311 write_msa_csr(current->thread.fpu.msacsr);
1312 set_thread_flag(TIF_USEDMSA);
1313
1314 /*
1315 * If this is the first time that the task is using MSA and it has
1316 * previously used scalar FP in this time slice then we already nave
Paul Burtonc9017752014-07-30 08:53:20 +01001317 * FP context which we shouldn't clobber. We do however need to clear
1318 * the upper 64b of each vector register so that this task has no
1319 * opportunity to see data left behind by another.
Paul Burton1db1af82014-01-27 15:23:11 +00001320 */
Paul Burtonc9017752014-07-30 08:53:20 +01001321 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1322 if (!prior_msa && was_fpu_owner) {
Maciej W. Rozyckie49d3842016-05-17 06:12:27 +01001323 init_msa_upper();
Paul Burton762a1f42014-07-11 16:44:35 +01001324
1325 goto out;
Paul Burtonc9017752014-07-30 08:53:20 +01001326 }
Paul Burton1db1af82014-01-27 15:23:11 +00001327
Paul Burtonc9017752014-07-30 08:53:20 +01001328 if (!prior_msa) {
1329 /*
1330 * Restore the least significant 64b of each vector register
1331 * from the existing scalar FP context.
1332 */
1333 _restore_fp(current);
Paul Burtonb8340672014-07-11 16:44:29 +01001334
Paul Burtonc9017752014-07-30 08:53:20 +01001335 /*
1336 * The task has not formerly used MSA, so clear the upper 64b
1337 * of each vector register such that it cannot see data left
1338 * behind by another task.
1339 */
Maciej W. Rozyckie49d3842016-05-17 06:12:27 +01001340 init_msa_upper();
Paul Burtonc9017752014-07-30 08:53:20 +01001341 } else {
1342 /* We need to restore the vector context. */
1343 restore_msa(current);
Paul Burtonb8340672014-07-11 16:44:29 +01001344
Paul Burtonc9017752014-07-30 08:53:20 +01001345 /* Restore the scalar FP control & status register */
1346 if (!was_fpu_owner)
James Hogand76e9b92015-01-30 15:40:20 +00001347 write_32bit_cp1_register(CP1_STATUS,
1348 current->thread.fpu.fcr31);
Paul Burtonc9017752014-07-30 08:53:20 +01001349 }
Paul Burton762a1f42014-07-11 16:44:35 +01001350
1351out:
1352 preempt_enable();
1353
Paul Burton1db1af82014-01-27 15:23:11 +00001354 return 0;
1355}
1356
Linus Torvalds1da177e2005-04-16 15:20:36 -07001357asmlinkage void do_cpu(struct pt_regs *regs)
1358{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001359 enum ctx_state prev_state;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001360 unsigned int __user *epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001361 unsigned long old_epc, old31;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001362 void __user *fault_addr;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001363 unsigned int opcode;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001364 unsigned long fcr31;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365 unsigned int cpid;
Paul Burton597ce172013-11-22 13:12:07 +00001366 int status, err;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001367 int sig;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001369 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1371
Jayachandran C83bee792013-06-10 06:30:01 +00001372 if (cpid != 2)
1373 die_if_kernel("do_cpu invoked from kernel context!", regs);
1374
Linus Torvalds1da177e2005-04-16 15:20:36 -07001375 switch (cpid) {
1376 case 0:
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001377 epc = (unsigned int __user *)exception_epc(regs);
1378 old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001379 old31 = regs->regs[31];
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001380 opcode = 0;
1381 status = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001383 if (unlikely(compute_return_epc(regs) < 0))
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001384 break;
Ralf Baechle3c370262005-04-13 17:43:59 +00001385
Maciej W. Rozycki10f6d99f2016-01-30 09:08:16 +00001386 if (!get_isa16_mode(regs->cp0_epc)) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001387 if (unlikely(get_user(opcode, epc) < 0))
1388 status = SIGSEGV;
1389
1390 if (!cpu_has_llsc && status < 0)
1391 status = simulate_llsc(regs, opcode);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001392 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001393
1394 if (status < 0)
1395 status = SIGILL;
1396
1397 if (unlikely(status > 0)) {
1398 regs->cp0_epc = old_epc; /* Undo skip-over. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001399 regs->regs[31] = old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001400 force_sig(status, current);
1401 }
1402
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001403 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001405 case 3:
1406 /*
Maciej W. Rozycki2d83fea2015-04-03 23:26:49 +01001407 * The COP3 opcode space and consequently the CP0.Status.CU3
1408 * bit and the CP0.Cause.CE=3 encoding have been removed as
1409 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1410 * up the space has been reused for COP1X instructions, that
1411 * are enabled by the CP0.Status.CU1 bit and consequently
1412 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1413 * exceptions. Some FPU-less processors that implement one
1414 * of these ISAs however use this code erroneously for COP1X
1415 * instructions. Therefore we redirect this trap to the FP
1416 * emulator too.
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001417 */
Maciej W. Rozycki2d83fea2015-04-03 23:26:49 +01001418 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001419 force_sig(SIGILL, current);
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001420 break;
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001421 }
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001422 /* Fall through. */
1423
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424 case 1:
Paul Burton1db1af82014-01-27 15:23:11 +00001425 err = enable_restore_fp_context(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001427 if (raw_cpu_has_fpu && !err)
1428 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001430 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1431 &fault_addr);
Maciej W. Rozycki443c4402015-04-03 23:27:10 +01001432
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001433 /*
1434 * We can't allow the emulated instruction to leave
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +01001435 * any enabled Cause bits set in $fcr31.
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001436 */
Maciej W. Rozycki5a1aca42016-10-28 08:21:03 +01001437 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1438 current->thread.fpu.fcr31 &= ~fcr31;
Maciej W. Rozycki304acb72015-04-03 23:27:15 +01001439
1440 /* Send a signal if required. */
1441 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1442 mt_ase_fp_affinity();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001444 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445
1446 case 2:
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001447 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
Maciej W. Rozycki27e28e82015-04-03 23:25:08 +01001448 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449 }
1450
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001451 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452}
1453
James Hogan64bedff2014-12-02 13:44:13 +00001454asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001455{
1456 enum ctx_state prev_state;
1457
1458 prev_state = exception_enter();
Ralf Baechlee3b28832015-07-28 20:37:43 +02001459 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
James Hogan64bedff2014-12-02 13:44:13 +00001460 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
Ralf Baechlee3b28832015-07-28 20:37:43 +02001461 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
James Hogan64bedff2014-12-02 13:44:13 +00001462 goto out;
1463
1464 /* Clear MSACSR.Cause before enabling interrupts */
1465 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1466 local_irq_enable();
1467
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001468 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1469 force_sig(SIGFPE, current);
James Hogan64bedff2014-12-02 13:44:13 +00001470out:
Paul Burton2bcb3fb2014-01-27 15:23:12 +00001471 exception_exit(prev_state);
1472}
1473
Paul Burton1db1af82014-01-27 15:23:11 +00001474asmlinkage void do_msa(struct pt_regs *regs)
1475{
1476 enum ctx_state prev_state;
1477 int err;
1478
1479 prev_state = exception_enter();
1480
1481 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1482 force_sig(SIGILL, current);
1483 goto out;
1484 }
1485
1486 die_if_kernel("do_msa invoked from kernel context!", regs);
1487
1488 err = enable_restore_fp_context(1);
1489 if (err)
1490 force_sig(SIGILL, current);
1491out:
1492 exception_exit(prev_state);
1493}
1494
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495asmlinkage void do_mdmx(struct pt_regs *regs)
1496{
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001497 enum ctx_state prev_state;
1498
1499 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500 force_sig(SIGILL, current);
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001501 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502}
1503
David Daney8bc6d052009-01-05 15:29:58 -08001504/*
1505 * Called with interrupts disabled.
1506 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001507asmlinkage void do_watch(struct pt_regs *regs)
1508{
Eric W. Biederman5f749722018-01-22 14:58:57 -06001509 siginfo_t info;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001510 enum ctx_state prev_state;
David Daneyb67b2b72008-09-23 00:08:45 -07001511
Eric W. Biederman5f749722018-01-22 14:58:57 -06001512 clear_siginfo(&info);
1513 info.si_signo = SIGTRAP;
1514 info.si_code = TRAP_HWBKPT;
1515
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001516 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517 /*
David Daneyb67b2b72008-09-23 00:08:45 -07001518 * Clear WP (bit 22) bit of cause register so we don't loop
1519 * forever.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001520 */
James Hogane233c732016-03-01 22:19:38 +00001521 clear_c0_cause(CAUSEF_WP);
David Daneyb67b2b72008-09-23 00:08:45 -07001522
1523 /*
1524 * If the current thread has the watch registers loaded, save
1525 * their values and send SIGTRAP. Otherwise another thread
1526 * left the registers set, clear them and continue.
1527 */
1528 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1529 mips_read_watch_registers();
David Daney8bc6d052009-01-05 15:29:58 -08001530 local_irq_enable();
Maciej W. Rozycki3b143cc2016-03-04 01:44:28 +00001531 force_sig_info(SIGTRAP, &info, current);
David Daney8bc6d052009-01-05 15:29:58 -08001532 } else {
David Daneyb67b2b72008-09-23 00:08:45 -07001533 mips_clear_watch_registers();
David Daney8bc6d052009-01-05 15:29:58 -08001534 local_irq_enable();
1535 }
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001536 exception_exit(prev_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537}
1538
1539asmlinkage void do_mcheck(struct pt_regs *regs)
1540{
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001541 int multi_match = regs->cp0_status & ST0_TS;
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001542 enum ctx_state prev_state;
James Hogan55c723e2015-07-27 13:50:21 +01001543 mm_segment_t old_fs = get_fs();
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001544
Ralf Baechlec3fc5cd2013-05-29 01:07:19 +02001545 prev_state = exception_enter();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001546 show_regs(regs);
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001547
1548 if (multi_match) {
James Hogan3c865dd2015-07-15 16:17:43 +01001549 dump_tlb_regs();
1550 pr_info("\n");
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001551 dump_tlb_all();
1552 }
1553
James Hogan55c723e2015-07-27 13:50:21 +01001554 if (!user_mode(regs))
1555 set_fs(KERNEL_DS);
1556
Atsushi Nemotoe1bb82892007-07-13 23:51:46 +09001557 show_code((unsigned int __user *) regs->cp0_epc);
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001558
James Hogan55c723e2015-07-27 13:50:21 +01001559 set_fs(old_fs);
1560
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561 /*
1562 * Some chips may have other causes of machine check (e.g. SB1
1563 * graduation timer)
1564 */
1565 panic("Caught Machine Check exception - %scaused by multiple "
1566 "matching entries in the TLB.",
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001567 (multi_match) ? "" : "not ");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568}
1569
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001570asmlinkage void do_mt(struct pt_regs *regs)
1571{
Ralf Baechle41c594a2006-04-05 09:45:45 +01001572 int subcode;
1573
Ralf Baechle41c594a2006-04-05 09:45:45 +01001574 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1575 >> VPECONTROL_EXCPT_SHIFT;
1576 switch (subcode) {
1577 case 0:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001578 printk(KERN_DEBUG "Thread Underflow\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001579 break;
1580 case 1:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001581 printk(KERN_DEBUG "Thread Overflow\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001582 break;
1583 case 2:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001584 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001585 break;
1586 case 3:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001587 printk(KERN_DEBUG "Gating Storage Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001588 break;
1589 case 4:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001590 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001591 break;
1592 case 5:
Masanari Iidaf232c7e2012-02-08 21:53:14 +09001593 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001594 break;
1595 default:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001596 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
Ralf Baechle41c594a2006-04-05 09:45:45 +01001597 subcode);
1598 break;
1599 }
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001600 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1601
1602 force_sig(SIGILL, current);
1603}
1604
1605
Ralf Baechlee50c0a82005-05-31 11:49:19 +00001606asmlinkage void do_dsp(struct pt_regs *regs)
1607{
1608 if (cpu_has_dsp)
Ralf Baechleab75dc02011-11-17 15:07:31 +00001609 panic("Unexpected DSP exception");
Ralf Baechlee50c0a82005-05-31 11:49:19 +00001610
1611 force_sig(SIGILL, current);
1612}
1613
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614asmlinkage void do_reserved(struct pt_regs *regs)
1615{
1616 /*
Ralf Baechle70342282013-01-22 12:59:30 +01001617 * Game over - no way to handle this if it ever occurs. Most probably
Linus Torvalds1da177e2005-04-16 15:20:36 -07001618 * caused by a new unknown cpu type or after another deadly
1619 * hard/software error.
1620 */
1621 show_regs(regs);
1622 panic("Caught reserved exception %ld - should not happen.",
1623 (regs->cp0_cause & 0x7f) >> 2);
1624}
1625
Ralf Baechle39b8d522008-04-28 17:14:26 +01001626static int __initdata l1parity = 1;
1627static int __init nol1parity(char *s)
1628{
1629 l1parity = 0;
1630 return 1;
1631}
1632__setup("nol1par", nol1parity);
1633static int __initdata l2parity = 1;
1634static int __init nol2parity(char *s)
1635{
1636 l2parity = 0;
1637 return 1;
1638}
1639__setup("nol2par", nol2parity);
1640
Linus Torvalds1da177e2005-04-16 15:20:36 -07001641/*
1642 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1643 * it different ways.
1644 */
1645static inline void parity_protection_init(void)
1646{
Paul Burton35e6de32016-10-17 16:01:07 +01001647#define ERRCTL_PE 0x80000000
1648#define ERRCTL_L2P 0x00800000
1649
1650 if (mips_cm_revision() >= CM_REV_CM3) {
1651 ulong gcr_ectl, cp0_ectl;
1652
1653 /*
1654 * With CM3 systems we need to ensure that the L1 & L2
1655 * parity enables are set to the same value, since this
1656 * is presumed by the hardware engineers.
1657 *
1658 * If the user disabled either of L1 or L2 ECC checking,
1659 * disable both.
1660 */
1661 l1parity &= l2parity;
1662 l2parity &= l1parity;
1663
1664 /* Probe L1 ECC support */
1665 cp0_ectl = read_c0_ecc();
1666 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1667 back_to_back_c0_hazard();
1668 cp0_ectl = read_c0_ecc();
1669
1670 /* Probe L2 ECC support */
1671 gcr_ectl = read_gcr_err_control();
1672
Paul Burton93c5bba52017-08-12 19:49:27 -07001673 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
Paul Burton35e6de32016-10-17 16:01:07 +01001674 !(cp0_ectl & ERRCTL_PE)) {
1675 /*
1676 * One of L1 or L2 ECC checking isn't supported,
1677 * so we cannot enable either.
1678 */
1679 l1parity = l2parity = 0;
1680 }
1681
1682 /* Configure L1 ECC checking */
1683 if (l1parity)
1684 cp0_ectl |= ERRCTL_PE;
1685 else
1686 cp0_ectl &= ~ERRCTL_PE;
1687 write_c0_ecc(cp0_ectl);
1688 back_to_back_c0_hazard();
1689 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1690
1691 /* Configure L2 ECC checking */
1692 if (l2parity)
Paul Burton93c5bba52017-08-12 19:49:27 -07001693 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
Paul Burton35e6de32016-10-17 16:01:07 +01001694 else
Paul Burton93c5bba52017-08-12 19:49:27 -07001695 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
Paul Burton35e6de32016-10-17 16:01:07 +01001696 write_gcr_err_control(gcr_ectl);
1697 gcr_ectl = read_gcr_err_control();
Paul Burton93c5bba52017-08-12 19:49:27 -07001698 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
Paul Burton35e6de32016-10-17 16:01:07 +01001699 WARN_ON(!!gcr_ectl != l2parity);
1700
1701 pr_info("Cache parity protection %sabled\n",
1702 l1parity ? "en" : "dis");
1703 return;
1704 }
1705
Ralf Baechle10cc3522007-10-11 23:46:15 +01001706 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001707 case CPU_24K:
Nigel Stephens98a41de2006-04-27 15:50:32 +01001708 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001709 case CPU_74K:
1710 case CPU_1004K:
Steven J. Hill442e14a2014-01-17 15:03:50 -06001711 case CPU_1074K:
Leonid Yegoshin26ab96d2013-11-27 10:07:53 +00001712 case CPU_INTERAPTIV:
Leonid Yegoshin708ac4b2013-11-14 16:12:27 +00001713 case CPU_PROAPTIV:
James Hoganaced4cb2014-01-22 16:19:38 +00001714 case CPU_P5600:
Leonid Yegoshin46950892014-11-24 12:59:01 +00001715 case CPU_QEMU_GENERIC:
Paul Burton1091bfa2016-02-03 03:26:38 +00001716 case CPU_P6600:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001717 {
Ralf Baechle39b8d522008-04-28 17:14:26 +01001718 unsigned long errctl;
1719 unsigned int l1parity_present, l2parity_present;
1720
1721 errctl = read_c0_ecc();
1722 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1723
1724 /* probe L1 parity support */
1725 write_c0_ecc(errctl | ERRCTL_PE);
1726 back_to_back_c0_hazard();
1727 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1728
1729 /* probe L2 parity support */
1730 write_c0_ecc(errctl|ERRCTL_L2P);
1731 back_to_back_c0_hazard();
1732 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1733
1734 if (l1parity_present && l2parity_present) {
1735 if (l1parity)
1736 errctl |= ERRCTL_PE;
1737 if (l1parity ^ l2parity)
1738 errctl |= ERRCTL_L2P;
1739 } else if (l1parity_present) {
1740 if (l1parity)
1741 errctl |= ERRCTL_PE;
1742 } else if (l2parity_present) {
1743 if (l2parity)
1744 errctl |= ERRCTL_L2P;
1745 } else {
1746 /* No parity available */
1747 }
1748
1749 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1750
1751 write_c0_ecc(errctl);
1752 back_to_back_c0_hazard();
1753 errctl = read_c0_ecc();
1754 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1755
1756 if (l1parity_present)
1757 printk(KERN_INFO "Cache parity protection %sabled\n",
1758 (errctl & ERRCTL_PE) ? "en" : "dis");
1759
1760 if (l2parity_present) {
1761 if (l1parity_present && l1parity)
1762 errctl ^= ERRCTL_L2P;
1763 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1764 (errctl & ERRCTL_L2P) ? "en" : "dis");
1765 }
1766 }
1767 break;
1768
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769 case CPU_5KC:
Leonid Yegoshin78d48032012-07-06 21:56:01 +02001770 case CPU_5KE:
Kelvin Cheung2fa36392012-06-20 20:05:32 +01001771 case CPU_LOONGSON1:
Ralf Baechle14f18b72005-03-01 18:15:08 +00001772 write_c0_ecc(0x80000000);
1773 back_to_back_c0_hazard();
1774 /* Set the PE bit (bit 31) in the c0_errctl register. */
1775 printk(KERN_INFO "Cache parity protection %sabled\n",
1776 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001777 break;
1778 case CPU_20KC:
1779 case CPU_25KF:
1780 /* Clear the DE bit (bit 16) in the c0_status register. */
1781 printk(KERN_INFO "Enable cache parity protection for "
1782 "MIPS 20KC/25KF CPUs.\n");
1783 clear_c0_status(ST0_DE);
1784 break;
1785 default:
1786 break;
1787 }
1788}
1789
1790asmlinkage void cache_parity_error(void)
1791{
1792 const int field = 2 * sizeof(unsigned long);
1793 unsigned int reg_val;
1794
1795 /* For the moment, report the problem and hang. */
1796 printk("Cache error exception:\n");
1797 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1798 reg_val = read_c0_cacheerr();
1799 printk("c0_cacheerr == %08x\n", reg_val);
1800
1801 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1802 reg_val & (1<<30) ? "secondary" : "primary",
1803 reg_val & (1<<31) ? "data" : "insn");
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00001804 if ((cpu_has_mips_r2_r6) &&
Markos Chandras721a9202014-05-21 12:35:00 +01001805 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
Leonid Yegoshin6de20452013-10-10 09:58:59 +01001806 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1807 reg_val & (1<<29) ? "ED " : "",
1808 reg_val & (1<<28) ? "ET " : "",
1809 reg_val & (1<<27) ? "ES " : "",
1810 reg_val & (1<<26) ? "EE " : "",
1811 reg_val & (1<<25) ? "EB " : "",
1812 reg_val & (1<<24) ? "EI " : "",
1813 reg_val & (1<<23) ? "E1 " : "",
1814 reg_val & (1<<22) ? "E0 " : "");
1815 } else {
1816 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1817 reg_val & (1<<29) ? "ED " : "",
1818 reg_val & (1<<28) ? "ET " : "",
1819 reg_val & (1<<26) ? "EE " : "",
1820 reg_val & (1<<25) ? "EB " : "",
1821 reg_val & (1<<24) ? "EI " : "",
1822 reg_val & (1<<23) ? "E1 " : "",
1823 reg_val & (1<<22) ? "E0 " : "");
1824 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1826
Ralf Baechleec917c2c2005-10-07 16:58:15 +01001827#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828 if (reg_val & (1<<22))
1829 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1830
1831 if (reg_val & (1<<23))
1832 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1833#endif
1834
1835 panic("Can't handle the cache error!");
1836}
1837
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +00001838asmlinkage void do_ftlb(void)
1839{
1840 const int field = 2 * sizeof(unsigned long);
1841 unsigned int reg_val;
1842
1843 /* For the moment, report the problem and hang. */
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00001844 if ((cpu_has_mips_r2_r6) &&
Huacai Chenb2edcfc2016-03-03 09:45:09 +08001845 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1846 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
Leonid Yegoshin75b5b5e2013-11-14 16:12:31 +00001847 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1848 read_c0_ecc());
1849 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1850 reg_val = read_c0_cacheerr();
1851 pr_err("c0_cacheerr == %08x\n", reg_val);
1852
1853 if ((reg_val & 0xc0000000) == 0xc0000000) {
1854 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1855 } else {
1856 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1857 reg_val & (1<<30) ? "secondary" : "primary",
1858 reg_val & (1<<31) ? "data" : "insn");
1859 }
1860 } else {
1861 pr_err("FTLB error exception\n");
1862 }
1863 /* Just print the cacheerr bits for now */
1864 cache_parity_error();
1865}
1866
Linus Torvalds1da177e2005-04-16 15:20:36 -07001867/*
1868 * SDBBP EJTAG debug exception handler.
1869 * We skip the instruction and return to the next instruction.
1870 */
1871void ejtag_exception_handler(struct pt_regs *regs)
1872{
1873 const int field = 2 * sizeof(unsigned long);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001874 unsigned long depc, old_epc, old_ra;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875 unsigned int debug;
1876
Chris Dearman70ae6122006-06-30 12:32:37 +01001877 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878 depc = read_c0_depc();
1879 debug = read_c0_debug();
Chris Dearman70ae6122006-06-30 12:32:37 +01001880 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001881 if (debug & 0x80000000) {
1882 /*
1883 * In branch delay slot.
1884 * We cheat a little bit here and use EPC to calculate the
1885 * debug return address (DEPC). EPC is restored after the
1886 * calculation.
1887 */
1888 old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001889 old_ra = regs->regs[31];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001890 regs->cp0_epc = depc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001891 compute_return_epc(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001892 depc = regs->cp0_epc;
1893 regs->cp0_epc = old_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001894 regs->regs[31] = old_ra;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 } else
1896 depc += 4;
1897 write_c0_depc(depc);
1898
1899#if 0
Chris Dearman70ae6122006-06-30 12:32:37 +01001900 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901 write_c0_debug(debug | 0x100);
1902#endif
1903}
1904
1905/*
1906 * NMI exception handler.
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001907 * No lock; only written during early bootup by CPU 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001908 */
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001909static RAW_NOTIFIER_HEAD(nmi_chain);
1910
1911int register_nmi_notifier(struct notifier_block *nb)
1912{
1913 return raw_notifier_chain_register(&nmi_chain, nb);
1914}
1915
Joe Perchesff2d8b12012-01-12 17:17:21 -08001916void __noreturn nmi_exception_handler(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917{
Leonid Yegoshin83e4da12013-10-08 12:39:31 +01001918 char str[100];
1919
Petri Gynther7963b3f2015-10-19 11:49:52 -07001920 nmi_enter();
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001921 raw_notifier_call_chain(&nmi_chain, 0, regs);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001922 bust_spinlocks(1);
Leonid Yegoshin83e4da12013-10-08 12:39:31 +01001923 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1924 smp_processor_id(), regs->cp0_epc);
1925 regs->cp0_epc = read_c0_errorepc();
1926 die(str, regs);
Petri Gynther7963b3f2015-10-19 11:49:52 -07001927 nmi_exit();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001928}
1929
Ralf Baechlee01402b2005-07-14 15:57:16 +00001930#define VECTORSPACING 0x100 /* for EI/VI mode */
1931
1932unsigned long ebase;
James Hogan878edf02016-06-09 14:19:14 +01001933EXPORT_SYMBOL_GPL(ebase);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001934unsigned long exception_handlers[32];
Ralf Baechlee01402b2005-07-14 15:57:16 +00001935unsigned long vi_handlers[64];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001936
Florian Fainelli2d1b6e92010-01-28 15:21:42 +01001937void __init *set_except_vector(int n, void *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001938{
1939 unsigned long handler = (unsigned long) addr;
Ralf Baechleb22d1b62013-05-09 17:57:30 +02001940 unsigned long old_handler;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001941
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001942#ifdef CONFIG_CPU_MICROMIPS
1943 /*
1944 * Only the TLB handlers are cache aligned with an even
1945 * address. All other handlers are on an odd address and
1946 * require no modification. Otherwise, MIPS32 mode will
1947 * be entered when handling any TLB exceptions. That
1948 * would be bad...since we must stay in microMIPS mode.
1949 */
1950 if (!(handler & 0x1))
1951 handler |= 1;
1952#endif
Ralf Baechleb22d1b62013-05-09 17:57:30 +02001953 old_handler = xchg(&exception_handlers[n], handler);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954
Linus Torvalds1da177e2005-04-16 15:20:36 -07001955 if (n == 0 && cpu_has_divec) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001956#ifdef CONFIG_CPU_MICROMIPS
1957 unsigned long jump_mask = ~((1 << 27) - 1);
1958#else
Florian Fainelli92bbe1b2010-01-28 15:22:37 +01001959 unsigned long jump_mask = ~((1 << 28) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001960#endif
Florian Fainelli92bbe1b2010-01-28 15:22:37 +01001961 u32 *buf = (u32 *)(ebase + 0x200);
1962 unsigned int k0 = 26;
1963 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1964 uasm_i_j(&buf, handler & ~jump_mask);
1965 uasm_i_nop(&buf);
1966 } else {
1967 UASM_i_LA(&buf, k0, handler);
1968 uasm_i_jr(&buf, k0);
1969 uasm_i_nop(&buf);
1970 }
1971 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001972 }
1973 return (void *)old_handler;
1974}
1975
Ralf Baechle86a17082013-02-08 01:21:34 +01001976static void do_default_vi(void)
Atsushi Nemoto6ba07e52007-05-21 23:45:38 +09001977{
1978 show_regs(get_irq_regs());
1979 panic("Caught unexpected vectored interrupt.");
1980}
1981
Ralf Baechleef300e42007-05-06 18:31:18 +01001982static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001983{
1984 unsigned long handler;
1985 unsigned long old_handler = vi_handlers[n];
Ralf Baechlef6771db2007-11-08 18:02:29 +00001986 int srssets = current_cpu_data.srsets;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001987 u16 *h;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001988 unsigned char *b;
1989
Ralf Baechleb72b7092009-03-30 14:49:44 +02001990 BUG_ON(!cpu_has_veic && !cpu_has_vint);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001991
1992 if (addr == NULL) {
1993 handler = (unsigned long) do_default_vi;
1994 srs = 0;
Ralf Baechle41c594a2006-04-05 09:45:45 +01001995 } else
Ralf Baechlee01402b2005-07-14 15:57:16 +00001996 handler = (unsigned long) addr;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001997 vi_handlers[n] = handler;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001998
1999 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
2000
Ralf Baechlef6771db2007-11-08 18:02:29 +00002001 if (srs >= srssets)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002002 panic("Shadow register set %d not supported", srs);
2003
2004 if (cpu_has_veic) {
2005 if (board_bind_eic_interrupt)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002006 board_bind_eic_interrupt(n, srs);
Ralf Baechle41c594a2006-04-05 09:45:45 +01002007 } else if (cpu_has_vint) {
Ralf Baechlee01402b2005-07-14 15:57:16 +00002008 /* SRSMap is only defined if shadow sets are implemented */
Ralf Baechlef6771db2007-11-08 18:02:29 +00002009 if (srssets > 1)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002010 change_c0_srsmap(0xf << n*4, srs << n*4);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002011 }
2012
2013 if (srs == 0) {
2014 /*
2015 * If no shadow set is selected then use the default handler
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002016 * that does normal register saving and standard interrupt exit
Ralf Baechlee01402b2005-07-14 15:57:16 +00002017 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002018 extern char except_vec_vi, except_vec_vi_lui;
2019 extern char except_vec_vi_ori, except_vec_vi_end;
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002020 extern char rollback_except_vec_vi;
Ralf Baechlef94d9a82013-05-21 17:30:36 +02002021 char *vec_start = using_rollback_handler() ?
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002022 &rollback_except_vec_vi : &except_vec_vi;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002023#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2024 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
2025 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
2026#else
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002027 const int lui_offset = &except_vec_vi_lui - vec_start;
2028 const int ori_offset = &except_vec_vi_ori - vec_start;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002029#endif
2030 const int handler_len = &except_vec_vi_end - vec_start;
Ralf Baechlee01402b2005-07-14 15:57:16 +00002031
2032 if (handler_len > VECTORSPACING) {
2033 /*
2034 * Sigh... panicing won't help as the console
2035 * is probably not configured :(
2036 */
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002037 panic("VECTORSPACING too small");
Ralf Baechlee01402b2005-07-14 15:57:16 +00002038 }
2039
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002040 set_handler(((unsigned long)b - ebase), vec_start,
2041#ifdef CONFIG_CPU_MICROMIPS
2042 (handler_len - 1));
2043#else
2044 handler_len);
2045#endif
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002046 h = (u16 *)(b + lui_offset);
2047 *h = (handler >> 16) & 0xffff;
2048 h = (u16 *)(b + ori_offset);
2049 *h = (handler & 0xffff);
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002050 local_flush_icache_range((unsigned long)b,
2051 (unsigned long)(b+handler_len));
Ralf Baechlee01402b2005-07-14 15:57:16 +00002052 }
2053 else {
2054 /*
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002055 * In other cases jump directly to the interrupt handler. It
2056 * is the handler's responsibility to save registers if required
2057 * (eg hi/lo) and return from the exception using "eret".
Ralf Baechlee01402b2005-07-14 15:57:16 +00002058 */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002059 u32 insn;
2060
2061 h = (u16 *)b;
2062 /* j handler */
2063#ifdef CONFIG_CPU_MICROMIPS
2064 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2065#else
2066 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2067#endif
2068 h[0] = (insn >> 16) & 0xffff;
2069 h[1] = insn & 0xffff;
2070 h[2] = 0;
2071 h[3] = 0;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002072 local_flush_icache_range((unsigned long)b,
2073 (unsigned long)(b+8));
Ralf Baechlee01402b2005-07-14 15:57:16 +00002074 }
2075
2076 return (void *)old_handler;
2077}
2078
Ralf Baechleef300e42007-05-06 18:31:18 +01002079void *set_vi_handler(int n, vi_handler_t addr)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002080{
Ralf Baechleff3eab22006-03-29 14:12:58 +01002081 return set_vi_srs_handler(n, addr, 0);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002082}
Ralf Baechlef41ae0b2006-06-05 17:24:46 +01002083
Linus Torvalds1da177e2005-04-16 15:20:36 -07002084extern void tlb_init(void);
2085
Ralf Baechle42f77542007-10-18 17:48:11 +01002086/*
2087 * Timer interrupt
2088 */
2089int cp0_compare_irq;
Ralf Baechle68b63522012-07-19 09:13:52 +02002090EXPORT_SYMBOL_GPL(cp0_compare_irq);
David VomLehn010c1082009-12-21 17:49:22 -08002091int cp0_compare_irq_shift;
Ralf Baechle42f77542007-10-18 17:48:11 +01002092
2093/*
2094 * Performance counter IRQ or -1 if shared with timer
2095 */
2096int cp0_perfcount_irq;
2097EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2098
James Hogan8f7ff022015-01-29 11:14:07 +00002099/*
2100 * Fast debug channel IRQ or -1 if not present
2101 */
2102int cp0_fdc_irq;
2103EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2104
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002105static int noulri;
Chris Dearmanbdc94eb2007-10-03 10:43:56 +01002106
2107static int __init ulri_disable(char *s)
2108{
2109 pr_info("Disabling ulri\n");
2110 noulri = 1;
2111
2112 return 1;
2113}
2114__setup("noulri", ulri_disable);
2115
James Hoganae4ce452014-03-04 10:20:43 +00002116/* configure STATUS register */
2117static void configure_status(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002118{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002119 /*
2120 * Disable coprocessors and select 32-bit or 64-bit addressing
2121 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2122 * flag that some firmware may have left set and the TS bit (for
2123 * IP27). Set XX for ISA IV code to work.
2124 */
James Hoganae4ce452014-03-04 10:20:43 +00002125 unsigned int status_set = ST0_CU0;
Ralf Baechle875d43e2005-09-03 15:56:16 -07002126#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07002127 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2128#endif
Deng-Cheng Zhuadb37892013-04-01 18:14:28 +00002129 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002130 status_set |= ST0_XX;
Chris Dearmanbbaf2382007-12-13 22:42:19 +00002131 if (cpu_has_dsp)
2132 status_set |= ST0_MX;
2133
Ralf Baechleb38c7392006-02-07 01:20:43 +00002134 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002135 status_set);
James Hoganae4ce452014-03-04 10:20:43 +00002136}
2137
James Hoganb937ff62016-06-15 19:29:53 +01002138unsigned int hwrena;
2139EXPORT_SYMBOL_GPL(hwrena);
2140
James Hoganae4ce452014-03-04 10:20:43 +00002141/* configure HWRENA register */
2142static void configure_hwrena(void)
2143{
James Hoganb937ff62016-06-15 19:29:53 +01002144 hwrena = cpu_hwrena_impl_bits;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002145
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00002146 if (cpu_has_mips_r2_r6)
James Hoganaff565a2016-06-15 19:29:52 +01002147 hwrena |= MIPS_HWRENA_CPUNUM |
2148 MIPS_HWRENA_SYNCISTEP |
2149 MIPS_HWRENA_CC |
2150 MIPS_HWRENA_CCRES;
Ralf Baechlea3692022007-07-10 17:33:02 +01002151
Kevin Cernekee18d693b2010-10-16 14:22:38 -07002152 if (!noulri && cpu_has_userlocal)
James Hoganaff565a2016-06-15 19:29:52 +01002153 hwrena |= MIPS_HWRENA_ULR;
Ralf Baechlea3692022007-07-10 17:33:02 +01002154
Kevin Cernekee18d693b2010-10-16 14:22:38 -07002155 if (hwrena)
2156 write_c0_hwrena(hwrena);
James Hoganae4ce452014-03-04 10:20:43 +00002157}
Ralf Baechlee01402b2005-07-14 15:57:16 +00002158
James Hoganae4ce452014-03-04 10:20:43 +00002159static void configure_exception_vector(void)
2160{
Ralf Baechlee01402b2005-07-14 15:57:16 +00002161 if (cpu_has_veic || cpu_has_vint) {
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002162 unsigned long sr = set_c0_status(ST0_BEV);
Matt Redfearn4b22c692016-09-01 17:30:09 +01002163 /* If available, use WG to set top bits of EBASE */
2164 if (cpu_has_ebase_wg) {
2165#ifdef CONFIG_64BIT
2166 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2167#else
2168 write_c0_ebase(ebase | MIPS_EBASE_WG);
2169#endif
2170 }
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002171 write_c0_ebase(ebase);
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002172 write_c0_status(sr);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002173 /* Setting vector spacing enables EI/VI mode */
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002174 change_c0_intctl(0x3e0, VECTORSPACING);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002175 }
Ralf Baechled03d0a52005-08-17 13:44:26 +00002176 if (cpu_has_divec) {
2177 if (cpu_has_mipsmt) {
2178 unsigned int vpflags = dvpe();
2179 set_c0_cause(CAUSEF_IV);
2180 evpe(vpflags);
2181 } else
2182 set_c0_cause(CAUSEF_IV);
2183 }
James Hoganae4ce452014-03-04 10:20:43 +00002184}
2185
2186void per_cpu_trap_init(bool is_boot_cpu)
2187{
2188 unsigned int cpu = smp_processor_id();
James Hoganae4ce452014-03-04 10:20:43 +00002189
2190 configure_status();
2191 configure_hwrena();
2192
James Hoganae4ce452014-03-04 10:20:43 +00002193 configure_exception_vector();
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002194
2195 /*
2196 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2197 *
2198 * o read IntCtl.IPTI to determine the timer interrupt
2199 * o read IntCtl.IPPCI to determine the performance counter interrupt
James Hogan8f7ff022015-01-29 11:14:07 +00002200 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002201 */
Leonid Yegoshin9c7d5762014-11-14 11:25:30 +00002202 if (cpu_has_mips_r2_r6) {
Markos Chandras04d83f92016-02-03 03:15:22 +00002203 /*
2204 * We shouldn't trust a secondary core has a sane EBASE register
2205 * so use the one calculated by the boot CPU.
2206 */
Matt Redfearn4b22c692016-09-01 17:30:09 +01002207 if (!is_boot_cpu) {
2208 /* If available, use WG to set top bits of EBASE */
2209 if (cpu_has_ebase_wg) {
2210#ifdef CONFIG_64BIT
2211 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2212#else
2213 write_c0_ebase(ebase | MIPS_EBASE_WG);
2214#endif
2215 }
Markos Chandras04d83f92016-02-03 03:15:22 +00002216 write_c0_ebase(ebase);
Matt Redfearn4b22c692016-09-01 17:30:09 +01002217 }
Markos Chandras04d83f92016-02-03 03:15:22 +00002218
David VomLehn010c1082009-12-21 17:49:22 -08002219 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2220 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2221 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
James Hogan8f7ff022015-01-29 11:14:07 +00002222 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2223 if (!cp0_fdc_irq)
2224 cp0_fdc_irq = -1;
2225
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002226 } else {
2227 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
Ralf Baechlec6a4ebb2012-07-06 23:56:00 +02002228 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
Chris Dearmanc3e838a2007-06-21 12:59:57 +01002229 cp0_perfcount_irq = -1;
James Hogan8f7ff022015-01-29 11:14:07 +00002230 cp0_fdc_irq = -1;
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01002231 }
2232
David Daney48c4ac92013-05-13 13:56:44 -07002233 if (!cpu_data[cpu].asid_cache)
Paul Burton4edf00a2016-05-06 14:36:23 +01002234 cpu_data[cpu].asid_cache = asid_first_version(cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002235
Vegard Nossumf1f10072017-02-27 14:30:07 -08002236 mmgrab(&init_mm);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002237 current->active_mm = &init_mm;
2238 BUG_ON(current->mm);
2239 enter_lazy_tlb(&init_mm, current);
2240
Markos Chandras761b4492015-06-24 09:29:20 +01002241 /* Boot CPU's cache setup in setup_arch(). */
2242 if (!is_boot_cpu)
2243 cpu_cache_init();
2244 tlb_init();
David Daney3d8bfdd2010-12-21 14:19:11 -08002245 TLBMISS_HANDLER_SETUP();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002246}
2247
Ralf Baechlee01402b2005-07-14 15:57:16 +00002248/* Install CPU exception handler */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002249void set_handler(unsigned long offset, void *addr, unsigned long size)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002250{
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002251#ifdef CONFIG_CPU_MICROMIPS
2252 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2253#else
Ralf Baechlee01402b2005-07-14 15:57:16 +00002254 memcpy((void *)(ebase + offset), addr, size);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002255#endif
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002256 local_flush_icache_range(ebase + offset, ebase + offset + size);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002257}
2258
Kees Cook06324662017-05-08 15:59:05 -07002259static const char panic_null_cerr[] =
2260 "Trying to set NULL cache error exception handler\n";
Ralf Baechle641e97f2007-10-11 23:46:05 +01002261
Ralf Baechle42fe7ee2009-01-28 18:48:23 +00002262/*
2263 * Install uncached CPU exception handler.
2264 * This is suitable only for the cache error exception which is the only
2265 * exception handler that is being run uncached.
2266 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +00002267void set_uncached_handler(unsigned long offset, void *addr,
Ralf Baechle234fcd12008-03-08 09:56:28 +00002268 unsigned long size)
Ralf Baechlee01402b2005-07-14 15:57:16 +00002269{
Sebastian Andrzej Siewior4f81b012010-04-27 22:53:30 +02002270 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002271
Ralf Baechle641e97f2007-10-11 23:46:05 +01002272 if (!addr)
2273 panic(panic_null_cerr);
2274
Ralf Baechlee01402b2005-07-14 15:57:16 +00002275 memcpy((void *)(uncached_ebase + offset), addr, size);
2276}
2277
Atsushi Nemoto5b104962006-09-11 17:50:29 +09002278static int __initdata rdhwr_noopt;
2279static int __init set_rdhwr_noopt(char *str)
2280{
2281 rdhwr_noopt = 1;
2282 return 1;
2283}
2284
2285__setup("rdhwr_noopt", set_rdhwr_noopt);
2286
Linus Torvalds1da177e2005-04-16 15:20:36 -07002287void __init trap_init(void)
2288{
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002289 extern char except_vec3_generic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002290 extern char except_vec4;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002291 extern char except_vec3_r4000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002292 unsigned long i;
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09002293
2294 check_wait();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002295
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002296 if (cpu_has_veic || cpu_has_vint) {
2297 unsigned long size = 0x200 + VECTORSPACING*64;
James Hoganc195e072016-09-01 17:30:08 +01002298 phys_addr_t ebase_pa;
2299
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002300 ebase = (unsigned long)
2301 __alloc_bootmem(size, 1 << fls(size), 0);
James Hoganc195e072016-09-01 17:30:08 +01002302
2303 /*
2304 * Try to ensure ebase resides in KSeg0 if possible.
2305 *
2306 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2307 * hitting a poorly defined exception base for Cache Errors.
2308 * The allocation is likely to be in the low 512MB of physical,
2309 * in which case we should be able to convert to KSeg0.
2310 *
2311 * EVA is special though as it allows segments to be rearranged
2312 * and to become uncached during cache error handling.
2313 */
2314 ebase_pa = __pa(ebase);
2315 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2316 ebase = CKSEG0ADDR(ebase_pa);
Chris Dearman9fb4c2b92009-03-20 15:33:55 -07002317 } else {
Paul Burtona13c9962015-09-22 10:15:22 -07002318 ebase = CAC_BASE;
2319
James Hogan18022892016-09-01 17:30:07 +01002320 if (cpu_has_mips_r2_r6) {
2321 if (cpu_has_ebase_wg) {
2322#ifdef CONFIG_64BIT
2323 ebase = (read_c0_ebase_64() & ~0xfff);
2324#else
2325 ebase = (read_c0_ebase() & ~0xfff);
2326#endif
2327 } else {
2328 ebase += (read_c0_ebase() & 0x3ffff000);
2329 }
2330 }
David Daney566f74f2008-10-23 17:56:35 -07002331 }
Ralf Baechlee01402b2005-07-14 15:57:16 +00002332
Steven J. Hillc6213c62013-06-05 21:25:17 +00002333 if (cpu_has_mmips) {
2334 unsigned int config3 = read_c0_config3();
2335
2336 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2337 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2338 else
2339 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2340 }
2341
Kevin Cernekee6fb97ef2011-11-16 01:25:45 +00002342 if (board_ebase_setup)
2343 board_ebase_setup();
David Daney6650df32012-05-15 00:04:50 -07002344 per_cpu_trap_init(true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002345
2346 /*
2347 * Copy the generic exception handlers to their final destination.
Adam Buchbinder92a76f62016-02-25 00:44:58 -08002348 * This will be overridden later as suitable for a particular
Linus Torvalds1da177e2005-04-16 15:20:36 -07002349 * configuration.
2350 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002351 set_handler(0x180, &except_vec3_generic, 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002352
2353 /*
2354 * Setup default vectors
2355 */
2356 for (i = 0; i <= 31; i++)
2357 set_except_vector(i, handle_reserved);
2358
2359 /*
2360 * Copy the EJTAG debug exception vector handler code to it's final
2361 * destination.
2362 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002363 if (cpu_has_ejtag && board_ejtag_handler_setup)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01002364 board_ejtag_handler_setup();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002365
2366 /*
2367 * Only some CPUs have the watch exceptions.
2368 */
2369 if (cpu_has_watch)
James Hogan1b505de2015-12-16 23:49:35 +00002370 set_except_vector(EXCCODE_WATCH, handle_watch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002371
2372 /*
Ralf Baechlee01402b2005-07-14 15:57:16 +00002373 * Initialise interrupt handlers
Linus Torvalds1da177e2005-04-16 15:20:36 -07002374 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00002375 if (cpu_has_veic || cpu_has_vint) {
2376 int nvec = cpu_has_veic ? 64 : 8;
2377 for (i = 0; i < nvec; i++)
Ralf Baechleff3eab22006-03-29 14:12:58 +01002378 set_vi_handler(i, NULL);
Ralf Baechlee01402b2005-07-14 15:57:16 +00002379 }
2380 else if (cpu_has_divec)
2381 set_handler(0x200, &except_vec4, 0x8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002382
2383 /*
2384 * Some CPUs can enable/disable for cache parity detection, but does
2385 * it different ways.
2386 */
2387 parity_protection_init();
2388
2389 /*
2390 * The Data Bus Errors / Instruction Bus Errors are signaled
2391 * by external hardware. Therefore these two exceptions
2392 * may have board specific handlers.
2393 */
2394 if (board_be_init)
2395 board_be_init();
2396
James Hogan1b505de2015-12-16 23:49:35 +00002397 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2398 rollback_handle_int : handle_int);
2399 set_except_vector(EXCCODE_MOD, handle_tlbm);
2400 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2401 set_except_vector(EXCCODE_TLBS, handle_tlbs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002402
James Hogan1b505de2015-12-16 23:49:35 +00002403 set_except_vector(EXCCODE_ADEL, handle_adel);
2404 set_except_vector(EXCCODE_ADES, handle_ades);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002405
James Hogan1b505de2015-12-16 23:49:35 +00002406 set_except_vector(EXCCODE_IBE, handle_ibe);
2407 set_except_vector(EXCCODE_DBE, handle_dbe);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002408
James Hogan1b505de2015-12-16 23:49:35 +00002409 set_except_vector(EXCCODE_SYS, handle_sys);
2410 set_except_vector(EXCCODE_BP, handle_bp);
Huacai Chen5a341332017-03-16 21:00:26 +08002411
2412 if (rdhwr_noopt)
2413 set_except_vector(EXCCODE_RI, handle_ri);
2414 else {
2415 if (cpu_has_vtag_icache)
2416 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2417 else if (current_cpu_type() == CPU_LOONGSON3)
2418 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2419 else
2420 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2421 }
2422
James Hogan1b505de2015-12-16 23:49:35 +00002423 set_except_vector(EXCCODE_CPU, handle_cpu);
2424 set_except_vector(EXCCODE_OV, handle_ov);
2425 set_except_vector(EXCCODE_TR, handle_tr);
2426 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002427
Ralf Baechlee01402b2005-07-14 15:57:16 +00002428 if (board_nmi_handler_setup)
2429 board_nmi_handler_setup();
2430
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002431 if (cpu_has_fpu && !cpu_has_nofpuex)
James Hogan1b505de2015-12-16 23:49:35 +00002432 set_except_vector(EXCCODE_FPE, handle_fpe);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002433
James Hogan1b505de2015-12-16 23:49:35 +00002434 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
Leonid Yegoshin5890f702014-07-15 14:09:56 +01002435
2436 if (cpu_has_rixiex) {
James Hogan1b505de2015-12-16 23:49:35 +00002437 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2438 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
Leonid Yegoshin5890f702014-07-15 14:09:56 +01002439 }
2440
James Hogan1b505de2015-12-16 23:49:35 +00002441 set_except_vector(EXCCODE_MSADIS, handle_msa);
2442 set_except_vector(EXCCODE_MDMX, handle_mdmx);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002443
2444 if (cpu_has_mcheck)
James Hogan1b505de2015-12-16 23:49:35 +00002445 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002446
Ralf Baechle340ee4b2005-08-17 17:44:08 +00002447 if (cpu_has_mipsmt)
James Hogan1b505de2015-12-16 23:49:35 +00002448 set_except_vector(EXCCODE_THREAD, handle_mt);
Ralf Baechle340ee4b2005-08-17 17:44:08 +00002449
James Hogan1b505de2015-12-16 23:49:35 +00002450 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002451
David Daneyfcbf1df2012-05-15 00:04:46 -07002452 if (board_cache_error_setup)
2453 board_cache_error_setup();
2454
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002455 if (cpu_has_vce)
2456 /* Special exception: R4[04]00 uses also the divec space. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002457 set_handler(0x180, &except_vec3_r4000, 0x100);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002458 else if (cpu_has_4kex)
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002459 set_handler(0x180, &except_vec3_generic, 0x80);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002460 else
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05002461 set_handler(0x080, &except_vec3_generic, 0x80);
Ralf Baechlee50c0a82005-05-31 11:49:19 +00002462
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02002463 local_flush_icache_range(ebase, ebase + 0x400);
Thomas Bogendoerfer05106172008-08-04 19:44:34 +02002464
2465 sort_extable(__start___dbe_table, __stop___dbe_table);
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00002466
Ralf Baechle4483b152010-08-05 13:25:59 +01002467 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002468}
James Hoganae4ce452014-03-04 10:20:43 +00002469
2470static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2471 void *v)
2472{
2473 switch (cmd) {
2474 case CPU_PM_ENTER_FAILED:
2475 case CPU_PM_EXIT:
2476 configure_status();
2477 configure_hwrena();
2478 configure_exception_vector();
2479
2480 /* Restore register with CPU number for TLB handlers */
2481 TLBMISS_HANDLER_RESTORE();
2482
2483 break;
2484 }
2485
2486 return NOTIFY_OK;
2487}
2488
2489static struct notifier_block trap_pm_notifier_block = {
2490 .notifier_call = trap_pm_notifier,
2491};
2492
2493static int __init trap_pm_init(void)
2494{
2495 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2496}
2497arch_initcall(trap_pm_init);