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Carlo Caionecfb61a42014-05-01 14:29:27 +02001/*
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08002 * MFD core driver for the X-Powers' Power Management ICs
Carlo Caionecfb61a42014-05-01 14:29:27 +02003 *
Jacob Panaf7e9062014-10-06 21:17:14 -07004 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
Carlo Caionecfb61a42014-05-01 14:29:27 +02007 *
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08008 * This file contains the interface independent core functions.
9 *
Chen-Yu Tsaie7402352016-02-12 10:02:41 +080010 * Copyright (C) 2014 Carlo Caione
11 *
Carlo Caionecfb61a42014-05-01 14:29:27 +020012 * Author: Carlo Caione <carlo@caione.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/err.h>
Hans de Goede179dc632016-06-05 15:50:48 +020020#include <linux/delay.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020021#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <linux/regmap.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020026#include <linux/regulator/consumer.h>
27#include <linux/mfd/axp20x.h>
28#include <linux/mfd/core.h>
29#include <linux/of_device.h>
Jacob Panaf7e9062014-10-06 21:17:14 -070030#include <linux/acpi.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020031
32#define AXP20X_OFF 0x80
33
Rask Ingemann Lambertsenc0369692017-02-22 20:42:02 +010034#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
Chen-Yu Tsai696f0b32017-01-05 12:01:03 +080035#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
36
Krzysztof Kozlowskic31e8582015-03-24 11:21:17 +010037static const char * const axp20x_model_names[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +020038 "AXP152",
Jacob Panaf7e9062014-10-06 21:17:14 -070039 "AXP202",
40 "AXP209",
Boris BREZILLONf05be582015-04-10 12:09:01 +080041 "AXP221",
Chen-Yu Tsai02071f02016-02-12 10:02:44 +080042 "AXP223",
Jacob Panaf7e9062014-10-06 21:17:14 -070043 "AXP288",
Icenowy Zheng15783532017-04-17 19:57:40 +080044 "AXP803",
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +080045 "AXP806",
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080046 "AXP809",
Chen-Yu Tsai73037332017-07-26 16:28:26 +080047 "AXP813",
Jacob Panaf7e9062014-10-06 21:17:14 -070048};
49
Michal Suchanekd8d79f82015-07-11 14:59:56 +020050static const struct regmap_range axp152_writeable_ranges[] = {
51 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
52 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
53};
54
55static const struct regmap_range axp152_volatile_ranges[] = {
56 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
57 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
58 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
59};
60
61static const struct regmap_access_table axp152_writeable_table = {
62 .yes_ranges = axp152_writeable_ranges,
63 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
64};
65
66static const struct regmap_access_table axp152_volatile_table = {
67 .yes_ranges = axp152_volatile_ranges,
68 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
69};
70
Carlo Caionecfb61a42014-05-01 14:29:27 +020071static const struct regmap_range axp20x_writeable_ranges[] = {
72 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
Quentin Schulz97602372017-03-20 09:16:53 +010073 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
Carlo Caionecfb61a42014-05-01 14:29:27 +020074 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020075 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
Carlo Caionecfb61a42014-05-01 14:29:27 +020076};
77
78static const struct regmap_range axp20x_volatile_ranges[] = {
Bruno Prémont553ed4b2015-08-08 17:58:40 +020079 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
80 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
Carlo Caionecfb61a42014-05-01 14:29:27 +020081 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020082 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
83 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
84 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
Carlo Caionecfb61a42014-05-01 14:29:27 +020085};
86
87static const struct regmap_access_table axp20x_writeable_table = {
88 .yes_ranges = axp20x_writeable_ranges,
89 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
90};
91
92static const struct regmap_access_table axp20x_volatile_table = {
93 .yes_ranges = axp20x_volatile_ranges,
94 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
95};
96
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080097/* AXP22x ranges are shared with the AXP809, as they cover the same range */
Boris BREZILLONf05be582015-04-10 12:09:01 +080098static const struct regmap_range axp22x_writeable_ranges[] = {
99 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
Quentin Schulz97602372017-03-20 09:16:53 +0100100 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3),
Boris BREZILLONf05be582015-04-10 12:09:01 +0800101 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
102};
103
104static const struct regmap_range axp22x_volatile_ranges[] = {
Hans de Goede15093252016-05-14 19:51:28 +0200105 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
Boris BREZILLONf05be582015-04-10 12:09:01 +0800106 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Hans de Goede15093252016-05-14 19:51:28 +0200107 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
Quentin Schulzed7311f2017-03-20 09:16:45 +0100108 regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
Hans de Goede15093252016-05-14 19:51:28 +0200109 regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
Boris BREZILLONf05be582015-04-10 12:09:01 +0800110};
111
112static const struct regmap_access_table axp22x_writeable_table = {
113 .yes_ranges = axp22x_writeable_ranges,
114 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
115};
116
117static const struct regmap_access_table axp22x_volatile_table = {
118 .yes_ranges = axp22x_volatile_ranges,
119 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
120};
121
Icenowy Zheng15783532017-04-17 19:57:40 +0800122/* AXP288 ranges are shared with the AXP803, as they cover the same range */
Jacob Panaf7e9062014-10-06 21:17:14 -0700123static const struct regmap_range axp288_writeable_ranges[] = {
124 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
125 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
126};
127
128static const struct regmap_range axp288_volatile_ranges[] = {
Hans de Goedecd532162016-12-16 21:09:06 +0100129 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
130 regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
131 regmap_reg_range(AXP288_BC_DET_STAT, AXP288_BC_DET_STAT),
Hans de Goede0c384fc2017-12-22 13:35:09 +0100132 regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
Jacob Panaf7e9062014-10-06 21:17:14 -0700133 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
Hans de Goedecd532162016-12-16 21:09:06 +0100134 regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
135 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
136 regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
137 regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
Jacob Panaf7e9062014-10-06 21:17:14 -0700138};
139
140static const struct regmap_access_table axp288_writeable_table = {
141 .yes_ranges = axp288_writeable_ranges,
142 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
143};
144
145static const struct regmap_access_table axp288_volatile_table = {
146 .yes_ranges = axp288_volatile_ranges,
147 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
148};
149
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800150static const struct regmap_range axp806_writeable_ranges[] = {
151 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
152 regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
153 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
154 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
Chen-Yu Tsai34d90302016-11-11 11:29:52 +0800155 regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800156};
157
158static const struct regmap_range axp806_volatile_ranges[] = {
159 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
160};
161
162static const struct regmap_access_table axp806_writeable_table = {
163 .yes_ranges = axp806_writeable_ranges,
164 .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
165};
166
167static const struct regmap_access_table axp806_volatile_table = {
168 .yes_ranges = axp806_volatile_ranges,
169 .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
170};
171
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800172static const struct resource axp152_pek_resources[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200173 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
174 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
175};
176
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800177static const struct resource axp20x_ac_power_supply_resources[] = {
Michael Haascd7cf272016-05-06 07:19:49 +0200178 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
179 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
180 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
181};
182
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800183static const struct resource axp20x_pek_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800184 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
185 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200186};
187
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800188static const struct resource axp20x_usb_power_supply_resources[] = {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200189 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
190 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
191 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
192 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
193};
194
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800195static const struct resource axp22x_usb_power_supply_resources[] = {
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200196 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
197 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
198};
199
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800200static const struct resource axp22x_pek_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800201 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
202 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
Boris BREZILLONf05be582015-04-10 12:09:01 +0800203};
204
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800205static const struct resource axp288_power_button_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800206 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKP, "PEK_DBR"),
207 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKN, "PEK_DBF"),
Borun Fue56e5ad2015-10-14 16:16:26 +0800208};
209
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800210static const struct resource axp288_fuel_gauge_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800211 DEFINE_RES_IRQ(AXP288_IRQ_QWBTU),
212 DEFINE_RES_IRQ(AXP288_IRQ_WBTU),
213 DEFINE_RES_IRQ(AXP288_IRQ_QWBTO),
214 DEFINE_RES_IRQ(AXP288_IRQ_WBTO),
215 DEFINE_RES_IRQ(AXP288_IRQ_WL2),
216 DEFINE_RES_IRQ(AXP288_IRQ_WL1),
Jacob Panaf7e9062014-10-06 21:17:14 -0700217};
218
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800219static const struct resource axp803_pek_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800220 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
221 DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
Icenowy Zheng15783532017-04-17 19:57:40 +0800222};
223
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800224static const struct resource axp809_pek_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800225 DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
226 DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800227};
228
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200229static const struct regmap_config axp152_regmap_config = {
230 .reg_bits = 8,
231 .val_bits = 8,
232 .wr_table = &axp152_writeable_table,
233 .volatile_table = &axp152_volatile_table,
234 .max_register = AXP152_PWM1_DUTY_CYCLE,
235 .cache_type = REGCACHE_RBTREE,
236};
237
Carlo Caionecfb61a42014-05-01 14:29:27 +0200238static const struct regmap_config axp20x_regmap_config = {
239 .reg_bits = 8,
240 .val_bits = 8,
241 .wr_table = &axp20x_writeable_table,
242 .volatile_table = &axp20x_volatile_table,
Bruno Prémont553ed4b2015-08-08 17:58:40 +0200243 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200244 .cache_type = REGCACHE_RBTREE,
245};
246
Boris BREZILLONf05be582015-04-10 12:09:01 +0800247static const struct regmap_config axp22x_regmap_config = {
248 .reg_bits = 8,
249 .val_bits = 8,
250 .wr_table = &axp22x_writeable_table,
251 .volatile_table = &axp22x_volatile_table,
252 .max_register = AXP22X_BATLOW_THRES1,
253 .cache_type = REGCACHE_RBTREE,
254};
255
Jacob Panaf7e9062014-10-06 21:17:14 -0700256static const struct regmap_config axp288_regmap_config = {
257 .reg_bits = 8,
258 .val_bits = 8,
259 .wr_table = &axp288_writeable_table,
260 .volatile_table = &axp288_volatile_table,
261 .max_register = AXP288_FG_TUNE5,
262 .cache_type = REGCACHE_RBTREE,
263};
264
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800265static const struct regmap_config axp806_regmap_config = {
266 .reg_bits = 8,
267 .val_bits = 8,
268 .wr_table = &axp806_writeable_table,
269 .volatile_table = &axp806_volatile_table,
Chen-Yu Tsai34d90302016-11-11 11:29:52 +0800270 .max_register = AXP806_REG_ADDR_EXT,
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800271 .cache_type = REGCACHE_RBTREE,
272};
273
Jacob Panaf7e9062014-10-06 21:17:14 -0700274#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
275 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
Carlo Caionecfb61a42014-05-01 14:29:27 +0200276
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200277static const struct regmap_irq axp152_regmap_irqs[] = {
278 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
279 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
280 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
281 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
282 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
283 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
284 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
285 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
286 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
287 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
288 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
289 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
290 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
291 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
292 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
293 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
294 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
295};
296
Carlo Caionecfb61a42014-05-01 14:29:27 +0200297static const struct regmap_irq axp20x_regmap_irqs[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700298 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
299 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
300 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
301 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
302 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
303 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
304 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
305 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
306 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
307 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
308 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
309 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
310 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
311 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
312 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
313 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
314 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
315 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
316 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
317 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
318 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
319 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
320 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
321 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
322 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
323 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
324 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
325 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
326 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
327 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
328 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
329 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
330 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
331 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
332 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
333 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
334 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
335};
336
Boris BREZILLONf05be582015-04-10 12:09:01 +0800337static const struct regmap_irq axp22x_regmap_irqs[] = {
338 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
339 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
340 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
341 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
342 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
343 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
344 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
345 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
346 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
347 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
348 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
349 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
350 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
351 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
352 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
353 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
354 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
355 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
356 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
357 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
358 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
359 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
360 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
361 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
362 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
363};
364
Jacob Panaf7e9062014-10-06 21:17:14 -0700365/* some IRQs are compatible with axp20x models */
366static const struct regmap_irq axp288_regmap_irqs[] = {
Jacob Panff3bbc52014-11-11 11:30:09 -0800367 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
368 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
369 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
Hans de Goede8b44e672016-12-14 14:52:06 +0100370 INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
371 INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
372 INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700373
Jacob Panff3bbc52014-11-11 11:30:09 -0800374 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
375 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700376 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
377 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
Jacob Panff3bbc52014-11-11 11:30:09 -0800378 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
379 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700380
381 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
382 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
383 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
Jacob Panff3bbc52014-11-11 11:30:09 -0800384 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700385 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
386 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
387 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
388 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
389
390 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
391 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
392 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
393 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
394
395 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
396 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
397 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
398 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
399 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
400 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
401 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
Jacob Panff3bbc52014-11-11 11:30:09 -0800402 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700403
404 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
405 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200406};
407
Icenowy Zheng15783532017-04-17 19:57:40 +0800408static const struct regmap_irq axp803_regmap_irqs[] = {
409 INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V, 0, 7),
410 INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN, 0, 6),
411 INIT_REGMAP_IRQ(AXP803, ACIN_REMOVAL, 0, 5),
412 INIT_REGMAP_IRQ(AXP803, VBUS_OVER_V, 0, 4),
413 INIT_REGMAP_IRQ(AXP803, VBUS_PLUGIN, 0, 3),
414 INIT_REGMAP_IRQ(AXP803, VBUS_REMOVAL, 0, 2),
415 INIT_REGMAP_IRQ(AXP803, BATT_PLUGIN, 1, 7),
416 INIT_REGMAP_IRQ(AXP803, BATT_REMOVAL, 1, 6),
417 INIT_REGMAP_IRQ(AXP803, BATT_ENT_ACT_MODE, 1, 5),
418 INIT_REGMAP_IRQ(AXP803, BATT_EXIT_ACT_MODE, 1, 4),
419 INIT_REGMAP_IRQ(AXP803, CHARG, 1, 3),
420 INIT_REGMAP_IRQ(AXP803, CHARG_DONE, 1, 2),
421 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH, 2, 7),
422 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH_END, 2, 6),
423 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW, 2, 5),
424 INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW_END, 2, 4),
425 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH, 2, 3),
426 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH_END, 2, 2),
427 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW, 2, 1),
428 INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW_END, 2, 0),
429 INIT_REGMAP_IRQ(AXP803, DIE_TEMP_HIGH, 3, 7),
430 INIT_REGMAP_IRQ(AXP803, GPADC, 3, 2),
431 INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL1, 3, 1),
432 INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL2, 3, 0),
433 INIT_REGMAP_IRQ(AXP803, TIMER, 4, 7),
434 INIT_REGMAP_IRQ(AXP803, PEK_RIS_EDGE, 4, 6),
435 INIT_REGMAP_IRQ(AXP803, PEK_FAL_EDGE, 4, 5),
436 INIT_REGMAP_IRQ(AXP803, PEK_SHORT, 4, 4),
437 INIT_REGMAP_IRQ(AXP803, PEK_LONG, 4, 3),
438 INIT_REGMAP_IRQ(AXP803, PEK_OVER_OFF, 4, 2),
439 INIT_REGMAP_IRQ(AXP803, GPIO1_INPUT, 4, 1),
440 INIT_REGMAP_IRQ(AXP803, GPIO0_INPUT, 4, 0),
441 INIT_REGMAP_IRQ(AXP803, BC_USB_CHNG, 5, 1),
442 INIT_REGMAP_IRQ(AXP803, MV_CHNG, 5, 0),
443};
444
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800445static const struct regmap_irq axp806_regmap_irqs[] = {
446 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
447 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
448 INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
449 INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
450 INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
451 INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
452 INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
Chen-Yu Tsaieef2b532018-03-29 12:31:15 +0800453 INIT_REGMAP_IRQ(AXP806, POK_LONG, 1, 0),
454 INIT_REGMAP_IRQ(AXP806, POK_SHORT, 1, 1),
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800455 INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
Chen-Yu Tsaieef2b532018-03-29 12:31:15 +0800456 INIT_REGMAP_IRQ(AXP806, POK_FALL, 1, 5),
457 INIT_REGMAP_IRQ(AXP806, POK_RISE, 1, 6),
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800458};
459
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800460static const struct regmap_irq axp809_regmap_irqs[] = {
461 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
462 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
463 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
464 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
465 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
466 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
467 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
468 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
469 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
470 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
471 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
472 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
473 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
474 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
475 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
476 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
477 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
478 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
479 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
480 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
481 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
482 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
483 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
484 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
485 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
486 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
487 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
488 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
489 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
490 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
491 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
492 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
493};
494
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200495static const struct regmap_irq_chip axp152_regmap_irq_chip = {
496 .name = "axp152_irq_chip",
497 .status_base = AXP152_IRQ1_STATE,
498 .ack_base = AXP152_IRQ1_STATE,
499 .mask_base = AXP152_IRQ1_EN,
500 .mask_invert = true,
501 .init_ack_masked = true,
502 .irqs = axp152_regmap_irqs,
503 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
504 .num_regs = 3,
505};
506
Carlo Caionecfb61a42014-05-01 14:29:27 +0200507static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
508 .name = "axp20x_irq_chip",
509 .status_base = AXP20X_IRQ1_STATE,
510 .ack_base = AXP20X_IRQ1_STATE,
511 .mask_base = AXP20X_IRQ1_EN,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200512 .mask_invert = true,
513 .init_ack_masked = true,
Jacob Panaf7e9062014-10-06 21:17:14 -0700514 .irqs = axp20x_regmap_irqs,
515 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
516 .num_regs = 5,
517
518};
519
Boris BREZILLONf05be582015-04-10 12:09:01 +0800520static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
521 .name = "axp22x_irq_chip",
522 .status_base = AXP20X_IRQ1_STATE,
523 .ack_base = AXP20X_IRQ1_STATE,
524 .mask_base = AXP20X_IRQ1_EN,
525 .mask_invert = true,
526 .init_ack_masked = true,
527 .irqs = axp22x_regmap_irqs,
528 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
529 .num_regs = 5,
530};
531
Jacob Panaf7e9062014-10-06 21:17:14 -0700532static const struct regmap_irq_chip axp288_regmap_irq_chip = {
533 .name = "axp288_irq_chip",
534 .status_base = AXP20X_IRQ1_STATE,
535 .ack_base = AXP20X_IRQ1_STATE,
536 .mask_base = AXP20X_IRQ1_EN,
537 .mask_invert = true,
538 .init_ack_masked = true,
539 .irqs = axp288_regmap_irqs,
540 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
541 .num_regs = 6,
542
Carlo Caionecfb61a42014-05-01 14:29:27 +0200543};
544
Icenowy Zheng15783532017-04-17 19:57:40 +0800545static const struct regmap_irq_chip axp803_regmap_irq_chip = {
546 .name = "axp803",
547 .status_base = AXP20X_IRQ1_STATE,
548 .ack_base = AXP20X_IRQ1_STATE,
549 .mask_base = AXP20X_IRQ1_EN,
550 .mask_invert = true,
551 .init_ack_masked = true,
552 .irqs = axp803_regmap_irqs,
553 .num_irqs = ARRAY_SIZE(axp803_regmap_irqs),
554 .num_regs = 6,
555};
556
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800557static const struct regmap_irq_chip axp806_regmap_irq_chip = {
558 .name = "axp806",
559 .status_base = AXP20X_IRQ1_STATE,
560 .ack_base = AXP20X_IRQ1_STATE,
561 .mask_base = AXP20X_IRQ1_EN,
562 .mask_invert = true,
563 .init_ack_masked = true,
564 .irqs = axp806_regmap_irqs,
565 .num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
566 .num_regs = 2,
567};
568
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800569static const struct regmap_irq_chip axp809_regmap_irq_chip = {
570 .name = "axp809",
571 .status_base = AXP20X_IRQ1_STATE,
572 .ack_base = AXP20X_IRQ1_STATE,
573 .mask_base = AXP20X_IRQ1_EN,
574 .mask_invert = true,
575 .init_ack_masked = true,
576 .irqs = axp809_regmap_irqs,
577 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
578 .num_regs = 5,
579};
580
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800581static const struct mfd_cell axp20x_cells[] = {
Carlo Caionecfb61a42014-05-01 14:29:27 +0200582 {
Maxime Ripardb419c162016-07-20 16:11:37 +0200583 .name = "axp20x-gpio",
584 .of_compatible = "x-powers,axp209-gpio",
585 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200586 .name = "axp20x-pek",
587 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
588 .resources = axp20x_pek_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200589 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200590 .name = "axp20x-regulator",
591 }, {
Quentin Schulz4d5e5c32017-03-20 09:16:47 +0100592 .name = "axp20x-adc",
Quentin Schulz034c3c92018-02-28 11:35:56 +0100593 .of_compatible = "x-powers,axp209-adc",
Quentin Schulz4d5e5c32017-03-20 09:16:47 +0100594 }, {
Quentin Schulzb4aeceb2017-04-05 10:10:55 +0200595 .name = "axp20x-battery-power-supply",
596 .of_compatible = "x-powers,axp209-battery-power-supply",
597 }, {
Michael Haascd7cf272016-05-06 07:19:49 +0200598 .name = "axp20x-ac-power-supply",
599 .of_compatible = "x-powers,axp202-ac-power-supply",
600 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
601 .resources = axp20x_ac_power_supply_resources,
602 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200603 .name = "axp20x-usb-power-supply",
604 .of_compatible = "x-powers,axp202-usb-power-supply",
605 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
606 .resources = axp20x_usb_power_supply_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200607 },
608};
609
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800610static const struct mfd_cell axp221_cells[] = {
Quentin Schulz4c650562016-12-09 12:04:14 +0100611 {
Quentin Schulzf4463632017-07-26 16:28:27 +0800612 .name = "axp221-pek",
Quentin Schulz4c650562016-12-09 12:04:14 +0100613 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
614 .resources = axp22x_pek_resources,
615 }, {
616 .name = "axp20x-regulator",
617 }, {
Quentin Schulz034c3c92018-02-28 11:35:56 +0100618 .name = "axp22x-adc",
619 .of_compatible = "x-powers,axp221-adc",
Quentin Schulz4d5e5c32017-03-20 09:16:47 +0100620 }, {
Quentin Schulz95c4f532017-03-20 09:16:48 +0100621 .name = "axp20x-ac-power-supply",
622 .of_compatible = "x-powers,axp221-ac-power-supply",
623 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
624 .resources = axp20x_ac_power_supply_resources,
625 }, {
Quentin Schulzb4aeceb2017-04-05 10:10:55 +0200626 .name = "axp20x-battery-power-supply",
627 .of_compatible = "x-powers,axp221-battery-power-supply",
628 }, {
Quentin Schulz4c650562016-12-09 12:04:14 +0100629 .name = "axp20x-usb-power-supply",
630 .of_compatible = "x-powers,axp221-usb-power-supply",
631 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
632 .resources = axp22x_usb_power_supply_resources,
633 },
634};
635
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800636static const struct mfd_cell axp223_cells[] = {
Boris BREZILLONf05be582015-04-10 12:09:01 +0800637 {
Quentin Schulzf4463632017-07-26 16:28:27 +0800638 .name = "axp221-pek",
Boris BREZILLONf05be582015-04-10 12:09:01 +0800639 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
640 .resources = axp22x_pek_resources,
Chen-Yu Tsai6d4fa892015-04-10 12:09:06 +0800641 }, {
Quentin Schulz4d5e5c32017-03-20 09:16:47 +0100642 .name = "axp22x-adc",
Quentin Schulz034c3c92018-02-28 11:35:56 +0100643 .of_compatible = "x-powers,axp221-adc",
Quentin Schulz4d5e5c32017-03-20 09:16:47 +0100644 }, {
Quentin Schulzb4aeceb2017-04-05 10:10:55 +0200645 .name = "axp20x-battery-power-supply",
646 .of_compatible = "x-powers,axp221-battery-power-supply",
647 }, {
Chen-Yu Tsai6d4fa892015-04-10 12:09:06 +0800648 .name = "axp20x-regulator",
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200649 }, {
Quentin Schulz95c4f532017-03-20 09:16:48 +0100650 .name = "axp20x-ac-power-supply",
651 .of_compatible = "x-powers,axp221-ac-power-supply",
652 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
653 .resources = axp20x_ac_power_supply_resources,
654 }, {
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200655 .name = "axp20x-usb-power-supply",
Quentin Schulz4c650562016-12-09 12:04:14 +0100656 .of_compatible = "x-powers,axp223-usb-power-supply",
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200657 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
658 .resources = axp22x_usb_power_supply_resources,
Boris BREZILLONf05be582015-04-10 12:09:01 +0800659 },
660};
661
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800662static const struct mfd_cell axp152_cells[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200663 {
664 .name = "axp20x-pek",
665 .num_resources = ARRAY_SIZE(axp152_pek_resources),
666 .resources = axp152_pek_resources,
667 },
668};
669
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800670static const struct resource axp288_adc_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800671 DEFINE_RES_IRQ_NAMED(AXP288_IRQ_GPADC, "GPADC"),
Jacob Panaf7e9062014-10-06 21:17:14 -0700672};
673
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800674static const struct resource axp288_extcon_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800675 DEFINE_RES_IRQ(AXP288_IRQ_VBUS_FALL),
676 DEFINE_RES_IRQ(AXP288_IRQ_VBUS_RISE),
677 DEFINE_RES_IRQ(AXP288_IRQ_MV_CHNG),
678 DEFINE_RES_IRQ(AXP288_IRQ_BC_USB_CHNG),
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530679};
680
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800681static const struct resource axp288_charger_resources[] = {
Chen-Yu Tsaie26f87e2018-03-29 12:31:14 +0800682 DEFINE_RES_IRQ(AXP288_IRQ_OV),
683 DEFINE_RES_IRQ(AXP288_IRQ_DONE),
684 DEFINE_RES_IRQ(AXP288_IRQ_CHARGING),
685 DEFINE_RES_IRQ(AXP288_IRQ_SAFE_QUIT),
686 DEFINE_RES_IRQ(AXP288_IRQ_SAFE_ENTER),
687 DEFINE_RES_IRQ(AXP288_IRQ_QCBTU),
688 DEFINE_RES_IRQ(AXP288_IRQ_CBTU),
689 DEFINE_RES_IRQ(AXP288_IRQ_QCBTO),
690 DEFINE_RES_IRQ(AXP288_IRQ_CBTO),
Jacob Panaf7e9062014-10-06 21:17:14 -0700691};
692
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800693static const struct mfd_cell axp288_cells[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700694 {
695 .name = "axp288_adc",
696 .num_resources = ARRAY_SIZE(axp288_adc_resources),
697 .resources = axp288_adc_resources,
698 },
699 {
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530700 .name = "axp288_extcon",
701 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
702 .resources = axp288_extcon_resources,
703 },
704 {
Jacob Panaf7e9062014-10-06 21:17:14 -0700705 .name = "axp288_charger",
706 .num_resources = ARRAY_SIZE(axp288_charger_resources),
707 .resources = axp288_charger_resources,
708 },
709 {
Todd Brandtd63878742015-02-02 15:41:41 -0800710 .name = "axp288_fuel_gauge",
711 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
712 .resources = axp288_fuel_gauge_resources,
Jacob Panaf7e9062014-10-06 21:17:14 -0700713 },
Aaron Lud8139f62014-11-24 17:24:47 +0800714 {
Quentin Schulzf4463632017-07-26 16:28:27 +0800715 .name = "axp221-pek",
Borun Fue56e5ad2015-10-14 16:16:26 +0800716 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
717 .resources = axp288_power_button_resources,
718 },
719 {
Aaron Lud8139f62014-11-24 17:24:47 +0800720 .name = "axp288_pmic_acpi",
721 },
Jacob Panaf7e9062014-10-06 21:17:14 -0700722};
723
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800724static const struct mfd_cell axp803_cells[] = {
Icenowy Zheng15783532017-04-17 19:57:40 +0800725 {
Quentin Schulzf4463632017-07-26 16:28:27 +0800726 .name = "axp221-pek",
Icenowy Zheng15783532017-04-17 19:57:40 +0800727 .num_resources = ARRAY_SIZE(axp803_pek_resources),
728 .resources = axp803_pek_resources,
Icenowy Zheng9b79ff12017-05-18 15:16:50 +0800729 },
730 { .name = "axp20x-regulator" },
Icenowy Zheng15783532017-04-17 19:57:40 +0800731};
732
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800733static const struct mfd_cell axp806_cells[] = {
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800734 {
735 .id = 2,
736 .name = "axp20x-regulator",
737 },
738};
739
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800740static const struct mfd_cell axp809_cells[] = {
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800741 {
Quentin Schulzf4463632017-07-26 16:28:27 +0800742 .name = "axp221-pek",
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800743 .num_resources = ARRAY_SIZE(axp809_pek_resources),
744 .resources = axp809_pek_resources,
745 }, {
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800746 .id = 1,
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800747 .name = "axp20x-regulator",
748 },
749};
750
Chen-Yu Tsai531a4692018-03-29 12:31:13 +0800751static const struct mfd_cell axp813_cells[] = {
Chen-Yu Tsai73037332017-07-26 16:28:26 +0800752 {
Quentin Schulzf4463632017-07-26 16:28:27 +0800753 .name = "axp221-pek",
Chen-Yu Tsai73037332017-07-26 16:28:26 +0800754 .num_resources = ARRAY_SIZE(axp803_pek_resources),
755 .resources = axp803_pek_resources,
Chen-Yu Tsai9a432062017-10-18 16:31:31 +0800756 }, {
757 .name = "axp20x-regulator",
Quentin Schulz2bb32532017-12-05 15:46:47 +0100758 }, {
759 .name = "axp20x-gpio",
760 .of_compatible = "x-powers,axp813-gpio",
Quentin Schulze5d590f2018-02-28 11:35:57 +0100761 }, {
762 .name = "axp813-adc",
763 .of_compatible = "x-powers,axp813-adc",
Quentin Schulz67203282018-02-28 11:36:01 +0100764 }, {
765 .name = "axp20x-battery-power-supply",
766 .of_compatible = "x-powers,axp813-battery-power-supply",
Quentin Schulze5d590f2018-02-28 11:35:57 +0100767 },
Chen-Yu Tsai73037332017-07-26 16:28:26 +0800768};
769
Carlo Caionecfb61a42014-05-01 14:29:27 +0200770static struct axp20x_dev *axp20x_pm_power_off;
771static void axp20x_power_off(void)
772{
Jacob Panaf7e9062014-10-06 21:17:14 -0700773 if (axp20x_pm_power_off->variant == AXP288_ID)
774 return;
775
Carlo Caionecfb61a42014-05-01 14:29:27 +0200776 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
777 AXP20X_OFF);
Hans de Goede179dc632016-06-05 15:50:48 +0200778
779 /* Give capacitors etc. time to drain to avoid kernel panic msg. */
780 msleep(500);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200781}
782
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800783int axp20x_match_device(struct axp20x_dev *axp20x)
Jacob Panaf7e9062014-10-06 21:17:14 -0700784{
Chen-Yu Tsaie47a3cf2016-02-12 10:02:39 +0800785 struct device *dev = axp20x->dev;
Jacob Panaf7e9062014-10-06 21:17:14 -0700786 const struct acpi_device_id *acpi_id;
787 const struct of_device_id *of_id;
788
789 if (dev->of_node) {
Chen-Yu Tsaiaf7acc32016-02-12 10:02:40 +0800790 of_id = of_match_device(dev->driver->of_match_table, dev);
Jacob Panaf7e9062014-10-06 21:17:14 -0700791 if (!of_id) {
792 dev_err(dev, "Unable to match OF ID\n");
793 return -ENODEV;
794 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800795 axp20x->variant = (long)of_id->data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700796 } else {
797 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
798 if (!acpi_id || !acpi_id->driver_data) {
799 dev_err(dev, "Unable to match ACPI ID and data\n");
800 return -ENODEV;
801 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800802 axp20x->variant = (long)acpi_id->driver_data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700803 }
804
805 switch (axp20x->variant) {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200806 case AXP152_ID:
807 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
808 axp20x->cells = axp152_cells;
809 axp20x->regmap_cfg = &axp152_regmap_config;
810 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
811 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700812 case AXP202_ID:
813 case AXP209_ID:
814 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
815 axp20x->cells = axp20x_cells;
816 axp20x->regmap_cfg = &axp20x_regmap_config;
817 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
818 break;
Boris BREZILLONf05be582015-04-10 12:09:01 +0800819 case AXP221_ID:
Quentin Schulz4c650562016-12-09 12:04:14 +0100820 axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
821 axp20x->cells = axp221_cells;
822 axp20x->regmap_cfg = &axp22x_regmap_config;
823 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
824 break;
Chen-Yu Tsai02071f02016-02-12 10:02:44 +0800825 case AXP223_ID:
Quentin Schulz4c650562016-12-09 12:04:14 +0100826 axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
827 axp20x->cells = axp223_cells;
Boris BREZILLONf05be582015-04-10 12:09:01 +0800828 axp20x->regmap_cfg = &axp22x_regmap_config;
829 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
830 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700831 case AXP288_ID:
832 axp20x->cells = axp288_cells;
833 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
834 axp20x->regmap_cfg = &axp288_regmap_config;
835 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
Hans de Goede0a5454c2016-12-14 14:52:05 +0100836 axp20x->irq_flags = IRQF_TRIGGER_LOW;
Jacob Panaf7e9062014-10-06 21:17:14 -0700837 break;
Icenowy Zheng15783532017-04-17 19:57:40 +0800838 case AXP803_ID:
839 axp20x->nr_cells = ARRAY_SIZE(axp803_cells);
840 axp20x->cells = axp803_cells;
841 axp20x->regmap_cfg = &axp288_regmap_config;
842 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
843 break;
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800844 case AXP806_ID:
845 axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
846 axp20x->cells = axp806_cells;
847 axp20x->regmap_cfg = &axp806_regmap_config;
848 axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
849 break;
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800850 case AXP809_ID:
851 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
852 axp20x->cells = axp809_cells;
853 axp20x->regmap_cfg = &axp22x_regmap_config;
854 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
855 break;
Chen-Yu Tsai73037332017-07-26 16:28:26 +0800856 case AXP813_ID:
857 axp20x->nr_cells = ARRAY_SIZE(axp813_cells);
858 axp20x->cells = axp813_cells;
859 axp20x->regmap_cfg = &axp288_regmap_config;
860 /*
861 * The IRQ table given in the datasheet is incorrect.
862 * In IRQ enable/status registers 1, there are separate
863 * IRQs for ACIN and VBUS, instead of bits [7:5] being
864 * the same as bits [4:2]. So it shares the same IRQs
865 * as the AXP803, rather than the AXP288.
866 */
867 axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
868 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700869 default:
870 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
871 return -EINVAL;
872 }
873 dev_info(dev, "AXP20x variant %s found\n",
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800874 axp20x_model_names[axp20x->variant]);
Jacob Panaf7e9062014-10-06 21:17:14 -0700875
876 return 0;
877}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800878EXPORT_SYMBOL(axp20x_match_device);
Jacob Panaf7e9062014-10-06 21:17:14 -0700879
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800880int axp20x_device_probe(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200881{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200882 int ret;
883
Chen-Yu Tsai696f0b32017-01-05 12:01:03 +0800884 /*
885 * The AXP806 supports either master/standalone or slave mode.
886 * Slave mode allows sharing the serial bus, even with multiple
887 * AXP806 which all have the same hardware address.
888 *
889 * This is done with extra "serial interface address extension",
890 * or AXP806_BUS_ADDR_EXT, and "register address extension", or
891 * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
892 * 1 bit customizable at the factory, and 1 bit depending on the
893 * state of an external pin. The latter is writable. The device
894 * will only respond to operations to its other registers when
895 * the these device addressing bits (in the upper 4 bits of the
896 * registers) match.
897 *
Rask Ingemann Lambertsenc0369692017-02-22 20:42:02 +0100898 * By default we support an AXP806 chained to an AXP809 in slave
899 * mode. Boards which use an AXP806 in master mode can set the
900 * property "x-powers,master-mode" to override the default.
Chen-Yu Tsai696f0b32017-01-05 12:01:03 +0800901 */
Rask Ingemann Lambertsenc0369692017-02-22 20:42:02 +0100902 if (axp20x->variant == AXP806_ID) {
903 if (of_property_read_bool(axp20x->dev->of_node,
904 "x-powers,master-mode"))
905 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
906 AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
907 else
908 regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
909 AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
910 }
Chen-Yu Tsai696f0b32017-01-05 12:01:03 +0800911
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800912 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
Hans de Goede0a5454c2016-12-14 14:52:05 +0100913 IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
914 -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200915 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800916 dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200917 return ret;
918 }
919
Jacob Panaf7e9062014-10-06 21:17:14 -0700920 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800921 axp20x->nr_cells, NULL, 0, NULL);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200922
923 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800924 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
925 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200926 return ret;
927 }
928
929 if (!pm_power_off) {
930 axp20x_pm_power_off = axp20x;
931 pm_power_off = axp20x_power_off;
932 }
933
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800934 dev_info(axp20x->dev, "AXP20X driver loaded\n");
Carlo Caionecfb61a42014-05-01 14:29:27 +0200935
936 return 0;
937}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800938EXPORT_SYMBOL(axp20x_device_probe);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200939
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800940int axp20x_device_remove(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200941{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200942 if (axp20x == axp20x_pm_power_off) {
943 axp20x_pm_power_off = NULL;
944 pm_power_off = NULL;
945 }
946
947 mfd_remove_devices(axp20x->dev);
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800948 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200949
950 return 0;
951}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800952EXPORT_SYMBOL(axp20x_device_remove);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200953
954MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
955MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
956MODULE_LICENSE("GPL");