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Carlo Caionecfb61a42014-05-01 14:29:27 +02001/*
Jacob Panaf7e9062014-10-06 21:17:14 -07002 * axp20x.c - MFD core driver for the X-Powers' Power Management ICs
Carlo Caionecfb61a42014-05-01 14:29:27 +02003 *
Jacob Panaf7e9062014-10-06 21:17:14 -07004 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
Carlo Caionecfb61a42014-05-01 14:29:27 +02007 *
8 * Author: Carlo Caione <carlo@caione.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/err.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23#include <linux/regulator/consumer.h>
24#include <linux/mfd/axp20x.h>
25#include <linux/mfd/core.h>
26#include <linux/of_device.h>
27#include <linux/of_irq.h>
Jacob Panaf7e9062014-10-06 21:17:14 -070028#include <linux/acpi.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020029
30#define AXP20X_OFF 0x80
31
Krzysztof Kozlowskic31e8582015-03-24 11:21:17 +010032static const char * const axp20x_model_names[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +020033 "AXP152",
Jacob Panaf7e9062014-10-06 21:17:14 -070034 "AXP202",
35 "AXP209",
Boris BREZILLONf05be582015-04-10 12:09:01 +080036 "AXP221",
Jacob Panaf7e9062014-10-06 21:17:14 -070037 "AXP288",
38};
39
Michal Suchanekd8d79f82015-07-11 14:59:56 +020040static const struct regmap_range axp152_writeable_ranges[] = {
41 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
42 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
43};
44
45static const struct regmap_range axp152_volatile_ranges[] = {
46 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
47 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
48 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
49};
50
51static const struct regmap_access_table axp152_writeable_table = {
52 .yes_ranges = axp152_writeable_ranges,
53 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
54};
55
56static const struct regmap_access_table axp152_volatile_table = {
57 .yes_ranges = axp152_volatile_ranges,
58 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
59};
60
Carlo Caionecfb61a42014-05-01 14:29:27 +020061static const struct regmap_range axp20x_writeable_ranges[] = {
62 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
63 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
64};
65
66static const struct regmap_range axp20x_volatile_ranges[] = {
67 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
68};
69
70static const struct regmap_access_table axp20x_writeable_table = {
71 .yes_ranges = axp20x_writeable_ranges,
72 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
73};
74
75static const struct regmap_access_table axp20x_volatile_table = {
76 .yes_ranges = axp20x_volatile_ranges,
77 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
78};
79
Boris BREZILLONf05be582015-04-10 12:09:01 +080080static const struct regmap_range axp22x_writeable_ranges[] = {
81 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
82 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
83};
84
85static const struct regmap_range axp22x_volatile_ranges[] = {
86 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
87};
88
89static const struct regmap_access_table axp22x_writeable_table = {
90 .yes_ranges = axp22x_writeable_ranges,
91 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
92};
93
94static const struct regmap_access_table axp22x_volatile_table = {
95 .yes_ranges = axp22x_volatile_ranges,
96 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
97};
98
Jacob Panaf7e9062014-10-06 21:17:14 -070099static const struct regmap_range axp288_writeable_ranges[] = {
100 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
101 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
102};
103
104static const struct regmap_range axp288_volatile_ranges[] = {
105 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
106};
107
108static const struct regmap_access_table axp288_writeable_table = {
109 .yes_ranges = axp288_writeable_ranges,
110 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
111};
112
113static const struct regmap_access_table axp288_volatile_table = {
114 .yes_ranges = axp288_volatile_ranges,
115 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
116};
117
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200118static struct resource axp152_pek_resources[] = {
119 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
120 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
121};
122
Carlo Caionecfb61a42014-05-01 14:29:27 +0200123static struct resource axp20x_pek_resources[] = {
124 {
125 .name = "PEK_DBR",
126 .start = AXP20X_IRQ_PEK_RIS_EDGE,
127 .end = AXP20X_IRQ_PEK_RIS_EDGE,
128 .flags = IORESOURCE_IRQ,
129 }, {
130 .name = "PEK_DBF",
131 .start = AXP20X_IRQ_PEK_FAL_EDGE,
132 .end = AXP20X_IRQ_PEK_FAL_EDGE,
133 .flags = IORESOURCE_IRQ,
134 },
135};
136
Boris BREZILLONf05be582015-04-10 12:09:01 +0800137static struct resource axp22x_pek_resources[] = {
138 {
139 .name = "PEK_DBR",
140 .start = AXP22X_IRQ_PEK_RIS_EDGE,
141 .end = AXP22X_IRQ_PEK_RIS_EDGE,
142 .flags = IORESOURCE_IRQ,
143 }, {
144 .name = "PEK_DBF",
145 .start = AXP22X_IRQ_PEK_FAL_EDGE,
146 .end = AXP22X_IRQ_PEK_FAL_EDGE,
147 .flags = IORESOURCE_IRQ,
148 },
149};
150
Todd Brandtd63878742015-02-02 15:41:41 -0800151static struct resource axp288_fuel_gauge_resources[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700152 {
153 .start = AXP288_IRQ_QWBTU,
154 .end = AXP288_IRQ_QWBTU,
155 .flags = IORESOURCE_IRQ,
156 },
157 {
158 .start = AXP288_IRQ_WBTU,
159 .end = AXP288_IRQ_WBTU,
160 .flags = IORESOURCE_IRQ,
161 },
162 {
163 .start = AXP288_IRQ_QWBTO,
164 .end = AXP288_IRQ_QWBTO,
165 .flags = IORESOURCE_IRQ,
166 },
167 {
168 .start = AXP288_IRQ_WBTO,
169 .end = AXP288_IRQ_WBTO,
170 .flags = IORESOURCE_IRQ,
171 },
172 {
173 .start = AXP288_IRQ_WL2,
174 .end = AXP288_IRQ_WL2,
175 .flags = IORESOURCE_IRQ,
176 },
177 {
178 .start = AXP288_IRQ_WL1,
179 .end = AXP288_IRQ_WL1,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200184static const struct regmap_config axp152_regmap_config = {
185 .reg_bits = 8,
186 .val_bits = 8,
187 .wr_table = &axp152_writeable_table,
188 .volatile_table = &axp152_volatile_table,
189 .max_register = AXP152_PWM1_DUTY_CYCLE,
190 .cache_type = REGCACHE_RBTREE,
191};
192
Carlo Caionecfb61a42014-05-01 14:29:27 +0200193static const struct regmap_config axp20x_regmap_config = {
194 .reg_bits = 8,
195 .val_bits = 8,
196 .wr_table = &axp20x_writeable_table,
197 .volatile_table = &axp20x_volatile_table,
198 .max_register = AXP20X_FG_RES,
199 .cache_type = REGCACHE_RBTREE,
200};
201
Boris BREZILLONf05be582015-04-10 12:09:01 +0800202static const struct regmap_config axp22x_regmap_config = {
203 .reg_bits = 8,
204 .val_bits = 8,
205 .wr_table = &axp22x_writeable_table,
206 .volatile_table = &axp22x_volatile_table,
207 .max_register = AXP22X_BATLOW_THRES1,
208 .cache_type = REGCACHE_RBTREE,
209};
210
Jacob Panaf7e9062014-10-06 21:17:14 -0700211static const struct regmap_config axp288_regmap_config = {
212 .reg_bits = 8,
213 .val_bits = 8,
214 .wr_table = &axp288_writeable_table,
215 .volatile_table = &axp288_volatile_table,
216 .max_register = AXP288_FG_TUNE5,
217 .cache_type = REGCACHE_RBTREE,
218};
219
220#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
221 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
Carlo Caionecfb61a42014-05-01 14:29:27 +0200222
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200223static const struct regmap_irq axp152_regmap_irqs[] = {
224 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
225 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
226 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
227 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
228 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
229 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
230 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
231 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
232 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
233 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
234 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
235 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
236 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
237 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
238 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
239 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
240 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
241};
242
Carlo Caionecfb61a42014-05-01 14:29:27 +0200243static const struct regmap_irq axp20x_regmap_irqs[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700244 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
245 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
246 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
247 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
248 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
249 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
250 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
251 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
252 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
253 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
254 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
255 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
256 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
257 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
258 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
259 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
260 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
261 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
262 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
263 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
264 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
265 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
266 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
267 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
268 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
269 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
270 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
271 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
272 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
273 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
274 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
275 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
276 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
277 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
278 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
279 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
280 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
281};
282
Boris BREZILLONf05be582015-04-10 12:09:01 +0800283static const struct regmap_irq axp22x_regmap_irqs[] = {
284 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
285 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
286 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
287 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
288 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
289 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
290 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
291 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
292 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
293 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
294 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
295 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
296 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
297 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
298 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
299 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
300 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
301 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
302 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
303 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
304 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
305 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
306 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
307 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
308 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
309};
310
Jacob Panaf7e9062014-10-06 21:17:14 -0700311/* some IRQs are compatible with axp20x models */
312static const struct regmap_irq axp288_regmap_irqs[] = {
Jacob Panff3bbc52014-11-11 11:30:09 -0800313 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
314 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
315 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
Jacob Panaf7e9062014-10-06 21:17:14 -0700316
Jacob Panff3bbc52014-11-11 11:30:09 -0800317 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
318 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700319 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
320 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
Jacob Panff3bbc52014-11-11 11:30:09 -0800321 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
322 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700323
324 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
325 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
326 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
Jacob Panff3bbc52014-11-11 11:30:09 -0800327 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700328 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
329 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
330 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
331 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
332
333 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
334 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
335 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
336 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
337
338 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
339 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
340 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
341 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
342 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
343 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
344 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
Jacob Panff3bbc52014-11-11 11:30:09 -0800345 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700346
347 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
348 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200349};
350
351static const struct of_device_id axp20x_of_match[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200352 { .compatible = "x-powers,axp152", .data = (void *) AXP152_ID },
Carlo Caionecfb61a42014-05-01 14:29:27 +0200353 { .compatible = "x-powers,axp202", .data = (void *) AXP202_ID },
354 { .compatible = "x-powers,axp209", .data = (void *) AXP209_ID },
Boris BREZILLONf05be582015-04-10 12:09:01 +0800355 { .compatible = "x-powers,axp221", .data = (void *) AXP221_ID },
Carlo Caionecfb61a42014-05-01 14:29:27 +0200356 { },
357};
358MODULE_DEVICE_TABLE(of, axp20x_of_match);
359
360/*
361 * This is useless for OF-enabled devices, but it is needed by I2C subsystem
362 */
363static const struct i2c_device_id axp20x_i2c_id[] = {
364 { },
365};
366MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id);
367
Lee Jones0e50e922014-11-11 12:36:46 +0000368static const struct acpi_device_id axp20x_acpi_match[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700369 {
370 .id = "INT33F4",
371 .driver_data = AXP288_ID,
372 },
373 { },
374};
375MODULE_DEVICE_TABLE(acpi, axp20x_acpi_match);
376
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200377static const struct regmap_irq_chip axp152_regmap_irq_chip = {
378 .name = "axp152_irq_chip",
379 .status_base = AXP152_IRQ1_STATE,
380 .ack_base = AXP152_IRQ1_STATE,
381 .mask_base = AXP152_IRQ1_EN,
382 .mask_invert = true,
383 .init_ack_masked = true,
384 .irqs = axp152_regmap_irqs,
385 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
386 .num_regs = 3,
387};
388
Carlo Caionecfb61a42014-05-01 14:29:27 +0200389static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
390 .name = "axp20x_irq_chip",
391 .status_base = AXP20X_IRQ1_STATE,
392 .ack_base = AXP20X_IRQ1_STATE,
393 .mask_base = AXP20X_IRQ1_EN,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200394 .mask_invert = true,
395 .init_ack_masked = true,
Jacob Panaf7e9062014-10-06 21:17:14 -0700396 .irqs = axp20x_regmap_irqs,
397 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
398 .num_regs = 5,
399
400};
401
Boris BREZILLONf05be582015-04-10 12:09:01 +0800402static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
403 .name = "axp22x_irq_chip",
404 .status_base = AXP20X_IRQ1_STATE,
405 .ack_base = AXP20X_IRQ1_STATE,
406 .mask_base = AXP20X_IRQ1_EN,
407 .mask_invert = true,
408 .init_ack_masked = true,
409 .irqs = axp22x_regmap_irqs,
410 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
411 .num_regs = 5,
412};
413
Jacob Panaf7e9062014-10-06 21:17:14 -0700414static const struct regmap_irq_chip axp288_regmap_irq_chip = {
415 .name = "axp288_irq_chip",
416 .status_base = AXP20X_IRQ1_STATE,
417 .ack_base = AXP20X_IRQ1_STATE,
418 .mask_base = AXP20X_IRQ1_EN,
419 .mask_invert = true,
420 .init_ack_masked = true,
421 .irqs = axp288_regmap_irqs,
422 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
423 .num_regs = 6,
424
Carlo Caionecfb61a42014-05-01 14:29:27 +0200425};
426
Carlo Caionecfb61a42014-05-01 14:29:27 +0200427static struct mfd_cell axp20x_cells[] = {
428 {
429 .name = "axp20x-pek",
430 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
431 .resources = axp20x_pek_resources,
432 }, {
433 .name = "axp20x-regulator",
Carlo Caionecfb61a42014-05-01 14:29:27 +0200434 },
435};
436
Boris BREZILLONf05be582015-04-10 12:09:01 +0800437static struct mfd_cell axp22x_cells[] = {
438 {
439 .name = "axp20x-pek",
440 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
441 .resources = axp22x_pek_resources,
Chen-Yu Tsai6d4fa892015-04-10 12:09:06 +0800442 }, {
443 .name = "axp20x-regulator",
Boris BREZILLONf05be582015-04-10 12:09:01 +0800444 },
445};
446
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200447static struct mfd_cell axp152_cells[] = {
448 {
449 .name = "axp20x-pek",
450 .num_resources = ARRAY_SIZE(axp152_pek_resources),
451 .resources = axp152_pek_resources,
452 },
453};
454
Jacob Panaf7e9062014-10-06 21:17:14 -0700455static struct resource axp288_adc_resources[] = {
456 {
457 .name = "GPADC",
458 .start = AXP288_IRQ_GPADC,
459 .end = AXP288_IRQ_GPADC,
460 .flags = IORESOURCE_IRQ,
461 },
462};
463
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530464static struct resource axp288_extcon_resources[] = {
465 {
466 .start = AXP288_IRQ_VBUS_FALL,
467 .end = AXP288_IRQ_VBUS_FALL,
468 .flags = IORESOURCE_IRQ,
469 },
470 {
471 .start = AXP288_IRQ_VBUS_RISE,
472 .end = AXP288_IRQ_VBUS_RISE,
473 .flags = IORESOURCE_IRQ,
474 },
475 {
476 .start = AXP288_IRQ_MV_CHNG,
477 .end = AXP288_IRQ_MV_CHNG,
478 .flags = IORESOURCE_IRQ,
479 },
480 {
481 .start = AXP288_IRQ_BC_USB_CHNG,
482 .end = AXP288_IRQ_BC_USB_CHNG,
483 .flags = IORESOURCE_IRQ,
484 },
485};
486
Jacob Panaf7e9062014-10-06 21:17:14 -0700487static struct resource axp288_charger_resources[] = {
488 {
489 .start = AXP288_IRQ_OV,
490 .end = AXP288_IRQ_OV,
491 .flags = IORESOURCE_IRQ,
492 },
493 {
494 .start = AXP288_IRQ_DONE,
495 .end = AXP288_IRQ_DONE,
496 .flags = IORESOURCE_IRQ,
497 },
498 {
499 .start = AXP288_IRQ_CHARGING,
500 .end = AXP288_IRQ_CHARGING,
501 .flags = IORESOURCE_IRQ,
502 },
503 {
504 .start = AXP288_IRQ_SAFE_QUIT,
505 .end = AXP288_IRQ_SAFE_QUIT,
506 .flags = IORESOURCE_IRQ,
507 },
508 {
509 .start = AXP288_IRQ_SAFE_ENTER,
510 .end = AXP288_IRQ_SAFE_ENTER,
511 .flags = IORESOURCE_IRQ,
512 },
513 {
514 .start = AXP288_IRQ_QCBTU,
515 .end = AXP288_IRQ_QCBTU,
516 .flags = IORESOURCE_IRQ,
517 },
518 {
519 .start = AXP288_IRQ_CBTU,
520 .end = AXP288_IRQ_CBTU,
521 .flags = IORESOURCE_IRQ,
522 },
523 {
524 .start = AXP288_IRQ_QCBTO,
525 .end = AXP288_IRQ_QCBTO,
526 .flags = IORESOURCE_IRQ,
527 },
528 {
529 .start = AXP288_IRQ_CBTO,
530 .end = AXP288_IRQ_CBTO,
531 .flags = IORESOURCE_IRQ,
532 },
533};
534
535static struct mfd_cell axp288_cells[] = {
536 {
537 .name = "axp288_adc",
538 .num_resources = ARRAY_SIZE(axp288_adc_resources),
539 .resources = axp288_adc_resources,
540 },
541 {
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530542 .name = "axp288_extcon",
543 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
544 .resources = axp288_extcon_resources,
545 },
546 {
Jacob Panaf7e9062014-10-06 21:17:14 -0700547 .name = "axp288_charger",
548 .num_resources = ARRAY_SIZE(axp288_charger_resources),
549 .resources = axp288_charger_resources,
550 },
551 {
Todd Brandtd63878742015-02-02 15:41:41 -0800552 .name = "axp288_fuel_gauge",
553 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
554 .resources = axp288_fuel_gauge_resources,
Jacob Panaf7e9062014-10-06 21:17:14 -0700555 },
Aaron Lud8139f62014-11-24 17:24:47 +0800556 {
557 .name = "axp288_pmic_acpi",
558 },
Jacob Panaf7e9062014-10-06 21:17:14 -0700559};
560
Carlo Caionecfb61a42014-05-01 14:29:27 +0200561static struct axp20x_dev *axp20x_pm_power_off;
562static void axp20x_power_off(void)
563{
Jacob Panaf7e9062014-10-06 21:17:14 -0700564 if (axp20x_pm_power_off->variant == AXP288_ID)
565 return;
566
Carlo Caionecfb61a42014-05-01 14:29:27 +0200567 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
568 AXP20X_OFF);
569}
570
Jacob Panaf7e9062014-10-06 21:17:14 -0700571static int axp20x_match_device(struct axp20x_dev *axp20x, struct device *dev)
572{
573 const struct acpi_device_id *acpi_id;
574 const struct of_device_id *of_id;
575
576 if (dev->of_node) {
577 of_id = of_match_device(axp20x_of_match, dev);
578 if (!of_id) {
579 dev_err(dev, "Unable to match OF ID\n");
580 return -ENODEV;
581 }
582 axp20x->variant = (long) of_id->data;
583 } else {
584 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
585 if (!acpi_id || !acpi_id->driver_data) {
586 dev_err(dev, "Unable to match ACPI ID and data\n");
587 return -ENODEV;
588 }
589 axp20x->variant = (long) acpi_id->driver_data;
590 }
591
592 switch (axp20x->variant) {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200593 case AXP152_ID:
594 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
595 axp20x->cells = axp152_cells;
596 axp20x->regmap_cfg = &axp152_regmap_config;
597 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
598 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700599 case AXP202_ID:
600 case AXP209_ID:
601 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
602 axp20x->cells = axp20x_cells;
603 axp20x->regmap_cfg = &axp20x_regmap_config;
604 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
605 break;
Boris BREZILLONf05be582015-04-10 12:09:01 +0800606 case AXP221_ID:
607 axp20x->nr_cells = ARRAY_SIZE(axp22x_cells);
608 axp20x->cells = axp22x_cells;
609 axp20x->regmap_cfg = &axp22x_regmap_config;
610 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
611 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700612 case AXP288_ID:
613 axp20x->cells = axp288_cells;
614 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
615 axp20x->regmap_cfg = &axp288_regmap_config;
616 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
617 break;
618 default:
619 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
620 return -EINVAL;
621 }
622 dev_info(dev, "AXP20x variant %s found\n",
623 axp20x_model_names[axp20x->variant]);
624
625 return 0;
626}
627
Carlo Caionecfb61a42014-05-01 14:29:27 +0200628static int axp20x_i2c_probe(struct i2c_client *i2c,
629 const struct i2c_device_id *id)
630{
631 struct axp20x_dev *axp20x;
Carlo Caionecfb61a42014-05-01 14:29:27 +0200632 int ret;
633
634 axp20x = devm_kzalloc(&i2c->dev, sizeof(*axp20x), GFP_KERNEL);
635 if (!axp20x)
636 return -ENOMEM;
637
Jacob Panaf7e9062014-10-06 21:17:14 -0700638 ret = axp20x_match_device(axp20x, &i2c->dev);
639 if (ret)
640 return ret;
Carlo Caionecfb61a42014-05-01 14:29:27 +0200641
642 axp20x->i2c_client = i2c;
643 axp20x->dev = &i2c->dev;
644 dev_set_drvdata(axp20x->dev, axp20x);
645
Jacob Panaf7e9062014-10-06 21:17:14 -0700646 axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200647 if (IS_ERR(axp20x->regmap)) {
648 ret = PTR_ERR(axp20x->regmap);
649 dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
650 return ret;
651 }
652
653 ret = regmap_add_irq_chip(axp20x->regmap, i2c->irq,
654 IRQF_ONESHOT | IRQF_SHARED, -1,
Jacob Panaf7e9062014-10-06 21:17:14 -0700655 axp20x->regmap_irq_chip,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200656 &axp20x->regmap_irqc);
657 if (ret) {
658 dev_err(&i2c->dev, "failed to add irq chip: %d\n", ret);
659 return ret;
660 }
661
Jacob Panaf7e9062014-10-06 21:17:14 -0700662 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
663 axp20x->nr_cells, NULL, 0, NULL);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200664
665 if (ret) {
666 dev_err(&i2c->dev, "failed to add MFD devices: %d\n", ret);
667 regmap_del_irq_chip(i2c->irq, axp20x->regmap_irqc);
668 return ret;
669 }
670
671 if (!pm_power_off) {
672 axp20x_pm_power_off = axp20x;
673 pm_power_off = axp20x_power_off;
674 }
675
676 dev_info(&i2c->dev, "AXP20X driver loaded\n");
677
678 return 0;
679}
680
681static int axp20x_i2c_remove(struct i2c_client *i2c)
682{
683 struct axp20x_dev *axp20x = i2c_get_clientdata(i2c);
684
685 if (axp20x == axp20x_pm_power_off) {
686 axp20x_pm_power_off = NULL;
687 pm_power_off = NULL;
688 }
689
690 mfd_remove_devices(axp20x->dev);
691 regmap_del_irq_chip(axp20x->i2c_client->irq, axp20x->regmap_irqc);
692
693 return 0;
694}
695
696static struct i2c_driver axp20x_i2c_driver = {
697 .driver = {
698 .name = "axp20x",
Carlo Caionecfb61a42014-05-01 14:29:27 +0200699 .of_match_table = of_match_ptr(axp20x_of_match),
Jacob Panaf7e9062014-10-06 21:17:14 -0700700 .acpi_match_table = ACPI_PTR(axp20x_acpi_match),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200701 },
702 .probe = axp20x_i2c_probe,
703 .remove = axp20x_i2c_remove,
704 .id_table = axp20x_i2c_id,
705};
706
707module_i2c_driver(axp20x_i2c_driver);
708
709MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
710MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
711MODULE_LICENSE("GPL");