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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
Pierre Ossman70f10482007-07-11 20:04:50 +02003 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
Russell Kingc8ebae32011-01-11 19:35:53 +00006 * Copyright (C) 2010 ST-Ericsson SA
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07008#include <linux/module.h>
9#include <linux/moduleparam.h>
10#include <linux/init.h>
11#include <linux/ioport.h>
12#include <linux/device.h>
Ulf Hanssonef289982014-03-17 13:56:32 +010013#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/interrupt.h>
Russell King613b1522011-01-30 21:06:53 +000015#include <linux/kernel.h>
Lee Jones000bc9d2012-04-16 10:18:43 +010016#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/highmem.h>
Nicolas Pitre019a5f52007-10-11 01:06:03 -040020#include <linux/log2.h>
Ludovic Barrec8073e52018-12-06 16:13:31 +010021#include <linux/mmc/mmc.h>
Ulf Hansson70be2082013-01-07 15:35:06 +010022#include <linux/mmc/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <linux/mmc/host.h>
Linus Walleij34177802010-10-19 12:43:58 +010024#include <linux/mmc/card.h>
Ulf Hanssond2762092014-03-17 13:56:19 +010025#include <linux/mmc/slot-gpio.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000026#include <linux/amba/bus.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000027#include <linux/clk.h>
Jens Axboebd6dee62007-10-24 09:01:09 +020028#include <linux/scatterlist.h>
Linus Walleij9ef986a2018-09-20 16:01:10 -070029#include <linux/of.h>
Linus Walleij34e84f32009-09-22 14:41:40 +010030#include <linux/regulator/consumer.h>
Russell Kingc8ebae32011-01-11 19:35:53 +000031#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/amba/mmci.h>
Russell King1c3be362011-08-14 09:17:05 +010034#include <linux/pm_runtime.h>
Viresh Kumar258aea72012-02-01 16:12:19 +053035#include <linux/types.h>
Linus Walleija9a83782012-10-29 14:39:30 +010036#include <linux/pinctrl/consumer.h>
Ludovic Barre15878e52018-10-08 14:08:51 +020037#include <linux/reset.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
Russell King7b09cda2005-07-01 12:02:59 +010039#include <asm/div64.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
42#include "mmci.h"
43
44#define DRIVER_NAME "mmci-pl18x"
45
Ulf Hansson71953e02019-03-06 15:04:56 +010046static void mmci_variant_init(struct mmci_host *host);
Ludovic Barreb3fb9d62019-03-27 10:05:29 +010047static void ux500v2_variant_init(struct mmci_host *host);
Ludovic Barrec3647fd2018-10-08 14:08:33 +020048
Linus Torvalds1da177e2005-04-16 15:20:36 -070049static unsigned int fmax = 515633;
50
Rabin Vincent4956e102010-07-21 12:54:40 +010051static struct variant_data variant_arm = {
Rabin Vincent8301bb62010-08-09 12:57:30 +010052 .fifosize = 16 * 4,
53 .fifohalfsize = 8 * 4,
Ludovic Barre0f244802018-10-08 14:08:45 +020054 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
55 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
56 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
57 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Rabin Vincent08458ef2010-07-21 12:55:59 +010058 .datalength_bits = 16,
Ludovic Barrec931d492018-10-08 14:08:43 +020059 .datactrl_blocksz = 11,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010060 .pwrreg_powerup = MCI_PWR_UP,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +010061 .f_max = 100000000,
Ulf Hansson78782892014-06-13 13:21:38 +020062 .reversed_irq_handling = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +010063 .mmcimask1 = true,
Ludovic Barre59db5e22018-10-08 14:08:47 +020064 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard7f7b5502018-01-18 15:34:18 +010065 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +010066 .opendrain = MCI_ROD,
Ludovic Barrec3647fd2018-10-08 14:08:33 +020067 .init = mmci_variant_init,
Rabin Vincent4956e102010-07-21 12:54:40 +010068};
69
Pawel Moll768fbc12011-03-11 17:18:07 +000070static struct variant_data variant_arm_extended_fifo = {
71 .fifosize = 128 * 4,
72 .fifohalfsize = 64 * 4,
Ludovic Barre0f244802018-10-08 14:08:45 +020073 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
74 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
75 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
76 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Pawel Moll768fbc12011-03-11 17:18:07 +000077 .datalength_bits = 16,
Ludovic Barrec931d492018-10-08 14:08:43 +020078 .datactrl_blocksz = 11,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010079 .pwrreg_powerup = MCI_PWR_UP,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +010080 .f_max = 100000000,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +010081 .mmcimask1 = true,
Ludovic Barre59db5e22018-10-08 14:08:47 +020082 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard7f7b5502018-01-18 15:34:18 +010083 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +010084 .opendrain = MCI_ROD,
Ludovic Barrec3647fd2018-10-08 14:08:33 +020085 .init = mmci_variant_init,
Pawel Moll768fbc12011-03-11 17:18:07 +000086};
87
Pawel Moll3a372982013-01-24 14:12:45 +010088static struct variant_data variant_arm_extended_fifo_hwfc = {
89 .fifosize = 128 * 4,
90 .fifohalfsize = 64 * 4,
91 .clkreg_enable = MCI_ARM_HWFCEN,
Ludovic Barre0f244802018-10-08 14:08:45 +020092 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
93 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
94 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
95 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Pawel Moll3a372982013-01-24 14:12:45 +010096 .datalength_bits = 16,
Ludovic Barrec931d492018-10-08 14:08:43 +020097 .datactrl_blocksz = 11,
Pawel Moll3a372982013-01-24 14:12:45 +010098 .pwrreg_powerup = MCI_PWR_UP,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +010099 .f_max = 100000000,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100100 .mmcimask1 = true,
Ludovic Barre59db5e22018-10-08 14:08:47 +0200101 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100102 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100103 .opendrain = MCI_ROD,
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200104 .init = mmci_variant_init,
Pawel Moll3a372982013-01-24 14:12:45 +0100105};
106
Rabin Vincent4956e102010-07-21 12:54:40 +0100107static struct variant_data variant_u300 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +0100108 .fifosize = 16 * 4,
109 .fifohalfsize = 8 * 4,
Linus Walleij49ac2152011-03-04 14:54:16 +0100110 .clkreg_enable = MCI_ST_U300_HWFCEN,
Srinivas Kandagatlae1412d82014-06-02 10:09:23 +0100111 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Ludovic Barre0f244802018-10-08 14:08:45 +0200112 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
113 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
114 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
115 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Rabin Vincent08458ef2010-07-21 12:55:59 +0100116 .datalength_bits = 16,
Ludovic Barrec931d492018-10-08 14:08:43 +0200117 .datactrl_blocksz = 11,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200118 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100119 .st_sdio = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100120 .pwrreg_powerup = MCI_PWR_ON,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +0100121 .f_max = 100000000,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100122 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100123 .pwrreg_clkgate = true,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100124 .pwrreg_nopower = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100125 .mmcimask1 = true,
Ludovic Barre59db5e22018-10-08 14:08:47 +0200126 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100127 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100128 .opendrain = MCI_OD,
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200129 .init = mmci_variant_init,
Rabin Vincent4956e102010-07-21 12:54:40 +0100130};
131
Linus Walleij34fd4212012-04-10 17:43:59 +0100132static struct variant_data variant_nomadik = {
133 .fifosize = 16 * 4,
134 .fifohalfsize = 8 * 4,
135 .clkreg = MCI_CLK_ENABLE,
Linus Walleijf5abc762016-01-04 02:22:08 +0100136 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Ludovic Barre0f244802018-10-08 14:08:45 +0200137 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
138 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
139 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
140 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Linus Walleij34fd4212012-04-10 17:43:59 +0100141 .datalength_bits = 24,
Ludovic Barrec931d492018-10-08 14:08:43 +0200142 .datactrl_blocksz = 11,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200143 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100144 .st_sdio = true,
Linus Walleij34fd4212012-04-10 17:43:59 +0100145 .st_clkdiv = true,
146 .pwrreg_powerup = MCI_PWR_ON,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +0100147 .f_max = 100000000,
Linus Walleij34fd4212012-04-10 17:43:59 +0100148 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100149 .pwrreg_clkgate = true,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100150 .pwrreg_nopower = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100151 .mmcimask1 = true,
Ludovic Barre59db5e22018-10-08 14:08:47 +0200152 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100153 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100154 .opendrain = MCI_OD,
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200155 .init = mmci_variant_init,
Linus Walleij34fd4212012-04-10 17:43:59 +0100156};
157
Rabin Vincent4956e102010-07-21 12:54:40 +0100158static struct variant_data variant_ux500 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +0100159 .fifosize = 30 * 4,
160 .fifohalfsize = 8 * 4,
Rabin Vincent4956e102010-07-21 12:54:40 +0100161 .clkreg = MCI_CLK_ENABLE,
Linus Walleij49ac2152011-03-04 14:54:16 +0100162 .clkreg_enable = MCI_ST_UX500_HWFCEN,
Srinivas Kandagatlae1412d82014-06-02 10:09:23 +0100163 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Srinivas Kandagatlae8740642014-06-02 10:09:30 +0100164 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
Ludovic Barre0f244802018-10-08 14:08:45 +0200165 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
166 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
167 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
168 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Rabin Vincent08458ef2010-07-21 12:55:59 +0100169 .datalength_bits = 24,
Ludovic Barrec931d492018-10-08 14:08:43 +0200170 .datactrl_blocksz = 11,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200171 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100172 .st_sdio = true,
Linus Walleijb70a67f2010-12-06 09:24:14 +0100173 .st_clkdiv = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100174 .pwrreg_powerup = MCI_PWR_ON,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +0100175 .f_max = 100000000,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100176 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100177 .pwrreg_clkgate = true,
Ulf Hansson01259622013-05-15 20:53:22 +0100178 .busy_detect = true,
Linus Walleij49adc0c2016-10-25 11:06:06 +0200179 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
180 .busy_detect_flag = MCI_ST_CARDBUSY,
181 .busy_detect_mask = MCI_ST_BUSYENDMASK,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100182 .pwrreg_nopower = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100183 .mmcimask1 = true,
Ludovic Barre59db5e22018-10-08 14:08:47 +0200184 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100185 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100186 .opendrain = MCI_OD,
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200187 .init = mmci_variant_init,
Rabin Vincent4956e102010-07-21 12:54:40 +0100188};
Linus Walleijb70a67f2010-12-06 09:24:14 +0100189
Philippe Langlais1784b152011-03-25 08:51:52 +0100190static struct variant_data variant_ux500v2 = {
191 .fifosize = 30 * 4,
192 .fifohalfsize = 8 * 4,
193 .clkreg = MCI_CLK_ENABLE,
194 .clkreg_enable = MCI_ST_UX500_HWFCEN,
Srinivas Kandagatlae1412d82014-06-02 10:09:23 +0100195 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Srinivas Kandagatlae8740642014-06-02 10:09:30 +0100196 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
Ludovic Barre0f244802018-10-08 14:08:45 +0200197 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
198 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
199 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
200 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200201 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
Philippe Langlais1784b152011-03-25 08:51:52 +0100202 .datalength_bits = 24,
Ludovic Barrec931d492018-10-08 14:08:43 +0200203 .datactrl_blocksz = 11,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200204 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100205 .st_sdio = true,
Philippe Langlais1784b152011-03-25 08:51:52 +0100206 .st_clkdiv = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100207 .pwrreg_powerup = MCI_PWR_ON,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +0100208 .f_max = 100000000,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100209 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100210 .pwrreg_clkgate = true,
Ulf Hansson01259622013-05-15 20:53:22 +0100211 .busy_detect = true,
Linus Walleij49adc0c2016-10-25 11:06:06 +0200212 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
213 .busy_detect_flag = MCI_ST_CARDBUSY,
214 .busy_detect_mask = MCI_ST_BUSYENDMASK,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100215 .pwrreg_nopower = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100216 .mmcimask1 = true,
Ludovic Barre59db5e22018-10-08 14:08:47 +0200217 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100218 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100219 .opendrain = MCI_OD,
Ludovic Barreb3fb9d62019-03-27 10:05:29 +0100220 .init = ux500v2_variant_init,
Philippe Langlais1784b152011-03-25 08:51:52 +0100221};
222
Patrice Chotard2a9d6c82018-01-18 15:34:21 +0100223static struct variant_data variant_stm32 = {
224 .fifosize = 32 * 4,
225 .fifohalfsize = 8 * 4,
226 .clkreg = MCI_CLK_ENABLE,
227 .clkreg_enable = MCI_ST_UX500_HWFCEN,
228 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
229 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
Ludovic Barre0f244802018-10-08 14:08:45 +0200230 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
231 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
232 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
233 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Ludovic Barre59db5e22018-10-08 14:08:47 +0200234 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard2a9d6c82018-01-18 15:34:21 +0100235 .datalength_bits = 24,
Ludovic Barrec931d492018-10-08 14:08:43 +0200236 .datactrl_blocksz = 11,
Patrice Chotard2a9d6c82018-01-18 15:34:21 +0100237 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
238 .st_sdio = true,
239 .st_clkdiv = true,
240 .pwrreg_powerup = MCI_PWR_ON,
241 .f_max = 48000000,
242 .pwrreg_clkgate = true,
243 .pwrreg_nopower = true,
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200244 .init = mmci_variant_init,
Patrice Chotard2a9d6c82018-01-18 15:34:21 +0100245};
246
Ludovic Barre46b723d2018-10-08 14:08:55 +0200247static struct variant_data variant_stm32_sdmmc = {
248 .fifosize = 16 * 4,
249 .fifohalfsize = 8 * 4,
250 .f_max = 208000000,
251 .stm32_clkdiv = true,
252 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
253 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
254 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
255 .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
Ludovic Barrec8073e52018-12-06 16:13:31 +0100256 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP,
Ludovic Barre46b723d2018-10-08 14:08:55 +0200257 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
258 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
259 .datactrl_first = true,
260 .datacnt_useless = true,
261 .datalength_bits = 25,
262 .datactrl_blocksz = 14,
263 .stm32_idmabsize_mask = GENMASK(12, 5),
264 .init = sdmmc_variant_init,
265};
266
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +0100267static struct variant_data variant_qcom = {
268 .fifosize = 16 * 4,
269 .fifohalfsize = 8 * 4,
270 .clkreg = MCI_CLK_ENABLE,
271 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
272 MCI_QCOM_CLK_SELECT_IN_FBCLK,
273 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
274 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
Ludovic Barre0f244802018-10-08 14:08:45 +0200275 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
276 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
277 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
278 .cmdreg_srsp = MCI_CPSM_RESPONSE,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200279 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +0100280 .datalength_bits = 24,
Ludovic Barrec931d492018-10-08 14:08:43 +0200281 .datactrl_blocksz = 11,
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +0100282 .pwrreg_powerup = MCI_PWR_UP,
283 .f_max = 208000000,
284 .explicit_mclk_control = true,
285 .qcom_fifo = true,
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100286 .qcom_dml = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100287 .mmcimask1 = true,
Ludovic Barre59db5e22018-10-08 14:08:47 +0200288 .irq_pio_mask = MCI_IRQ_PIO_MASK,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100289 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100290 .opendrain = MCI_ROD,
Ulf Hansson29aba072018-07-16 13:08:18 +0200291 .init = qcom_variant_init,
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +0100292};
293
Linus Walleij49adc0c2016-10-25 11:06:06 +0200294/* Busy detection for the ST Micro variant */
Ulf Hansson01259622013-05-15 20:53:22 +0100295static int mmci_card_busy(struct mmc_host *mmc)
296{
297 struct mmci_host *host = mmc_priv(mmc);
298 unsigned long flags;
299 int busy = 0;
300
Ulf Hansson01259622013-05-15 20:53:22 +0100301 spin_lock_irqsave(&host->lock, flags);
Linus Walleij49adc0c2016-10-25 11:06:06 +0200302 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
Ulf Hansson01259622013-05-15 20:53:22 +0100303 busy = 1;
304 spin_unlock_irqrestore(&host->lock, flags);
305
Ulf Hansson01259622013-05-15 20:53:22 +0100306 return busy;
307}
308
Ulf Hanssonf829c042013-09-04 09:01:15 +0100309static void mmci_reg_delay(struct mmci_host *host)
310{
311 /*
312 * According to the spec, at least three feedback clock cycles
313 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
314 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
315 * Worst delay time during card init is at 100 kHz => 30 us.
316 * Worst delay time when up and running is at 25 MHz => 120 ns.
317 */
318 if (host->cclk < 25000000)
319 udelay(30);
320 else
321 ndelay(120);
322}
323
Ulf Hansson653a7612013-01-21 21:29:34 +0100324/*
Linus Walleija6a64642009-09-14 12:56:14 +0100325 * This must be called with host->lock held
326 */
Ludovic Barrecd3ee8c2018-10-08 14:08:42 +0200327void mmci_write_clkreg(struct mmci_host *host, u32 clk)
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100328{
329 if (host->clk_reg != clk) {
330 host->clk_reg = clk;
331 writel(clk, host->base + MMCICLOCK);
332 }
333}
334
335/*
336 * This must be called with host->lock held
337 */
Ludovic Barrecd3ee8c2018-10-08 14:08:42 +0200338void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100339{
340 if (host->pwr_reg != pwr) {
341 host->pwr_reg = pwr;
342 writel(pwr, host->base + MMCIPOWER);
343 }
344}
345
346/*
347 * This must be called with host->lock held
348 */
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100349static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
350{
Linus Walleij49adc0c2016-10-25 11:06:06 +0200351 /* Keep busy mode in DPSM if enabled */
352 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
Ulf Hansson01259622013-05-15 20:53:22 +0100353
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100354 if (host->datactrl_reg != datactrl) {
355 host->datactrl_reg = datactrl;
356 writel(datactrl, host->base + MMCIDATACTRL);
357 }
358}
359
360/*
361 * This must be called with host->lock held
362 */
Linus Walleija6a64642009-09-14 12:56:14 +0100363static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
364{
Rabin Vincent4956e102010-07-21 12:54:40 +0100365 struct variant_data *variant = host->variant;
366 u32 clk = variant->clkreg;
Linus Walleija6a64642009-09-14 12:56:14 +0100367
Ulf Hanssonc58a8502013-05-13 15:40:03 +0100368 /* Make sure cclk reflects the current calculated clock */
369 host->cclk = 0;
370
Linus Walleija6a64642009-09-14 12:56:14 +0100371 if (desired) {
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +0100372 if (variant->explicit_mclk_control) {
373 host->cclk = host->mclk;
374 } else if (desired >= host->mclk) {
Linus Walleij991a86e2010-12-10 09:35:53 +0100375 clk = MCI_CLK_BYPASS;
Linus Walleij399bc482011-04-01 07:59:17 +0100376 if (variant->st_clkdiv)
377 clk |= MCI_ST_UX500_NEG_EDGE;
Linus Walleija6a64642009-09-14 12:56:14 +0100378 host->cclk = host->mclk;
Linus Walleijb70a67f2010-12-06 09:24:14 +0100379 } else if (variant->st_clkdiv) {
380 /*
381 * DB8500 TRM says f = mclk / (clkdiv + 2)
382 * => clkdiv = (mclk / f) - 2
383 * Round the divider up so we don't exceed the max
384 * frequency
385 */
386 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
387 if (clk >= 256)
388 clk = 255;
389 host->cclk = host->mclk / (clk + 2);
Linus Walleija6a64642009-09-14 12:56:14 +0100390 } else {
Linus Walleijb70a67f2010-12-06 09:24:14 +0100391 /*
392 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
393 * => clkdiv = mclk / (2 * f) - 1
394 */
Linus Walleija6a64642009-09-14 12:56:14 +0100395 clk = host->mclk / (2 * desired) - 1;
396 if (clk >= 256)
397 clk = 255;
398 host->cclk = host->mclk / (2 * (clk + 1));
399 }
Rabin Vincent4380c142010-07-21 12:55:18 +0100400
401 clk |= variant->clkreg_enable;
Linus Walleija6a64642009-09-14 12:56:14 +0100402 clk |= MCI_CLK_ENABLE;
403 /* This hasn't proven to be worthwhile */
404 /* clk |= MCI_CLK_PWRSAVE; */
405 }
406
Ulf Hanssonc58a8502013-05-13 15:40:03 +0100407 /* Set actual clock for debug */
408 host->mmc->actual_clock = host->cclk;
409
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100410 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
Linus Walleij771dc152010-04-08 07:38:52 +0100411 clk |= MCI_4BIT_BUS;
412 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
Srinivas Kandagatlae1412d82014-06-02 10:09:23 +0100413 clk |= variant->clkreg_8bit_bus_enable;
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100414
Seungwon Jeon6dad6c92014-03-14 21:12:13 +0900415 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
416 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
Srinivas Kandagatlae8740642014-06-02 10:09:30 +0100417 clk |= variant->clkreg_neg_edge_enable;
Ulf Hansson6dbb6ee2013-01-07 15:30:44 +0100418
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100419 mmci_write_clkreg(host, clk);
Linus Walleija6a64642009-09-14 12:56:14 +0100420}
421
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200422void mmci_dma_release(struct mmci_host *host)
423{
424 if (host->ops && host->ops->dma_release)
425 host->ops->dma_release(host);
426
427 host->use_dma = false;
428}
429
430void mmci_dma_setup(struct mmci_host *host)
431{
432 if (!host->ops || !host->ops->dma_setup)
433 return;
434
435 if (host->ops->dma_setup(host))
436 return;
437
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200438 /* initialize pre request cookie */
439 host->next_cookie = 1;
440
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200441 host->use_dma = true;
442}
443
Ludovic Barree0da1722018-10-08 14:08:41 +0200444/*
445 * Validate mmc prerequisites
446 */
447static int mmci_validate_data(struct mmci_host *host,
448 struct mmc_data *data)
449{
450 if (!data)
451 return 0;
452
453 if (!is_power_of_2(data->blksz)) {
454 dev_err(mmc_dev(host->mmc),
455 "unsupported block size (%d bytes)\n", data->blksz);
456 return -EINVAL;
457 }
458
459 if (host->ops && host->ops->validate_data)
460 return host->ops->validate_data(host, data);
461
462 return 0;
463}
464
Ludovic Barre47983512018-10-08 14:08:36 +0200465int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
466{
467 int err;
468
469 if (!host->ops || !host->ops->prep_data)
470 return 0;
471
472 err = host->ops->prep_data(host, data, next);
473
474 if (next && !err)
475 data->host_cookie = ++host->next_cookie < 0 ?
476 1 : host->next_cookie;
477
478 return err;
479}
480
481void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
482 int err)
483{
484 if (host->ops && host->ops->unprep_data)
485 host->ops->unprep_data(host, data, err);
486
487 data->host_cookie = 0;
488}
489
Ludovic Barre02769962018-10-08 14:08:37 +0200490void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
491{
492 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
493
494 if (host->ops && host->ops->get_next_data)
495 host->ops->get_next_data(host, data);
496}
497
Ludovic Barre135ea302018-10-08 14:08:38 +0200498int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
499{
500 struct mmc_data *data = host->data;
501 int ret;
502
503 if (!host->use_dma)
504 return -EINVAL;
505
506 ret = mmci_prep_data(host, data, false);
507 if (ret)
508 return ret;
509
510 if (!host->ops || !host->ops->dma_start)
511 return -EINVAL;
512
513 /* Okay, go for it. */
514 dev_vdbg(mmc_dev(host->mmc),
515 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
516 data->sg_len, data->blksz, data->blocks, data->flags);
517
518 host->ops->dma_start(host, &datactrl);
519
520 /* Trigger the DMA transfer */
521 mmci_write_datactrlreg(host, datactrl);
522
523 /*
524 * Let the MMCI say when the data is ended and it's time
525 * to fire next DMA request. When that happens, MMCI will
526 * call mmci_data_end()
527 */
528 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
529 host->base + MMCIMASK0);
530 return 0;
531}
532
Ludovic Barre5a9f10c2018-10-08 14:08:39 +0200533void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
534{
535 if (!host->use_dma)
536 return;
537
538 if (host->ops && host->ops->dma_finalize)
539 host->ops->dma_finalize(host, data);
540}
541
Ludovic Barrecfccc6a2018-10-08 14:08:40 +0200542void mmci_dma_error(struct mmci_host *host)
543{
544 if (!host->use_dma)
545 return;
546
547 if (host->ops && host->ops->dma_error)
548 host->ops->dma_error(host);
549}
550
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551static void
552mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
553{
554 writel(0, host->base + MMCICOMMAND);
555
Russell Kinge47c2222007-01-08 16:42:51 +0000556 BUG_ON(host->data);
557
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 host->mrq = NULL;
559 host->cmd = NULL;
560
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561 mmc_request_done(host->mmc, mrq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562}
563
Linus Walleij2686b4b2010-10-19 12:39:48 +0100564static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
565{
566 void __iomem *base = host->base;
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100567 struct variant_data *variant = host->variant;
Linus Walleij2686b4b2010-10-19 12:39:48 +0100568
569 if (host->singleirq) {
570 unsigned int mask0 = readl(base + MMCIMASK0);
571
Ludovic Barre59db5e22018-10-08 14:08:47 +0200572 mask0 &= ~variant->irq_pio_mask;
Linus Walleij2686b4b2010-10-19 12:39:48 +0100573 mask0 |= mask;
574
575 writel(mask0, base + MMCIMASK0);
576 }
577
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100578 if (variant->mmcimask1)
579 writel(mask, base + MMCIMASK1);
580
581 host->mask1_reg = mask;
Linus Walleij2686b4b2010-10-19 12:39:48 +0100582}
583
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584static void mmci_stop_data(struct mmci_host *host)
585{
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100586 mmci_write_datactrlreg(host, 0);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100587 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 host->data = NULL;
589}
590
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100591static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
592{
593 unsigned int flags = SG_MITER_ATOMIC;
594
595 if (data->flags & MMC_DATA_READ)
596 flags |= SG_MITER_TO_SG;
597 else
598 flags |= SG_MITER_FROM_SG;
599
600 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
601}
602
Ludovic Barreb3fb9d62019-03-27 10:05:29 +0100603static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
604{
605 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
606}
607
608static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
609{
610 return MCI_DPSM_ENABLE | (host->data->blksz << 16);
611}
612
Russell Kingc8ebae32011-01-11 19:35:53 +0000613/*
614 * All the DMA operation mode stuff goes inside this ifdef.
615 * This assumes that you have a generic DMA device interface,
616 * no custom DMA interfaces are supported.
617 */
618#ifdef CONFIG_DMA_ENGINE
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200619struct mmci_dmae_next {
620 struct dma_async_tx_descriptor *desc;
621 struct dma_chan *chan;
622};
623
624struct mmci_dmae_priv {
625 struct dma_chan *cur;
626 struct dma_chan *rx_channel;
627 struct dma_chan *tx_channel;
628 struct dma_async_tx_descriptor *desc_current;
629 struct mmci_dmae_next next_data;
630};
631
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200632int mmci_dmae_setup(struct mmci_host *host)
Russell Kingc8ebae32011-01-11 19:35:53 +0000633{
Russell Kingc8ebae32011-01-11 19:35:53 +0000634 const char *rxname, *txname;
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200635 struct mmci_dmae_priv *dmae;
Russell Kingc8ebae32011-01-11 19:35:53 +0000636
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200637 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
638 if (!dmae)
639 return -ENOMEM;
Russell Kingc8ebae32011-01-11 19:35:53 +0000640
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200641 host->dma_priv = dmae;
642
643 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
644 "rx");
645 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
646 "tx");
Per Forlin58c7ccb2011-07-01 18:55:24 +0200647
Russell Kingc8ebae32011-01-11 19:35:53 +0000648 /*
649 * If only an RX channel is specified, the driver will
650 * attempt to use it bidirectionally, however if it is
651 * is specified but cannot be located, DMA will be disabled.
652 */
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200653 if (dmae->rx_channel && !dmae->tx_channel)
654 dmae->tx_channel = dmae->rx_channel;
Russell Kingc8ebae32011-01-11 19:35:53 +0000655
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200656 if (dmae->rx_channel)
657 rxname = dma_chan_name(dmae->rx_channel);
Russell Kingc8ebae32011-01-11 19:35:53 +0000658 else
659 rxname = "none";
660
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200661 if (dmae->tx_channel)
662 txname = dma_chan_name(dmae->tx_channel);
Russell Kingc8ebae32011-01-11 19:35:53 +0000663 else
664 txname = "none";
665
666 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
667 rxname, txname);
668
669 /*
670 * Limit the maximum segment size in any SG entry according to
671 * the parameters of the DMA engine device.
672 */
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200673 if (dmae->tx_channel) {
674 struct device *dev = dmae->tx_channel->device->dev;
Russell Kingc8ebae32011-01-11 19:35:53 +0000675 unsigned int max_seg_size = dma_get_max_seg_size(dev);
676
677 if (max_seg_size < host->mmc->max_seg_size)
678 host->mmc->max_seg_size = max_seg_size;
679 }
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200680 if (dmae->rx_channel) {
681 struct device *dev = dmae->rx_channel->device->dev;
Russell Kingc8ebae32011-01-11 19:35:53 +0000682 unsigned int max_seg_size = dma_get_max_seg_size(dev);
683
684 if (max_seg_size < host->mmc->max_seg_size)
685 host->mmc->max_seg_size = max_seg_size;
686 }
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100687
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200688 if (!dmae->tx_channel || !dmae->rx_channel) {
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200689 mmci_dmae_release(host);
690 return -EINVAL;
691 }
692
693 return 0;
Russell Kingc8ebae32011-01-11 19:35:53 +0000694}
695
696/*
Bill Pemberton6e0ee712012-11-19 13:26:03 -0500697 * This is used in or so inline it
Russell Kingc8ebae32011-01-11 19:35:53 +0000698 * so it can be discarded.
699 */
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200700void mmci_dmae_release(struct mmci_host *host)
Russell Kingc8ebae32011-01-11 19:35:53 +0000701{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200702 struct mmci_dmae_priv *dmae = host->dma_priv;
703
704 if (dmae->rx_channel)
705 dma_release_channel(dmae->rx_channel);
706 if (dmae->tx_channel)
707 dma_release_channel(dmae->tx_channel);
708 dmae->rx_channel = dmae->tx_channel = NULL;
Russell Kingc8ebae32011-01-11 19:35:53 +0000709}
710
711static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
712{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200713 struct mmci_dmae_priv *dmae = host->dma_priv;
Ulf Hansson653a7612013-01-21 21:29:34 +0100714 struct dma_chan *chan;
Ulf Hansson653a7612013-01-21 21:29:34 +0100715
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200716 if (data->flags & MMC_DATA_READ)
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200717 chan = dmae->rx_channel;
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200718 else
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200719 chan = dmae->tx_channel;
Ulf Hansson653a7612013-01-21 21:29:34 +0100720
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200721 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
722 mmc_get_dma_dir(data));
Ulf Hansson653a7612013-01-21 21:29:34 +0100723}
724
Ludovic Barrecfccc6a2018-10-08 14:08:40 +0200725void mmci_dmae_error(struct mmci_host *host)
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200726{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200727 struct mmci_dmae_priv *dmae = host->dma_priv;
728
Ludovic Barrecfccc6a2018-10-08 14:08:40 +0200729 if (!dma_inprogress(host))
Ludovic Barrecdea1942018-09-21 11:45:56 +0200730 return;
731
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200732 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200733 dmaengine_terminate_all(dmae->cur);
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200734 host->dma_in_progress = false;
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200735 dmae->cur = NULL;
736 dmae->desc_current = NULL;
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200737 host->data->host_cookie = 0;
738
739 mmci_dma_unmap(host, host->data);
740}
741
Ludovic Barre5a9f10c2018-10-08 14:08:39 +0200742void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
Ulf Hansson653a7612013-01-21 21:29:34 +0100743{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200744 struct mmci_dmae_priv *dmae = host->dma_priv;
Russell Kingc8ebae32011-01-11 19:35:53 +0000745 u32 status;
746 int i;
747
Ludovic Barre5a9f10c2018-10-08 14:08:39 +0200748 if (!dma_inprogress(host))
Ludovic Barrecdea1942018-09-21 11:45:56 +0200749 return;
750
Russell Kingc8ebae32011-01-11 19:35:53 +0000751 /* Wait up to 1ms for the DMA to complete */
752 for (i = 0; ; i++) {
753 status = readl(host->base + MMCISTATUS);
754 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
755 break;
756 udelay(10);
757 }
758
759 /*
760 * Check to see whether we still have some data left in the FIFO -
761 * this catches DMA controllers which are unable to monitor the
762 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
763 * contiguous buffers. On TX, we'll get a FIFO underrun error.
764 */
765 if (status & MCI_RXDATAAVLBLMASK) {
Ludovic Barrecfccc6a2018-10-08 14:08:40 +0200766 mmci_dma_error(host);
Russell Kingc8ebae32011-01-11 19:35:53 +0000767 if (!data->error)
768 data->error = -EIO;
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200769 } else if (!data->host_cookie) {
Ulf Hansson653a7612013-01-21 21:29:34 +0100770 mmci_dma_unmap(host, data);
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200771 }
Russell Kingc8ebae32011-01-11 19:35:53 +0000772
773 /*
774 * Use of DMA with scatter-gather is impossible.
775 * Give up with DMA and switch back to PIO mode.
776 */
777 if (status & MCI_RXDATAAVLBLMASK) {
778 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
779 mmci_dma_release(host);
780 }
Ulf Hansson653a7612013-01-21 21:29:34 +0100781
Linus Walleije13934b2017-01-27 15:04:54 +0100782 host->dma_in_progress = false;
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200783 dmae->cur = NULL;
784 dmae->desc_current = NULL;
Russell Kingc8ebae32011-01-11 19:35:53 +0000785}
786
Ulf Hansson653a7612013-01-21 21:29:34 +0100787/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
Ludovic Barre47983512018-10-08 14:08:36 +0200788static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
Ulf Hansson653a7612013-01-21 21:29:34 +0100789 struct dma_chan **dma_chan,
790 struct dma_async_tx_descriptor **dma_desc)
Russell Kingc8ebae32011-01-11 19:35:53 +0000791{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200792 struct mmci_dmae_priv *dmae = host->dma_priv;
Russell Kingc8ebae32011-01-11 19:35:53 +0000793 struct variant_data *variant = host->variant;
794 struct dma_slave_config conf = {
795 .src_addr = host->phybase + MMCIFIFO,
796 .dst_addr = host->phybase + MMCIFIFO,
797 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
798 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
799 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
800 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
Viresh Kumar258aea72012-02-01 16:12:19 +0530801 .device_fc = false,
Russell Kingc8ebae32011-01-11 19:35:53 +0000802 };
Russell Kingc8ebae32011-01-11 19:35:53 +0000803 struct dma_chan *chan;
804 struct dma_device *device;
805 struct dma_async_tx_descriptor *desc;
806 int nr_sg;
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100807 unsigned long flags = DMA_CTRL_ACK;
Russell Kingc8ebae32011-01-11 19:35:53 +0000808
Russell Kingc8ebae32011-01-11 19:35:53 +0000809 if (data->flags & MMC_DATA_READ) {
Vinod Koul05f57992011-10-14 10:45:11 +0530810 conf.direction = DMA_DEV_TO_MEM;
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200811 chan = dmae->rx_channel;
Russell Kingc8ebae32011-01-11 19:35:53 +0000812 } else {
Vinod Koul05f57992011-10-14 10:45:11 +0530813 conf.direction = DMA_MEM_TO_DEV;
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200814 chan = dmae->tx_channel;
Russell Kingc8ebae32011-01-11 19:35:53 +0000815 }
816
817 /* If there's no DMA channel, fall back to PIO */
818 if (!chan)
819 return -EINVAL;
820
821 /* If less than or equal to the fifo size, don't bother with DMA */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200822 if (data->blksz * data->blocks <= variant->fifosize)
Russell Kingc8ebae32011-01-11 19:35:53 +0000823 return -EINVAL;
824
825 device = chan->device;
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200826 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
827 mmc_get_dma_dir(data));
Russell Kingc8ebae32011-01-11 19:35:53 +0000828 if (nr_sg == 0)
829 return -EINVAL;
830
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100831 if (host->variant->qcom_dml)
832 flags |= DMA_PREP_INTERRUPT;
833
Russell Kingc8ebae32011-01-11 19:35:53 +0000834 dmaengine_slave_config(chan, &conf);
Alexandre Bounine16052822012-03-08 16:11:18 -0500835 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100836 conf.direction, flags);
Russell Kingc8ebae32011-01-11 19:35:53 +0000837 if (!desc)
838 goto unmap_exit;
839
Ulf Hansson653a7612013-01-21 21:29:34 +0100840 *dma_chan = chan;
841 *dma_desc = desc;
Russell Kingc8ebae32011-01-11 19:35:53 +0000842
Per Forlin58c7ccb2011-07-01 18:55:24 +0200843 return 0;
844
845 unmap_exit:
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200846 dma_unmap_sg(device->dev, data->sg, data->sg_len,
847 mmc_get_dma_dir(data));
Per Forlin58c7ccb2011-07-01 18:55:24 +0200848 return -ENOMEM;
849}
850
Ludovic Barre47983512018-10-08 14:08:36 +0200851int mmci_dmae_prep_data(struct mmci_host *host,
852 struct mmc_data *data,
853 bool next)
Ulf Hansson653a7612013-01-21 21:29:34 +0100854{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200855 struct mmci_dmae_priv *dmae = host->dma_priv;
Ludovic Barread7b8912018-10-08 14:08:35 +0200856 struct mmci_dmae_next *nd = &dmae->next_data;
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200857
Ludovic Barre47983512018-10-08 14:08:36 +0200858 if (!host->use_dma)
859 return -EINVAL;
860
Ludovic Barread7b8912018-10-08 14:08:35 +0200861 if (next)
Ludovic Barre47983512018-10-08 14:08:36 +0200862 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
Ulf Hansson653a7612013-01-21 21:29:34 +0100863 /* Check if next job is already prepared. */
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200864 if (dmae->cur && dmae->desc_current)
Ulf Hansson653a7612013-01-21 21:29:34 +0100865 return 0;
866
867 /* No job were prepared thus do it now. */
Ludovic Barre47983512018-10-08 14:08:36 +0200868 return _mmci_dmae_prep_data(host, data, &dmae->cur,
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200869 &dmae->desc_current);
Ulf Hansson653a7612013-01-21 21:29:34 +0100870}
871
Ludovic Barre135ea302018-10-08 14:08:38 +0200872int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
Per Forlin58c7ccb2011-07-01 18:55:24 +0200873{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200874 struct mmci_dmae_priv *dmae = host->dma_priv;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200875
Linus Walleije13934b2017-01-27 15:04:54 +0100876 host->dma_in_progress = true;
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200877 dmaengine_submit(dmae->desc_current);
878 dma_async_issue_pending(dmae->cur);
Russell Kingc8ebae32011-01-11 19:35:53 +0000879
Ludovic Barre135ea302018-10-08 14:08:38 +0200880 *datactrl |= MCI_DPSM_DMAENABLE;
Russell Kingc8ebae32011-01-11 19:35:53 +0000881
Russell Kingc8ebae32011-01-11 19:35:53 +0000882 return 0;
Russell Kingc8ebae32011-01-11 19:35:53 +0000883}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200884
Ludovic Barre02769962018-10-08 14:08:37 +0200885void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
Per Forlin58c7ccb2011-07-01 18:55:24 +0200886{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200887 struct mmci_dmae_priv *dmae = host->dma_priv;
888 struct mmci_dmae_next *next = &dmae->next_data;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200889
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200890 if (!host->use_dma)
891 return;
892
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200893 WARN_ON(!data->host_cookie && (next->desc || next->chan));
Per Forlin58c7ccb2011-07-01 18:55:24 +0200894
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200895 dmae->desc_current = next->desc;
896 dmae->cur = next->chan;
897 next->desc = NULL;
898 next->chan = NULL;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200899}
900
Ludovic Barre47983512018-10-08 14:08:36 +0200901void mmci_dmae_unprep_data(struct mmci_host *host,
902 struct mmc_data *data, int err)
903
Per Forlin58c7ccb2011-07-01 18:55:24 +0200904{
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200905 struct mmci_dmae_priv *dmae = host->dma_priv;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200906
Ludovic Barre47983512018-10-08 14:08:36 +0200907 if (!host->use_dma)
Per Forlin58c7ccb2011-07-01 18:55:24 +0200908 return;
909
Ulf Hansson653a7612013-01-21 21:29:34 +0100910 mmci_dma_unmap(host, data);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200911
Ulf Hansson653a7612013-01-21 21:29:34 +0100912 if (err) {
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200913 struct mmci_dmae_next *next = &dmae->next_data;
Ulf Hansson653a7612013-01-21 21:29:34 +0100914 struct dma_chan *chan;
915 if (data->flags & MMC_DATA_READ)
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200916 chan = dmae->rx_channel;
Ulf Hansson653a7612013-01-21 21:29:34 +0100917 else
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200918 chan = dmae->tx_channel;
Ulf Hansson653a7612013-01-21 21:29:34 +0100919 dmaengine_terminate_all(chan);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200920
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200921 if (dmae->desc_current == next->desc)
922 dmae->desc_current = NULL;
Srinivas Kandagatlab5c16a62014-10-08 12:25:17 +0100923
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200924 if (dmae->cur == next->chan) {
Linus Walleije13934b2017-01-27 15:04:54 +0100925 host->dma_in_progress = false;
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200926 dmae->cur = NULL;
Linus Walleije13934b2017-01-27 15:04:54 +0100927 }
Srinivas Kandagatlab5c16a62014-10-08 12:25:17 +0100928
Ludovic Barrea813f2a2018-10-08 14:08:34 +0200929 next->desc = NULL;
930 next->chan = NULL;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200931 }
932}
933
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200934static struct mmci_host_ops mmci_variant_ops = {
Ludovic Barre47983512018-10-08 14:08:36 +0200935 .prep_data = mmci_dmae_prep_data,
936 .unprep_data = mmci_dmae_unprep_data,
Ludovic Barreb3fb9d62019-03-27 10:05:29 +0100937 .get_datactrl_cfg = mmci_get_dctrl_cfg,
Ludovic Barre02769962018-10-08 14:08:37 +0200938 .get_next_data = mmci_dmae_get_next_data,
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200939 .dma_setup = mmci_dmae_setup,
940 .dma_release = mmci_dmae_release,
Ludovic Barre135ea302018-10-08 14:08:38 +0200941 .dma_start = mmci_dmae_start,
Ludovic Barre5a9f10c2018-10-08 14:08:39 +0200942 .dma_finalize = mmci_dmae_finalize,
Ludovic Barrecfccc6a2018-10-08 14:08:40 +0200943 .dma_error = mmci_dmae_error,
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200944};
Ludovic Barreb3fb9d62019-03-27 10:05:29 +0100945#else
946static struct mmci_host_ops mmci_variant_ops = {
947 .get_datactrl_cfg = mmci_get_dctrl_cfg,
948};
949#endif
Ludovic Barrec3647fd2018-10-08 14:08:33 +0200950
951void mmci_variant_init(struct mmci_host *host)
952{
953 host->ops = &mmci_variant_ops;
954}
Ludovic Barreb3fb9d62019-03-27 10:05:29 +0100955
956void ux500v2_variant_init(struct mmci_host *host)
957{
958 host->ops = &mmci_variant_ops;
959 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
960}
Russell Kingc8ebae32011-01-11 19:35:53 +0000961
Ludovic Barre47983512018-10-08 14:08:36 +0200962static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
963{
964 struct mmci_host *host = mmc_priv(mmc);
965 struct mmc_data *data = mrq->data;
966
967 if (!data)
968 return;
969
970 WARN_ON(data->host_cookie);
971
972 if (mmci_validate_data(host, data))
973 return;
974
975 mmci_prep_data(host, data, true);
976}
977
978static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
979 int err)
980{
981 struct mmci_host *host = mmc_priv(mmc);
982 struct mmc_data *data = mrq->data;
983
984 if (!data || !data->host_cookie)
985 return;
986
987 mmci_unprep_data(host, data, err);
988}
989
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
991{
Rabin Vincent8301bb62010-08-09 12:57:30 +0100992 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 unsigned int datactrl, timeout, irqmask;
Russell King7b09cda2005-07-01 12:02:59 +0100994 unsigned long long clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995 void __iomem *base;
996
Linus Walleij64de0282010-02-19 01:09:10 +0100997 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
998 data->blksz, data->blocks, data->flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999
1000 host->data = data;
Rabin Vincent528320d2010-07-21 12:49:49 +01001001 host->size = data->blksz * data->blocks;
Russell King51d43752011-01-27 10:56:52 +00001002 data->bytes_xfered = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003
Russell King7b09cda2005-07-01 12:02:59 +01001004 clks = (unsigned long long)data->timeout_ns * host->cclk;
Srinivas Kandagatlac4a35762014-06-02 10:08:39 +01001005 do_div(clks, NSEC_PER_SEC);
Russell King7b09cda2005-07-01 12:02:59 +01001006
1007 timeout = data->timeout_clks + (unsigned int)clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008
1009 base = host->base;
1010 writel(timeout, base + MMCIDATATIMER);
1011 writel(host->size, base + MMCIDATALENGTH);
1012
Ludovic Barre41ed65e2019-03-27 10:05:32 +01001013 datactrl = host->ops->get_datactrl_cfg(host);
1014 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
Russell Kingc8ebae32011-01-11 19:35:53 +00001015
Srinivas Kandagatlac7354132014-08-22 05:55:16 +01001016 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
1017 u32 clk;
Ulf Hansson7258db72011-12-13 17:05:28 +01001018
Srinivas Kandagatlac7354132014-08-22 05:55:16 +01001019 datactrl |= variant->datactrl_mask_sdio;
Ulf Hansson06c1a122012-10-12 14:01:50 +01001020
Srinivas Kandagatlac7354132014-08-22 05:55:16 +01001021 /*
1022 * The ST Micro variant for SDIO small write transfers
1023 * needs to have clock H/W flow control disabled,
1024 * otherwise the transfer will not start. The threshold
1025 * depends on the rate of MCLK.
1026 */
1027 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
1028 (host->size < 8 ||
1029 (host->size <= 8 && host->mclk > 50000000)))
1030 clk = host->clk_reg & ~variant->clkreg_enable;
1031 else
1032 clk = host->clk_reg | variant->clkreg_enable;
1033
1034 mmci_write_clkreg(host, clk);
1035 }
Ulf Hansson06c1a122012-10-12 14:01:50 +01001036
Seungwon Jeon6dad6c92014-03-14 21:12:13 +09001037 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
1038 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
Srinivas Kandagatlae17dca22014-06-02 10:09:15 +01001039 datactrl |= variant->datactrl_mask_ddrmode;
Ulf Hansson6dbb6ee2013-01-07 15:30:44 +01001040
Russell Kingc8ebae32011-01-11 19:35:53 +00001041 /*
1042 * Attempt to use DMA operation mode, if this
1043 * should fail, fall back to PIO mode
1044 */
Ludovic Barre135ea302018-10-08 14:08:38 +02001045 if (!mmci_dma_start(host, datactrl))
Russell Kingc8ebae32011-01-11 19:35:53 +00001046 return;
1047
1048 /* IRQ mode, map the SG list for CPU reading/writing */
1049 mmci_init_sg(host, data);
1050
1051 if (data->flags & MMC_DATA_READ) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 irqmask = MCI_RXFIFOHALFFULLMASK;
Russell King0425a142006-02-16 16:48:31 +00001053
1054 /*
Russell Kingc4d877c2011-01-27 09:50:13 +00001055 * If we have less than the fifo 'half-full' threshold to
1056 * transfer, trigger a PIO interrupt as soon as any data
1057 * is available.
Russell King0425a142006-02-16 16:48:31 +00001058 */
Russell Kingc4d877c2011-01-27 09:50:13 +00001059 if (host->size < variant->fifohalfsize)
Russell King0425a142006-02-16 16:48:31 +00001060 irqmask |= MCI_RXDATAAVLBLMASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 } else {
1062 /*
1063 * We don't actually need to include "FIFO empty" here
1064 * since its implicit in "FIFO half empty".
1065 */
1066 irqmask = MCI_TXFIFOHALFEMPTYMASK;
1067 }
1068
Ulf Hansson9cc639a2013-05-15 20:48:23 +01001069 mmci_write_datactrlreg(host, datactrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001071 mmci_set_mask1(host, irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072}
1073
1074static void
1075mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1076{
1077 void __iomem *base = host->base;
1078
Linus Walleij64de0282010-02-19 01:09:10 +01001079 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 cmd->opcode, cmd->arg, cmd->flags);
1081
Ludovic Barre0f244802018-10-08 14:08:45 +02001082 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 writel(0, base + MMCICOMMAND);
Srinivas Kandagatla6adb2a82014-06-02 10:08:57 +01001084 mmci_reg_delay(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085 }
1086
Ludovic Barrec8073e52018-12-06 16:13:31 +01001087 if (host->variant->cmdreg_stop &&
1088 cmd->opcode == MMC_STOP_TRANSMISSION)
1089 c |= host->variant->cmdreg_stop;
1090
Ludovic Barre0f244802018-10-08 14:08:45 +02001091 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
Russell Kinge9225172006-02-02 12:23:12 +00001092 if (cmd->flags & MMC_RSP_PRESENT) {
1093 if (cmd->flags & MMC_RSP_136)
Ludovic Barre0f244802018-10-08 14:08:45 +02001094 c |= host->variant->cmdreg_lrsp_crc;
1095 else if (cmd->flags & MMC_RSP_CRC)
1096 c |= host->variant->cmdreg_srsp_crc;
1097 else
1098 c |= host->variant->cmdreg_srsp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 }
1100 if (/*interrupt*/0)
1101 c |= MCI_CPSM_INTERRUPT;
1102
Srinivas Kandagatlaae7b0062014-06-02 10:09:39 +01001103 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
1104 c |= host->variant->data_cmd_enable;
1105
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106 host->cmd = cmd;
1107
1108 writel(cmd->arg, base + MMCIARGUMENT);
1109 writel(c, base + MMCICOMMAND);
1110}
1111
Ulf Hanssone9968c62019-01-29 15:35:56 +01001112static void mmci_stop_command(struct mmci_host *host)
1113{
1114 host->stop_abort.error = 0;
1115 mmci_start_command(host, &host->stop_abort, 0);
1116}
1117
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118static void
1119mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1120 unsigned int status)
1121{
Ludovic Barredaf97132018-10-08 14:08:44 +02001122 unsigned int status_err;
1123
Ulf Hansson1cb9da52014-06-12 14:42:23 +02001124 /* Make sure we have data to handle */
1125 if (!data)
1126 return;
1127
Linus Walleijf20f8f212010-10-19 13:41:24 +01001128 /* First check for errors */
Ludovic Barredaf97132018-10-08 14:08:44 +02001129 status_err = status & (host->variant->start_err |
1130 MCI_DATACRCFAIL | MCI_DATATIMEOUT |
1131 MCI_TXUNDERRUN | MCI_RXOVERRUN);
1132
1133 if (status_err) {
Linus Walleij8cb28152011-01-24 15:22:13 +01001134 u32 remain, success;
Linus Walleijf20f8f212010-10-19 13:41:24 +01001135
Russell Kingc8ebae32011-01-11 19:35:53 +00001136 /* Terminate the DMA transfer */
Ludovic Barrecfccc6a2018-10-08 14:08:40 +02001137 mmci_dma_error(host);
Russell Kingc8ebae32011-01-11 19:35:53 +00001138
Russell Kingc8afc9d2011-02-04 09:19:46 +00001139 /*
1140 * Calculate how far we are into the transfer. Note that
1141 * the data counter gives the number of bytes transferred
1142 * on the MMC bus, not on the host side. On reads, this
1143 * can be as much as a FIFO-worth of data ahead. This
1144 * matters for FIFO overruns only.
1145 */
Ludovic Barreb79220b2018-10-08 14:08:49 +02001146 if (!host->variant->datacnt_useless) {
1147 remain = readl(host->base + MMCIDATACNT);
1148 success = data->blksz * data->blocks - remain;
1149 } else {
1150 success = 0;
1151 }
Linus Walleij8cb28152011-01-24 15:22:13 +01001152
Russell Kingc8afc9d2011-02-04 09:19:46 +00001153 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
Ludovic Barredaf97132018-10-08 14:08:44 +02001154 status_err, success);
1155 if (status_err & MCI_DATACRCFAIL) {
Linus Walleij8cb28152011-01-24 15:22:13 +01001156 /* Last block was not successful */
Russell Kingc8afc9d2011-02-04 09:19:46 +00001157 success -= 1;
Pierre Ossman17b04292007-07-22 22:18:46 +02001158 data->error = -EILSEQ;
Ludovic Barredaf97132018-10-08 14:08:44 +02001159 } else if (status_err & MCI_DATATIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +02001160 data->error = -ETIMEDOUT;
Ludovic Barredaf97132018-10-08 14:08:44 +02001161 } else if (status_err & MCI_STARTBITERR) {
Linus Walleij757df742011-06-30 15:10:21 +01001162 data->error = -ECOMM;
Ludovic Barredaf97132018-10-08 14:08:44 +02001163 } else if (status_err & MCI_TXUNDERRUN) {
Pierre Ossman17b04292007-07-22 22:18:46 +02001164 data->error = -EIO;
Ludovic Barredaf97132018-10-08 14:08:44 +02001165 } else if (status_err & MCI_RXOVERRUN) {
Russell Kingc8afc9d2011-02-04 09:19:46 +00001166 if (success > host->variant->fifosize)
1167 success -= host->variant->fifosize;
1168 else
1169 success = 0;
Linus Walleij8cb28152011-01-24 15:22:13 +01001170 data->error = -EIO;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001171 }
Russell King51d43752011-01-27 10:56:52 +00001172 data->bytes_xfered = round_down(success, data->blksz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173 }
Linus Walleijf20f8f212010-10-19 13:41:24 +01001174
Linus Walleij8cb28152011-01-24 15:22:13 +01001175 if (status & MCI_DATABLOCKEND)
1176 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
Linus Walleijf20f8f212010-10-19 13:41:24 +01001177
Russell Kingccff9b52011-01-30 21:03:50 +00001178 if (status & MCI_DATAEND || data->error) {
Ludovic Barrecdea1942018-09-21 11:45:56 +02001179 mmci_dma_finalize(host, data);
1180
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 mmci_stop_data(host);
1182
Linus Walleij8cb28152011-01-24 15:22:13 +01001183 if (!data->error)
1184 /* The error clause is handled above, success! */
Russell King51d43752011-01-27 10:56:52 +00001185 data->bytes_xfered = data->blksz * data->blocks;
Linus Walleijf20f8f212010-10-19 13:41:24 +01001186
Ulf Hanssone9968c62019-01-29 15:35:56 +01001187 if (!data->stop) {
1188 if (host->variant->cmdreg_stop && data->error)
1189 mmci_stop_command(host);
1190 else
1191 mmci_request_end(host, data->mrq);
1192 } else if (host->mrq->sbc && !data->error) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 mmci_request_end(host, data->mrq);
Ulf Hanssone9968c62019-01-29 15:35:56 +01001194 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195 mmci_start_command(host, data->stop, 0);
Ulf Hanssone9968c62019-01-29 15:35:56 +01001196 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197 }
1198}
1199
1200static void
1201mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1202 unsigned int status)
1203{
1204 void __iomem *base = host->base;
Ludovic Barre812513c2019-04-26 09:46:34 +02001205 bool sbc, busy_resp;
Ulf Hanssonad82bfe2014-06-12 15:01:57 +02001206
1207 if (!cmd)
1208 return;
1209
1210 sbc = (cmd == host->mrq->sbc);
Ludovic Barre812513c2019-04-26 09:46:34 +02001211 busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
Ulf Hanssonad82bfe2014-06-12 15:01:57 +02001212
Linus Walleij49adc0c2016-10-25 11:06:06 +02001213 /*
1214 * We need to be one of these interrupts to be considered worth
1215 * handling. Note that we tag on any latent IRQs postponed
1216 * due to waiting for busy status.
1217 */
1218 if (!((status|host->busy_status) &
1219 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
Ulf Hanssonad82bfe2014-06-12 15:01:57 +02001220 return;
Ulf Hansson8d94b542014-01-13 16:49:31 +01001221
Linus Walleij49adc0c2016-10-25 11:06:06 +02001222 /*
1223 * ST Micro variant: handle busy detection.
1224 */
Ludovic Barre812513c2019-04-26 09:46:34 +02001225 if (busy_resp && host->variant->busy_detect) {
Ulf Hansson8d94b542014-01-13 16:49:31 +01001226
Linus Walleij49adc0c2016-10-25 11:06:06 +02001227 /* We are busy with a command, return */
1228 if (host->busy_status &&
1229 (status & host->variant->busy_detect_flag))
1230 return;
Ulf Hansson8d94b542014-01-13 16:49:31 +01001231
Linus Walleij49adc0c2016-10-25 11:06:06 +02001232 /*
1233 * We were not busy, but we now got a busy response on
1234 * something that was not an error, and we double-check
1235 * that the special busy status bit is still set before
1236 * proceeding.
1237 */
Ludovic Barre812513c2019-04-26 09:46:34 +02001238 if (!host->busy_status &&
Linus Walleij49adc0c2016-10-25 11:06:06 +02001239 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1240 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001241
1242 /* Clear the busy start IRQ */
1243 writel(host->variant->busy_detect_mask,
1244 host->base + MMCICLEAR);
1245
1246 /* Unmask the busy end IRQ */
Linus Walleij49adc0c2016-10-25 11:06:06 +02001247 writel(readl(base + MMCIMASK0) |
1248 host->variant->busy_detect_mask,
1249 base + MMCIMASK0);
1250 /*
1251 * Now cache the last response status code (until
1252 * the busy bit goes low), and return.
1253 */
1254 host->busy_status =
1255 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1256 return;
1257 }
1258
1259 /*
1260 * At this point we are not busy with a command, we have
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001261 * not received a new busy request, clear and mask the busy
1262 * end IRQ and fall through to process the IRQ.
Linus Walleij49adc0c2016-10-25 11:06:06 +02001263 */
1264 if (host->busy_status) {
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001265
1266 writel(host->variant->busy_detect_mask,
1267 host->base + MMCICLEAR);
1268
Linus Walleij49adc0c2016-10-25 11:06:06 +02001269 writel(readl(base + MMCIMASK0) &
1270 ~host->variant->busy_detect_mask,
1271 base + MMCIMASK0);
1272 host->busy_status = 0;
1273 }
Ulf Hansson8d94b542014-01-13 16:49:31 +01001274 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275
1276 host->cmd = NULL;
1277
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 if (status & MCI_CMDTIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +02001279 cmd->error = -ETIMEDOUT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001280 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
Pierre Ossman17b04292007-07-22 22:18:46 +02001281 cmd->error = -EILSEQ;
Russell King - ARM Linux9047b432011-01-11 16:35:56 +00001282 } else {
1283 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1284 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1285 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1286 cmd->resp[3] = readl(base + MMCIRESPONSE3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287 }
1288
Ulf Hansson024629c2013-05-13 15:40:56 +01001289 if ((!sbc && !cmd->data) || cmd->error) {
Ulf Hansson3b6e3c72011-12-13 16:58:43 +01001290 if (host->data) {
1291 /* Terminate the DMA transfer */
Ludovic Barrecfccc6a2018-10-08 14:08:40 +02001292 mmci_dma_error(host);
Ludovic Barre7b2a6d52018-09-21 11:45:55 +02001293
Russell Kinge47c2222007-01-08 16:42:51 +00001294 mmci_stop_data(host);
Ulf Hanssone9968c62019-01-29 15:35:56 +01001295 if (host->variant->cmdreg_stop && cmd->error) {
1296 mmci_stop_command(host);
1297 return;
1298 }
Ulf Hansson3b6e3c72011-12-13 16:58:43 +01001299 }
Ulf Hansson024629c2013-05-13 15:40:56 +01001300 mmci_request_end(host, host->mrq);
1301 } else if (sbc) {
1302 mmci_start_command(host, host->mrq->cmd, 0);
Ludovic Barred2141542018-10-08 14:08:48 +02001303 } else if (!host->variant->datactrl_first &&
1304 !(cmd->data->flags & MMC_DATA_READ)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 mmci_start_data(host, cmd->data);
1306 }
1307}
1308
Srinivas Kandagatla9c34b732014-06-02 10:10:04 +01001309static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1310{
1311 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1312}
1313
1314static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1315{
1316 /*
1317 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1318 * from the fifo range should be used
1319 */
1320 if (status & MCI_RXFIFOHALFFULL)
1321 return host->variant->fifohalfsize;
1322 else if (status & MCI_RXDATAAVLBL)
1323 return 4;
1324
1325 return 0;
1326}
1327
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1329{
1330 void __iomem *base = host->base;
1331 char *ptr = buffer;
Srinivas Kandagatla9c34b732014-06-02 10:10:04 +01001332 u32 status = readl(host->base + MMCISTATUS);
Linus Walleij26eed9a2008-04-26 23:39:44 +01001333 int host_remain = host->size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334
1335 do {
Srinivas Kandagatla9c34b732014-06-02 10:10:04 +01001336 int count = host->get_rx_fifocnt(host, status, host_remain);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337
1338 if (count > remain)
1339 count = remain;
1340
1341 if (count <= 0)
1342 break;
1343
Ulf Hansson393e5e22011-12-13 17:08:04 +01001344 /*
1345 * SDIO especially may want to send something that is
1346 * not divisible by 4 (as opposed to card sectors
1347 * etc). Therefore make sure to always read the last bytes
1348 * while only doing full 32-bit reads towards the FIFO.
1349 */
1350 if (unlikely(count & 0x3)) {
1351 if (count < 4) {
1352 unsigned char buf[4];
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001353 ioread32_rep(base + MMCIFIFO, buf, 1);
Ulf Hansson393e5e22011-12-13 17:08:04 +01001354 memcpy(ptr, buf, count);
1355 } else {
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001356 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
Ulf Hansson393e5e22011-12-13 17:08:04 +01001357 count &= ~0x3;
1358 }
1359 } else {
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001360 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
Ulf Hansson393e5e22011-12-13 17:08:04 +01001361 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362
1363 ptr += count;
1364 remain -= count;
Linus Walleij26eed9a2008-04-26 23:39:44 +01001365 host_remain -= count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366
1367 if (remain == 0)
1368 break;
1369
1370 status = readl(base + MMCISTATUS);
1371 } while (status & MCI_RXDATAAVLBL);
1372
1373 return ptr - buffer;
1374}
1375
1376static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1377{
Rabin Vincent8301bb62010-08-09 12:57:30 +01001378 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001379 void __iomem *base = host->base;
1380 char *ptr = buffer;
1381
1382 do {
1383 unsigned int count, maxcnt;
1384
Rabin Vincent8301bb62010-08-09 12:57:30 +01001385 maxcnt = status & MCI_TXFIFOEMPTY ?
1386 variant->fifosize : variant->fifohalfsize;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001387 count = min(remain, maxcnt);
1388
Linus Walleij34177802010-10-19 12:43:58 +01001389 /*
Linus Walleij34177802010-10-19 12:43:58 +01001390 * SDIO especially may want to send something that is
1391 * not divisible by 4 (as opposed to card sectors
1392 * etc), and the FIFO only accept full 32-bit writes.
1393 * So compensate by adding +3 on the count, a single
1394 * byte become a 32bit write, 7 bytes will be two
1395 * 32bit writes etc.
1396 */
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001397 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001398
1399 ptr += count;
1400 remain -= count;
1401
1402 if (remain == 0)
1403 break;
1404
1405 status = readl(base + MMCISTATUS);
1406 } while (status & MCI_TXFIFOHALFEMPTY);
1407
1408 return ptr - buffer;
1409}
1410
1411/*
1412 * PIO data transfer IRQ handler.
1413 */
David Howells7d12e782006-10-05 14:55:46 +01001414static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415{
1416 struct mmci_host *host = dev_id;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001417 struct sg_mapping_iter *sg_miter = &host->sg_miter;
Rabin Vincent8301bb62010-08-09 12:57:30 +01001418 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419 void __iomem *base = host->base;
1420 u32 status;
1421
1422 status = readl(base + MMCISTATUS);
1423
Linus Walleij64de0282010-02-19 01:09:10 +01001424 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425
1426 do {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427 unsigned int remain, len;
1428 char *buffer;
1429
1430 /*
1431 * For write, we only need to test the half-empty flag
1432 * here - if the FIFO is completely empty, then by
1433 * definition it is more than half empty.
1434 *
1435 * For read, check for data available.
1436 */
1437 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1438 break;
1439
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001440 if (!sg_miter_next(sg_miter))
1441 break;
1442
1443 buffer = sg_miter->addr;
1444 remain = sg_miter->length;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445
1446 len = 0;
1447 if (status & MCI_RXACTIVE)
1448 len = mmci_pio_read(host, buffer, remain);
1449 if (status & MCI_TXACTIVE)
1450 len = mmci_pio_write(host, buffer, remain, status);
1451
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001452 sg_miter->consumed = len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001453
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454 host->size -= len;
1455 remain -= len;
1456
1457 if (remain)
1458 break;
1459
Linus Torvalds1da177e2005-04-16 15:20:36 -07001460 status = readl(base + MMCISTATUS);
1461 } while (1);
1462
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001463 sg_miter_stop(sg_miter);
1464
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465 /*
Russell Kingc4d877c2011-01-27 09:50:13 +00001466 * If we have less than the fifo 'half-full' threshold to transfer,
1467 * trigger a PIO interrupt as soon as any data is available.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001468 */
Russell Kingc4d877c2011-01-27 09:50:13 +00001469 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
Linus Walleij2686b4b2010-10-19 12:39:48 +01001470 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001471
1472 /*
1473 * If we run out of data, disable the data IRQs; this
1474 * prevents a race where the FIFO becomes empty before
1475 * the chip itself has disabled the data path, and
1476 * stops us racing with our data end IRQ.
1477 */
1478 if (host->size == 0) {
Linus Walleij2686b4b2010-10-19 12:39:48 +01001479 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1481 }
1482
1483 return IRQ_HANDLED;
1484}
1485
1486/*
1487 * Handle completion of command and data transfers.
1488 */
David Howells7d12e782006-10-05 14:55:46 +01001489static irqreturn_t mmci_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490{
1491 struct mmci_host *host = dev_id;
1492 u32 status;
1493 int ret = 0;
1494
1495 spin_lock(&host->lock);
1496
1497 do {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498 status = readl(host->base + MMCISTATUS);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001499
1500 if (host->singleirq) {
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +01001501 if (status & host->mask1_reg)
Linus Walleij2686b4b2010-10-19 12:39:48 +01001502 mmci_pio_irq(irq, dev_id);
1503
Ludovic Barre59db5e22018-10-08 14:08:47 +02001504 status &= ~host->variant->irq_pio_mask;
Linus Walleij2686b4b2010-10-19 12:39:48 +01001505 }
1506
Ulf Hansson8d94b542014-01-13 16:49:31 +01001507 /*
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001508 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1509 * enabled) in mmci_cmd_irq() function where ST Micro busy
1510 * detection variant is handled. Considering the HW seems to be
1511 * triggering the IRQ on both edges while monitoring DAT0 for
1512 * busy completion and that same status bit is used to monitor
1513 * start and end of busy detection, special care must be taken
1514 * to make sure that both start and end interrupts are always
1515 * cleared one after the other.
Ulf Hansson8d94b542014-01-13 16:49:31 +01001516 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517 status &= readl(host->base + MMCIMASK0);
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001518 if (host->variant->busy_detect)
1519 writel(status & ~host->variant->busy_detect_mask,
1520 host->base + MMCICLEAR);
1521 else
1522 writel(status, host->base + MMCICLEAR);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001523
Linus Walleij64de0282010-02-19 01:09:10 +01001524 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001525
Ulf Hansson78782892014-06-13 13:21:38 +02001526 if (host->variant->reversed_irq_handling) {
1527 mmci_data_irq(host, host->data, status);
1528 mmci_cmd_irq(host, host->cmd, status);
1529 } else {
1530 mmci_cmd_irq(host, host->cmd, status);
1531 mmci_data_irq(host, host->data, status);
1532 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001533
Linus Walleij49adc0c2016-10-25 11:06:06 +02001534 /*
Ludovic Barre8520ce12019-04-26 09:46:35 +02001535 * Busy detection has been handled by mmci_cmd_irq() above.
1536 * Clear the status bit to prevent polling in IRQ context.
Linus Walleij49adc0c2016-10-25 11:06:06 +02001537 */
Ludovic Barre8520ce12019-04-26 09:46:35 +02001538 if (host->variant->busy_detect_flag)
Linus Walleij49adc0c2016-10-25 11:06:06 +02001539 status &= ~host->variant->busy_detect_flag;
Ulf Hansson8d94b542014-01-13 16:49:31 +01001540
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541 ret = 1;
1542 } while (status);
1543
1544 spin_unlock(&host->lock);
1545
1546 return IRQ_RETVAL(ret);
1547}
1548
1549static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1550{
1551 struct mmci_host *host = mmc_priv(mmc);
Linus Walleij9e943022008-10-24 21:17:50 +01001552 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553
1554 WARN_ON(host->mrq != NULL);
1555
Ulf Hansson653a7612013-01-21 21:29:34 +01001556 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1557 if (mrq->cmd->error) {
Pierre Ossman255d01a2007-07-24 20:38:53 +02001558 mmc_request_done(mmc, mrq);
1559 return;
1560 }
1561
Linus Walleij9e943022008-10-24 21:17:50 +01001562 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563
1564 host->mrq = mrq;
1565
Per Forlin58c7ccb2011-07-01 18:55:24 +02001566 if (mrq->data)
1567 mmci_get_next_data(host, mrq->data);
1568
Ludovic Barred2141542018-10-08 14:08:48 +02001569 if (mrq->data &&
1570 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571 mmci_start_data(host, mrq->data);
1572
Ulf Hansson024629c2013-05-13 15:40:56 +01001573 if (mrq->sbc)
1574 mmci_start_command(host, mrq->sbc, 0);
1575 else
1576 mmci_start_command(host, mrq->cmd, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577
Linus Walleij9e943022008-10-24 21:17:50 +01001578 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579}
1580
1581static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1582{
1583 struct mmci_host *host = mmc_priv(mmc);
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001584 struct variant_data *variant = host->variant;
Linus Walleija6a64642009-09-14 12:56:14 +01001585 u32 pwr = 0;
1586 unsigned long flags;
Lee Jonesdb90f912013-05-03 12:52:12 +01001587 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001588
Ulf Hanssonbc521812011-12-13 16:57:55 +01001589 if (host->plat->ios_handler &&
1590 host->plat->ios_handler(mmc_dev(mmc), ios))
1591 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1592
Linus Torvalds1da177e2005-04-16 15:20:36 -07001593 switch (ios->power_mode) {
1594 case MMC_POWER_OFF:
Ulf Hansson599c1d52013-01-07 16:22:50 +01001595 if (!IS_ERR(mmc->supply.vmmc))
1596 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
Lee Jones237fb5e2013-01-31 11:27:52 +00001597
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001598 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
Lee Jones237fb5e2013-01-31 11:27:52 +00001599 regulator_disable(mmc->supply.vqmmc);
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001600 host->vqmmc_enabled = false;
1601 }
Lee Jones237fb5e2013-01-31 11:27:52 +00001602
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603 break;
1604 case MMC_POWER_UP:
Ulf Hansson599c1d52013-01-07 16:22:50 +01001605 if (!IS_ERR(mmc->supply.vmmc))
1606 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1607
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001608 /*
1609 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1610 * and instead uses MCI_PWR_ON so apply whatever value is
1611 * configured in the variant data.
1612 */
1613 pwr |= variant->pwrreg_powerup;
1614
1615 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616 case MMC_POWER_ON:
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001617 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
Lee Jonesdb90f912013-05-03 12:52:12 +01001618 ret = regulator_enable(mmc->supply.vqmmc);
1619 if (ret < 0)
1620 dev_err(mmc_dev(mmc),
1621 "failed to enable vqmmc regulator\n");
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001622 else
1623 host->vqmmc_enabled = true;
Lee Jonesdb90f912013-05-03 12:52:12 +01001624 }
Lee Jones237fb5e2013-01-31 11:27:52 +00001625
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626 pwr |= MCI_PWR_ON;
1627 break;
1628 }
1629
Ulf Hansson4d1a3a02011-12-13 16:57:07 +01001630 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1631 /*
1632 * The ST Micro variant has some additional bits
1633 * indicating signal direction for the signals in
1634 * the SD/MMC bus and feedback-clock usage.
1635 */
Ulf Hansson4593df22014-03-21 10:13:05 +01001636 pwr |= host->pwr_reg_add;
Ulf Hansson4d1a3a02011-12-13 16:57:07 +01001637
1638 if (ios->bus_width == MMC_BUS_WIDTH_4)
1639 pwr &= ~MCI_ST_DATA74DIREN;
1640 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1641 pwr &= (~MCI_ST_DATA74DIREN &
1642 ~MCI_ST_DATA31DIREN &
1643 ~MCI_ST_DATA2DIREN);
1644 }
1645
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001646 if (variant->opendrain) {
1647 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1648 pwr |= variant->opendrain;
1649 } else {
1650 /*
1651 * If the variant cannot configure the pads by its own, then we
1652 * expect the pinctrl to be able to do that for us
1653 */
1654 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1655 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1656 else
1657 pinctrl_select_state(host->pinctrl, host->pins_default);
1658 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659
Ulf Hanssonf4670da2013-01-09 17:19:54 +01001660 /*
1661 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1662 * gating the clock, the MCI_PWR_ON bit is cleared.
1663 */
1664 if (!ios->clock && variant->pwrreg_clkgate)
1665 pwr &= ~MCI_PWR_ON;
1666
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001667 if (host->variant->explicit_mclk_control &&
1668 ios->clock != host->clock_cache) {
1669 ret = clk_set_rate(host->clk, ios->clock);
1670 if (ret < 0)
1671 dev_err(mmc_dev(host->mmc),
1672 "Error setting clock rate (%d)\n", ret);
1673 else
1674 host->mclk = clk_get_rate(host->clk);
1675 }
1676 host->clock_cache = ios->clock;
1677
Linus Walleija6a64642009-09-14 12:56:14 +01001678 spin_lock_irqsave(&host->lock, flags);
1679
Ludovic Barrecd3ee8c2018-10-08 14:08:42 +02001680 if (host->ops && host->ops->set_clkreg)
1681 host->ops->set_clkreg(host, ios->clock);
1682 else
1683 mmci_set_clkreg(host, ios->clock);
1684
1685 if (host->ops && host->ops->set_pwrreg)
1686 host->ops->set_pwrreg(host, pwr);
1687 else
1688 mmci_write_pwrreg(host, pwr);
1689
Ulf Hanssonf829c042013-09-04 09:01:15 +01001690 mmci_reg_delay(host);
Linus Walleija6a64642009-09-14 12:56:14 +01001691
1692 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001693}
1694
Russell King89001442009-07-09 15:16:07 +01001695static int mmci_get_cd(struct mmc_host *mmc)
1696{
1697 struct mmci_host *host = mmc_priv(mmc);
Rabin Vincent29719442010-08-09 12:54:43 +01001698 struct mmci_platform_data *plat = host->plat;
Ulf Hanssond2762092014-03-17 13:56:19 +01001699 unsigned int status = mmc_gpio_get_cd(mmc);
Russell King89001442009-07-09 15:16:07 +01001700
Ulf Hanssond2762092014-03-17 13:56:19 +01001701 if (status == -ENOSYS) {
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001702 if (!plat->status)
1703 return 1; /* Assume always present */
1704
Rabin Vincent29719442010-08-09 12:54:43 +01001705 status = plat->status(mmc_dev(host->mmc));
Ulf Hanssond2762092014-03-17 13:56:19 +01001706 }
Russell King74bc8092010-07-29 15:58:59 +01001707 return status;
Russell King89001442009-07-09 15:16:07 +01001708}
1709
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001710static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1711{
1712 int ret = 0;
1713
1714 if (!IS_ERR(mmc->supply.vqmmc)) {
1715
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001716 switch (ios->signal_voltage) {
1717 case MMC_SIGNAL_VOLTAGE_330:
1718 ret = regulator_set_voltage(mmc->supply.vqmmc,
1719 2700000, 3600000);
1720 break;
1721 case MMC_SIGNAL_VOLTAGE_180:
1722 ret = regulator_set_voltage(mmc->supply.vqmmc,
1723 1700000, 1950000);
1724 break;
1725 case MMC_SIGNAL_VOLTAGE_120:
1726 ret = regulator_set_voltage(mmc->supply.vqmmc,
1727 1100000, 1300000);
1728 break;
1729 }
1730
1731 if (ret)
1732 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001733 }
1734
1735 return ret;
1736}
1737
Ulf Hansson01259622013-05-15 20:53:22 +01001738static struct mmc_host_ops mmci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739 .request = mmci_request,
Per Forlin58c7ccb2011-07-01 18:55:24 +02001740 .pre_req = mmci_pre_request,
1741 .post_req = mmci_post_request,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001742 .set_ios = mmci_set_ios,
Ulf Hanssond2762092014-03-17 13:56:19 +01001743 .get_ro = mmc_gpio_get_ro,
Russell King89001442009-07-09 15:16:07 +01001744 .get_cd = mmci_get_cd,
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001745 .start_signal_voltage_switch = mmci_sig_volt_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746};
1747
Ulf Hansson78f87df2014-03-17 15:53:07 +01001748static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1749{
Ulf Hansson4593df22014-03-21 10:13:05 +01001750 struct mmci_host *host = mmc_priv(mmc);
Ulf Hansson78f87df2014-03-17 15:53:07 +01001751 int ret = mmc_of_parse(mmc);
Lee Jones000bc9d2012-04-16 10:18:43 +01001752
Ulf Hansson78f87df2014-03-17 15:53:07 +01001753 if (ret)
1754 return ret;
Lee Jones000bc9d2012-04-16 10:18:43 +01001755
Ulf Hansson4593df22014-03-21 10:13:05 +01001756 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1757 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1758 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1759 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1760 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1761 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1762 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1763 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1764 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1765 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1766 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1767 host->pwr_reg_add |= MCI_ST_FBCLKEN;
Ludovic Barre46b723d2018-10-08 14:08:55 +02001768 if (of_get_property(np, "st,sig-dir", NULL))
1769 host->pwr_reg_add |= MCI_STM32_DIRPOL;
1770 if (of_get_property(np, "st,neg-edge", NULL))
1771 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
1772 if (of_get_property(np, "st,use-ckin", NULL))
1773 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
Ulf Hansson4593df22014-03-21 10:13:05 +01001774
Lee Jones000bc9d2012-04-16 10:18:43 +01001775 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
Ulf Hansson78f87df2014-03-17 15:53:07 +01001776 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
Lee Jones000bc9d2012-04-16 10:18:43 +01001777 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
Ulf Hansson78f87df2014-03-17 15:53:07 +01001778 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
Lee Jones000bc9d2012-04-16 10:18:43 +01001779
Ulf Hansson78f87df2014-03-17 15:53:07 +01001780 return 0;
Lee Jones000bc9d2012-04-16 10:18:43 +01001781}
Lee Jones000bc9d2012-04-16 10:18:43 +01001782
Bill Pembertonc3be1ef2012-11-19 13:23:06 -05001783static int mmci_probe(struct amba_device *dev,
Russell Kingaa25afa2011-02-19 15:55:00 +00001784 const struct amba_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785{
Linus Walleij6ef297f2009-09-22 14:29:36 +01001786 struct mmci_platform_data *plat = dev->dev.platform_data;
Lee Jones000bc9d2012-04-16 10:18:43 +01001787 struct device_node *np = dev->dev.of_node;
Rabin Vincent4956e102010-07-21 12:54:40 +01001788 struct variant_data *variant = id->data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001789 struct mmci_host *host;
1790 struct mmc_host *mmc;
1791 int ret;
1792
Lee Jones000bc9d2012-04-16 10:18:43 +01001793 /* Must have platform data or Device Tree. */
1794 if (!plat && !np) {
1795 dev_err(&dev->dev, "No plat data or DT found\n");
1796 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001797 }
1798
Lee Jonesb9b52912012-06-12 10:49:51 +01001799 if (!plat) {
1800 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1801 if (!plat)
1802 return -ENOMEM;
1803 }
1804
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
Ulf Hanssonef289982014-03-17 13:56:32 +01001806 if (!mmc)
1807 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808
Ulf Hansson78f87df2014-03-17 15:53:07 +01001809 ret = mmci_of_parse(np, mmc);
1810 if (ret)
1811 goto host_free;
1812
Linus Torvalds1da177e2005-04-16 15:20:36 -07001813 host = mmc_priv(mmc);
Rabin Vincent4ea580f2009-04-17 08:44:19 +05301814 host->mmc = mmc;
Russell King012b7d32009-07-09 15:13:56 +01001815
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001816 /*
1817 * Some variant (STM32) doesn't have opendrain bit, nevertheless
1818 * pins can be set accordingly using pinctrl
1819 */
1820 if (!variant->opendrain) {
1821 host->pinctrl = devm_pinctrl_get(&dev->dev);
1822 if (IS_ERR(host->pinctrl)) {
1823 dev_err(&dev->dev, "failed to get pinctrl");
Wei Yongjun310eb252018-01-23 02:09:13 +00001824 ret = PTR_ERR(host->pinctrl);
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001825 goto host_free;
1826 }
1827
1828 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1829 PINCTRL_STATE_DEFAULT);
1830 if (IS_ERR(host->pins_default)) {
1831 dev_err(mmc_dev(mmc), "Can't select default pins\n");
Wei Yongjun310eb252018-01-23 02:09:13 +00001832 ret = PTR_ERR(host->pins_default);
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001833 goto host_free;
1834 }
1835
1836 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1837 MMCI_PINCTRL_STATE_OPENDRAIN);
1838 if (IS_ERR(host->pins_opendrain)) {
1839 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
Wei Yongjun310eb252018-01-23 02:09:13 +00001840 ret = PTR_ERR(host->pins_opendrain);
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001841 goto host_free;
1842 }
1843 }
1844
Russell King012b7d32009-07-09 15:13:56 +01001845 host->hw_designer = amba_manf(dev);
1846 host->hw_revision = amba_rev(dev);
Linus Walleij64de0282010-02-19 01:09:10 +01001847 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1848 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
Russell King012b7d32009-07-09 15:13:56 +01001849
Ulf Hansson665ba562013-05-13 15:39:17 +01001850 host->clk = devm_clk_get(&dev->dev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851 if (IS_ERR(host->clk)) {
1852 ret = PTR_ERR(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001853 goto host_free;
1854 }
1855
Julia Lawallac940932012-08-26 16:00:59 +00001856 ret = clk_prepare_enable(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857 if (ret)
Ulf Hansson665ba562013-05-13 15:39:17 +01001858 goto host_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001859
Srinivas Kandagatla9c34b732014-06-02 10:10:04 +01001860 if (variant->qcom_fifo)
1861 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1862 else
1863 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1864
Linus Torvalds1da177e2005-04-16 15:20:36 -07001865 host->plat = plat;
Rabin Vincent4956e102010-07-21 12:54:40 +01001866 host->variant = variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001867 host->mclk = clk_get_rate(host->clk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001868 /*
1869 * According to the spec, mclk is max 100 MHz,
1870 * so we try to adjust the clock down to this,
1871 * (if possible).
1872 */
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +01001873 if (host->mclk > variant->f_max) {
1874 ret = clk_set_rate(host->clk, variant->f_max);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001875 if (ret < 0)
1876 goto clk_disable;
1877 host->mclk = clk_get_rate(host->clk);
Linus Walleij64de0282010-02-19 01:09:10 +01001878 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1879 host->mclk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001880 }
Ulf Hanssonef289982014-03-17 13:56:32 +01001881
Russell Kingc8ebae32011-01-11 19:35:53 +00001882 host->phybase = dev->res.start;
Ulf Hanssonef289982014-03-17 13:56:32 +01001883 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1884 if (IS_ERR(host->base)) {
1885 ret = PTR_ERR(host->base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886 goto clk_disable;
1887 }
1888
Ulf Hanssoned9067f2018-07-13 13:15:23 +02001889 if (variant->init)
1890 variant->init(host);
1891
Linus Walleij7f294e42011-07-08 09:57:15 +01001892 /*
1893 * The ARM and ST versions of the block have slightly different
1894 * clock divider equations which means that the minimum divider
1895 * differs too.
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001896 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
Linus Walleij7f294e42011-07-08 09:57:15 +01001897 */
1898 if (variant->st_clkdiv)
1899 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
Ludovic Barre00e930d2018-10-08 14:08:52 +02001900 else if (variant->stm32_clkdiv)
1901 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001902 else if (variant->explicit_mclk_control)
1903 mmc->f_min = clk_round_rate(host->clk, 100000);
Linus Walleij7f294e42011-07-08 09:57:15 +01001904 else
1905 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
Linus Walleij808d97c2010-04-08 07:39:38 +01001906 /*
Ulf Hansson78f87df2014-03-17 15:53:07 +01001907 * If no maximum operating frequency is supplied, fall back to use
1908 * the module parameter, which has a (low) default value in case it
1909 * is not specified. Either value must not exceed the clock rate into
Ulf Hansson5080a082014-03-21 10:46:39 +01001910 * the block, of course.
Linus Walleij808d97c2010-04-08 07:39:38 +01001911 */
Ulf Hansson78f87df2014-03-17 15:53:07 +01001912 if (mmc->f_max)
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001913 mmc->f_max = variant->explicit_mclk_control ?
1914 min(variant->f_max, mmc->f_max) :
1915 min(host->mclk, mmc->f_max);
Linus Walleij808d97c2010-04-08 07:39:38 +01001916 else
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001917 mmc->f_max = variant->explicit_mclk_control ?
1918 fmax : min(host->mclk, fmax);
1919
1920
Linus Walleij64de0282010-02-19 01:09:10 +01001921 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1922
Ludovic Barre15878e52018-10-08 14:08:51 +02001923 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
1924 if (IS_ERR(host->rst)) {
1925 ret = PTR_ERR(host->rst);
1926 goto clk_disable;
1927 }
1928
Ulf Hansson599c1d52013-01-07 16:22:50 +01001929 /* Get regulators and the supported OCR mask */
Bjorn Andersson9369c972015-03-24 18:39:49 -07001930 ret = mmc_regulator_get_supply(mmc);
Wolfram Sang51006952017-10-14 21:17:14 +02001931 if (ret)
Bjorn Andersson9369c972015-03-24 18:39:49 -07001932 goto clk_disable;
1933
Ulf Hansson599c1d52013-01-07 16:22:50 +01001934 if (!mmc->ocr_avail)
Linus Walleij34e84f32009-09-22 14:41:40 +01001935 mmc->ocr_avail = plat->ocr_mask;
Ulf Hansson599c1d52013-01-07 16:22:50 +01001936 else if (plat->ocr_mask)
1937 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1938
Ulf Hansson9dd8a8b2014-03-19 13:54:18 +01001939 /* We support these capabilities. */
1940 mmc->caps |= MMC_CAP_CMD23;
1941
Linus Walleij49adc0c2016-10-25 11:06:06 +02001942 /*
1943 * Enable busy detection.
1944 */
Ulf Hansson8d94b542014-01-13 16:49:31 +01001945 if (variant->busy_detect) {
1946 mmci_ops.card_busy = mmci_card_busy;
Linus Walleij49adc0c2016-10-25 11:06:06 +02001947 /*
1948 * Not all variants have a flag to enable busy detection
1949 * in the DPSM, but if they do, set it here.
1950 */
1951 if (variant->busy_dpsm_flag)
1952 mmci_write_datactrlreg(host,
1953 host->variant->busy_dpsm_flag);
Ulf Hansson8d94b542014-01-13 16:49:31 +01001954 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1955 mmc->max_busy_timeout = 0;
1956 }
1957
Ulf Hanssone9968c62019-01-29 15:35:56 +01001958 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */
1959 host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
1960 host->stop_abort.arg = 0;
1961 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
1962
Ulf Hansson8d94b542014-01-13 16:49:31 +01001963 mmc->ops = &mmci_ops;
1964
Ulf Hansson70be2082013-01-07 15:35:06 +01001965 /* We support these PM capabilities. */
Ulf Hansson78f87df2014-03-17 15:53:07 +01001966 mmc->pm_caps |= MMC_PM_KEEP_POWER;
Ulf Hansson70be2082013-01-07 15:35:06 +01001967
Linus Torvalds1da177e2005-04-16 15:20:36 -07001968 /*
1969 * We can do SGIO
1970 */
Martin K. Petersena36274e2010-09-10 01:33:59 -04001971 mmc->max_segs = NR_SG;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001972
1973 /*
Rabin Vincent08458ef2010-07-21 12:55:59 +01001974 * Since only a certain number of bits are valid in the data length
1975 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1976 * single request.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001977 */
Rabin Vincent08458ef2010-07-21 12:55:59 +01001978 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979
1980 /*
1981 * Set the maximum segment size. Since we aren't doing DMA
1982 * (yet) we are only limited by the data length register.
1983 */
Pierre Ossman55db8902006-11-21 17:55:45 +01001984 mmc->max_seg_size = mmc->max_req_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001985
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001986 /*
1987 * Block size can be up to 2048 bytes, but must be a power of two.
1988 */
Ludovic Barrec931d492018-10-08 14:08:43 +02001989 mmc->max_blk_size = 1 << variant->datactrl_blocksz;
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001990
Pierre Ossman55db8902006-11-21 17:55:45 +01001991 /*
Will Deacon8f7f6b7e2012-02-24 11:25:21 +00001992 * Limit the number of blocks transferred so that we don't overflow
1993 * the maximum request size.
Pierre Ossman55db8902006-11-21 17:55:45 +01001994 */
Ludovic Barrec931d492018-10-08 14:08:43 +02001995 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
Pierre Ossman55db8902006-11-21 17:55:45 +01001996
Linus Torvalds1da177e2005-04-16 15:20:36 -07001997 spin_lock_init(&host->lock);
1998
1999 writel(0, host->base + MMCIMASK0);
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +01002000
2001 if (variant->mmcimask1)
2002 writel(0, host->base + MMCIMASK1);
2003
Linus Torvalds1da177e2005-04-16 15:20:36 -07002004 writel(0xfff, host->base + MMCICLEAR);
2005
Linus Walleijce437aa2014-08-27 15:13:54 +02002006 /*
2007 * If:
2008 * - not using DT but using a descriptor table, or
2009 * - using a table of descriptors ALONGSIDE DT, or
2010 * look up these descriptors named "cd" and "wp" right here, fail
Linus Walleij9ef986a2018-09-20 16:01:10 -07002011 * silently of these do not exist
Linus Walleijce437aa2014-08-27 15:13:54 +02002012 */
2013 if (!np) {
Linus Walleij89168b42014-10-02 09:08:46 +02002014 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
Linus Walleij9ef986a2018-09-20 16:01:10 -07002015 if (ret == -EPROBE_DEFER)
2016 goto clk_disable;
Linus Walleijce437aa2014-08-27 15:13:54 +02002017
Linus Walleija2b760a2019-02-05 10:30:22 +01002018 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0, NULL);
Linus Walleij9ef986a2018-09-20 16:01:10 -07002019 if (ret == -EPROBE_DEFER)
2020 goto clk_disable;
Russell King89001442009-07-09 15:16:07 +01002021 }
2022
Ulf Hanssonef289982014-03-17 13:56:32 +01002023 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
2024 DRIVER_NAME " (cmd)", host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025 if (ret)
Ulf Hanssonef289982014-03-17 13:56:32 +01002026 goto clk_disable;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002027
Russell Kingdfb85182012-05-03 11:33:15 +01002028 if (!dev->irq[1])
Linus Walleij2686b4b2010-10-19 12:39:48 +01002029 host->singleirq = true;
2030 else {
Ulf Hanssonef289982014-03-17 13:56:32 +01002031 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
2032 IRQF_SHARED, DRIVER_NAME " (pio)", host);
Linus Walleij2686b4b2010-10-19 12:39:48 +01002033 if (ret)
Ulf Hanssonef289982014-03-17 13:56:32 +01002034 goto clk_disable;
Linus Walleij2686b4b2010-10-19 12:39:48 +01002035 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002036
Ludovic Barredaf97132018-10-08 14:08:44 +02002037 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002038
2039 amba_set_drvdata(dev, mmc);
2040
Russell Kingc8ebae32011-01-11 19:35:53 +00002041 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
2042 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
2043 amba_rev(dev), (unsigned long long)dev->res.start,
2044 dev->irq[0], dev->irq[1]);
2045
2046 mmci_dma_setup(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002047
Ulf Hansson2cd976c2011-12-13 17:01:11 +01002048 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
2049 pm_runtime_use_autosuspend(&dev->dev);
Russell King1c3be362011-08-14 09:17:05 +01002050
Russell King8c11a942010-12-28 19:40:40 +00002051 mmc_add_host(mmc);
2052
Ulf Hansson6f2d3c82014-12-11 14:35:55 +01002053 pm_runtime_put(&dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002054 return 0;
2055
Linus Torvalds1da177e2005-04-16 15:20:36 -07002056 clk_disable:
Julia Lawallac940932012-08-26 16:00:59 +00002057 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058 host_free:
2059 mmc_free_host(mmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002060 return ret;
2061}
2062
Bill Pemberton6e0ee712012-11-19 13:26:03 -05002063static int mmci_remove(struct amba_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002064{
2065 struct mmc_host *mmc = amba_get_drvdata(dev);
2066
Linus Torvalds1da177e2005-04-16 15:20:36 -07002067 if (mmc) {
2068 struct mmci_host *host = mmc_priv(mmc);
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +01002069 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002070
Russell King1c3be362011-08-14 09:17:05 +01002071 /*
2072 * Undo pm_runtime_put() in probe. We use the _sync
2073 * version here so that we can access the primecell.
2074 */
2075 pm_runtime_get_sync(&dev->dev);
2076
Linus Torvalds1da177e2005-04-16 15:20:36 -07002077 mmc_remove_host(mmc);
2078
2079 writel(0, host->base + MMCIMASK0);
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +01002080
2081 if (variant->mmcimask1)
2082 writel(0, host->base + MMCIMASK1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002083
2084 writel(0, host->base + MMCICOMMAND);
2085 writel(0, host->base + MMCIDATACTRL);
2086
Russell Kingc8ebae32011-01-11 19:35:53 +00002087 mmci_dma_release(host);
Julia Lawallac940932012-08-26 16:00:59 +00002088 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089 mmc_free_host(mmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002090 }
2091
2092 return 0;
2093}
2094
Ulf Hansson571dce42014-01-23 00:38:00 +01002095#ifdef CONFIG_PM
Ulf Hansson1ff44432013-09-04 09:05:17 +01002096static void mmci_save(struct mmci_host *host)
2097{
2098 unsigned long flags;
2099
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01002100 spin_lock_irqsave(&host->lock, flags);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002101
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01002102 writel(0, host->base + MMCIMASK0);
2103 if (host->variant->pwrreg_nopower) {
Ulf Hansson1ff44432013-09-04 09:05:17 +01002104 writel(0, host->base + MMCIDATACTRL);
2105 writel(0, host->base + MMCIPOWER);
2106 writel(0, host->base + MMCICLOCK);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002107 }
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01002108 mmci_reg_delay(host);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002109
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01002110 spin_unlock_irqrestore(&host->lock, flags);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002111}
2112
2113static void mmci_restore(struct mmci_host *host)
2114{
2115 unsigned long flags;
2116
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01002117 spin_lock_irqsave(&host->lock, flags);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002118
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01002119 if (host->variant->pwrreg_nopower) {
Ulf Hansson1ff44432013-09-04 09:05:17 +01002120 writel(host->clk_reg, host->base + MMCICLOCK);
2121 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2122 writel(host->pwr_reg, host->base + MMCIPOWER);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002123 }
Ludovic Barredaf97132018-10-08 14:08:44 +02002124 writel(MCI_IRQENABLE | host->variant->start_err,
2125 host->base + MMCIMASK0);
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01002126 mmci_reg_delay(host);
2127
2128 spin_unlock_irqrestore(&host->lock, flags);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002129}
2130
Ulf Hansson82592932013-01-09 11:15:26 +01002131static int mmci_runtime_suspend(struct device *dev)
2132{
2133 struct amba_device *adev = to_amba_device(dev);
2134 struct mmc_host *mmc = amba_get_drvdata(adev);
2135
2136 if (mmc) {
2137 struct mmci_host *host = mmc_priv(mmc);
Ulf Hanssone36bd9c62013-09-04 09:00:37 +01002138 pinctrl_pm_select_sleep_state(dev);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002139 mmci_save(host);
Ulf Hansson82592932013-01-09 11:15:26 +01002140 clk_disable_unprepare(host->clk);
2141 }
2142
2143 return 0;
2144}
2145
2146static int mmci_runtime_resume(struct device *dev)
2147{
2148 struct amba_device *adev = to_amba_device(dev);
2149 struct mmc_host *mmc = amba_get_drvdata(adev);
2150
2151 if (mmc) {
2152 struct mmci_host *host = mmc_priv(mmc);
2153 clk_prepare_enable(host->clk);
Ulf Hansson1ff44432013-09-04 09:05:17 +01002154 mmci_restore(host);
Ulf Hanssone36bd9c62013-09-04 09:00:37 +01002155 pinctrl_pm_select_default_state(dev);
Ulf Hansson82592932013-01-09 11:15:26 +01002156 }
2157
2158 return 0;
2159}
2160#endif
2161
Ulf Hansson48fa7002011-12-13 16:59:34 +01002162static const struct dev_pm_ops mmci_dev_pm_ops = {
Ulf Hanssonf3737fa2014-01-23 01:11:33 +01002163 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2164 pm_runtime_force_resume)
Rafael J. Wysocki6ed23b82014-12-04 00:34:11 +01002165 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
Ulf Hansson48fa7002011-12-13 16:59:34 +01002166};
2167
Arvind Yadav88411de2017-08-23 22:00:49 +05302168static const struct amba_id mmci_ids[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002169 {
2170 .id = 0x00041180,
Pawel Moll768fbc12011-03-11 17:18:07 +00002171 .mask = 0xff0fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01002172 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002173 },
2174 {
Pawel Moll768fbc12011-03-11 17:18:07 +00002175 .id = 0x01041180,
2176 .mask = 0xff0fffff,
2177 .data = &variant_arm_extended_fifo,
2178 },
2179 {
Pawel Moll3a372982013-01-24 14:12:45 +01002180 .id = 0x02041180,
2181 .mask = 0xff0fffff,
2182 .data = &variant_arm_extended_fifo_hwfc,
2183 },
2184 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002185 .id = 0x00041181,
2186 .mask = 0x000fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01002187 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002188 },
Linus Walleijcc30d602009-01-04 15:18:54 +01002189 /* ST Micro variants */
2190 {
2191 .id = 0x00180180,
2192 .mask = 0x00ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01002193 .data = &variant_u300,
Linus Walleijcc30d602009-01-04 15:18:54 +01002194 },
2195 {
Linus Walleij34fd4212012-04-10 17:43:59 +01002196 .id = 0x10180180,
2197 .mask = 0xf0ffffff,
2198 .data = &variant_nomadik,
2199 },
2200 {
Linus Walleijcc30d602009-01-04 15:18:54 +01002201 .id = 0x00280180,
2202 .mask = 0x00ffffff,
Linus Walleij0bcb7ef2016-01-04 02:21:55 +01002203 .data = &variant_nomadik,
Rabin Vincent4956e102010-07-21 12:54:40 +01002204 },
2205 {
2206 .id = 0x00480180,
Philippe Langlais1784b152011-03-25 08:51:52 +01002207 .mask = 0xf0ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01002208 .data = &variant_ux500,
Linus Walleijcc30d602009-01-04 15:18:54 +01002209 },
Philippe Langlais1784b152011-03-25 08:51:52 +01002210 {
2211 .id = 0x10480180,
2212 .mask = 0xf0ffffff,
2213 .data = &variant_ux500v2,
2214 },
Patrice Chotard2a9d6c82018-01-18 15:34:21 +01002215 {
2216 .id = 0x00880180,
2217 .mask = 0x00ffffff,
2218 .data = &variant_stm32,
2219 },
Ludovic Barre46b723d2018-10-08 14:08:55 +02002220 {
2221 .id = 0x10153180,
2222 .mask = 0xf0ffffff,
2223 .data = &variant_stm32_sdmmc,
2224 },
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +01002225 /* Qualcomm variants */
2226 {
2227 .id = 0x00051180,
2228 .mask = 0x000fffff,
2229 .data = &variant_qcom,
2230 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002231 { 0, 0 },
2232};
2233
Dave Martin9f998352011-10-05 15:15:21 +01002234MODULE_DEVICE_TABLE(amba, mmci_ids);
2235
Linus Torvalds1da177e2005-04-16 15:20:36 -07002236static struct amba_driver mmci_driver = {
2237 .drv = {
2238 .name = DRIVER_NAME,
Ulf Hansson48fa7002011-12-13 16:59:34 +01002239 .pm = &mmci_dev_pm_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002240 },
2241 .probe = mmci_probe,
Bill Pemberton0433c142012-11-19 13:20:26 -05002242 .remove = mmci_remove,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002243 .id_table = mmci_ids,
2244};
2245
viresh kumar9e5ed092012-03-15 10:40:38 +01002246module_amba_driver(mmci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002247
Linus Torvalds1da177e2005-04-16 15:20:36 -07002248module_param(fmax, uint, 0444);
2249
2250MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
2251MODULE_LICENSE("GPL");