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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Pierre Ossman70f10482007-07-11 20:04:50 +02002 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
Russell Kingc8ebae32011-01-11 19:35:53 +00005 * Copyright (C) 2010 ST-Ericsson SA
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
Ulf Hanssonef289982014-03-17 13:56:32 +010016#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/interrupt.h>
Russell King613b1522011-01-30 21:06:53 +000018#include <linux/kernel.h>
Lee Jones000bc9d2012-04-16 10:18:43 +010019#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/highmem.h>
Nicolas Pitre019a5f52007-10-11 01:06:03 -040023#include <linux/log2.h>
Ulf Hansson70be2082013-01-07 15:35:06 +010024#include <linux/mmc/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/mmc/host.h>
Linus Walleij34177802010-10-19 12:43:58 +010026#include <linux/mmc/card.h>
Ulf Hanssond2762092014-03-17 13:56:19 +010027#include <linux/mmc/slot-gpio.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000028#include <linux/amba/bus.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000029#include <linux/clk.h>
Jens Axboebd6dee62007-10-24 09:01:09 +020030#include <linux/scatterlist.h>
Linus Walleij9ef986a2018-09-20 16:01:10 -070031#include <linux/of.h>
Linus Walleij34e84f32009-09-22 14:41:40 +010032#include <linux/regulator/consumer.h>
Russell Kingc8ebae32011-01-11 19:35:53 +000033#include <linux/dmaengine.h>
34#include <linux/dma-mapping.h>
35#include <linux/amba/mmci.h>
Russell King1c3be362011-08-14 09:17:05 +010036#include <linux/pm_runtime.h>
Viresh Kumar258aea72012-02-01 16:12:19 +053037#include <linux/types.h>
Linus Walleija9a83782012-10-29 14:39:30 +010038#include <linux/pinctrl/consumer.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Russell King7b09cda2005-07-01 12:02:59 +010040#include <asm/div64.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
43#include "mmci.h"
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +010044#include "mmci_qcom_dml.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
46#define DRIVER_NAME "mmci-pl18x"
47
Linus Torvalds1da177e2005-04-16 15:20:36 -070048static unsigned int fmax = 515633;
49
Rabin Vincent4956e102010-07-21 12:54:40 +010050static struct variant_data variant_arm = {
Rabin Vincent8301bb62010-08-09 12:57:30 +010051 .fifosize = 16 * 4,
52 .fifohalfsize = 8 * 4,
Rabin Vincent08458ef2010-07-21 12:55:59 +010053 .datalength_bits = 16,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010054 .pwrreg_powerup = MCI_PWR_UP,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +010055 .f_max = 100000000,
Ulf Hansson78782892014-06-13 13:21:38 +020056 .reversed_irq_handling = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +010057 .mmcimask1 = true,
Patrice Chotard7f7b5502018-01-18 15:34:18 +010058 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +010059 .opendrain = MCI_ROD,
Rabin Vincent4956e102010-07-21 12:54:40 +010060};
61
Pawel Moll768fbc12011-03-11 17:18:07 +000062static struct variant_data variant_arm_extended_fifo = {
63 .fifosize = 128 * 4,
64 .fifohalfsize = 64 * 4,
65 .datalength_bits = 16,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010066 .pwrreg_powerup = MCI_PWR_UP,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +010067 .f_max = 100000000,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +010068 .mmcimask1 = true,
Patrice Chotard7f7b5502018-01-18 15:34:18 +010069 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +010070 .opendrain = MCI_ROD,
Pawel Moll768fbc12011-03-11 17:18:07 +000071};
72
Pawel Moll3a372982013-01-24 14:12:45 +010073static struct variant_data variant_arm_extended_fifo_hwfc = {
74 .fifosize = 128 * 4,
75 .fifohalfsize = 64 * 4,
76 .clkreg_enable = MCI_ARM_HWFCEN,
77 .datalength_bits = 16,
78 .pwrreg_powerup = MCI_PWR_UP,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +010079 .f_max = 100000000,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +010080 .mmcimask1 = true,
Patrice Chotard7f7b5502018-01-18 15:34:18 +010081 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +010082 .opendrain = MCI_ROD,
Pawel Moll3a372982013-01-24 14:12:45 +010083};
84
Rabin Vincent4956e102010-07-21 12:54:40 +010085static struct variant_data variant_u300 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +010086 .fifosize = 16 * 4,
87 .fifohalfsize = 8 * 4,
Linus Walleij49ac2152011-03-04 14:54:16 +010088 .clkreg_enable = MCI_ST_U300_HWFCEN,
Srinivas Kandagatlae1412d82014-06-02 10:09:23 +010089 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Rabin Vincent08458ef2010-07-21 12:55:59 +010090 .datalength_bits = 16,
Linus Walleij5db3eee2016-10-25 11:06:05 +020091 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
Srinivas Kandagatlac7354132014-08-22 05:55:16 +010092 .st_sdio = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010093 .pwrreg_powerup = MCI_PWR_ON,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +010094 .f_max = 100000000,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +010095 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +010096 .pwrreg_clkgate = true,
Ulf Hansson1ff44432013-09-04 09:05:17 +010097 .pwrreg_nopower = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +010098 .mmcimask1 = true,
Patrice Chotard7f7b5502018-01-18 15:34:18 +010099 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100100 .opendrain = MCI_OD,
Rabin Vincent4956e102010-07-21 12:54:40 +0100101};
102
Linus Walleij34fd4212012-04-10 17:43:59 +0100103static struct variant_data variant_nomadik = {
104 .fifosize = 16 * 4,
105 .fifohalfsize = 8 * 4,
106 .clkreg = MCI_CLK_ENABLE,
Linus Walleijf5abc762016-01-04 02:22:08 +0100107 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Linus Walleij34fd4212012-04-10 17:43:59 +0100108 .datalength_bits = 24,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200109 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100110 .st_sdio = true,
Linus Walleij34fd4212012-04-10 17:43:59 +0100111 .st_clkdiv = true,
112 .pwrreg_powerup = MCI_PWR_ON,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +0100113 .f_max = 100000000,
Linus Walleij34fd4212012-04-10 17:43:59 +0100114 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100115 .pwrreg_clkgate = true,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100116 .pwrreg_nopower = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100117 .mmcimask1 = true,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100118 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100119 .opendrain = MCI_OD,
Linus Walleij34fd4212012-04-10 17:43:59 +0100120};
121
Rabin Vincent4956e102010-07-21 12:54:40 +0100122static struct variant_data variant_ux500 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +0100123 .fifosize = 30 * 4,
124 .fifohalfsize = 8 * 4,
Rabin Vincent4956e102010-07-21 12:54:40 +0100125 .clkreg = MCI_CLK_ENABLE,
Linus Walleij49ac2152011-03-04 14:54:16 +0100126 .clkreg_enable = MCI_ST_UX500_HWFCEN,
Srinivas Kandagatlae1412d82014-06-02 10:09:23 +0100127 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Srinivas Kandagatlae8740642014-06-02 10:09:30 +0100128 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
Rabin Vincent08458ef2010-07-21 12:55:59 +0100129 .datalength_bits = 24,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200130 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100131 .st_sdio = true,
Linus Walleijb70a67f2010-12-06 09:24:14 +0100132 .st_clkdiv = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100133 .pwrreg_powerup = MCI_PWR_ON,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +0100134 .f_max = 100000000,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100135 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100136 .pwrreg_clkgate = true,
Ulf Hansson01259622013-05-15 20:53:22 +0100137 .busy_detect = true,
Linus Walleij49adc0c2016-10-25 11:06:06 +0200138 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
139 .busy_detect_flag = MCI_ST_CARDBUSY,
140 .busy_detect_mask = MCI_ST_BUSYENDMASK,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100141 .pwrreg_nopower = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100142 .mmcimask1 = true,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100143 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100144 .opendrain = MCI_OD,
Rabin Vincent4956e102010-07-21 12:54:40 +0100145};
Linus Walleijb70a67f2010-12-06 09:24:14 +0100146
Philippe Langlais1784b152011-03-25 08:51:52 +0100147static struct variant_data variant_ux500v2 = {
148 .fifosize = 30 * 4,
149 .fifohalfsize = 8 * 4,
150 .clkreg = MCI_CLK_ENABLE,
151 .clkreg_enable = MCI_ST_UX500_HWFCEN,
Srinivas Kandagatlae1412d82014-06-02 10:09:23 +0100152 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Srinivas Kandagatlae8740642014-06-02 10:09:30 +0100153 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200154 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
Philippe Langlais1784b152011-03-25 08:51:52 +0100155 .datalength_bits = 24,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200156 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100157 .st_sdio = true,
Philippe Langlais1784b152011-03-25 08:51:52 +0100158 .st_clkdiv = true,
159 .blksz_datactrl16 = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100160 .pwrreg_powerup = MCI_PWR_ON,
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +0100161 .f_max = 100000000,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100162 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100163 .pwrreg_clkgate = true,
Ulf Hansson01259622013-05-15 20:53:22 +0100164 .busy_detect = true,
Linus Walleij49adc0c2016-10-25 11:06:06 +0200165 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
166 .busy_detect_flag = MCI_ST_CARDBUSY,
167 .busy_detect_mask = MCI_ST_BUSYENDMASK,
Ulf Hansson1ff44432013-09-04 09:05:17 +0100168 .pwrreg_nopower = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100169 .mmcimask1 = true,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100170 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100171 .opendrain = MCI_OD,
Philippe Langlais1784b152011-03-25 08:51:52 +0100172};
173
Patrice Chotard2a9d6c82018-01-18 15:34:21 +0100174static struct variant_data variant_stm32 = {
175 .fifosize = 32 * 4,
176 .fifohalfsize = 8 * 4,
177 .clkreg = MCI_CLK_ENABLE,
178 .clkreg_enable = MCI_ST_UX500_HWFCEN,
179 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
180 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
181 .datalength_bits = 24,
182 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
183 .st_sdio = true,
184 .st_clkdiv = true,
185 .pwrreg_powerup = MCI_PWR_ON,
186 .f_max = 48000000,
187 .pwrreg_clkgate = true,
188 .pwrreg_nopower = true,
189};
190
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +0100191static struct variant_data variant_qcom = {
192 .fifosize = 16 * 4,
193 .fifohalfsize = 8 * 4,
194 .clkreg = MCI_CLK_ENABLE,
195 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
196 MCI_QCOM_CLK_SELECT_IN_FBCLK,
197 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
198 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
Linus Walleij5db3eee2016-10-25 11:06:05 +0200199 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +0100200 .blksz_datactrl4 = true,
201 .datalength_bits = 24,
202 .pwrreg_powerup = MCI_PWR_UP,
203 .f_max = 208000000,
204 .explicit_mclk_control = true,
205 .qcom_fifo = true,
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100206 .qcom_dml = true,
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100207 .mmcimask1 = true,
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100208 .start_err = MCI_STARTBITERR,
Patrice Chotard11dfb972018-01-18 15:34:19 +0100209 .opendrain = MCI_ROD,
Ulf Hansson29aba072018-07-16 13:08:18 +0200210 .init = qcom_variant_init,
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +0100211};
212
Linus Walleij49adc0c2016-10-25 11:06:06 +0200213/* Busy detection for the ST Micro variant */
Ulf Hansson01259622013-05-15 20:53:22 +0100214static int mmci_card_busy(struct mmc_host *mmc)
215{
216 struct mmci_host *host = mmc_priv(mmc);
217 unsigned long flags;
218 int busy = 0;
219
Ulf Hansson01259622013-05-15 20:53:22 +0100220 spin_lock_irqsave(&host->lock, flags);
Linus Walleij49adc0c2016-10-25 11:06:06 +0200221 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
Ulf Hansson01259622013-05-15 20:53:22 +0100222 busy = 1;
223 spin_unlock_irqrestore(&host->lock, flags);
224
Ulf Hansson01259622013-05-15 20:53:22 +0100225 return busy;
226}
227
Linus Walleija6a64642009-09-14 12:56:14 +0100228/*
Ulf Hansson653a7612013-01-21 21:29:34 +0100229 * Validate mmc prerequisites
230 */
231static int mmci_validate_data(struct mmci_host *host,
232 struct mmc_data *data)
233{
234 if (!data)
235 return 0;
236
237 if (!is_power_of_2(data->blksz)) {
238 dev_err(mmc_dev(host->mmc),
239 "unsupported block size (%d bytes)\n", data->blksz);
240 return -EINVAL;
241 }
242
243 return 0;
244}
245
Ulf Hanssonf829c042013-09-04 09:01:15 +0100246static void mmci_reg_delay(struct mmci_host *host)
247{
248 /*
249 * According to the spec, at least three feedback clock cycles
250 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
251 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
252 * Worst delay time during card init is at 100 kHz => 30 us.
253 * Worst delay time when up and running is at 25 MHz => 120 ns.
254 */
255 if (host->cclk < 25000000)
256 udelay(30);
257 else
258 ndelay(120);
259}
260
Ulf Hansson653a7612013-01-21 21:29:34 +0100261/*
Linus Walleija6a64642009-09-14 12:56:14 +0100262 * This must be called with host->lock held
263 */
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100264static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
265{
266 if (host->clk_reg != clk) {
267 host->clk_reg = clk;
268 writel(clk, host->base + MMCICLOCK);
269 }
270}
271
272/*
273 * This must be called with host->lock held
274 */
275static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
276{
277 if (host->pwr_reg != pwr) {
278 host->pwr_reg = pwr;
279 writel(pwr, host->base + MMCIPOWER);
280 }
281}
282
283/*
284 * This must be called with host->lock held
285 */
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100286static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
287{
Linus Walleij49adc0c2016-10-25 11:06:06 +0200288 /* Keep busy mode in DPSM if enabled */
289 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
Ulf Hansson01259622013-05-15 20:53:22 +0100290
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100291 if (host->datactrl_reg != datactrl) {
292 host->datactrl_reg = datactrl;
293 writel(datactrl, host->base + MMCIDATACTRL);
294 }
295}
296
297/*
298 * This must be called with host->lock held
299 */
Linus Walleija6a64642009-09-14 12:56:14 +0100300static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
301{
Rabin Vincent4956e102010-07-21 12:54:40 +0100302 struct variant_data *variant = host->variant;
303 u32 clk = variant->clkreg;
Linus Walleija6a64642009-09-14 12:56:14 +0100304
Ulf Hanssonc58a8502013-05-13 15:40:03 +0100305 /* Make sure cclk reflects the current calculated clock */
306 host->cclk = 0;
307
Linus Walleija6a64642009-09-14 12:56:14 +0100308 if (desired) {
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +0100309 if (variant->explicit_mclk_control) {
310 host->cclk = host->mclk;
311 } else if (desired >= host->mclk) {
Linus Walleij991a86e2010-12-10 09:35:53 +0100312 clk = MCI_CLK_BYPASS;
Linus Walleij399bc482011-04-01 07:59:17 +0100313 if (variant->st_clkdiv)
314 clk |= MCI_ST_UX500_NEG_EDGE;
Linus Walleija6a64642009-09-14 12:56:14 +0100315 host->cclk = host->mclk;
Linus Walleijb70a67f2010-12-06 09:24:14 +0100316 } else if (variant->st_clkdiv) {
317 /*
318 * DB8500 TRM says f = mclk / (clkdiv + 2)
319 * => clkdiv = (mclk / f) - 2
320 * Round the divider up so we don't exceed the max
321 * frequency
322 */
323 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
324 if (clk >= 256)
325 clk = 255;
326 host->cclk = host->mclk / (clk + 2);
Linus Walleija6a64642009-09-14 12:56:14 +0100327 } else {
Linus Walleijb70a67f2010-12-06 09:24:14 +0100328 /*
329 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
330 * => clkdiv = mclk / (2 * f) - 1
331 */
Linus Walleija6a64642009-09-14 12:56:14 +0100332 clk = host->mclk / (2 * desired) - 1;
333 if (clk >= 256)
334 clk = 255;
335 host->cclk = host->mclk / (2 * (clk + 1));
336 }
Rabin Vincent4380c142010-07-21 12:55:18 +0100337
338 clk |= variant->clkreg_enable;
Linus Walleija6a64642009-09-14 12:56:14 +0100339 clk |= MCI_CLK_ENABLE;
340 /* This hasn't proven to be worthwhile */
341 /* clk |= MCI_CLK_PWRSAVE; */
342 }
343
Ulf Hanssonc58a8502013-05-13 15:40:03 +0100344 /* Set actual clock for debug */
345 host->mmc->actual_clock = host->cclk;
346
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100347 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
Linus Walleij771dc152010-04-08 07:38:52 +0100348 clk |= MCI_4BIT_BUS;
349 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
Srinivas Kandagatlae1412d82014-06-02 10:09:23 +0100350 clk |= variant->clkreg_8bit_bus_enable;
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100351
Seungwon Jeon6dad6c92014-03-14 21:12:13 +0900352 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
353 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
Srinivas Kandagatlae8740642014-06-02 10:09:30 +0100354 clk |= variant->clkreg_neg_edge_enable;
Ulf Hansson6dbb6ee2013-01-07 15:30:44 +0100355
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100356 mmci_write_clkreg(host, clk);
Linus Walleija6a64642009-09-14 12:56:14 +0100357}
358
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359static void
360mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
361{
362 writel(0, host->base + MMCICOMMAND);
363
Russell Kinge47c2222007-01-08 16:42:51 +0000364 BUG_ON(host->data);
365
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 host->mrq = NULL;
367 host->cmd = NULL;
368
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 mmc_request_done(host->mmc, mrq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370}
371
Linus Walleij2686b4b2010-10-19 12:39:48 +0100372static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
373{
374 void __iomem *base = host->base;
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100375 struct variant_data *variant = host->variant;
Linus Walleij2686b4b2010-10-19 12:39:48 +0100376
377 if (host->singleirq) {
378 unsigned int mask0 = readl(base + MMCIMASK0);
379
380 mask0 &= ~MCI_IRQ1MASK;
381 mask0 |= mask;
382
383 writel(mask0, base + MMCIMASK0);
384 }
385
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +0100386 if (variant->mmcimask1)
387 writel(mask, base + MMCIMASK1);
388
389 host->mask1_reg = mask;
Linus Walleij2686b4b2010-10-19 12:39:48 +0100390}
391
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392static void mmci_stop_data(struct mmci_host *host)
393{
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100394 mmci_write_datactrlreg(host, 0);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100395 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 host->data = NULL;
397}
398
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100399static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
400{
401 unsigned int flags = SG_MITER_ATOMIC;
402
403 if (data->flags & MMC_DATA_READ)
404 flags |= SG_MITER_TO_SG;
405 else
406 flags |= SG_MITER_FROM_SG;
407
408 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
409}
410
Russell Kingc8ebae32011-01-11 19:35:53 +0000411/*
412 * All the DMA operation mode stuff goes inside this ifdef.
413 * This assumes that you have a generic DMA device interface,
414 * no custom DMA interfaces are supported.
415 */
416#ifdef CONFIG_DMA_ENGINE
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500417static void mmci_dma_setup(struct mmci_host *host)
Russell Kingc8ebae32011-01-11 19:35:53 +0000418{
Russell Kingc8ebae32011-01-11 19:35:53 +0000419 const char *rxname, *txname;
Russell Kingc8ebae32011-01-11 19:35:53 +0000420
Lee Jones1fd83f02013-05-03 12:51:17 +0100421 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
422 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
Russell Kingc8ebae32011-01-11 19:35:53 +0000423
Per Forlin58c7ccb2011-07-01 18:55:24 +0200424 /* initialize pre request cookie */
425 host->next_data.cookie = 1;
426
Russell Kingc8ebae32011-01-11 19:35:53 +0000427 /*
428 * If only an RX channel is specified, the driver will
429 * attempt to use it bidirectionally, however if it is
430 * is specified but cannot be located, DMA will be disabled.
431 */
Lee Jones1fd83f02013-05-03 12:51:17 +0100432 if (host->dma_rx_channel && !host->dma_tx_channel)
Russell Kingc8ebae32011-01-11 19:35:53 +0000433 host->dma_tx_channel = host->dma_rx_channel;
Russell Kingc8ebae32011-01-11 19:35:53 +0000434
435 if (host->dma_rx_channel)
436 rxname = dma_chan_name(host->dma_rx_channel);
437 else
438 rxname = "none";
439
440 if (host->dma_tx_channel)
441 txname = dma_chan_name(host->dma_tx_channel);
442 else
443 txname = "none";
444
445 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
446 rxname, txname);
447
448 /*
449 * Limit the maximum segment size in any SG entry according to
450 * the parameters of the DMA engine device.
451 */
452 if (host->dma_tx_channel) {
453 struct device *dev = host->dma_tx_channel->device->dev;
454 unsigned int max_seg_size = dma_get_max_seg_size(dev);
455
456 if (max_seg_size < host->mmc->max_seg_size)
457 host->mmc->max_seg_size = max_seg_size;
458 }
459 if (host->dma_rx_channel) {
460 struct device *dev = host->dma_rx_channel->device->dev;
461 unsigned int max_seg_size = dma_get_max_seg_size(dev);
462
463 if (max_seg_size < host->mmc->max_seg_size)
464 host->mmc->max_seg_size = max_seg_size;
465 }
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100466
Ulf Hansson29aba072018-07-16 13:08:18 +0200467 if (host->ops && host->ops->dma_setup)
468 host->ops->dma_setup(host);
Russell Kingc8ebae32011-01-11 19:35:53 +0000469}
470
471/*
Bill Pemberton6e0ee712012-11-19 13:26:03 -0500472 * This is used in or so inline it
Russell Kingc8ebae32011-01-11 19:35:53 +0000473 * so it can be discarded.
474 */
475static inline void mmci_dma_release(struct mmci_host *host)
476{
Russell Kingc8ebae32011-01-11 19:35:53 +0000477 if (host->dma_rx_channel)
478 dma_release_channel(host->dma_rx_channel);
Ulf Hansson8c3a05b2014-05-20 06:45:54 +0200479 if (host->dma_tx_channel)
Russell Kingc8ebae32011-01-11 19:35:53 +0000480 dma_release_channel(host->dma_tx_channel);
481 host->dma_rx_channel = host->dma_tx_channel = NULL;
482}
483
484static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
485{
Ulf Hansson653a7612013-01-21 21:29:34 +0100486 struct dma_chan *chan;
Ulf Hansson653a7612013-01-21 21:29:34 +0100487
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200488 if (data->flags & MMC_DATA_READ)
Ulf Hansson653a7612013-01-21 21:29:34 +0100489 chan = host->dma_rx_channel;
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200490 else
Ulf Hansson653a7612013-01-21 21:29:34 +0100491 chan = host->dma_tx_channel;
Ulf Hansson653a7612013-01-21 21:29:34 +0100492
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200493 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
494 mmc_get_dma_dir(data));
Ulf Hansson653a7612013-01-21 21:29:34 +0100495}
496
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200497static void mmci_dma_data_error(struct mmci_host *host)
498{
Ludovic Barrecdea1942018-09-21 11:45:56 +0200499 if (!dma_inprogress(host))
500 return;
501
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200502 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
503 dmaengine_terminate_all(host->dma_current);
504 host->dma_in_progress = false;
505 host->dma_current = NULL;
506 host->dma_desc_current = NULL;
507 host->data->host_cookie = 0;
508
509 mmci_dma_unmap(host, host->data);
510}
511
Ulf Hansson653a7612013-01-21 21:29:34 +0100512static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
513{
Russell Kingc8ebae32011-01-11 19:35:53 +0000514 u32 status;
515 int i;
516
Ludovic Barrecdea1942018-09-21 11:45:56 +0200517 if (!dma_inprogress(host))
518 return;
519
Russell Kingc8ebae32011-01-11 19:35:53 +0000520 /* Wait up to 1ms for the DMA to complete */
521 for (i = 0; ; i++) {
522 status = readl(host->base + MMCISTATUS);
523 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
524 break;
525 udelay(10);
526 }
527
528 /*
529 * Check to see whether we still have some data left in the FIFO -
530 * this catches DMA controllers which are unable to monitor the
531 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
532 * contiguous buffers. On TX, we'll get a FIFO underrun error.
533 */
534 if (status & MCI_RXDATAAVLBLMASK) {
Ulf Hansson653a7612013-01-21 21:29:34 +0100535 mmci_dma_data_error(host);
Russell Kingc8ebae32011-01-11 19:35:53 +0000536 if (!data->error)
537 data->error = -EIO;
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200538 } else if (!data->host_cookie) {
Ulf Hansson653a7612013-01-21 21:29:34 +0100539 mmci_dma_unmap(host, data);
Ludovic Barre7b2a6d52018-09-21 11:45:55 +0200540 }
Russell Kingc8ebae32011-01-11 19:35:53 +0000541
542 /*
543 * Use of DMA with scatter-gather is impossible.
544 * Give up with DMA and switch back to PIO mode.
545 */
546 if (status & MCI_RXDATAAVLBLMASK) {
547 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
548 mmci_dma_release(host);
549 }
Ulf Hansson653a7612013-01-21 21:29:34 +0100550
Linus Walleije13934b2017-01-27 15:04:54 +0100551 host->dma_in_progress = false;
Ulf Hansson653a7612013-01-21 21:29:34 +0100552 host->dma_current = NULL;
553 host->dma_desc_current = NULL;
Russell Kingc8ebae32011-01-11 19:35:53 +0000554}
555
Ulf Hansson653a7612013-01-21 21:29:34 +0100556/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
557static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
558 struct dma_chan **dma_chan,
559 struct dma_async_tx_descriptor **dma_desc)
Russell Kingc8ebae32011-01-11 19:35:53 +0000560{
561 struct variant_data *variant = host->variant;
562 struct dma_slave_config conf = {
563 .src_addr = host->phybase + MMCIFIFO,
564 .dst_addr = host->phybase + MMCIFIFO,
565 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
566 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
567 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
568 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
Viresh Kumar258aea72012-02-01 16:12:19 +0530569 .device_fc = false,
Russell Kingc8ebae32011-01-11 19:35:53 +0000570 };
Russell Kingc8ebae32011-01-11 19:35:53 +0000571 struct dma_chan *chan;
572 struct dma_device *device;
573 struct dma_async_tx_descriptor *desc;
574 int nr_sg;
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100575 unsigned long flags = DMA_CTRL_ACK;
Russell Kingc8ebae32011-01-11 19:35:53 +0000576
Russell Kingc8ebae32011-01-11 19:35:53 +0000577 if (data->flags & MMC_DATA_READ) {
Vinod Koul05f57992011-10-14 10:45:11 +0530578 conf.direction = DMA_DEV_TO_MEM;
Russell Kingc8ebae32011-01-11 19:35:53 +0000579 chan = host->dma_rx_channel;
580 } else {
Vinod Koul05f57992011-10-14 10:45:11 +0530581 conf.direction = DMA_MEM_TO_DEV;
Russell Kingc8ebae32011-01-11 19:35:53 +0000582 chan = host->dma_tx_channel;
583 }
584
585 /* If there's no DMA channel, fall back to PIO */
586 if (!chan)
587 return -EINVAL;
588
589 /* If less than or equal to the fifo size, don't bother with DMA */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200590 if (data->blksz * data->blocks <= variant->fifosize)
Russell Kingc8ebae32011-01-11 19:35:53 +0000591 return -EINVAL;
592
593 device = chan->device;
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200594 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
595 mmc_get_dma_dir(data));
Russell Kingc8ebae32011-01-11 19:35:53 +0000596 if (nr_sg == 0)
597 return -EINVAL;
598
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100599 if (host->variant->qcom_dml)
600 flags |= DMA_PREP_INTERRUPT;
601
Russell Kingc8ebae32011-01-11 19:35:53 +0000602 dmaengine_slave_config(chan, &conf);
Alexandre Bounine16052822012-03-08 16:11:18 -0500603 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100604 conf.direction, flags);
Russell Kingc8ebae32011-01-11 19:35:53 +0000605 if (!desc)
606 goto unmap_exit;
607
Ulf Hansson653a7612013-01-21 21:29:34 +0100608 *dma_chan = chan;
609 *dma_desc = desc;
Russell Kingc8ebae32011-01-11 19:35:53 +0000610
Per Forlin58c7ccb2011-07-01 18:55:24 +0200611 return 0;
612
613 unmap_exit:
Heiner Kallweitfeeef092017-03-26 20:45:56 +0200614 dma_unmap_sg(device->dev, data->sg, data->sg_len,
615 mmc_get_dma_dir(data));
Per Forlin58c7ccb2011-07-01 18:55:24 +0200616 return -ENOMEM;
617}
618
Ulf Hansson653a7612013-01-21 21:29:34 +0100619static inline int mmci_dma_prep_data(struct mmci_host *host,
620 struct mmc_data *data)
621{
622 /* Check if next job is already prepared. */
623 if (host->dma_current && host->dma_desc_current)
624 return 0;
625
626 /* No job were prepared thus do it now. */
627 return __mmci_dma_prep_data(host, data, &host->dma_current,
628 &host->dma_desc_current);
629}
630
631static inline int mmci_dma_prep_next(struct mmci_host *host,
632 struct mmc_data *data)
633{
634 struct mmci_host_next *nd = &host->next_data;
635 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
636}
637
Per Forlin58c7ccb2011-07-01 18:55:24 +0200638static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
639{
640 int ret;
641 struct mmc_data *data = host->data;
642
Ulf Hansson653a7612013-01-21 21:29:34 +0100643 ret = mmci_dma_prep_data(host, host->data);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200644 if (ret)
645 return ret;
646
647 /* Okay, go for it. */
Russell Kingc8ebae32011-01-11 19:35:53 +0000648 dev_vdbg(mmc_dev(host->mmc),
649 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
650 data->sg_len, data->blksz, data->blocks, data->flags);
Linus Walleije13934b2017-01-27 15:04:54 +0100651 host->dma_in_progress = true;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200652 dmaengine_submit(host->dma_desc_current);
653 dma_async_issue_pending(host->dma_current);
Russell Kingc8ebae32011-01-11 19:35:53 +0000654
Srinivas Kandagatla9cb15142014-07-29 03:50:30 +0100655 if (host->variant->qcom_dml)
656 dml_start_xfer(host, data);
657
Russell Kingc8ebae32011-01-11 19:35:53 +0000658 datactrl |= MCI_DPSM_DMAENABLE;
659
660 /* Trigger the DMA transfer */
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100661 mmci_write_datactrlreg(host, datactrl);
Russell Kingc8ebae32011-01-11 19:35:53 +0000662
663 /*
664 * Let the MMCI say when the data is ended and it's time
665 * to fire next DMA request. When that happens, MMCI will
666 * call mmci_data_end()
667 */
668 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
669 host->base + MMCIMASK0);
670 return 0;
Russell Kingc8ebae32011-01-11 19:35:53 +0000671}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200672
673static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
674{
675 struct mmci_host_next *next = &host->next_data;
676
Ulf Hansson653a7612013-01-21 21:29:34 +0100677 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
678 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
Per Forlin58c7ccb2011-07-01 18:55:24 +0200679
680 host->dma_desc_current = next->dma_desc;
681 host->dma_current = next->dma_chan;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200682 next->dma_desc = NULL;
683 next->dma_chan = NULL;
684}
685
Linus Walleijd3c6aac2016-11-23 11:02:24 +0100686static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
Per Forlin58c7ccb2011-07-01 18:55:24 +0200687{
688 struct mmci_host *host = mmc_priv(mmc);
689 struct mmc_data *data = mrq->data;
690 struct mmci_host_next *nd = &host->next_data;
691
692 if (!data)
693 return;
694
Ulf Hansson653a7612013-01-21 21:29:34 +0100695 BUG_ON(data->host_cookie);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200696
Ulf Hansson653a7612013-01-21 21:29:34 +0100697 if (mmci_validate_data(host, data))
698 return;
699
700 if (!mmci_dma_prep_next(host, data))
701 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200702}
703
704static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
705 int err)
706{
707 struct mmci_host *host = mmc_priv(mmc);
708 struct mmc_data *data = mrq->data;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200709
Ulf Hansson653a7612013-01-21 21:29:34 +0100710 if (!data || !data->host_cookie)
Per Forlin58c7ccb2011-07-01 18:55:24 +0200711 return;
712
Ulf Hansson653a7612013-01-21 21:29:34 +0100713 mmci_dma_unmap(host, data);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200714
Ulf Hansson653a7612013-01-21 21:29:34 +0100715 if (err) {
716 struct mmci_host_next *next = &host->next_data;
717 struct dma_chan *chan;
718 if (data->flags & MMC_DATA_READ)
719 chan = host->dma_rx_channel;
720 else
721 chan = host->dma_tx_channel;
722 dmaengine_terminate_all(chan);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200723
Srinivas Kandagatlab5c16a62014-10-08 12:25:17 +0100724 if (host->dma_desc_current == next->dma_desc)
725 host->dma_desc_current = NULL;
726
Linus Walleije13934b2017-01-27 15:04:54 +0100727 if (host->dma_current == next->dma_chan) {
728 host->dma_in_progress = false;
Srinivas Kandagatlab5c16a62014-10-08 12:25:17 +0100729 host->dma_current = NULL;
Linus Walleije13934b2017-01-27 15:04:54 +0100730 }
Srinivas Kandagatlab5c16a62014-10-08 12:25:17 +0100731
Ulf Hansson653a7612013-01-21 21:29:34 +0100732 next->dma_desc = NULL;
733 next->dma_chan = NULL;
Srinivas Kandagatlab5c16a62014-10-08 12:25:17 +0100734 data->host_cookie = 0;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200735 }
736}
737
Russell Kingc8ebae32011-01-11 19:35:53 +0000738#else
739/* Blank functions if the DMA engine is not available */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200740static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
741{
742}
Russell Kingc8ebae32011-01-11 19:35:53 +0000743static inline void mmci_dma_setup(struct mmci_host *host)
744{
745}
746
747static inline void mmci_dma_release(struct mmci_host *host)
748{
749}
750
Ulf Hansson653a7612013-01-21 21:29:34 +0100751static inline void mmci_dma_finalize(struct mmci_host *host,
752 struct mmc_data *data)
753{
754}
755
Russell Kingc8ebae32011-01-11 19:35:53 +0000756static inline void mmci_dma_data_error(struct mmci_host *host)
757{
758}
759
760static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
761{
762 return -ENOSYS;
763}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200764
765#define mmci_pre_request NULL
766#define mmci_post_request NULL
767
Russell Kingc8ebae32011-01-11 19:35:53 +0000768#endif
769
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
771{
Rabin Vincent8301bb62010-08-09 12:57:30 +0100772 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773 unsigned int datactrl, timeout, irqmask;
Russell King7b09cda2005-07-01 12:02:59 +0100774 unsigned long long clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 void __iomem *base;
Russell King3bc87f22006-08-27 13:51:28 +0100776 int blksz_bits;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777
Linus Walleij64de0282010-02-19 01:09:10 +0100778 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
779 data->blksz, data->blocks, data->flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780
781 host->data = data;
Rabin Vincent528320d2010-07-21 12:49:49 +0100782 host->size = data->blksz * data->blocks;
Russell King51d43752011-01-27 10:56:52 +0000783 data->bytes_xfered = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784
Russell King7b09cda2005-07-01 12:02:59 +0100785 clks = (unsigned long long)data->timeout_ns * host->cclk;
Srinivas Kandagatlac4a35762014-06-02 10:08:39 +0100786 do_div(clks, NSEC_PER_SEC);
Russell King7b09cda2005-07-01 12:02:59 +0100787
788 timeout = data->timeout_clks + (unsigned int)clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789
790 base = host->base;
791 writel(timeout, base + MMCIDATATIMER);
792 writel(host->size, base + MMCIDATALENGTH);
793
Russell King3bc87f22006-08-27 13:51:28 +0100794 blksz_bits = ffs(data->blksz) - 1;
795 BUG_ON(1 << blksz_bits != data->blksz);
796
Philippe Langlais1784b152011-03-25 08:51:52 +0100797 if (variant->blksz_datactrl16)
798 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
Srinivas Kandagatlaff783232014-06-02 10:09:06 +0100799 else if (variant->blksz_datactrl4)
800 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
Philippe Langlais1784b152011-03-25 08:51:52 +0100801 else
802 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
Russell Kingc8ebae32011-01-11 19:35:53 +0000803
804 if (data->flags & MMC_DATA_READ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805 datactrl |= MCI_DPSM_DIRECTION;
Russell Kingc8ebae32011-01-11 19:35:53 +0000806
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100807 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
808 u32 clk;
Ulf Hansson7258db72011-12-13 17:05:28 +0100809
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100810 datactrl |= variant->datactrl_mask_sdio;
Ulf Hansson06c1a122012-10-12 14:01:50 +0100811
Srinivas Kandagatlac7354132014-08-22 05:55:16 +0100812 /*
813 * The ST Micro variant for SDIO small write transfers
814 * needs to have clock H/W flow control disabled,
815 * otherwise the transfer will not start. The threshold
816 * depends on the rate of MCLK.
817 */
818 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
819 (host->size < 8 ||
820 (host->size <= 8 && host->mclk > 50000000)))
821 clk = host->clk_reg & ~variant->clkreg_enable;
822 else
823 clk = host->clk_reg | variant->clkreg_enable;
824
825 mmci_write_clkreg(host, clk);
826 }
Ulf Hansson06c1a122012-10-12 14:01:50 +0100827
Seungwon Jeon6dad6c92014-03-14 21:12:13 +0900828 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
829 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
Srinivas Kandagatlae17dca22014-06-02 10:09:15 +0100830 datactrl |= variant->datactrl_mask_ddrmode;
Ulf Hansson6dbb6ee2013-01-07 15:30:44 +0100831
Russell Kingc8ebae32011-01-11 19:35:53 +0000832 /*
833 * Attempt to use DMA operation mode, if this
834 * should fail, fall back to PIO mode
835 */
836 if (!mmci_dma_start_data(host, datactrl))
837 return;
838
839 /* IRQ mode, map the SG list for CPU reading/writing */
840 mmci_init_sg(host, data);
841
842 if (data->flags & MMC_DATA_READ) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 irqmask = MCI_RXFIFOHALFFULLMASK;
Russell King0425a142006-02-16 16:48:31 +0000844
845 /*
Russell Kingc4d877c2011-01-27 09:50:13 +0000846 * If we have less than the fifo 'half-full' threshold to
847 * transfer, trigger a PIO interrupt as soon as any data
848 * is available.
Russell King0425a142006-02-16 16:48:31 +0000849 */
Russell Kingc4d877c2011-01-27 09:50:13 +0000850 if (host->size < variant->fifohalfsize)
Russell King0425a142006-02-16 16:48:31 +0000851 irqmask |= MCI_RXDATAAVLBLMASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 } else {
853 /*
854 * We don't actually need to include "FIFO empty" here
855 * since its implicit in "FIFO half empty".
856 */
857 irqmask = MCI_TXFIFOHALFEMPTYMASK;
858 }
859
Ulf Hansson9cc639a2013-05-15 20:48:23 +0100860 mmci_write_datactrlreg(host, datactrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100862 mmci_set_mask1(host, irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863}
864
865static void
866mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
867{
868 void __iomem *base = host->base;
869
Linus Walleij64de0282010-02-19 01:09:10 +0100870 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 cmd->opcode, cmd->arg, cmd->flags);
872
873 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
874 writel(0, base + MMCICOMMAND);
Srinivas Kandagatla6adb2a82014-06-02 10:08:57 +0100875 mmci_reg_delay(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 }
877
878 c |= cmd->opcode | MCI_CPSM_ENABLE;
Russell Kinge9225172006-02-02 12:23:12 +0000879 if (cmd->flags & MMC_RSP_PRESENT) {
880 if (cmd->flags & MMC_RSP_136)
881 c |= MCI_CPSM_LONGRSP;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882 c |= MCI_CPSM_RESPONSE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 }
884 if (/*interrupt*/0)
885 c |= MCI_CPSM_INTERRUPT;
886
Srinivas Kandagatlaae7b0062014-06-02 10:09:39 +0100887 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
888 c |= host->variant->data_cmd_enable;
889
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 host->cmd = cmd;
891
892 writel(cmd->arg, base + MMCIARGUMENT);
893 writel(c, base + MMCICOMMAND);
894}
895
896static void
897mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
898 unsigned int status)
899{
Ulf Hansson1cb9da52014-06-12 14:42:23 +0200900 /* Make sure we have data to handle */
901 if (!data)
902 return;
903
Linus Walleijf20f8f212010-10-19 13:41:24 +0100904 /* First check for errors */
Patrice Chotard7f7b5502018-01-18 15:34:18 +0100905 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
906 host->variant->start_err |
907 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
Linus Walleij8cb28152011-01-24 15:22:13 +0100908 u32 remain, success;
Linus Walleijf20f8f212010-10-19 13:41:24 +0100909
Russell Kingc8ebae32011-01-11 19:35:53 +0000910 /* Terminate the DMA transfer */
Ludovic Barrecdea1942018-09-21 11:45:56 +0200911 mmci_dma_data_error(host);
Russell Kingc8ebae32011-01-11 19:35:53 +0000912
Russell Kingc8afc9d2011-02-04 09:19:46 +0000913 /*
914 * Calculate how far we are into the transfer. Note that
915 * the data counter gives the number of bytes transferred
916 * on the MMC bus, not on the host side. On reads, this
917 * can be as much as a FIFO-worth of data ahead. This
918 * matters for FIFO overruns only.
919 */
Linus Walleijf5a106d2011-01-27 17:44:34 +0100920 remain = readl(host->base + MMCIDATACNT);
Linus Walleij8cb28152011-01-24 15:22:13 +0100921 success = data->blksz * data->blocks - remain;
922
Russell Kingc8afc9d2011-02-04 09:19:46 +0000923 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
924 status, success);
Linus Walleij8cb28152011-01-24 15:22:13 +0100925 if (status & MCI_DATACRCFAIL) {
926 /* Last block was not successful */
Russell Kingc8afc9d2011-02-04 09:19:46 +0000927 success -= 1;
Pierre Ossman17b04292007-07-22 22:18:46 +0200928 data->error = -EILSEQ;
Linus Walleij8cb28152011-01-24 15:22:13 +0100929 } else if (status & MCI_DATATIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200930 data->error = -ETIMEDOUT;
Linus Walleij757df742011-06-30 15:10:21 +0100931 } else if (status & MCI_STARTBITERR) {
932 data->error = -ECOMM;
Russell Kingc8afc9d2011-02-04 09:19:46 +0000933 } else if (status & MCI_TXUNDERRUN) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200934 data->error = -EIO;
Russell Kingc8afc9d2011-02-04 09:19:46 +0000935 } else if (status & MCI_RXOVERRUN) {
936 if (success > host->variant->fifosize)
937 success -= host->variant->fifosize;
938 else
939 success = 0;
Linus Walleij8cb28152011-01-24 15:22:13 +0100940 data->error = -EIO;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100941 }
Russell King51d43752011-01-27 10:56:52 +0000942 data->bytes_xfered = round_down(success, data->blksz);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943 }
Linus Walleijf20f8f212010-10-19 13:41:24 +0100944
Linus Walleij8cb28152011-01-24 15:22:13 +0100945 if (status & MCI_DATABLOCKEND)
946 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
Linus Walleijf20f8f212010-10-19 13:41:24 +0100947
Russell Kingccff9b52011-01-30 21:03:50 +0000948 if (status & MCI_DATAEND || data->error) {
Ludovic Barrecdea1942018-09-21 11:45:56 +0200949 mmci_dma_finalize(host, data);
950
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951 mmci_stop_data(host);
952
Linus Walleij8cb28152011-01-24 15:22:13 +0100953 if (!data->error)
954 /* The error clause is handled above, success! */
Russell King51d43752011-01-27 10:56:52 +0000955 data->bytes_xfered = data->blksz * data->blocks;
Linus Walleijf20f8f212010-10-19 13:41:24 +0100956
Ulf Hansson024629c2013-05-13 15:40:56 +0100957 if (!data->stop || host->mrq->sbc) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958 mmci_request_end(host, data->mrq);
959 } else {
960 mmci_start_command(host, data->stop, 0);
961 }
962 }
963}
964
965static void
966mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
967 unsigned int status)
968{
969 void __iomem *base = host->base;
Linus Walleij49adc0c2016-10-25 11:06:06 +0200970 bool sbc;
Ulf Hanssonad82bfe2014-06-12 15:01:57 +0200971
972 if (!cmd)
973 return;
974
975 sbc = (cmd == host->mrq->sbc);
Ulf Hanssonad82bfe2014-06-12 15:01:57 +0200976
Linus Walleij49adc0c2016-10-25 11:06:06 +0200977 /*
978 * We need to be one of these interrupts to be considered worth
979 * handling. Note that we tag on any latent IRQs postponed
980 * due to waiting for busy status.
981 */
982 if (!((status|host->busy_status) &
983 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
Ulf Hanssonad82bfe2014-06-12 15:01:57 +0200984 return;
Ulf Hansson8d94b542014-01-13 16:49:31 +0100985
Linus Walleij49adc0c2016-10-25 11:06:06 +0200986 /*
987 * ST Micro variant: handle busy detection.
988 */
989 if (host->variant->busy_detect) {
990 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
Ulf Hansson8d94b542014-01-13 16:49:31 +0100991
Linus Walleij49adc0c2016-10-25 11:06:06 +0200992 /* We are busy with a command, return */
993 if (host->busy_status &&
994 (status & host->variant->busy_detect_flag))
995 return;
Ulf Hansson8d94b542014-01-13 16:49:31 +0100996
Linus Walleij49adc0c2016-10-25 11:06:06 +0200997 /*
998 * We were not busy, but we now got a busy response on
999 * something that was not an error, and we double-check
1000 * that the special busy status bit is still set before
1001 * proceeding.
1002 */
1003 if (!host->busy_status && busy_resp &&
1004 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1005 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001006
1007 /* Clear the busy start IRQ */
1008 writel(host->variant->busy_detect_mask,
1009 host->base + MMCICLEAR);
1010
1011 /* Unmask the busy end IRQ */
Linus Walleij49adc0c2016-10-25 11:06:06 +02001012 writel(readl(base + MMCIMASK0) |
1013 host->variant->busy_detect_mask,
1014 base + MMCIMASK0);
1015 /*
1016 * Now cache the last response status code (until
1017 * the busy bit goes low), and return.
1018 */
1019 host->busy_status =
1020 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1021 return;
1022 }
1023
1024 /*
1025 * At this point we are not busy with a command, we have
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001026 * not received a new busy request, clear and mask the busy
1027 * end IRQ and fall through to process the IRQ.
Linus Walleij49adc0c2016-10-25 11:06:06 +02001028 */
1029 if (host->busy_status) {
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001030
1031 writel(host->variant->busy_detect_mask,
1032 host->base + MMCICLEAR);
1033
Linus Walleij49adc0c2016-10-25 11:06:06 +02001034 writel(readl(base + MMCIMASK0) &
1035 ~host->variant->busy_detect_mask,
1036 base + MMCIMASK0);
1037 host->busy_status = 0;
1038 }
Ulf Hansson8d94b542014-01-13 16:49:31 +01001039 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040
1041 host->cmd = NULL;
1042
Linus Torvalds1da177e2005-04-16 15:20:36 -07001043 if (status & MCI_CMDTIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +02001044 cmd->error = -ETIMEDOUT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
Pierre Ossman17b04292007-07-22 22:18:46 +02001046 cmd->error = -EILSEQ;
Russell King - ARM Linux9047b432011-01-11 16:35:56 +00001047 } else {
1048 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1049 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1050 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1051 cmd->resp[3] = readl(base + MMCIRESPONSE3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 }
1053
Ulf Hansson024629c2013-05-13 15:40:56 +01001054 if ((!sbc && !cmd->data) || cmd->error) {
Ulf Hansson3b6e3c72011-12-13 16:58:43 +01001055 if (host->data) {
1056 /* Terminate the DMA transfer */
Ludovic Barrecdea1942018-09-21 11:45:56 +02001057 mmci_dma_data_error(host);
Ludovic Barre7b2a6d52018-09-21 11:45:55 +02001058
Russell Kinge47c2222007-01-08 16:42:51 +00001059 mmci_stop_data(host);
Ulf Hansson3b6e3c72011-12-13 16:58:43 +01001060 }
Ulf Hansson024629c2013-05-13 15:40:56 +01001061 mmci_request_end(host, host->mrq);
1062 } else if (sbc) {
1063 mmci_start_command(host, host->mrq->cmd, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
1065 mmci_start_data(host, cmd->data);
1066 }
1067}
1068
Srinivas Kandagatla9c34b732014-06-02 10:10:04 +01001069static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1070{
1071 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1072}
1073
1074static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1075{
1076 /*
1077 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1078 * from the fifo range should be used
1079 */
1080 if (status & MCI_RXFIFOHALFFULL)
1081 return host->variant->fifohalfsize;
1082 else if (status & MCI_RXDATAAVLBL)
1083 return 4;
1084
1085 return 0;
1086}
1087
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1089{
1090 void __iomem *base = host->base;
1091 char *ptr = buffer;
Srinivas Kandagatla9c34b732014-06-02 10:10:04 +01001092 u32 status = readl(host->base + MMCISTATUS);
Linus Walleij26eed9a2008-04-26 23:39:44 +01001093 int host_remain = host->size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094
1095 do {
Srinivas Kandagatla9c34b732014-06-02 10:10:04 +01001096 int count = host->get_rx_fifocnt(host, status, host_remain);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097
1098 if (count > remain)
1099 count = remain;
1100
1101 if (count <= 0)
1102 break;
1103
Ulf Hansson393e5e22011-12-13 17:08:04 +01001104 /*
1105 * SDIO especially may want to send something that is
1106 * not divisible by 4 (as opposed to card sectors
1107 * etc). Therefore make sure to always read the last bytes
1108 * while only doing full 32-bit reads towards the FIFO.
1109 */
1110 if (unlikely(count & 0x3)) {
1111 if (count < 4) {
1112 unsigned char buf[4];
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001113 ioread32_rep(base + MMCIFIFO, buf, 1);
Ulf Hansson393e5e22011-12-13 17:08:04 +01001114 memcpy(ptr, buf, count);
1115 } else {
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001116 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
Ulf Hansson393e5e22011-12-13 17:08:04 +01001117 count &= ~0x3;
1118 }
1119 } else {
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001120 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
Ulf Hansson393e5e22011-12-13 17:08:04 +01001121 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122
1123 ptr += count;
1124 remain -= count;
Linus Walleij26eed9a2008-04-26 23:39:44 +01001125 host_remain -= count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126
1127 if (remain == 0)
1128 break;
1129
1130 status = readl(base + MMCISTATUS);
1131 } while (status & MCI_RXDATAAVLBL);
1132
1133 return ptr - buffer;
1134}
1135
1136static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1137{
Rabin Vincent8301bb62010-08-09 12:57:30 +01001138 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139 void __iomem *base = host->base;
1140 char *ptr = buffer;
1141
1142 do {
1143 unsigned int count, maxcnt;
1144
Rabin Vincent8301bb62010-08-09 12:57:30 +01001145 maxcnt = status & MCI_TXFIFOEMPTY ?
1146 variant->fifosize : variant->fifohalfsize;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147 count = min(remain, maxcnt);
1148
Linus Walleij34177802010-10-19 12:43:58 +01001149 /*
Linus Walleij34177802010-10-19 12:43:58 +01001150 * SDIO especially may want to send something that is
1151 * not divisible by 4 (as opposed to card sectors
1152 * etc), and the FIFO only accept full 32-bit writes.
1153 * So compensate by adding +3 on the count, a single
1154 * byte become a 32bit write, 7 bytes will be two
1155 * 32bit writes etc.
1156 */
Davide Ciminaghi4b85da02012-12-10 14:47:21 +01001157 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158
1159 ptr += count;
1160 remain -= count;
1161
1162 if (remain == 0)
1163 break;
1164
1165 status = readl(base + MMCISTATUS);
1166 } while (status & MCI_TXFIFOHALFEMPTY);
1167
1168 return ptr - buffer;
1169}
1170
1171/*
1172 * PIO data transfer IRQ handler.
1173 */
David Howells7d12e782006-10-05 14:55:46 +01001174static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175{
1176 struct mmci_host *host = dev_id;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001177 struct sg_mapping_iter *sg_miter = &host->sg_miter;
Rabin Vincent8301bb62010-08-09 12:57:30 +01001178 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 void __iomem *base = host->base;
1180 u32 status;
1181
1182 status = readl(base + MMCISTATUS);
1183
Linus Walleij64de0282010-02-19 01:09:10 +01001184 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185
1186 do {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187 unsigned int remain, len;
1188 char *buffer;
1189
1190 /*
1191 * For write, we only need to test the half-empty flag
1192 * here - if the FIFO is completely empty, then by
1193 * definition it is more than half empty.
1194 *
1195 * For read, check for data available.
1196 */
1197 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1198 break;
1199
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001200 if (!sg_miter_next(sg_miter))
1201 break;
1202
1203 buffer = sg_miter->addr;
1204 remain = sg_miter->length;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205
1206 len = 0;
1207 if (status & MCI_RXACTIVE)
1208 len = mmci_pio_read(host, buffer, remain);
1209 if (status & MCI_TXACTIVE)
1210 len = mmci_pio_write(host, buffer, remain, status);
1211
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001212 sg_miter->consumed = len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214 host->size -= len;
1215 remain -= len;
1216
1217 if (remain)
1218 break;
1219
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220 status = readl(base + MMCISTATUS);
1221 } while (1);
1222
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001223 sg_miter_stop(sg_miter);
1224
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 /*
Russell Kingc4d877c2011-01-27 09:50:13 +00001226 * If we have less than the fifo 'half-full' threshold to transfer,
1227 * trigger a PIO interrupt as soon as any data is available.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228 */
Russell Kingc4d877c2011-01-27 09:50:13 +00001229 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
Linus Walleij2686b4b2010-10-19 12:39:48 +01001230 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231
1232 /*
1233 * If we run out of data, disable the data IRQs; this
1234 * prevents a race where the FIFO becomes empty before
1235 * the chip itself has disabled the data path, and
1236 * stops us racing with our data end IRQ.
1237 */
1238 if (host->size == 0) {
Linus Walleij2686b4b2010-10-19 12:39:48 +01001239 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1241 }
1242
1243 return IRQ_HANDLED;
1244}
1245
1246/*
1247 * Handle completion of command and data transfers.
1248 */
David Howells7d12e782006-10-05 14:55:46 +01001249static irqreturn_t mmci_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250{
1251 struct mmci_host *host = dev_id;
1252 u32 status;
1253 int ret = 0;
1254
1255 spin_lock(&host->lock);
1256
1257 do {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258 status = readl(host->base + MMCISTATUS);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001259
1260 if (host->singleirq) {
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +01001261 if (status & host->mask1_reg)
Linus Walleij2686b4b2010-10-19 12:39:48 +01001262 mmci_pio_irq(irq, dev_id);
1263
1264 status &= ~MCI_IRQ1MASK;
1265 }
1266
Ulf Hansson8d94b542014-01-13 16:49:31 +01001267 /*
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001268 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1269 * enabled) in mmci_cmd_irq() function where ST Micro busy
1270 * detection variant is handled. Considering the HW seems to be
1271 * triggering the IRQ on both edges while monitoring DAT0 for
1272 * busy completion and that same status bit is used to monitor
1273 * start and end of busy detection, special care must be taken
1274 * to make sure that both start and end interrupts are always
1275 * cleared one after the other.
Ulf Hansson8d94b542014-01-13 16:49:31 +01001276 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001277 status &= readl(host->base + MMCIMASK0);
Jean-Nicolas Graux5cad24d2017-02-07 12:12:41 +01001278 if (host->variant->busy_detect)
1279 writel(status & ~host->variant->busy_detect_mask,
1280 host->base + MMCICLEAR);
1281 else
1282 writel(status, host->base + MMCICLEAR);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283
Linus Walleij64de0282010-02-19 01:09:10 +01001284 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285
Ulf Hansson78782892014-06-13 13:21:38 +02001286 if (host->variant->reversed_irq_handling) {
1287 mmci_data_irq(host, host->data, status);
1288 mmci_cmd_irq(host, host->cmd, status);
1289 } else {
1290 mmci_cmd_irq(host, host->cmd, status);
1291 mmci_data_irq(host, host->data, status);
1292 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293
Linus Walleij49adc0c2016-10-25 11:06:06 +02001294 /*
1295 * Don't poll for busy completion in irq context.
1296 */
1297 if (host->variant->busy_detect && host->busy_status)
1298 status &= ~host->variant->busy_detect_flag;
Ulf Hansson8d94b542014-01-13 16:49:31 +01001299
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 ret = 1;
1301 } while (status);
1302
1303 spin_unlock(&host->lock);
1304
1305 return IRQ_RETVAL(ret);
1306}
1307
1308static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1309{
1310 struct mmci_host *host = mmc_priv(mmc);
Linus Walleij9e943022008-10-24 21:17:50 +01001311 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001312
1313 WARN_ON(host->mrq != NULL);
1314
Ulf Hansson653a7612013-01-21 21:29:34 +01001315 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1316 if (mrq->cmd->error) {
Pierre Ossman255d01a2007-07-24 20:38:53 +02001317 mmc_request_done(mmc, mrq);
1318 return;
1319 }
1320
Linus Walleij9e943022008-10-24 21:17:50 +01001321 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322
1323 host->mrq = mrq;
1324
Per Forlin58c7ccb2011-07-01 18:55:24 +02001325 if (mrq->data)
1326 mmci_get_next_data(host, mrq->data);
1327
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1329 mmci_start_data(host, mrq->data);
1330
Ulf Hansson024629c2013-05-13 15:40:56 +01001331 if (mrq->sbc)
1332 mmci_start_command(host, mrq->sbc, 0);
1333 else
1334 mmci_start_command(host, mrq->cmd, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335
Linus Walleij9e943022008-10-24 21:17:50 +01001336 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337}
1338
1339static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1340{
1341 struct mmci_host *host = mmc_priv(mmc);
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001342 struct variant_data *variant = host->variant;
Linus Walleija6a64642009-09-14 12:56:14 +01001343 u32 pwr = 0;
1344 unsigned long flags;
Lee Jonesdb90f912013-05-03 12:52:12 +01001345 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001346
Ulf Hanssonbc521812011-12-13 16:57:55 +01001347 if (host->plat->ios_handler &&
1348 host->plat->ios_handler(mmc_dev(mmc), ios))
1349 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1350
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351 switch (ios->power_mode) {
1352 case MMC_POWER_OFF:
Ulf Hansson599c1d52013-01-07 16:22:50 +01001353 if (!IS_ERR(mmc->supply.vmmc))
1354 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
Lee Jones237fb5e2013-01-31 11:27:52 +00001355
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001356 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
Lee Jones237fb5e2013-01-31 11:27:52 +00001357 regulator_disable(mmc->supply.vqmmc);
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001358 host->vqmmc_enabled = false;
1359 }
Lee Jones237fb5e2013-01-31 11:27:52 +00001360
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361 break;
1362 case MMC_POWER_UP:
Ulf Hansson599c1d52013-01-07 16:22:50 +01001363 if (!IS_ERR(mmc->supply.vmmc))
1364 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1365
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001366 /*
1367 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1368 * and instead uses MCI_PWR_ON so apply whatever value is
1369 * configured in the variant data.
1370 */
1371 pwr |= variant->pwrreg_powerup;
1372
1373 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 case MMC_POWER_ON:
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001375 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
Lee Jonesdb90f912013-05-03 12:52:12 +01001376 ret = regulator_enable(mmc->supply.vqmmc);
1377 if (ret < 0)
1378 dev_err(mmc_dev(mmc),
1379 "failed to enable vqmmc regulator\n");
Ulf Hansson7c0136e2013-05-14 13:53:10 +01001380 else
1381 host->vqmmc_enabled = true;
Lee Jonesdb90f912013-05-03 12:52:12 +01001382 }
Lee Jones237fb5e2013-01-31 11:27:52 +00001383
Linus Torvalds1da177e2005-04-16 15:20:36 -07001384 pwr |= MCI_PWR_ON;
1385 break;
1386 }
1387
Ulf Hansson4d1a3a02011-12-13 16:57:07 +01001388 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1389 /*
1390 * The ST Micro variant has some additional bits
1391 * indicating signal direction for the signals in
1392 * the SD/MMC bus and feedback-clock usage.
1393 */
Ulf Hansson4593df22014-03-21 10:13:05 +01001394 pwr |= host->pwr_reg_add;
Ulf Hansson4d1a3a02011-12-13 16:57:07 +01001395
1396 if (ios->bus_width == MMC_BUS_WIDTH_4)
1397 pwr &= ~MCI_ST_DATA74DIREN;
1398 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1399 pwr &= (~MCI_ST_DATA74DIREN &
1400 ~MCI_ST_DATA31DIREN &
1401 ~MCI_ST_DATA2DIREN);
1402 }
1403
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001404 if (variant->opendrain) {
1405 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1406 pwr |= variant->opendrain;
1407 } else {
1408 /*
1409 * If the variant cannot configure the pads by its own, then we
1410 * expect the pinctrl to be able to do that for us
1411 */
1412 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1413 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1414 else
1415 pinctrl_select_state(host->pinctrl, host->pins_default);
1416 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417
Ulf Hanssonf4670da2013-01-09 17:19:54 +01001418 /*
1419 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1420 * gating the clock, the MCI_PWR_ON bit is cleared.
1421 */
1422 if (!ios->clock && variant->pwrreg_clkgate)
1423 pwr &= ~MCI_PWR_ON;
1424
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001425 if (host->variant->explicit_mclk_control &&
1426 ios->clock != host->clock_cache) {
1427 ret = clk_set_rate(host->clk, ios->clock);
1428 if (ret < 0)
1429 dev_err(mmc_dev(host->mmc),
1430 "Error setting clock rate (%d)\n", ret);
1431 else
1432 host->mclk = clk_get_rate(host->clk);
1433 }
1434 host->clock_cache = ios->clock;
1435
Linus Walleija6a64642009-09-14 12:56:14 +01001436 spin_lock_irqsave(&host->lock, flags);
1437
1438 mmci_set_clkreg(host, ios->clock);
Ulf Hansson7437cfa2012-01-18 09:17:27 +01001439 mmci_write_pwrreg(host, pwr);
Ulf Hanssonf829c042013-09-04 09:01:15 +01001440 mmci_reg_delay(host);
Linus Walleija6a64642009-09-14 12:56:14 +01001441
1442 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443}
1444
Russell King89001442009-07-09 15:16:07 +01001445static int mmci_get_cd(struct mmc_host *mmc)
1446{
1447 struct mmci_host *host = mmc_priv(mmc);
Rabin Vincent29719442010-08-09 12:54:43 +01001448 struct mmci_platform_data *plat = host->plat;
Ulf Hanssond2762092014-03-17 13:56:19 +01001449 unsigned int status = mmc_gpio_get_cd(mmc);
Russell King89001442009-07-09 15:16:07 +01001450
Ulf Hanssond2762092014-03-17 13:56:19 +01001451 if (status == -ENOSYS) {
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001452 if (!plat->status)
1453 return 1; /* Assume always present */
1454
Rabin Vincent29719442010-08-09 12:54:43 +01001455 status = plat->status(mmc_dev(host->mmc));
Ulf Hanssond2762092014-03-17 13:56:19 +01001456 }
Russell King74bc8092010-07-29 15:58:59 +01001457 return status;
Russell King89001442009-07-09 15:16:07 +01001458}
1459
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001460static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1461{
1462 int ret = 0;
1463
1464 if (!IS_ERR(mmc->supply.vqmmc)) {
1465
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001466 switch (ios->signal_voltage) {
1467 case MMC_SIGNAL_VOLTAGE_330:
1468 ret = regulator_set_voltage(mmc->supply.vqmmc,
1469 2700000, 3600000);
1470 break;
1471 case MMC_SIGNAL_VOLTAGE_180:
1472 ret = regulator_set_voltage(mmc->supply.vqmmc,
1473 1700000, 1950000);
1474 break;
1475 case MMC_SIGNAL_VOLTAGE_120:
1476 ret = regulator_set_voltage(mmc->supply.vqmmc,
1477 1100000, 1300000);
1478 break;
1479 }
1480
1481 if (ret)
1482 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001483 }
1484
1485 return ret;
1486}
1487
Ulf Hansson01259622013-05-15 20:53:22 +01001488static struct mmc_host_ops mmci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001489 .request = mmci_request,
Per Forlin58c7ccb2011-07-01 18:55:24 +02001490 .pre_req = mmci_pre_request,
1491 .post_req = mmci_post_request,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492 .set_ios = mmci_set_ios,
Ulf Hanssond2762092014-03-17 13:56:19 +01001493 .get_ro = mmc_gpio_get_ro,
Russell King89001442009-07-09 15:16:07 +01001494 .get_cd = mmci_get_cd,
Ulf Hansson0f3ed7f2013-05-15 20:47:33 +01001495 .start_signal_voltage_switch = mmci_sig_volt_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496};
1497
Ulf Hansson78f87df2014-03-17 15:53:07 +01001498static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1499{
Ulf Hansson4593df22014-03-21 10:13:05 +01001500 struct mmci_host *host = mmc_priv(mmc);
Ulf Hansson78f87df2014-03-17 15:53:07 +01001501 int ret = mmc_of_parse(mmc);
Lee Jones000bc9d2012-04-16 10:18:43 +01001502
Ulf Hansson78f87df2014-03-17 15:53:07 +01001503 if (ret)
1504 return ret;
Lee Jones000bc9d2012-04-16 10:18:43 +01001505
Ulf Hansson4593df22014-03-21 10:13:05 +01001506 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1507 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1508 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1509 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1510 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1511 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1512 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1513 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1514 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1515 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1516 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1517 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1518
Lee Jones000bc9d2012-04-16 10:18:43 +01001519 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
Ulf Hansson78f87df2014-03-17 15:53:07 +01001520 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
Lee Jones000bc9d2012-04-16 10:18:43 +01001521 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
Ulf Hansson78f87df2014-03-17 15:53:07 +01001522 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
Lee Jones000bc9d2012-04-16 10:18:43 +01001523
Ulf Hansson78f87df2014-03-17 15:53:07 +01001524 return 0;
Lee Jones000bc9d2012-04-16 10:18:43 +01001525}
Lee Jones000bc9d2012-04-16 10:18:43 +01001526
Bill Pembertonc3be1ef2012-11-19 13:23:06 -05001527static int mmci_probe(struct amba_device *dev,
Russell Kingaa25afa2011-02-19 15:55:00 +00001528 const struct amba_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001529{
Linus Walleij6ef297f2009-09-22 14:29:36 +01001530 struct mmci_platform_data *plat = dev->dev.platform_data;
Lee Jones000bc9d2012-04-16 10:18:43 +01001531 struct device_node *np = dev->dev.of_node;
Rabin Vincent4956e102010-07-21 12:54:40 +01001532 struct variant_data *variant = id->data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001533 struct mmci_host *host;
1534 struct mmc_host *mmc;
1535 int ret;
1536
Lee Jones000bc9d2012-04-16 10:18:43 +01001537 /* Must have platform data or Device Tree. */
1538 if (!plat && !np) {
1539 dev_err(&dev->dev, "No plat data or DT found\n");
1540 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541 }
1542
Lee Jonesb9b52912012-06-12 10:49:51 +01001543 if (!plat) {
1544 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1545 if (!plat)
1546 return -ENOMEM;
1547 }
1548
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
Ulf Hanssonef289982014-03-17 13:56:32 +01001550 if (!mmc)
1551 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001552
Ulf Hansson78f87df2014-03-17 15:53:07 +01001553 ret = mmci_of_parse(np, mmc);
1554 if (ret)
1555 goto host_free;
1556
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557 host = mmc_priv(mmc);
Rabin Vincent4ea580f2009-04-17 08:44:19 +05301558 host->mmc = mmc;
Russell King012b7d32009-07-09 15:13:56 +01001559
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001560 /*
1561 * Some variant (STM32) doesn't have opendrain bit, nevertheless
1562 * pins can be set accordingly using pinctrl
1563 */
1564 if (!variant->opendrain) {
1565 host->pinctrl = devm_pinctrl_get(&dev->dev);
1566 if (IS_ERR(host->pinctrl)) {
1567 dev_err(&dev->dev, "failed to get pinctrl");
Wei Yongjun310eb252018-01-23 02:09:13 +00001568 ret = PTR_ERR(host->pinctrl);
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001569 goto host_free;
1570 }
1571
1572 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1573 PINCTRL_STATE_DEFAULT);
1574 if (IS_ERR(host->pins_default)) {
1575 dev_err(mmc_dev(mmc), "Can't select default pins\n");
Wei Yongjun310eb252018-01-23 02:09:13 +00001576 ret = PTR_ERR(host->pins_default);
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001577 goto host_free;
1578 }
1579
1580 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1581 MMCI_PINCTRL_STATE_OPENDRAIN);
1582 if (IS_ERR(host->pins_opendrain)) {
1583 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
Wei Yongjun310eb252018-01-23 02:09:13 +00001584 ret = PTR_ERR(host->pins_opendrain);
Patrice Chotardf9bb3042018-01-18 15:34:20 +01001585 goto host_free;
1586 }
1587 }
1588
Russell King012b7d32009-07-09 15:13:56 +01001589 host->hw_designer = amba_manf(dev);
1590 host->hw_revision = amba_rev(dev);
Linus Walleij64de0282010-02-19 01:09:10 +01001591 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1592 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
Russell King012b7d32009-07-09 15:13:56 +01001593
Ulf Hansson665ba562013-05-13 15:39:17 +01001594 host->clk = devm_clk_get(&dev->dev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001595 if (IS_ERR(host->clk)) {
1596 ret = PTR_ERR(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597 goto host_free;
1598 }
1599
Julia Lawallac940932012-08-26 16:00:59 +00001600 ret = clk_prepare_enable(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601 if (ret)
Ulf Hansson665ba562013-05-13 15:39:17 +01001602 goto host_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603
Srinivas Kandagatla9c34b732014-06-02 10:10:04 +01001604 if (variant->qcom_fifo)
1605 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1606 else
1607 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1608
Linus Torvalds1da177e2005-04-16 15:20:36 -07001609 host->plat = plat;
Rabin Vincent4956e102010-07-21 12:54:40 +01001610 host->variant = variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 host->mclk = clk_get_rate(host->clk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001612 /*
1613 * According to the spec, mclk is max 100 MHz,
1614 * so we try to adjust the clock down to this,
1615 * (if possible).
1616 */
Srinivas Kandagatladc6500b2014-06-02 10:09:47 +01001617 if (host->mclk > variant->f_max) {
1618 ret = clk_set_rate(host->clk, variant->f_max);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001619 if (ret < 0)
1620 goto clk_disable;
1621 host->mclk = clk_get_rate(host->clk);
Linus Walleij64de0282010-02-19 01:09:10 +01001622 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1623 host->mclk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001624 }
Ulf Hanssonef289982014-03-17 13:56:32 +01001625
Russell Kingc8ebae32011-01-11 19:35:53 +00001626 host->phybase = dev->res.start;
Ulf Hanssonef289982014-03-17 13:56:32 +01001627 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1628 if (IS_ERR(host->base)) {
1629 ret = PTR_ERR(host->base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630 goto clk_disable;
1631 }
1632
Ulf Hanssoned9067f2018-07-13 13:15:23 +02001633 if (variant->init)
1634 variant->init(host);
1635
Linus Walleij7f294e42011-07-08 09:57:15 +01001636 /*
1637 * The ARM and ST versions of the block have slightly different
1638 * clock divider equations which means that the minimum divider
1639 * differs too.
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001640 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
Linus Walleij7f294e42011-07-08 09:57:15 +01001641 */
1642 if (variant->st_clkdiv)
1643 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001644 else if (variant->explicit_mclk_control)
1645 mmc->f_min = clk_round_rate(host->clk, 100000);
Linus Walleij7f294e42011-07-08 09:57:15 +01001646 else
1647 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
Linus Walleij808d97c2010-04-08 07:39:38 +01001648 /*
Ulf Hansson78f87df2014-03-17 15:53:07 +01001649 * If no maximum operating frequency is supplied, fall back to use
1650 * the module parameter, which has a (low) default value in case it
1651 * is not specified. Either value must not exceed the clock rate into
Ulf Hansson5080a082014-03-21 10:46:39 +01001652 * the block, of course.
Linus Walleij808d97c2010-04-08 07:39:38 +01001653 */
Ulf Hansson78f87df2014-03-17 15:53:07 +01001654 if (mmc->f_max)
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001655 mmc->f_max = variant->explicit_mclk_control ?
1656 min(variant->f_max, mmc->f_max) :
1657 min(host->mclk, mmc->f_max);
Linus Walleij808d97c2010-04-08 07:39:38 +01001658 else
Srinivas Kandagatla3f4e6f72014-06-02 10:09:55 +01001659 mmc->f_max = variant->explicit_mclk_control ?
1660 fmax : min(host->mclk, fmax);
1661
1662
Linus Walleij64de0282010-02-19 01:09:10 +01001663 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1664
Ulf Hansson599c1d52013-01-07 16:22:50 +01001665 /* Get regulators and the supported OCR mask */
Bjorn Andersson9369c972015-03-24 18:39:49 -07001666 ret = mmc_regulator_get_supply(mmc);
Wolfram Sang51006952017-10-14 21:17:14 +02001667 if (ret)
Bjorn Andersson9369c972015-03-24 18:39:49 -07001668 goto clk_disable;
1669
Ulf Hansson599c1d52013-01-07 16:22:50 +01001670 if (!mmc->ocr_avail)
Linus Walleij34e84f32009-09-22 14:41:40 +01001671 mmc->ocr_avail = plat->ocr_mask;
Ulf Hansson599c1d52013-01-07 16:22:50 +01001672 else if (plat->ocr_mask)
1673 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1674
Ulf Hansson9dd8a8b2014-03-19 13:54:18 +01001675 /* We support these capabilities. */
1676 mmc->caps |= MMC_CAP_CMD23;
1677
Linus Walleij49adc0c2016-10-25 11:06:06 +02001678 /*
1679 * Enable busy detection.
1680 */
Ulf Hansson8d94b542014-01-13 16:49:31 +01001681 if (variant->busy_detect) {
1682 mmci_ops.card_busy = mmci_card_busy;
Linus Walleij49adc0c2016-10-25 11:06:06 +02001683 /*
1684 * Not all variants have a flag to enable busy detection
1685 * in the DPSM, but if they do, set it here.
1686 */
1687 if (variant->busy_dpsm_flag)
1688 mmci_write_datactrlreg(host,
1689 host->variant->busy_dpsm_flag);
Ulf Hansson8d94b542014-01-13 16:49:31 +01001690 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1691 mmc->max_busy_timeout = 0;
1692 }
1693
1694 mmc->ops = &mmci_ops;
1695
Ulf Hansson70be2082013-01-07 15:35:06 +01001696 /* We support these PM capabilities. */
Ulf Hansson78f87df2014-03-17 15:53:07 +01001697 mmc->pm_caps |= MMC_PM_KEEP_POWER;
Ulf Hansson70be2082013-01-07 15:35:06 +01001698
Linus Torvalds1da177e2005-04-16 15:20:36 -07001699 /*
1700 * We can do SGIO
1701 */
Martin K. Petersena36274e2010-09-10 01:33:59 -04001702 mmc->max_segs = NR_SG;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001703
1704 /*
Rabin Vincent08458ef2010-07-21 12:55:59 +01001705 * Since only a certain number of bits are valid in the data length
1706 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1707 * single request.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001708 */
Rabin Vincent08458ef2010-07-21 12:55:59 +01001709 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001710
1711 /*
1712 * Set the maximum segment size. Since we aren't doing DMA
1713 * (yet) we are only limited by the data length register.
1714 */
Pierre Ossman55db8902006-11-21 17:55:45 +01001715 mmc->max_seg_size = mmc->max_req_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001717 /*
1718 * Block size can be up to 2048 bytes, but must be a power of two.
1719 */
Will Deacon8f7f6b7e2012-02-24 11:25:21 +00001720 mmc->max_blk_size = 1 << 11;
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001721
Pierre Ossman55db8902006-11-21 17:55:45 +01001722 /*
Will Deacon8f7f6b7e2012-02-24 11:25:21 +00001723 * Limit the number of blocks transferred so that we don't overflow
1724 * the maximum request size.
Pierre Ossman55db8902006-11-21 17:55:45 +01001725 */
Will Deacon8f7f6b7e2012-02-24 11:25:21 +00001726 mmc->max_blk_count = mmc->max_req_size >> 11;
Pierre Ossman55db8902006-11-21 17:55:45 +01001727
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728 spin_lock_init(&host->lock);
1729
1730 writel(0, host->base + MMCIMASK0);
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +01001731
1732 if (variant->mmcimask1)
1733 writel(0, host->base + MMCIMASK1);
1734
Linus Torvalds1da177e2005-04-16 15:20:36 -07001735 writel(0xfff, host->base + MMCICLEAR);
1736
Linus Walleijce437aa2014-08-27 15:13:54 +02001737 /*
1738 * If:
1739 * - not using DT but using a descriptor table, or
1740 * - using a table of descriptors ALONGSIDE DT, or
1741 * look up these descriptors named "cd" and "wp" right here, fail
Linus Walleij9ef986a2018-09-20 16:01:10 -07001742 * silently of these do not exist
Linus Walleijce437aa2014-08-27 15:13:54 +02001743 */
1744 if (!np) {
Linus Walleij89168b42014-10-02 09:08:46 +02001745 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
Linus Walleij9ef986a2018-09-20 16:01:10 -07001746 if (ret == -EPROBE_DEFER)
1747 goto clk_disable;
Linus Walleijce437aa2014-08-27 15:13:54 +02001748
Linus Walleij89168b42014-10-02 09:08:46 +02001749 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
Linus Walleij9ef986a2018-09-20 16:01:10 -07001750 if (ret == -EPROBE_DEFER)
1751 goto clk_disable;
Russell King89001442009-07-09 15:16:07 +01001752 }
1753
Ulf Hanssonef289982014-03-17 13:56:32 +01001754 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1755 DRIVER_NAME " (cmd)", host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001756 if (ret)
Ulf Hanssonef289982014-03-17 13:56:32 +01001757 goto clk_disable;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001758
Russell Kingdfb85182012-05-03 11:33:15 +01001759 if (!dev->irq[1])
Linus Walleij2686b4b2010-10-19 12:39:48 +01001760 host->singleirq = true;
1761 else {
Ulf Hanssonef289982014-03-17 13:56:32 +01001762 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1763 IRQF_SHARED, DRIVER_NAME " (pio)", host);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001764 if (ret)
Ulf Hanssonef289982014-03-17 13:56:32 +01001765 goto clk_disable;
Linus Walleij2686b4b2010-10-19 12:39:48 +01001766 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767
Linus Walleij8cb28152011-01-24 15:22:13 +01001768 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769
1770 amba_set_drvdata(dev, mmc);
1771
Russell Kingc8ebae32011-01-11 19:35:53 +00001772 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1773 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1774 amba_rev(dev), (unsigned long long)dev->res.start,
1775 dev->irq[0], dev->irq[1]);
1776
1777 mmci_dma_setup(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001778
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001779 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1780 pm_runtime_use_autosuspend(&dev->dev);
Russell King1c3be362011-08-14 09:17:05 +01001781
Russell King8c11a942010-12-28 19:40:40 +00001782 mmc_add_host(mmc);
1783
Ulf Hansson6f2d3c82014-12-11 14:35:55 +01001784 pm_runtime_put(&dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785 return 0;
1786
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787 clk_disable:
Julia Lawallac940932012-08-26 16:00:59 +00001788 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001789 host_free:
1790 mmc_free_host(mmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001791 return ret;
1792}
1793
Bill Pemberton6e0ee712012-11-19 13:26:03 -05001794static int mmci_remove(struct amba_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795{
1796 struct mmc_host *mmc = amba_get_drvdata(dev);
1797
Linus Torvalds1da177e2005-04-16 15:20:36 -07001798 if (mmc) {
1799 struct mmci_host *host = mmc_priv(mmc);
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +01001800 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001801
Russell King1c3be362011-08-14 09:17:05 +01001802 /*
1803 * Undo pm_runtime_put() in probe. We use the _sync
1804 * version here so that we can access the primecell.
1805 */
1806 pm_runtime_get_sync(&dev->dev);
1807
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808 mmc_remove_host(mmc);
1809
1810 writel(0, host->base + MMCIMASK0);
Patrice Chotard6ea9cdf2018-01-18 15:34:17 +01001811
1812 if (variant->mmcimask1)
1813 writel(0, host->base + MMCIMASK1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814
1815 writel(0, host->base + MMCICOMMAND);
1816 writel(0, host->base + MMCIDATACTRL);
1817
Russell Kingc8ebae32011-01-11 19:35:53 +00001818 mmci_dma_release(host);
Julia Lawallac940932012-08-26 16:00:59 +00001819 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001820 mmc_free_host(mmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821 }
1822
1823 return 0;
1824}
1825
Ulf Hansson571dce42014-01-23 00:38:00 +01001826#ifdef CONFIG_PM
Ulf Hansson1ff44432013-09-04 09:05:17 +01001827static void mmci_save(struct mmci_host *host)
1828{
1829 unsigned long flags;
1830
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01001831 spin_lock_irqsave(&host->lock, flags);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001832
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01001833 writel(0, host->base + MMCIMASK0);
1834 if (host->variant->pwrreg_nopower) {
Ulf Hansson1ff44432013-09-04 09:05:17 +01001835 writel(0, host->base + MMCIDATACTRL);
1836 writel(0, host->base + MMCIPOWER);
1837 writel(0, host->base + MMCICLOCK);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001838 }
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01001839 mmci_reg_delay(host);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001840
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01001841 spin_unlock_irqrestore(&host->lock, flags);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001842}
1843
1844static void mmci_restore(struct mmci_host *host)
1845{
1846 unsigned long flags;
1847
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01001848 spin_lock_irqsave(&host->lock, flags);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001849
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01001850 if (host->variant->pwrreg_nopower) {
Ulf Hansson1ff44432013-09-04 09:05:17 +01001851 writel(host->clk_reg, host->base + MMCICLOCK);
1852 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1853 writel(host->pwr_reg, host->base + MMCIPOWER);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001854 }
Ulf Hansson42dcc89a2014-01-23 00:19:38 +01001855 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1856 mmci_reg_delay(host);
1857
1858 spin_unlock_irqrestore(&host->lock, flags);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001859}
1860
Ulf Hansson82592932013-01-09 11:15:26 +01001861static int mmci_runtime_suspend(struct device *dev)
1862{
1863 struct amba_device *adev = to_amba_device(dev);
1864 struct mmc_host *mmc = amba_get_drvdata(adev);
1865
1866 if (mmc) {
1867 struct mmci_host *host = mmc_priv(mmc);
Ulf Hanssone36bd9c62013-09-04 09:00:37 +01001868 pinctrl_pm_select_sleep_state(dev);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001869 mmci_save(host);
Ulf Hansson82592932013-01-09 11:15:26 +01001870 clk_disable_unprepare(host->clk);
1871 }
1872
1873 return 0;
1874}
1875
1876static int mmci_runtime_resume(struct device *dev)
1877{
1878 struct amba_device *adev = to_amba_device(dev);
1879 struct mmc_host *mmc = amba_get_drvdata(adev);
1880
1881 if (mmc) {
1882 struct mmci_host *host = mmc_priv(mmc);
1883 clk_prepare_enable(host->clk);
Ulf Hansson1ff44432013-09-04 09:05:17 +01001884 mmci_restore(host);
Ulf Hanssone36bd9c62013-09-04 09:00:37 +01001885 pinctrl_pm_select_default_state(dev);
Ulf Hansson82592932013-01-09 11:15:26 +01001886 }
1887
1888 return 0;
1889}
1890#endif
1891
Ulf Hansson48fa7002011-12-13 16:59:34 +01001892static const struct dev_pm_ops mmci_dev_pm_ops = {
Ulf Hanssonf3737fa2014-01-23 01:11:33 +01001893 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1894 pm_runtime_force_resume)
Rafael J. Wysocki6ed23b82014-12-04 00:34:11 +01001895 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
Ulf Hansson48fa7002011-12-13 16:59:34 +01001896};
1897
Arvind Yadav88411de2017-08-23 22:00:49 +05301898static const struct amba_id mmci_ids[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899 {
1900 .id = 0x00041180,
Pawel Moll768fbc12011-03-11 17:18:07 +00001901 .mask = 0xff0fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001902 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001903 },
1904 {
Pawel Moll768fbc12011-03-11 17:18:07 +00001905 .id = 0x01041180,
1906 .mask = 0xff0fffff,
1907 .data = &variant_arm_extended_fifo,
1908 },
1909 {
Pawel Moll3a372982013-01-24 14:12:45 +01001910 .id = 0x02041180,
1911 .mask = 0xff0fffff,
1912 .data = &variant_arm_extended_fifo_hwfc,
1913 },
1914 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001915 .id = 0x00041181,
1916 .mask = 0x000fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001917 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001918 },
Linus Walleijcc30d602009-01-04 15:18:54 +01001919 /* ST Micro variants */
1920 {
1921 .id = 0x00180180,
1922 .mask = 0x00ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001923 .data = &variant_u300,
Linus Walleijcc30d602009-01-04 15:18:54 +01001924 },
1925 {
Linus Walleij34fd4212012-04-10 17:43:59 +01001926 .id = 0x10180180,
1927 .mask = 0xf0ffffff,
1928 .data = &variant_nomadik,
1929 },
1930 {
Linus Walleijcc30d602009-01-04 15:18:54 +01001931 .id = 0x00280180,
1932 .mask = 0x00ffffff,
Linus Walleij0bcb7ef2016-01-04 02:21:55 +01001933 .data = &variant_nomadik,
Rabin Vincent4956e102010-07-21 12:54:40 +01001934 },
1935 {
1936 .id = 0x00480180,
Philippe Langlais1784b152011-03-25 08:51:52 +01001937 .mask = 0xf0ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001938 .data = &variant_ux500,
Linus Walleijcc30d602009-01-04 15:18:54 +01001939 },
Philippe Langlais1784b152011-03-25 08:51:52 +01001940 {
1941 .id = 0x10480180,
1942 .mask = 0xf0ffffff,
1943 .data = &variant_ux500v2,
1944 },
Patrice Chotard2a9d6c82018-01-18 15:34:21 +01001945 {
1946 .id = 0x00880180,
1947 .mask = 0x00ffffff,
1948 .data = &variant_stm32,
1949 },
Srinivas Kandagatla55b604a2014-06-02 10:10:13 +01001950 /* Qualcomm variants */
1951 {
1952 .id = 0x00051180,
1953 .mask = 0x000fffff,
1954 .data = &variant_qcom,
1955 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001956 { 0, 0 },
1957};
1958
Dave Martin9f998352011-10-05 15:15:21 +01001959MODULE_DEVICE_TABLE(amba, mmci_ids);
1960
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961static struct amba_driver mmci_driver = {
1962 .drv = {
1963 .name = DRIVER_NAME,
Ulf Hansson48fa7002011-12-13 16:59:34 +01001964 .pm = &mmci_dev_pm_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001965 },
1966 .probe = mmci_probe,
Bill Pemberton0433c142012-11-19 13:20:26 -05001967 .remove = mmci_remove,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001968 .id_table = mmci_ids,
1969};
1970
viresh kumar9e5ed092012-03-15 10:40:38 +01001971module_amba_driver(mmci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001972
Linus Torvalds1da177e2005-04-16 15:20:36 -07001973module_param(fmax, uint, 0444);
1974
1975MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1976MODULE_LICENSE("GPL");