Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 2 | /* |
| 3 | * linux/arch/arm/mach-mmp/time.c |
| 4 | * |
| 5 | * Support for clocksource and clockevents |
| 6 | * |
| 7 | * Copyright (C) 2008 Marvell International Ltd. |
| 8 | * All rights reserved. |
| 9 | * |
| 10 | * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> |
| 11 | * 2008-10-08: Bin Yang <bin.yang@marvell.com> |
| 12 | * |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 13 | * The timers module actually includes three timers, each timer with up to |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 14 | * three match comparators. Timer #0 is used here in free-running mode as |
| 15 | * the clock source, and match comparator #1 used as clock event device. |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/clockchips.h> |
Lubomir Rintel | f36797e | 2018-11-28 18:53:20 +0100 | [diff] [blame] | 22 | #include <linux/clk.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 23 | |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/irq.h> |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 26 | #include <linux/of.h> |
| 27 | #include <linux/of_address.h> |
| 28 | #include <linux/of_irq.h> |
Stephen Boyd | 38ff87f | 2013-06-01 23:39:40 -0700 | [diff] [blame] | 29 | #include <linux/sched_clock.h> |
Haojian Zhuang | 2f7e8fa | 2009-12-04 09:41:28 -0500 | [diff] [blame] | 30 | #include <asm/mach/time.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 31 | |
Arnd Bergmann | b501fd7 | 2014-04-15 20:38:32 +0200 | [diff] [blame] | 32 | #include "addr-map.h" |
| 33 | #include "regs-timers.h" |
| 34 | #include "regs-apbc.h" |
| 35 | #include "irqs.h" |
| 36 | #include "cputype.h" |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 37 | #include "clock.h" |
| 38 | |
| 39 | #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE |
| 40 | |
| 41 | #define MAX_DELTA (0xfffffffe) |
| 42 | #define MIN_DELTA (16) |
| 43 | |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 44 | static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; |
| 45 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 46 | /* |
| 47 | * FIXME: the timer needs some delay to stablize the counter capture |
| 48 | */ |
| 49 | static inline uint32_t timer_read(void) |
| 50 | { |
| 51 | int delay = 100; |
| 52 | |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 53 | __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 54 | |
| 55 | while (delay--) |
| 56 | cpu_relax(); |
| 57 | |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 58 | return __raw_readl(mmp_timer_base + TMR_CVWR(1)); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 59 | } |
| 60 | |
Stephen Boyd | e5c0228 | 2013-11-15 15:26:15 -0800 | [diff] [blame] | 61 | static u64 notrace mmp_read_sched_clock(void) |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 62 | { |
Marc Zyngier | 2f0778af | 2011-12-15 12:19:23 +0100 | [diff] [blame] | 63 | return timer_read(); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
| 67 | { |
| 68 | struct clock_event_device *c = dev_id; |
| 69 | |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 70 | /* |
| 71 | * Clear pending interrupt status. |
| 72 | */ |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 73 | __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * Disable timer 0. |
| 77 | */ |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 78 | __raw_writel(0x02, mmp_timer_base + TMR_CER); |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 79 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 80 | c->event_handler(c); |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 81 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 82 | return IRQ_HANDLED; |
| 83 | } |
| 84 | |
| 85 | static int timer_set_next_event(unsigned long delta, |
| 86 | struct clock_event_device *dev) |
| 87 | { |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 88 | unsigned long flags; |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 89 | |
| 90 | local_irq_save(flags); |
| 91 | |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 92 | /* |
| 93 | * Disable timer 0. |
| 94 | */ |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 95 | __raw_writel(0x02, mmp_timer_base + TMR_CER); |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * Clear and enable timer match 0 interrupt. |
| 99 | */ |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 100 | __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); |
| 101 | __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 102 | |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 103 | /* |
| 104 | * Setup new clockevent timer value. |
| 105 | */ |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 106 | __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 107 | |
| 108 | /* |
| 109 | * Enable timer 0. |
| 110 | */ |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 111 | __raw_writel(0x03, mmp_timer_base + TMR_CER); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 112 | |
| 113 | local_irq_restore(flags); |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 114 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 115 | return 0; |
| 116 | } |
| 117 | |
Viresh Kumar | a785fb3 | 2015-02-27 13:39:52 +0530 | [diff] [blame] | 118 | static int timer_set_shutdown(struct clock_event_device *evt) |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 119 | { |
| 120 | unsigned long flags; |
| 121 | |
| 122 | local_irq_save(flags); |
Viresh Kumar | a785fb3 | 2015-02-27 13:39:52 +0530 | [diff] [blame] | 123 | /* disable the matching interrupt */ |
| 124 | __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 125 | local_irq_restore(flags); |
Viresh Kumar | a785fb3 | 2015-02-27 13:39:52 +0530 | [diff] [blame] | 126 | |
| 127 | return 0; |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | static struct clock_event_device ckevt = { |
Viresh Kumar | a785fb3 | 2015-02-27 13:39:52 +0530 | [diff] [blame] | 131 | .name = "clockevent", |
| 132 | .features = CLOCK_EVT_FEAT_ONESHOT, |
| 133 | .rating = 200, |
| 134 | .set_next_event = timer_set_next_event, |
| 135 | .set_state_shutdown = timer_set_shutdown, |
| 136 | .set_state_oneshot = timer_set_shutdown, |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 137 | }; |
| 138 | |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 139 | static u64 clksrc_read(struct clocksource *cs) |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 140 | { |
| 141 | return timer_read(); |
| 142 | } |
| 143 | |
| 144 | static struct clocksource cksrc = { |
| 145 | .name = "clocksource", |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 146 | .rating = 200, |
| 147 | .read = clksrc_read, |
| 148 | .mask = CLOCKSOURCE_MASK(32), |
| 149 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 150 | }; |
| 151 | |
| 152 | static void __init timer_config(void) |
| 153 | { |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 154 | uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 155 | |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 156 | __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 157 | |
Lennert Buytenhek | 7ce5ae3 | 2011-08-10 02:36:59 +0800 | [diff] [blame] | 158 | ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) : |
| 159 | (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3)); |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 160 | __raw_writel(ccr, mmp_timer_base + TMR_CCR); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 161 | |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 162 | /* set timer 0 to periodic mode, and timer 1 to free-running mode */ |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 163 | __raw_writel(0x2, mmp_timer_base + TMR_CMR); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 164 | |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 165 | __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */ |
| 166 | __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */ |
| 167 | __raw_writel(0x0, mmp_timer_base + TMR_IER(0)); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 168 | |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 169 | __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */ |
| 170 | __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */ |
| 171 | __raw_writel(0x0, mmp_timer_base + TMR_IER(1)); |
Lennert Buytenhek | 7ce5ae3 | 2011-08-10 02:36:59 +0800 | [diff] [blame] | 172 | |
Lennert Buytenhek | af9dafb | 2011-08-10 02:37:55 +0800 | [diff] [blame] | 173 | /* enable timer 1 counter */ |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 174 | __raw_writel(0x2, mmp_timer_base + TMR_CER); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | static struct irqaction timer_irq = { |
| 178 | .name = "timer", |
Michael Opdenacker | 9929eed | 2014-03-04 22:07:26 +0100 | [diff] [blame] | 179 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 180 | .handler = timer_interrupt, |
| 181 | .dev_id = &ckevt, |
| 182 | }; |
| 183 | |
Arnd Bergmann | 12d3a30 | 2018-12-10 21:43:01 +0100 | [diff] [blame] | 184 | void __init mmp_timer_init(int irq, unsigned long rate) |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 185 | { |
| 186 | timer_config(); |
| 187 | |
Lubomir Rintel | f36797e | 2018-11-28 18:53:20 +0100 | [diff] [blame] | 188 | sched_clock_register(mmp_read_sched_clock, 32, rate); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 189 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 190 | ckevt.cpumask = cpumask_of(0); |
| 191 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 192 | setup_irq(irq, &timer_irq); |
| 193 | |
Lubomir Rintel | f36797e | 2018-11-28 18:53:20 +0100 | [diff] [blame] | 194 | clocksource_register_hz(&cksrc, rate); |
| 195 | clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 196 | } |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 197 | |
| 198 | #ifdef CONFIG_OF |
Uwe Kleine-König | 444d2d3 | 2015-02-18 21:19:56 +0100 | [diff] [blame] | 199 | static const struct of_device_id mmp_timer_dt_ids[] = { |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 200 | { .compatible = "mrvl,mmp-timer", }, |
| 201 | {} |
| 202 | }; |
| 203 | |
| 204 | void __init mmp_dt_init_timer(void) |
| 205 | { |
| 206 | struct device_node *np; |
Lubomir Rintel | f36797e | 2018-11-28 18:53:20 +0100 | [diff] [blame] | 207 | struct clk *clk; |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 208 | int irq, ret; |
Lubomir Rintel | f36797e | 2018-11-28 18:53:20 +0100 | [diff] [blame] | 209 | unsigned long rate; |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 210 | |
| 211 | np = of_find_matching_node(NULL, mmp_timer_dt_ids); |
| 212 | if (!np) { |
| 213 | ret = -ENODEV; |
| 214 | goto out; |
| 215 | } |
| 216 | |
Lubomir Rintel | f36797e | 2018-11-28 18:53:20 +0100 | [diff] [blame] | 217 | clk = of_clk_get(np, 0); |
| 218 | if (!IS_ERR(clk)) { |
| 219 | ret = clk_prepare_enable(clk); |
| 220 | if (ret) |
| 221 | goto out; |
| 222 | rate = clk_get_rate(clk) / 2; |
| 223 | } else if (cpu_is_pj4()) { |
| 224 | rate = 6500000; |
| 225 | } else { |
| 226 | rate = 3250000; |
| 227 | } |
| 228 | |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 229 | irq = irq_of_parse_and_map(np, 0); |
| 230 | if (!irq) { |
| 231 | ret = -EINVAL; |
| 232 | goto out; |
| 233 | } |
| 234 | mmp_timer_base = of_iomap(np, 0); |
| 235 | if (!mmp_timer_base) { |
| 236 | ret = -ENOMEM; |
| 237 | goto out; |
| 238 | } |
Arnd Bergmann | 12d3a30 | 2018-12-10 21:43:01 +0100 | [diff] [blame] | 239 | mmp_timer_init(irq, rate); |
Haojian Zhuang | c68ef2b | 2012-04-12 19:05:40 +0800 | [diff] [blame] | 240 | return; |
| 241 | out: |
| 242 | pr_err("Failed to get timer from device tree with error:%d\n", ret); |
| 243 | } |
| 244 | #endif |