blob: 483df32583be66654d4f7f01681bd5cc4f1d8999 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Eric Miao49cbe782009-01-20 14:15:18 +08002/*
3 * linux/arch/arm/mach-mmp/time.c
4 *
5 * Support for clocksource and clockevents
6 *
7 * Copyright (C) 2008 Marvell International Ltd.
8 * All rights reserved.
9 *
10 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
11 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
12 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -030013 * The timers module actually includes three timers, each timer with up to
Eric Miao49cbe782009-01-20 14:15:18 +080014 * three match comparators. Timer #0 is used here in free-running mode as
15 * the clock source, and match comparator #1 used as clock event device.
Eric Miao49cbe782009-01-20 14:15:18 +080016 */
17
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/interrupt.h>
21#include <linux/clockchips.h>
Lubomir Rintelf36797e2018-11-28 18:53:20 +010022#include <linux/clk.h>
Eric Miao49cbe782009-01-20 14:15:18 +080023
24#include <linux/io.h>
25#include <linux/irq.h>
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +080026#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070029#include <linux/sched_clock.h>
Haojian Zhuang2f7e8fa2009-12-04 09:41:28 -050030#include <asm/mach/time.h>
Eric Miao49cbe782009-01-20 14:15:18 +080031
Arnd Bergmannb501fd72014-04-15 20:38:32 +020032#include "addr-map.h"
33#include "regs-timers.h"
34#include "regs-apbc.h"
35#include "irqs.h"
36#include "cputype.h"
Eric Miao49cbe782009-01-20 14:15:18 +080037#include "clock.h"
38
39#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
40
41#define MAX_DELTA (0xfffffffe)
42#define MIN_DELTA (16)
43
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +080044static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
45
Eric Miao49cbe782009-01-20 14:15:18 +080046/*
47 * FIXME: the timer needs some delay to stablize the counter capture
48 */
49static inline uint32_t timer_read(void)
50{
51 int delay = 100;
52
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +080053 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
Eric Miao49cbe782009-01-20 14:15:18 +080054
55 while (delay--)
56 cpu_relax();
57
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +080058 return __raw_readl(mmp_timer_base + TMR_CVWR(1));
Eric Miao49cbe782009-01-20 14:15:18 +080059}
60
Stephen Boyde5c02282013-11-15 15:26:15 -080061static u64 notrace mmp_read_sched_clock(void)
Eric Miao49cbe782009-01-20 14:15:18 +080062{
Marc Zyngier2f0778af2011-12-15 12:19:23 +010063 return timer_read();
Eric Miao49cbe782009-01-20 14:15:18 +080064}
65
66static irqreturn_t timer_interrupt(int irq, void *dev_id)
67{
68 struct clock_event_device *c = dev_id;
69
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +080070 /*
71 * Clear pending interrupt status.
72 */
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +080073 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +080074
75 /*
76 * Disable timer 0.
77 */
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +080078 __raw_writel(0x02, mmp_timer_base + TMR_CER);
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +080079
Eric Miao49cbe782009-01-20 14:15:18 +080080 c->event_handler(c);
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +080081
Eric Miao49cbe782009-01-20 14:15:18 +080082 return IRQ_HANDLED;
83}
84
85static int timer_set_next_event(unsigned long delta,
86 struct clock_event_device *dev)
87{
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +080088 unsigned long flags;
Eric Miao49cbe782009-01-20 14:15:18 +080089
90 local_irq_save(flags);
91
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +080092 /*
93 * Disable timer 0.
94 */
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +080095 __raw_writel(0x02, mmp_timer_base + TMR_CER);
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +080096
97 /*
98 * Clear and enable timer match 0 interrupt.
99 */
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800100 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
101 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
Eric Miao49cbe782009-01-20 14:15:18 +0800102
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +0800103 /*
104 * Setup new clockevent timer value.
105 */
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800106 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +0800107
108 /*
109 * Enable timer 0.
110 */
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800111 __raw_writel(0x03, mmp_timer_base + TMR_CER);
Eric Miao49cbe782009-01-20 14:15:18 +0800112
113 local_irq_restore(flags);
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +0800114
Eric Miao49cbe782009-01-20 14:15:18 +0800115 return 0;
116}
117
Viresh Kumara785fb32015-02-27 13:39:52 +0530118static int timer_set_shutdown(struct clock_event_device *evt)
Eric Miao49cbe782009-01-20 14:15:18 +0800119{
120 unsigned long flags;
121
122 local_irq_save(flags);
Viresh Kumara785fb32015-02-27 13:39:52 +0530123 /* disable the matching interrupt */
124 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
Eric Miao49cbe782009-01-20 14:15:18 +0800125 local_irq_restore(flags);
Viresh Kumara785fb32015-02-27 13:39:52 +0530126
127 return 0;
Eric Miao49cbe782009-01-20 14:15:18 +0800128}
129
130static struct clock_event_device ckevt = {
Viresh Kumara785fb32015-02-27 13:39:52 +0530131 .name = "clockevent",
132 .features = CLOCK_EVT_FEAT_ONESHOT,
133 .rating = 200,
134 .set_next_event = timer_set_next_event,
135 .set_state_shutdown = timer_set_shutdown,
136 .set_state_oneshot = timer_set_shutdown,
Eric Miao49cbe782009-01-20 14:15:18 +0800137};
138
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +0100139static u64 clksrc_read(struct clocksource *cs)
Eric Miao49cbe782009-01-20 14:15:18 +0800140{
141 return timer_read();
142}
143
144static struct clocksource cksrc = {
145 .name = "clocksource",
Eric Miao49cbe782009-01-20 14:15:18 +0800146 .rating = 200,
147 .read = clksrc_read,
148 .mask = CLOCKSOURCE_MASK(32),
149 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
150};
151
152static void __init timer_config(void)
153{
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800154 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
Eric Miao49cbe782009-01-20 14:15:18 +0800155
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800156 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
Eric Miao49cbe782009-01-20 14:15:18 +0800157
Lennert Buytenhek7ce5ae32011-08-10 02:36:59 +0800158 ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
159 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800160 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
Eric Miao49cbe782009-01-20 14:15:18 +0800161
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +0800162 /* set timer 0 to periodic mode, and timer 1 to free-running mode */
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800163 __raw_writel(0x2, mmp_timer_base + TMR_CMR);
Eric Miao49cbe782009-01-20 14:15:18 +0800164
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800165 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
166 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
167 __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
Eric Miao49cbe782009-01-20 14:15:18 +0800168
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800169 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
170 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
171 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
Lennert Buytenhek7ce5ae32011-08-10 02:36:59 +0800172
Lennert Buytenhekaf9dafb2011-08-10 02:37:55 +0800173 /* enable timer 1 counter */
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800174 __raw_writel(0x2, mmp_timer_base + TMR_CER);
Eric Miao49cbe782009-01-20 14:15:18 +0800175}
176
177static struct irqaction timer_irq = {
178 .name = "timer",
Michael Opdenacker9929eed2014-03-04 22:07:26 +0100179 .flags = IRQF_TIMER | IRQF_IRQPOLL,
Eric Miao49cbe782009-01-20 14:15:18 +0800180 .handler = timer_interrupt,
181 .dev_id = &ckevt,
182};
183
Arnd Bergmann12d3a302018-12-10 21:43:01 +0100184void __init mmp_timer_init(int irq, unsigned long rate)
Eric Miao49cbe782009-01-20 14:15:18 +0800185{
186 timer_config();
187
Lubomir Rintelf36797e2018-11-28 18:53:20 +0100188 sched_clock_register(mmp_read_sched_clock, 32, rate);
Eric Miao49cbe782009-01-20 14:15:18 +0800189
Eric Miao49cbe782009-01-20 14:15:18 +0800190 ckevt.cpumask = cpumask_of(0);
191
Eric Miao49cbe782009-01-20 14:15:18 +0800192 setup_irq(irq, &timer_irq);
193
Lubomir Rintelf36797e2018-11-28 18:53:20 +0100194 clocksource_register_hz(&cksrc, rate);
195 clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
Eric Miao49cbe782009-01-20 14:15:18 +0800196}
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800197
198#ifdef CONFIG_OF
Uwe Kleine-König444d2d32015-02-18 21:19:56 +0100199static const struct of_device_id mmp_timer_dt_ids[] = {
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800200 { .compatible = "mrvl,mmp-timer", },
201 {}
202};
203
204void __init mmp_dt_init_timer(void)
205{
206 struct device_node *np;
Lubomir Rintelf36797e2018-11-28 18:53:20 +0100207 struct clk *clk;
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800208 int irq, ret;
Lubomir Rintelf36797e2018-11-28 18:53:20 +0100209 unsigned long rate;
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800210
211 np = of_find_matching_node(NULL, mmp_timer_dt_ids);
212 if (!np) {
213 ret = -ENODEV;
214 goto out;
215 }
216
Lubomir Rintelf36797e2018-11-28 18:53:20 +0100217 clk = of_clk_get(np, 0);
218 if (!IS_ERR(clk)) {
219 ret = clk_prepare_enable(clk);
220 if (ret)
221 goto out;
222 rate = clk_get_rate(clk) / 2;
223 } else if (cpu_is_pj4()) {
224 rate = 6500000;
225 } else {
226 rate = 3250000;
227 }
228
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800229 irq = irq_of_parse_and_map(np, 0);
230 if (!irq) {
231 ret = -EINVAL;
232 goto out;
233 }
234 mmp_timer_base = of_iomap(np, 0);
235 if (!mmp_timer_base) {
236 ret = -ENOMEM;
237 goto out;
238 }
Arnd Bergmann12d3a302018-12-10 21:43:01 +0100239 mmp_timer_init(irq, rate);
Haojian Zhuangc68ef2b2012-04-12 19:05:40 +0800240 return;
241out:
242 pr_err("Failed to get timer from device tree with error:%d\n", ret);
243}
244#endif