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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
3 * linux/arch/arm/kernel/debug.S
4 *
5 * Copyright (C) 1994-1999 Russell King
6 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * 32-bit debugging code
8 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/linkage.h>
Rob Herring6f6f6a72012-03-10 10:30:31 -060010#include <asm/assembler.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011
12 .text
13
14/*
15 * Some debugging routines (useful if you've got MM problems and
16 * printk isn't working). For DEBUGGING ONLY!!! Do not leave
17 * references to these in a production kernel!
18 */
19
Rob Herring91a9fec2012-08-31 00:03:46 -050020#if !defined(CONFIG_DEBUG_SEMIHOSTING)
21#include CONFIG_DEBUG_LL_INCLUDE
22#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Jeremy Kerr0ea12932010-07-06 18:30:06 +080024#ifdef CONFIG_MMU
25 .macro addruart_current, rx, tmp1, tmp2
Nicolas Pitre639da5e2011-08-31 22:55:46 -040026 addruart \tmp1, \tmp2, \rx
Jeremy Kerr0ea12932010-07-06 18:30:06 +080027 mrc p15, 0, \rx, c1, c0
28 tst \rx, #1
29 moveq \rx, \tmp1
30 movne \rx, \tmp2
31 .endm
32
33#else /* !CONFIG_MMU */
34 .macro addruart_current, rx, tmp1, tmp2
Stefan Agner7505f042015-05-20 00:03:50 +020035 addruart \rx, \tmp1, \tmp2
Jeremy Kerr0ea12932010-07-06 18:30:06 +080036 .endm
37
38#endif /* CONFIG_MMU */
39
Linus Torvalds1da177e2005-04-16 15:20:36 -070040/*
41 * Useful debugging routines
42 */
43ENTRY(printhex8)
44 mov r1, #8
45 b printhex
Catalin Marinas93ed3972008-08-28 11:22:32 +010046ENDPROC(printhex8)
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48ENTRY(printhex4)
49 mov r1, #4
50 b printhex
Catalin Marinas93ed3972008-08-28 11:22:32 +010051ENDPROC(printhex4)
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53ENTRY(printhex2)
54 mov r1, #2
Nicolas Pitree11d1312017-10-06 19:36:58 +010055printhex: adr r2, hexbuf_rel
56 ldr r3, [r2]
57 add r2, r2, r3
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 add r3, r2, r1
59 mov r1, #0
60 strb r1, [r3]
611: and r1, r0, #15
62 mov r0, r0, lsr #4
63 cmp r1, #10
64 addlt r1, r1, #'0'
65 addge r1, r1, #'a' - 10
66 strb r1, [r3, #-1]!
67 teq r3, r2
68 bne 1b
69 mov r0, r2
70 b printascii
Catalin Marinas93ed3972008-08-28 11:22:32 +010071ENDPROC(printhex2)
Linus Torvalds1da177e2005-04-16 15:20:36 -070072
Nicolas Pitree11d1312017-10-06 19:36:58 +010073 .pushsection .bss
74hexbuf_addr: .space 16
75 .popsection
76 .align
77hexbuf_rel: .long hexbuf_addr - .
Afzal Mohammedb55fa182011-10-20 19:32:07 +010078
Linus Torvalds1da177e2005-04-16 15:20:36 -070079 .ltorg
80
Nicolas Pitre9b5a1462012-02-22 21:58:03 +010081#ifndef CONFIG_DEBUG_SEMIHOSTING
82
Linus Torvalds1da177e2005-04-16 15:20:36 -070083ENTRY(printascii)
Jeremy Kerr0ea12932010-07-06 18:30:06 +080084 addruart_current r3, r1, r2
Nicolas Pitre2a14b802017-11-02 21:58:41 +0100851: teq r0, #0
Stefan Agnere44fc382019-02-18 00:57:38 +010086 ldrbne r1, [r0], #1
Linus Torvalds1da177e2005-04-16 15:20:36 -070087 teqne r1, #0
Nicolas Pitre2a14b802017-11-02 21:58:41 +010088 reteq lr
892: teq r1, #'\n'
90 bne 3f
91 mov r1, #'\r'
92 waituart r2, r3
93 senduart r1, r3
94 busyuart r2, r3
95 mov r1, #'\n'
963: waituart r2, r3
97 senduart r1, r3
98 busyuart r2, r3
99 b 1b
Catalin Marinas93ed3972008-08-28 11:22:32 +0100100ENDPROC(printascii)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
102ENTRY(printch)
Jeremy Kerr0ea12932010-07-06 18:30:06 +0800103 addruart_current r3, r1, r2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 mov r1, r0
105 mov r0, #0
Nicolas Pitre2a14b802017-11-02 21:58:41 +0100106 b 2b
Catalin Marinas93ed3972008-08-28 11:22:32 +0100107ENDPROC(printch)
Nicolas Pitre9b5a1462012-02-22 21:58:03 +0100108
Uwe Kleine-Königa73b59c2013-01-16 15:32:06 +0100109#ifdef CONFIG_MMU
Rob Herringe5c5f2a2012-10-22 11:42:54 -0600110ENTRY(debug_ll_addr)
111 addruart r2, r3, ip
112 str r2, [r0]
113 str r3, [r1]
Russell King6ebbf2c2014-06-30 16:29:12 +0100114 ret lr
Rob Herringe5c5f2a2012-10-22 11:42:54 -0600115ENDPROC(debug_ll_addr)
Uwe Kleine-Königa73b59c2013-01-16 15:32:06 +0100116#endif
Rob Herringe5c5f2a2012-10-22 11:42:54 -0600117
Nicolas Pitre9b5a1462012-02-22 21:58:03 +0100118#else
119
120ENTRY(printascii)
121 mov r1, r0
122 mov r0, #0x04 @ SYS_WRITE0
123 ARM( svc #0x123456 )
Nicolas Pitreee3eaee2017-10-06 19:39:57 +0100124#ifdef CONFIG_CPU_V7M
125 THUMB( bkpt #0xab )
126#else
Nicolas Pitre9b5a1462012-02-22 21:58:03 +0100127 THUMB( svc #0xab )
Nicolas Pitreee3eaee2017-10-06 19:39:57 +0100128#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100129 ret lr
Nicolas Pitre9b5a1462012-02-22 21:58:03 +0100130ENDPROC(printascii)
131
132ENTRY(printch)
Nicolas Pitree11d1312017-10-06 19:36:58 +0100133 adr r1, hexbuf_rel
134 ldr r2, [r1]
135 add r1, r1, r2
Nicolas Pitre9b5a1462012-02-22 21:58:03 +0100136 strb r0, [r1]
137 mov r0, #0x03 @ SYS_WRITEC
138 ARM( svc #0x123456 )
Nicolas Pitreee3eaee2017-10-06 19:39:57 +0100139#ifdef CONFIG_CPU_V7M
140 THUMB( bkpt #0xab )
141#else
Nicolas Pitre9b5a1462012-02-22 21:58:03 +0100142 THUMB( svc #0xab )
Nicolas Pitreee3eaee2017-10-06 19:39:57 +0100143#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100144 ret lr
Nicolas Pitre9b5a1462012-02-22 21:58:03 +0100145ENDPROC(printch)
146
Rob Herringe5c5f2a2012-10-22 11:42:54 -0600147ENTRY(debug_ll_addr)
148 mov r2, #0
149 str r2, [r0]
150 str r2, [r1]
Russell King6ebbf2c2014-06-30 16:29:12 +0100151 ret lr
Rob Herringe5c5f2a2012-10-22 11:42:54 -0600152ENDPROC(debug_ll_addr)
153
Nicolas Pitre9b5a1462012-02-22 21:58:03 +0100154#endif