Gitiles
Code Review Sign In
nv-tegra.nvidia.com / linux-4.4 / b2ffec46ea230acac52170dd0a747526328d25fe / . / drivers / net / wireless / brcm80211 / brcmsmac / aiutils.h
blob: 347b8a26f025232dac7c71bc3eb561878fac2d0c [file] [log] [blame]
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_AIUTILS_H_
18#define _BRCM_AIUTILS_H_
19
20#include "types.h"
21
22/*
23 * SOC Interconnect Address Map.
24 * All regions may not exist on all chips.
25 */
26/* each core gets 4Kbytes for registers */
27#define SI_CORE_SIZE 0x1000
28/*
29 * Max cores (this is arbitrary, for software
30 * convenience and could be changed if we
31 * make any larger chips
32 */
33#define SI_MAXCORES 16
34
35/* Client Mode sb2pcitranslation2 size in bytes */
36#define SI_PCI_DMA_SZ 0x40000000
37
38/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
39#define SI_PCIE_DMA_H32 0x80000000
40
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]41/* chipcommon being the first core: */
42#define SI_CC_IDX 0
43
44/* SOC Interconnect types (aka chip types) */
45#define SOCI_AI 1
46
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]47/* A register that is common to all cores to
48 * communicate w/PMU regarding clock control.
49 */
50#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
51
52/* clk_ctl_st register */
53#define CCS_FORCEALP 0x00000001 /* force ALP request */
54#define CCS_FORCEHT 0x00000002 /* force HT request */
55#define CCS_FORCEILP 0x00000004 /* force ILP request */
56#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
57#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
58#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
59#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
60#define CCS_ERSRC_REQ_SHIFT 8
61#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
62#define CCS_HTAVAIL 0x00020000 /* HT is available */
63#define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
64#define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
65#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
66#define CCS_ERSRC_STS_SHIFT 24
67
68/* HT avail in chipc and pcmcia on 4328a0 */
69#define CCS0_HTAVAIL 0x00010000
70/* ALP avail in chipc and pcmcia on 4328a0 */
71#define CCS0_ALPAVAIL 0x00020000
72
73/* Not really related to SOC Interconnect, but a couple of software
74 * conventions for the use the flash space:
75 */
76
77/* Minumum amount of flash we support */
78#define FLASH_MIN 0x00020000 /* Minimum flash size */
79
80#define CC_SROM_OTP 0x800 /* SROM/OTP address space */
81
82/* gpiotimerval */
83#define GPIO_ONTIME_SHIFT 16
84
85/* Fields in clkdiv */
86#define CLKD_OTP 0x000f0000
87#define CLKD_OTP_SHIFT 16
88
89/* Package IDs */
90#define BCM4717_PKG_ID 9 /* 4717 package id */
91#define BCM4718_PKG_ID 10 /* 4718 package id */
92#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
93
94/* these are router chips */
95#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
96#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
97#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
98
99/* dynamic clock control defines */
100#define LPOMINFREQ 25000 /* low power oscillator min */
101#define LPOMAXFREQ 43000 /* low power oscillator max */
102#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
103#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
104#define PCIMINFREQ 25000000 /* 25 MHz */
105#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
106
107#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
108#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
109
110/* clkctl xtal what flags */
111#define XTAL 0x1 /* primary crystal oscillator (2050) */
112#define PLL 0x2 /* main chip pll */
113
114/* clkctl clk mode */
115#define CLK_FAST 0 /* force fast (pll) clock */
116#define CLK_DYNAMIC 2 /* enable dynamic clock control */
117
118/* GPIO usage priorities */
119#define GPIO_DRV_PRIORITY 0 /* Driver */
120#define GPIO_APP_PRIORITY 1 /* Application */
121#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
122 * reservation
123 */
124
125/* GPIO pull up/down */
126#define GPIO_PULLUP 0
127#define GPIO_PULLDN 1
128
129/* GPIO event regtype */
130#define GPIO_REGEVT 0 /* GPIO register event */
131#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
132#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
133
134/* device path */
135#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
136
137/* SI routine enumeration: to be used by update function with multiple hooks */
138#define SI_DOATTACH 1
139#define SI_PCIDOWN 2
140#define SI_PCIUP 3
141
142/*
143 * Data structure to export all chip specific common variables
144 * public (read-only) portion of aiutils handle returned by si_attach()
145 */
146struct si_pub {
147 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
148 uint buscorerev; /* buscore rev */
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]149 int ccrev; /* chip common core rev */
150 u32 cccaps; /* chip common capabilities */
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]151 int pmurev; /* pmu core rev */
152 u32 pmucaps; /* pmu capabilities */
153 uint boardtype; /* board type */
154 uint boardvendor; /* board vendor */
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]155 uint chip; /* chip number */
156 uint chiprev; /* chip revision */
157 uint chippkg; /* chip package option */
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]158};
159
160struct pci_dev;
161
162struct gpioh_item {
163 void *arg;
164 bool level;
165 void (*handler) (u32 stat, void *arg);
166 u32 event;
167 struct gpioh_item *next;
168};
169
170/* misc si info needed by some of the routines */
171struct si_info {
172 struct si_pub pub; /* back plane public state (must be first) */
173 struct pci_dev *pbus; /* handle to pci bus */
174 uint dev_coreid; /* the core provides driver functions */
175 void *intr_arg; /* interrupt callback function arg */
176 u32 (*intrsoff_fn) (void *intr_arg); /* turns chip interrupts off */
177 /* restore chip interrupts */
178 void (*intrsrestore_fn) (void *intr_arg, u32 arg);
179 /* check if interrupts are enabled */
180 bool (*intrsenabled_fn) (void *intr_arg);
181
182 struct pcicore_info *pch; /* PCI/E core handle */
183
184 struct list_head var_list; /* list of srom variables */
185
186 void __iomem *curmap; /* current regs va */
187 void __iomem *regs[SI_MAXCORES]; /* other regs va */
188
Arend van Spriel2e397c32011-12-08 15:06:44 -0800[diff] [blame]189 u32 chipst; /* chip status */
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]190 uint curidx; /* current core index */
Arend van Spriel2e397c32011-12-08 15:06:44 -0800[diff] [blame]191 uint buscoreidx; /* buscore index */
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]192 uint numcores; /* # discovered cores */
193 uint coreid[SI_MAXCORES]; /* id of each core */
194 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
195 void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
196 u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
197 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
198 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
199
200 void *curwrap; /* current wrapper va */
201 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
202 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
203
204 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
205 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
206 u32 oob_router; /* oob router registers for axi */
207};
208
209/*
210 * Many of the routines below take an 'sih' handle as their first arg.
211 * Allocate this by calling si_attach(). Free it by calling si_detach().
212 * At any one time, the sih is logically focused on one particular si core
213 * (the "current core").
214 * Use si_setcore() or si_setcoreidx() to change the association to another core
215 */
216
217
218/* AMBA Interconnect exported externs */
219extern uint ai_flag(struct si_pub *sih);
220extern void ai_setint(struct si_pub *sih, int siflag);
221extern uint ai_coreidx(struct si_pub *sih);
222extern uint ai_corevendor(struct si_pub *sih);
223extern uint ai_corerev(struct si_pub *sih);
224extern bool ai_iscoreup(struct si_pub *sih);
225extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
226extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
227extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
228extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
229 uint val);
230extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
231extern void ai_core_disable(struct si_pub *sih, u32 bits);
232extern int ai_numaddrspaces(struct si_pub *sih);
233extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
234extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
235extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
236
237/* === exported functions === */
238extern struct si_pub *ai_attach(void __iomem *regs, struct pci_dev *sdh);
239extern void ai_detach(struct si_pub *sih);
240extern uint ai_coreid(struct si_pub *sih);
241extern uint ai_corerev(struct si_pub *sih);
242extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
243 uint val);
244extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
245extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
246extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
247extern bool ai_iscoreup(struct si_pub *sih);
248extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
249extern void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx);
250extern void __iomem *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
251extern void __iomem *ai_switch_core(struct si_pub *sih, uint coreid,
252 uint *origidx, uint *intr_val);
253extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
254extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
255extern void ai_core_disable(struct si_pub *sih, u32 bits);
256extern u32 ai_alp_clock(struct si_pub *sih);
257extern u32 ai_ilp_clock(struct si_pub *sih);
258extern void ai_pci_setup(struct si_pub *sih, uint coremask);
259extern void ai_setint(struct si_pub *sih, int siflag);
260extern bool ai_backplane64(struct si_pub *sih);
261extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
262 void *intrsrestore_fn,
263 void *intrsenabled_fn, void *intr_arg);
264extern void ai_deregister_intr_callback(struct si_pub *sih);
265extern void ai_clkctl_init(struct si_pub *sih);
266extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
267extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
268extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
269extern bool ai_deviceremoved(struct si_pub *sih);
270extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
271 u8 priority);
272
273/* OTP status */
274extern bool ai_is_otp_disabled(struct si_pub *sih);
275
276/* SPROM availability */
277extern bool ai_is_sprom_available(struct si_pub *sih);
278
279/*
280 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
281 * The returned path is NULL terminated and has trailing '/'.
282 * Return 0 on success, nonzero otherwise.
283 */
284extern int ai_devpath(struct si_pub *sih, char *path, int size);
285
286extern void ai_pci_sleep(struct si_pub *sih);
287extern void ai_pci_down(struct si_pub *sih);
288extern void ai_pci_up(struct si_pub *sih);
289extern int ai_pci_fixcfg(struct si_pub *sih);
290
291extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
292/* Enable Ex-PA for 4313 */
293extern void ai_epa_4313war(struct si_pub *sih);
294
Arend van Sprielb2ffec42011-12-08 15:06:45 -0800[diff] [blame^]295static inline uint ai_get_buscoretype(struct si_pub *sih)
296{
297 return sih->buscoretype;
298}
299
300static inline uint ai_get_buscorerev(struct si_pub *sih)
301{
302 return sih->buscorerev;
303}
304static inline int ai_get_ccrev(struct si_pub *sih)
305{
306 return sih->ccrev;
307}
308static inline u32 ai_get_cccaps(struct si_pub *sih)
309{
310 return sih->cccaps;
311}
312static inline int ai_get_pmurev(struct si_pub *sih)
313{
314 return sih->pmurev;
315}
316static inline u32 ai_get_pmucaps(struct si_pub *sih)
317{
318 return sih->pmucaps;
319}
320static inline uint ai_get_boardtype(struct si_pub *sih)
321{
322 return sih->boardtype;
323}
324static inline uint ai_get_boardvendor(struct si_pub *sih)
325{
326 return sih->boardvendor;
327}
328static inline uint ai_get_chip_id(struct si_pub *sih)
329{
330 return sih->chip;
331}
332static inline uint ai_get_chiprev(struct si_pub *sih)
333{
334 return sih->chiprev;
335}
336static inline uint ai_get_chippkg(struct si_pub *sih)
337{
338 return sih->chippkg;
339}
340
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame]341#endif /* _BRCM_AIUTILS_H_ */