Gitiles
Code Review Sign In
nv-tegra.nvidia.com / linux-4.4 / 5b435de0d786869c95d1962121af0d7df2542009 / . / drivers / net / wireless / brcm80211 / brcmsmac / aiutils.h
blob: 106a7424a7cd4d60ee098d691db77e21067ba77c [file] [log] [blame]
Arend van Spriel5b435de2011-10-05 13:19:03 +0200[diff] [blame^]1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_AIUTILS_H_
18#define _BRCM_AIUTILS_H_
19
20#include "types.h"
21
22/*
23 * SOC Interconnect Address Map.
24 * All regions may not exist on all chips.
25 */
26/* each core gets 4Kbytes for registers */
27#define SI_CORE_SIZE 0x1000
28/*
29 * Max cores (this is arbitrary, for software
30 * convenience and could be changed if we
31 * make any larger chips
32 */
33#define SI_MAXCORES 16
34
35/* Client Mode sb2pcitranslation2 size in bytes */
36#define SI_PCI_DMA_SZ 0x40000000
37
38/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
39#define SI_PCIE_DMA_H32 0x80000000
40
41/* core codes */
42#define NODEV_CORE_ID 0x700 /* Invalid coreid */
43#define CC_CORE_ID 0x800 /* chipcommon core */
44#define ILINE20_CORE_ID 0x801 /* iline20 core */
45#define SRAM_CORE_ID 0x802 /* sram core */
46#define SDRAM_CORE_ID 0x803 /* sdram core */
47#define PCI_CORE_ID 0x804 /* pci core */
48#define MIPS_CORE_ID 0x805 /* mips core */
49#define ENET_CORE_ID 0x806 /* enet mac core */
50#define CODEC_CORE_ID 0x807 /* v90 codec core */
51#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
52#define ADSL_CORE_ID 0x809 /* ADSL core */
53#define ILINE100_CORE_ID 0x80a /* iline100 core */
54#define IPSEC_CORE_ID 0x80b /* ipsec core */
55#define UTOPIA_CORE_ID 0x80c /* utopia core */
56#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
57#define SOCRAM_CORE_ID 0x80e /* internal memory core */
58#define MEMC_CORE_ID 0x80f /* memc sdram core */
59#define OFDM_CORE_ID 0x810 /* OFDM phy core */
60#define EXTIF_CORE_ID 0x811 /* external interface core */
61#define D11_CORE_ID 0x812 /* 802.11 MAC core */
62#define APHY_CORE_ID 0x813 /* 802.11a phy core */
63#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
64#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
65#define MIPS33_CORE_ID 0x816 /* mips3302 core */
66#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
67#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
68#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
69#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
70#define SDIOH_CORE_ID 0x81b /* sdio host core */
71#define ROBO_CORE_ID 0x81c /* roboswitch core */
72#define ATA100_CORE_ID 0x81d /* parallel ATA core */
73#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
74#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
75#define PCIE_CORE_ID 0x820 /* pci express core */
76#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
77#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
78#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
79#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
80#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
81#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
82#define PMU_CORE_ID 0x827 /* PMU core */
83#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
84#define SDIOD_CORE_ID 0x829 /* SDIO device core */
85#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
86#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
87#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
88#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
89#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
90#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
91#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
92#define SC_CORE_ID 0x831 /* shared common core */
93#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
94#define SPIH_CORE_ID 0x833 /* SPI host core */
95#define I2S_CORE_ID 0x834 /* I2S core */
96#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
97#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
98#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
99#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
100 * maps all unused address ranges
101 */
102
103/* chipcommon being the first core: */
104#define SI_CC_IDX 0
105
106/* SOC Interconnect types (aka chip types) */
107#define SOCI_AI 1
108
109/* Common core control flags */
110#define SICF_BIST_EN 0x8000
111#define SICF_PME_EN 0x4000
112#define SICF_CORE_BITS 0x3ffc
113#define SICF_FGC 0x0002
114#define SICF_CLOCK_EN 0x0001
115
116/* Common core status flags */
117#define SISF_BIST_DONE 0x8000
118#define SISF_BIST_ERROR 0x4000
119#define SISF_GATED_CLK 0x2000
120#define SISF_DMA64 0x1000
121#define SISF_CORE_BITS 0x0fff
122
123/* A register that is common to all cores to
124 * communicate w/PMU regarding clock control.
125 */
126#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
127
128/* clk_ctl_st register */
129#define CCS_FORCEALP 0x00000001 /* force ALP request */
130#define CCS_FORCEHT 0x00000002 /* force HT request */
131#define CCS_FORCEILP 0x00000004 /* force ILP request */
132#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
133#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
134#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
135#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
136#define CCS_ERSRC_REQ_SHIFT 8
137#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
138#define CCS_HTAVAIL 0x00020000 /* HT is available */
139#define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
140#define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
141#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
142#define CCS_ERSRC_STS_SHIFT 24
143
144/* HT avail in chipc and pcmcia on 4328a0 */
145#define CCS0_HTAVAIL 0x00010000
146/* ALP avail in chipc and pcmcia on 4328a0 */
147#define CCS0_ALPAVAIL 0x00020000
148
149/* Not really related to SOC Interconnect, but a couple of software
150 * conventions for the use the flash space:
151 */
152
153/* Minumum amount of flash we support */
154#define FLASH_MIN 0x00020000 /* Minimum flash size */
155
156#define CC_SROM_OTP 0x800 /* SROM/OTP address space */
157
158/* gpiotimerval */
159#define GPIO_ONTIME_SHIFT 16
160
161/* Fields in clkdiv */
162#define CLKD_OTP 0x000f0000
163#define CLKD_OTP_SHIFT 16
164
165/* Package IDs */
166#define BCM4717_PKG_ID 9 /* 4717 package id */
167#define BCM4718_PKG_ID 10 /* 4718 package id */
168#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
169
170/* these are router chips */
171#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
172#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
173#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
174
175/* dynamic clock control defines */
176#define LPOMINFREQ 25000 /* low power oscillator min */
177#define LPOMAXFREQ 43000 /* low power oscillator max */
178#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
179#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
180#define PCIMINFREQ 25000000 /* 25 MHz */
181#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
182
183#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
184#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
185
186/* clkctl xtal what flags */
187#define XTAL 0x1 /* primary crystal oscillator (2050) */
188#define PLL 0x2 /* main chip pll */
189
190/* clkctl clk mode */
191#define CLK_FAST 0 /* force fast (pll) clock */
192#define CLK_DYNAMIC 2 /* enable dynamic clock control */
193
194/* GPIO usage priorities */
195#define GPIO_DRV_PRIORITY 0 /* Driver */
196#define GPIO_APP_PRIORITY 1 /* Application */
197#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
198 * reservation
199 */
200
201/* GPIO pull up/down */
202#define GPIO_PULLUP 0
203#define GPIO_PULLDN 1
204
205/* GPIO event regtype */
206#define GPIO_REGEVT 0 /* GPIO register event */
207#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
208#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
209
210/* device path */
211#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
212
213/* SI routine enumeration: to be used by update function with multiple hooks */
214#define SI_DOATTACH 1
215#define SI_PCIDOWN 2
216#define SI_PCIUP 3
217
218/*
219 * Data structure to export all chip specific common variables
220 * public (read-only) portion of aiutils handle returned by si_attach()
221 */
222struct si_pub {
223 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
224 uint buscorerev; /* buscore rev */
225 uint buscoreidx; /* buscore index */
226 int ccrev; /* chip common core rev */
227 u32 cccaps; /* chip common capabilities */
228 u32 cccaps_ext; /* chip common capabilities extension */
229 int pmurev; /* pmu core rev */
230 u32 pmucaps; /* pmu capabilities */
231 uint boardtype; /* board type */
232 uint boardvendor; /* board vendor */
233 uint boardflags; /* board flags */
234 uint boardflags2; /* board flags2 */
235 uint chip; /* chip number */
236 uint chiprev; /* chip revision */
237 uint chippkg; /* chip package option */
238 u32 chipst; /* chip status */
239 bool issim; /* chip is in simulation or emulation */
240 uint socirev; /* SOC interconnect rev */
241 bool pci_pr32414;
242
243};
244
245struct pci_dev;
246
247struct gpioh_item {
248 void *arg;
249 bool level;
250 void (*handler) (u32 stat, void *arg);
251 u32 event;
252 struct gpioh_item *next;
253};
254
255/* misc si info needed by some of the routines */
256struct si_info {
257 struct si_pub pub; /* back plane public state (must be first) */
258 struct pci_dev *pbus; /* handle to pci bus */
259 uint dev_coreid; /* the core provides driver functions */
260 void *intr_arg; /* interrupt callback function arg */
261 u32 (*intrsoff_fn) (void *intr_arg); /* turns chip interrupts off */
262 /* restore chip interrupts */
263 void (*intrsrestore_fn) (void *intr_arg, u32 arg);
264 /* check if interrupts are enabled */
265 bool (*intrsenabled_fn) (void *intr_arg);
266
267 struct pcicore_info *pch; /* PCI/E core handle */
268
269 struct list_head var_list; /* list of srom variables */
270
271 void __iomem *curmap; /* current regs va */
272 void __iomem *regs[SI_MAXCORES]; /* other regs va */
273
274 uint curidx; /* current core index */
275 uint numcores; /* # discovered cores */
276 uint coreid[SI_MAXCORES]; /* id of each core */
277 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
278 void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
279 u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
280 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
281 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
282
283 void *curwrap; /* current wrapper va */
284 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
285 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
286
287 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
288 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
289 u32 oob_router; /* oob router registers for axi */
290};
291
292/*
293 * Many of the routines below take an 'sih' handle as their first arg.
294 * Allocate this by calling si_attach(). Free it by calling si_detach().
295 * At any one time, the sih is logically focused on one particular si core
296 * (the "current core").
297 * Use si_setcore() or si_setcoreidx() to change the association to another core
298 */
299
300
301/* AMBA Interconnect exported externs */
302extern uint ai_flag(struct si_pub *sih);
303extern void ai_setint(struct si_pub *sih, int siflag);
304extern uint ai_coreidx(struct si_pub *sih);
305extern uint ai_corevendor(struct si_pub *sih);
306extern uint ai_corerev(struct si_pub *sih);
307extern bool ai_iscoreup(struct si_pub *sih);
308extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
309extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
310extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
311extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
312 uint val);
313extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
314extern void ai_core_disable(struct si_pub *sih, u32 bits);
315extern int ai_numaddrspaces(struct si_pub *sih);
316extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
317extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
318extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
319
320/* === exported functions === */
321extern struct si_pub *ai_attach(void __iomem *regs, struct pci_dev *sdh);
322extern void ai_detach(struct si_pub *sih);
323extern uint ai_coreid(struct si_pub *sih);
324extern uint ai_corerev(struct si_pub *sih);
325extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
326 uint val);
327extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
328extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
329extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
330extern bool ai_iscoreup(struct si_pub *sih);
331extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
332extern void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx);
333extern void __iomem *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
334extern void __iomem *ai_switch_core(struct si_pub *sih, uint coreid,
335 uint *origidx, uint *intr_val);
336extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
337extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
338extern void ai_core_disable(struct si_pub *sih, u32 bits);
339extern u32 ai_alp_clock(struct si_pub *sih);
340extern u32 ai_ilp_clock(struct si_pub *sih);
341extern void ai_pci_setup(struct si_pub *sih, uint coremask);
342extern void ai_setint(struct si_pub *sih, int siflag);
343extern bool ai_backplane64(struct si_pub *sih);
344extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
345 void *intrsrestore_fn,
346 void *intrsenabled_fn, void *intr_arg);
347extern void ai_deregister_intr_callback(struct si_pub *sih);
348extern void ai_clkctl_init(struct si_pub *sih);
349extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
350extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
351extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
352extern bool ai_deviceremoved(struct si_pub *sih);
353extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
354 u8 priority);
355
356/* OTP status */
357extern bool ai_is_otp_disabled(struct si_pub *sih);
358
359/* SPROM availability */
360extern bool ai_is_sprom_available(struct si_pub *sih);
361
362/*
363 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
364 * The returned path is NULL terminated and has trailing '/'.
365 * Return 0 on success, nonzero otherwise.
366 */
367extern int ai_devpath(struct si_pub *sih, char *path, int size);
368
369extern void ai_pci_sleep(struct si_pub *sih);
370extern void ai_pci_down(struct si_pub *sih);
371extern void ai_pci_up(struct si_pub *sih);
372extern int ai_pci_fixcfg(struct si_pub *sih);
373
374extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
375/* Enable Ex-PA for 4313 */
376extern void ai_epa_4313war(struct si_pub *sih);
377
378#endif /* _BRCM_AIUTILS_H_ */