blob: 30da617d18e4735de234904fdc005cf527930c89 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
Ingo Molnar8f47e162009-01-31 02:03:42 +01004 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070028#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
Alexey Dobriyan129f6942005-06-23 00:08:33 -070032#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <linux/sysdev.h>
Eric W. Biederman3b7d1922006-10-04 02:16:59 -070034#include <linux/msi.h>
Eric W. Biederman95d77882006-10-04 02:17:01 -070035#include <linux/htirq.h>
Nigel Cunningham7dfb7102006-12-06 20:34:23 -080036#include <linux/freezer.h>
Eric W. Biedermanf26d6a22007-05-02 19:27:19 +020037#include <linux/kthread.h>
Ingo Molnar54168ed2008-08-20 09:07:45 +020038#include <linux/jiffies.h> /* time_after() */
Yinghai Lud4057bd2008-08-19 20:50:38 -070039#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -070044#include <linux/hpet.h>
Ashok Raj54d5d422005-09-06 15:16:15 -070045
Yinghai Lud4057bd2008-08-19 20:50:38 -070046#include <asm/idle.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <asm/io.h>
48#include <asm/smp.h>
Jaswinder Singh Rajput6d652ea2009-01-07 21:38:59 +053049#include <asm/cpu.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#include <asm/desc.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070051#include <asm/proto.h>
52#include <asm/acpi.h>
53#include <asm/dma.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#include <asm/timer.h>
Ingo Molnar306e4402005-06-30 02:58:55 -070055#include <asm/i8259.h>
Don Zickus3e4ff112006-06-26 13:57:01 +020056#include <asm/nmi.h>
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -070057#include <asm/msidef.h>
Eric W. Biederman8b955b02006-10-04 02:16:55 -070058#include <asm/hypertransport.h>
Yinghai Lua4dbc342008-07-25 02:14:28 -070059#include <asm/setup.h>
Yinghai Lud4057bd2008-08-19 20:50:38 -070060#include <asm/irq_remapping.h>
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -070061#include <asm/hpet.h>
Dean Nelson4173a0e2008-10-02 12:18:21 -050062#include <asm/uv/uv_hub.h>
63#include <asm/uv/uv_irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
Ingo Molnar7b6aa332009-02-17 13:58:15 +010065#include <asm/apic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +010067#define __apicdebuginit(type) static type __init
68
Linus Torvalds1da177e2005-04-16 15:20:36 -070069/*
Ingo Molnar54168ed2008-08-20 09:07:45 +020070 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 */
73int sis_apic_bug = -1;
74
Yinghai Luefa25592008-08-19 20:50:36 -070075static DEFINE_SPINLOCK(ioapic_lock);
76static DEFINE_SPINLOCK(vector_lock);
77
Yinghai Luefa25592008-08-19 20:50:36 -070078/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070079 * # of IRQ routing registers
80 */
81int nr_ioapic_registers[MAX_IO_APICS];
82
Alexey Starikovskiy9f640cc2008-04-04 23:41:13 +040083/* I/O APIC entries */
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +053084struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
Alexey Starikovskiy9f640cc2008-04-04 23:41:13 +040085int nr_ioapics;
86
Alexey Starikovskiy584f7342008-04-04 23:41:32 +040087/* MP IRQ source entries */
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +053088struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
Alexey Starikovskiy584f7342008-04-04 23:41:32 +040089
90/* # of MP IRQ source entries */
91int mp_irq_entries;
92
Alexey Starikovskiy8732fc42008-05-19 19:47:16 +040093#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94int mp_bus_id_to_type[MAX_MP_BUSSES];
95#endif
96
97DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
98
Yinghai Luefa25592008-08-19 20:50:36 -070099int skip_ioapic_setup;
100
Ingo Molnar65a4e572009-01-31 03:36:17 +0100101void arch_disable_smp_support(void)
102{
103#ifdef CONFIG_PCI
104 noioapicquirk = 1;
105 noioapicreroute = -1;
106#endif
107 skip_ioapic_setup = 1;
108}
109
Ingo Molnar54168ed2008-08-20 09:07:45 +0200110static int __init parse_noapic(char *str)
Yinghai Luefa25592008-08-19 20:50:36 -0700111{
112 /* disable IO-APIC */
Ingo Molnar65a4e572009-01-31 03:36:17 +0100113 arch_disable_smp_support();
Yinghai Luefa25592008-08-19 20:50:36 -0700114 return 0;
115}
116early_param("noapic", parse_noapic);
Chuck Ebbert66759a02005-09-12 18:49:25 +0200117
Yinghai Lu0f978f42008-08-19 20:50:26 -0700118struct irq_pin_list;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +0200119
120/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 * This is performance-critical, we want to do it O(1)
122 *
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
125 */
126
Yinghai Lu0f978f42008-08-19 20:50:26 -0700127struct irq_pin_list {
128 int apic, pin;
129 struct irq_pin_list *next;
130};
Yinghai Lu301e6192008-08-19 20:50:02 -0700131
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800132static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
Yinghai Lu0f978f42008-08-19 20:50:26 -0700133{
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800134 struct irq_pin_list *pin;
135 int node;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700136
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800137 node = cpu_to_node(cpu);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700138
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800139 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700140
Yinghai Lu0f978f42008-08-19 20:50:26 -0700141 return pin;
142}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800144struct irq_cfg {
145 struct irq_pin_list *irq_2_pin;
Mike Travis22f65d32008-12-16 17:33:56 -0800146 cpumask_var_t domain;
147 cpumask_var_t old_domain;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800148 unsigned move_cleanup_count;
149 u8 vector;
150 u8 move_in_progress : 1;
Yinghai Lu48a1b102008-12-11 00:15:01 -0800151#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending : 1;
153#endif
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800154};
155
156/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157#ifdef CONFIG_SPARSE_IRQ
158static struct irq_cfg irq_cfgx[] = {
159#else
160static struct irq_cfg irq_cfgx[NR_IRQS] = {
161#endif
Mike Travis22f65d32008-12-16 17:33:56 -0800162 [0] = { .vector = IRQ0_VECTOR, },
163 [1] = { .vector = IRQ1_VECTOR, },
164 [2] = { .vector = IRQ2_VECTOR, },
165 [3] = { .vector = IRQ3_VECTOR, },
166 [4] = { .vector = IRQ4_VECTOR, },
167 [5] = { .vector = IRQ5_VECTOR, },
168 [6] = { .vector = IRQ6_VECTOR, },
169 [7] = { .vector = IRQ7_VECTOR, },
170 [8] = { .vector = IRQ8_VECTOR, },
171 [9] = { .vector = IRQ9_VECTOR, },
172 [10] = { .vector = IRQ10_VECTOR, },
173 [11] = { .vector = IRQ11_VECTOR, },
174 [12] = { .vector = IRQ12_VECTOR, },
175 [13] = { .vector = IRQ13_VECTOR, },
176 [14] = { .vector = IRQ14_VECTOR, },
177 [15] = { .vector = IRQ15_VECTOR, },
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800178};
179
Yinghai Lu13a0c3c2008-12-26 02:05:47 -0800180int __init arch_early_irq_init(void)
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800181{
182 struct irq_cfg *cfg;
183 struct irq_desc *desc;
184 int count;
185 int i;
186
187 cfg = irq_cfgx;
188 count = ARRAY_SIZE(irq_cfgx);
189
190 for (i = 0; i < count; i++) {
191 desc = irq_to_desc(i);
192 desc->chip_data = &cfg[i];
Mike Travis22f65d32008-12-16 17:33:56 -0800193 alloc_bootmem_cpumask_var(&cfg[i].domain);
194 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195 if (i < NR_IRQS_LEGACY)
196 cpumask_setall(cfg[i].domain);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800197 }
Yinghai Lu13a0c3c2008-12-26 02:05:47 -0800198
199 return 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800200}
201
202#ifdef CONFIG_SPARSE_IRQ
203static struct irq_cfg *irq_cfg(unsigned int irq)
204{
205 struct irq_cfg *cfg = NULL;
206 struct irq_desc *desc;
207
208 desc = irq_to_desc(irq);
209 if (desc)
210 cfg = desc->chip_data;
211
212 return cfg;
213}
214
215static struct irq_cfg *get_one_free_irq_cfg(int cpu)
216{
217 struct irq_cfg *cfg;
218 int node;
219
220 node = cpu_to_node(cpu);
221
222 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
Mike Travis22f65d32008-12-16 17:33:56 -0800223 if (cfg) {
Mike Travis80855f72008-12-31 18:08:47 -0800224 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
Mike Travis22f65d32008-12-16 17:33:56 -0800225 kfree(cfg);
226 cfg = NULL;
Mike Travis80855f72008-12-31 18:08:47 -0800227 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
228 GFP_ATOMIC, node)) {
Mike Travis22f65d32008-12-16 17:33:56 -0800229 free_cpumask_var(cfg->domain);
230 kfree(cfg);
231 cfg = NULL;
232 } else {
233 cpumask_clear(cfg->domain);
234 cpumask_clear(cfg->old_domain);
235 }
236 }
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800237
238 return cfg;
239}
240
Yinghai Lu13a0c3c2008-12-26 02:05:47 -0800241int arch_init_chip_data(struct irq_desc *desc, int cpu)
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800242{
243 struct irq_cfg *cfg;
244
245 cfg = desc->chip_data;
246 if (!cfg) {
247 desc->chip_data = get_one_free_irq_cfg(cpu);
248 if (!desc->chip_data) {
249 printk(KERN_ERR "can not alloc irq_cfg\n");
250 BUG_ON(1);
251 }
252 }
Yinghai Lu13a0c3c2008-12-26 02:05:47 -0800253
254 return 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800255}
256
Yinghai Lu48a1b102008-12-11 00:15:01 -0800257#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
258
259static void
260init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
261{
262 struct irq_pin_list *old_entry, *head, *tail, *entry;
263
264 cfg->irq_2_pin = NULL;
265 old_entry = old_cfg->irq_2_pin;
266 if (!old_entry)
267 return;
268
269 entry = get_one_free_irq_2_pin(cpu);
270 if (!entry)
271 return;
272
273 entry->apic = old_entry->apic;
274 entry->pin = old_entry->pin;
275 head = entry;
276 tail = entry;
277 old_entry = old_entry->next;
278 while (old_entry) {
279 entry = get_one_free_irq_2_pin(cpu);
280 if (!entry) {
281 entry = head;
282 while (entry) {
283 head = entry->next;
284 kfree(entry);
285 entry = head;
286 }
287 /* still use the old one */
288 return;
289 }
290 entry->apic = old_entry->apic;
291 entry->pin = old_entry->pin;
292 tail->next = entry;
293 tail = entry;
294 old_entry = old_entry->next;
295 }
296
297 tail->next = NULL;
298 cfg->irq_2_pin = head;
299}
300
301static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
302{
303 struct irq_pin_list *entry, *next;
304
305 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
306 return;
307
308 entry = old_cfg->irq_2_pin;
309
310 while (entry) {
311 next = entry->next;
312 kfree(entry);
313 entry = next;
314 }
315 old_cfg->irq_2_pin = NULL;
316}
317
318void arch_init_copy_chip_data(struct irq_desc *old_desc,
319 struct irq_desc *desc, int cpu)
320{
321 struct irq_cfg *cfg;
322 struct irq_cfg *old_cfg;
323
324 cfg = get_one_free_irq_cfg(cpu);
325
326 if (!cfg)
327 return;
328
329 desc->chip_data = cfg;
330
331 old_cfg = old_desc->chip_data;
332
333 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
334
335 init_copy_irq_2_pin(old_cfg, cfg, cpu);
336}
337
338static void free_irq_cfg(struct irq_cfg *old_cfg)
339{
340 kfree(old_cfg);
341}
342
343void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
344{
345 struct irq_cfg *old_cfg, *cfg;
346
347 old_cfg = old_desc->chip_data;
348 cfg = desc->chip_data;
349
350 if (old_cfg == cfg)
351 return;
352
353 if (old_cfg) {
354 free_irq_2_pin(old_cfg, cfg);
355 free_irq_cfg(old_cfg);
356 old_desc->chip_data = NULL;
357 }
358}
359
Ingo Molnard733e002008-12-17 13:35:51 +0100360static void
361set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu48a1b102008-12-11 00:15:01 -0800362{
363 struct irq_cfg *cfg = desc->chip_data;
364
365 if (!cfg->move_in_progress) {
366 /* it means that domain is not changed */
Mike Travis7f7ace02009-01-10 21:58:08 -0800367 if (!cpumask_intersects(desc->affinity, mask))
Yinghai Lu48a1b102008-12-11 00:15:01 -0800368 cfg->move_desc_pending = 1;
369 }
370}
371#endif
372
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800373#else
374static struct irq_cfg *irq_cfg(unsigned int irq)
375{
376 return irq < nr_irqs ? irq_cfgx + irq : NULL;
377}
378
379#endif
380
Yinghai Lu48a1b102008-12-11 00:15:01 -0800381#ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
Mike Travise7986732008-12-16 17:33:52 -0800382static inline void
383set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu3145e942008-12-05 18:58:34 -0800384{
385}
Yinghai Lu48a1b102008-12-11 00:15:01 -0800386#endif
Yinghai Lu3145e942008-12-05 18:58:34 -0800387
Linus Torvalds130fe052006-11-01 09:11:00 -0800388struct io_apic {
389 unsigned int index;
390 unsigned int unused[3];
391 unsigned int data;
Suresh Siddha0280f7c2009-03-16 17:05:01 -0700392 unsigned int unused2[11];
393 unsigned int eoi;
Linus Torvalds130fe052006-11-01 09:11:00 -0800394};
395
396static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
397{
398 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +0530399 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
Linus Torvalds130fe052006-11-01 09:11:00 -0800400}
401
Suresh Siddha0280f7c2009-03-16 17:05:01 -0700402static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
403{
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(vector, &io_apic->eoi);
406}
407
Linus Torvalds130fe052006-11-01 09:11:00 -0800408static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
409{
410 struct io_apic __iomem *io_apic = io_apic_base(apic);
411 writel(reg, &io_apic->index);
412 return readl(&io_apic->data);
413}
414
415static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
416{
417 struct io_apic __iomem *io_apic = io_apic_base(apic);
418 writel(reg, &io_apic->index);
419 writel(value, &io_apic->data);
420}
421
422/*
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
425 *
426 * Older SiS APIC requires we rewrite the index register
427 */
428static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
429{
Ingo Molnar54168ed2008-08-20 09:07:45 +0200430 struct io_apic __iomem *io_apic = io_apic_base(apic);
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +0200431
432 if (sis_apic_bug)
433 writel(reg, &io_apic->index);
Linus Torvalds130fe052006-11-01 09:11:00 -0800434 writel(value, &io_apic->data);
435}
436
Yinghai Lu3145e942008-12-05 18:58:34 -0800437static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700438{
439 struct irq_pin_list *entry;
440 unsigned long flags;
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700441
442 spin_lock_irqsave(&ioapic_lock, flags);
443 entry = cfg->irq_2_pin;
444 for (;;) {
445 unsigned int reg;
446 int pin;
447
448 if (!entry)
449 break;
450 pin = entry->pin;
451 reg = io_apic_read(entry->apic, 0x10 + pin*2);
452 /* Is the remote IRR bit set? */
453 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
454 spin_unlock_irqrestore(&ioapic_lock, flags);
455 return true;
456 }
457 if (!entry->next)
458 break;
459 entry = entry->next;
460 }
461 spin_unlock_irqrestore(&ioapic_lock, flags);
462
463 return false;
464}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700465
Andi Kleencf4c6a22006-09-26 10:52:30 +0200466union entry_union {
467 struct { u32 w1, w2; };
468 struct IO_APIC_route_entry entry;
469};
470
471static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
472{
473 union entry_union eu;
474 unsigned long flags;
475 spin_lock_irqsave(&ioapic_lock, flags);
476 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
477 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
478 spin_unlock_irqrestore(&ioapic_lock, flags);
479 return eu.entry;
480}
481
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800482/*
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
487 */
Andi Kleend15512f2006-12-07 02:14:07 +0100488static void
489__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
490{
491 union entry_union eu;
492 eu.entry = e;
493 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
494 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
495}
496
Jeremy Fitzhardingeca97ab92009-02-09 12:05:47 -0800497void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
Andi Kleencf4c6a22006-09-26 10:52:30 +0200498{
499 unsigned long flags;
Andi Kleencf4c6a22006-09-26 10:52:30 +0200500 spin_lock_irqsave(&ioapic_lock, flags);
Andi Kleend15512f2006-12-07 02:14:07 +0100501 __ioapic_write_entry(apic, pin, e);
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800502 spin_unlock_irqrestore(&ioapic_lock, flags);
503}
504
505/*
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
508 * high bits!
509 */
510static void ioapic_mask_entry(int apic, int pin)
511{
512 unsigned long flags;
513 union entry_union eu = { .entry.mask = 1 };
514
515 spin_lock_irqsave(&ioapic_lock, flags);
Andi Kleencf4c6a22006-09-26 10:52:30 +0200516 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
517 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
518 spin_unlock_irqrestore(&ioapic_lock, flags);
519}
520
Yinghai Lu497c9a12008-08-19 20:50:28 -0700521#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -0800522static void send_cleanup_vector(struct irq_cfg *cfg)
523{
524 cpumask_var_t cleanup_mask;
525
526 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
527 unsigned int i;
528 cfg->move_cleanup_count = 0;
529 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
530 cfg->move_cleanup_count++;
531 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
Ingo Molnardac5f412009-01-28 15:42:24 +0100532 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
Mike Travis22f65d32008-12-16 17:33:56 -0800533 } else {
534 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
535 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
Ingo Molnardac5f412009-01-28 15:42:24 +0100536 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
Mike Travis22f65d32008-12-16 17:33:56 -0800537 free_cpumask_var(cleanup_mask);
538 }
539 cfg->move_in_progress = 0;
540}
541
Yinghai Lu3145e942008-12-05 18:58:34 -0800542static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
Yinghai Lu497c9a12008-08-19 20:50:28 -0700543{
544 int apic, pin;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700545 struct irq_pin_list *entry;
Yinghai Lu3145e942008-12-05 18:58:34 -0800546 u8 vector = cfg->vector;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700547
Yinghai Lu497c9a12008-08-19 20:50:28 -0700548 entry = cfg->irq_2_pin;
549 for (;;) {
550 unsigned int reg;
551
552 if (!entry)
553 break;
554
555 apic = entry->apic;
556 pin = entry->pin;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200557 /*
558 * With interrupt-remapping, destination information comes
559 * from interrupt-remapping table entry.
560 */
561 if (!irq_remapped(irq))
562 io_apic_write(apic, 0x11 + pin*2, dest);
Yinghai Lu497c9a12008-08-19 20:50:28 -0700563 reg = io_apic_read(apic, 0x10 + pin*2);
564 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
565 reg |= vector;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200566 io_apic_modify(apic, 0x10 + pin*2, reg);
Yinghai Lu497c9a12008-08-19 20:50:28 -0700567 if (!entry->next)
568 break;
569 entry = entry->next;
570 }
571}
Yinghai Luefa25592008-08-19 20:50:36 -0700572
Mike Travise7986732008-12-16 17:33:52 -0800573static int
574assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
Yinghai Luefa25592008-08-19 20:50:36 -0700575
Mike Travis22f65d32008-12-16 17:33:56 -0800576/*
Ingo Molnardebccb32009-01-28 15:20:18 +0100577 * Either sets desc->affinity to a valid value, and returns
578 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
579 * leaves desc->affinity untouched.
Mike Travis22f65d32008-12-16 17:33:56 -0800580 */
581static unsigned int
582set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -0700583{
584 struct irq_cfg *cfg;
Yinghai Lu3145e942008-12-05 18:58:34 -0800585 unsigned int irq;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700586
Rusty Russell0de26522008-12-13 21:20:26 +1030587 if (!cpumask_intersects(mask, cpu_online_mask))
Mike Travis22f65d32008-12-16 17:33:56 -0800588 return BAD_APICID;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700589
Yinghai Lu3145e942008-12-05 18:58:34 -0800590 irq = desc->irq;
591 cfg = desc->chip_data;
592 if (assign_irq_vector(irq, cfg, mask))
Mike Travis22f65d32008-12-16 17:33:56 -0800593 return BAD_APICID;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700594
Yinghai Lufa74c902009-03-24 13:23:16 -0700595 /* check that before desc->addinity get updated */
Yinghai Lu3145e942008-12-05 18:58:34 -0800596 set_extra_move_desc(desc, mask);
Ingo Molnardebccb32009-01-28 15:20:18 +0100597
Rusty Russelle06b1b52009-03-24 14:17:19 -0700598 cpumask_copy(desc->affinity, mask);
599
600 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
Mike Travis22f65d32008-12-16 17:33:56 -0800601}
Yinghai Lu3145e942008-12-05 18:58:34 -0800602
Mike Travis22f65d32008-12-16 17:33:56 -0800603static void
604set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -0700605{
606 struct irq_cfg *cfg;
607 unsigned long flags;
608 unsigned int dest;
Mike Travis22f65d32008-12-16 17:33:56 -0800609 unsigned int irq;
610
611 irq = desc->irq;
612 cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -0700613
614 spin_lock_irqsave(&ioapic_lock, flags);
Mike Travis22f65d32008-12-16 17:33:56 -0800615 dest = set_desc_affinity(desc, mask);
616 if (dest != BAD_APICID) {
617 /* Only the high 8 bits are valid. */
618 dest = SET_APIC_LOGICAL_ID(dest);
619 __target_IO_APIC_irq(irq, dest, cfg);
620 }
Yinghai Lu497c9a12008-08-19 20:50:28 -0700621 spin_unlock_irqrestore(&ioapic_lock, flags);
622}
Yinghai Lu3145e942008-12-05 18:58:34 -0800623
Mike Travis22f65d32008-12-16 17:33:56 -0800624static void
625set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
Yinghai Lu3145e942008-12-05 18:58:34 -0800626{
Yinghai Lu497c9a12008-08-19 20:50:28 -0700627 struct irq_desc *desc;
628
Yinghai Lu497c9a12008-08-19 20:50:28 -0700629 desc = irq_to_desc(irq);
Yinghai Lu3145e942008-12-05 18:58:34 -0800630
631 set_ioapic_affinity_irq_desc(desc, mask);
Yinghai Lu497c9a12008-08-19 20:50:28 -0700632}
Yinghai Lu497c9a12008-08-19 20:50:28 -0700633#endif /* CONFIG_SMP */
634
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635/*
636 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
637 * shared ISA-space IRQs, so we have to support them. We are super
638 * fast in the common case, and fast for shared ISA-space IRQs.
639 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800640static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641{
Yinghai Lu0f978f42008-08-19 20:50:26 -0700642 struct irq_pin_list *entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643
Yinghai Lu0f978f42008-08-19 20:50:26 -0700644 entry = cfg->irq_2_pin;
645 if (!entry) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800646 entry = get_one_free_irq_2_pin(cpu);
647 if (!entry) {
648 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
649 apic, pin);
650 return;
651 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700652 cfg->irq_2_pin = entry;
653 entry->apic = apic;
654 entry->pin = pin;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700655 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700657
658 while (entry->next) {
659 /* not again, please */
660 if (entry->apic == apic && entry->pin == pin)
661 return;
662
663 entry = entry->next;
664 }
665
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -0800666 entry->next = get_one_free_irq_2_pin(cpu);
Yinghai Lu0f978f42008-08-19 20:50:26 -0700667 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 entry->apic = apic;
669 entry->pin = pin;
670}
671
672/*
673 * Reroute an IRQ to a different pin.
674 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800675static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676 int oldapic, int oldpin,
677 int newapic, int newpin)
678{
Yinghai Lu0f978f42008-08-19 20:50:26 -0700679 struct irq_pin_list *entry = cfg->irq_2_pin;
680 int replaced = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681
Yinghai Lu0f978f42008-08-19 20:50:26 -0700682 while (entry) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 if (entry->apic == oldapic && entry->pin == oldpin) {
684 entry->apic = newapic;
685 entry->pin = newpin;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700686 replaced = 1;
687 /* every one is different, right? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 break;
Yinghai Lu0f978f42008-08-19 20:50:26 -0700689 }
690 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 }
Yinghai Lu0f978f42008-08-19 20:50:26 -0700692
693 /* why? call replace before add? */
694 if (!replaced)
Yinghai Lu3145e942008-12-05 18:58:34 -0800695 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696}
697
Yinghai Lu3145e942008-12-05 18:58:34 -0800698static inline void io_apic_modify_irq(struct irq_cfg *cfg,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400699 int mask_and, int mask_or,
700 void (*final)(struct irq_pin_list *entry))
701{
702 int pin;
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400703 struct irq_pin_list *entry;
704
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400705 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
706 unsigned int reg;
707 pin = entry->pin;
708 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
709 reg &= mask_and;
710 reg |= mask_or;
711 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
712 if (final)
713 final(entry);
714 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700715}
716
Yinghai Lu3145e942008-12-05 18:58:34 -0800717static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400718{
Yinghai Lu3145e942008-12-05 18:58:34 -0800719 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400720}
Yinghai Lu4e738e22008-08-19 20:50:47 -0700721
722#ifdef CONFIG_X86_64
Jaswinder Singh Rajput7f3e6322008-12-29 20:34:35 +0530723static void io_apic_sync(struct irq_pin_list *entry)
Yinghai Lu4e738e22008-08-19 20:50:47 -0700724{
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400725 /*
726 * Synchronize the IO-APIC and the CPU by doing
727 * a dummy read from the IO-APIC
728 */
729 struct io_apic __iomem *io_apic;
730 io_apic = io_apic_base(entry->apic);
Yinghai Lu4e738e22008-08-19 20:50:47 -0700731 readl(&io_apic->data);
732}
733
Yinghai Lu3145e942008-12-05 18:58:34 -0800734static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400735{
Yinghai Lu3145e942008-12-05 18:58:34 -0800736 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400737}
738#else /* CONFIG_X86_32 */
Yinghai Lu3145e942008-12-05 18:58:34 -0800739static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400740{
Yinghai Lu3145e942008-12-05 18:58:34 -0800741 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400742}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700743
Yinghai Lu3145e942008-12-05 18:58:34 -0800744static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400745{
Yinghai Lu3145e942008-12-05 18:58:34 -0800746 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400747 IO_APIC_REDIR_MASKED, NULL);
748}
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700749
Yinghai Lu3145e942008-12-05 18:58:34 -0800750static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400751{
Yinghai Lu3145e942008-12-05 18:58:34 -0800752 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
Cyrill Gorcunov87783be2008-09-10 22:19:50 +0400753 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
754}
755#endif /* CONFIG_X86_32 */
Yinghai Lu047c8fd2008-08-19 20:50:41 -0700756
Yinghai Lu3145e942008-12-05 18:58:34 -0800757static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758{
Yinghai Lu3145e942008-12-05 18:58:34 -0800759 struct irq_cfg *cfg = desc->chip_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 unsigned long flags;
761
Yinghai Lu3145e942008-12-05 18:58:34 -0800762 BUG_ON(!cfg);
763
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -0800765 __mask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 spin_unlock_irqrestore(&ioapic_lock, flags);
767}
768
Yinghai Lu3145e942008-12-05 18:58:34 -0800769static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770{
Yinghai Lu3145e942008-12-05 18:58:34 -0800771 struct irq_cfg *cfg = desc->chip_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 unsigned long flags;
773
774 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -0800775 __unmask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 spin_unlock_irqrestore(&ioapic_lock, flags);
777}
778
Yinghai Lu3145e942008-12-05 18:58:34 -0800779static void mask_IO_APIC_irq(unsigned int irq)
780{
781 struct irq_desc *desc = irq_to_desc(irq);
782
783 mask_IO_APIC_irq_desc(desc);
784}
785static void unmask_IO_APIC_irq(unsigned int irq)
786{
787 struct irq_desc *desc = irq_to_desc(irq);
788
789 unmask_IO_APIC_irq_desc(desc);
790}
791
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
793{
794 struct IO_APIC_route_entry entry;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +0200795
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 /* Check delivery_mode to be sure we're not clearing an SMI pin */
Andi Kleencf4c6a22006-09-26 10:52:30 +0200797 entry = ioapic_read_entry(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 if (entry.delivery_mode == dest_SMI)
799 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 /*
801 * Disable it in the IO-APIC irq-routing table:
802 */
Linus Torvaldsf9dadfa2006-11-01 10:05:35 -0800803 ioapic_mask_entry(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804}
805
Ingo Molnar54168ed2008-08-20 09:07:45 +0200806static void clear_IO_APIC (void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807{
808 int apic, pin;
809
810 for (apic = 0; apic < nr_ioapics; apic++)
811 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
812 clear_IO_APIC_pin(apic, pin);
813}
814
Ingo Molnar54168ed2008-08-20 09:07:45 +0200815#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816/*
817 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
818 * specific CPU-side IRQs.
819 */
820
821#define MAX_PIRQS 8
Yinghai Lu3bd25d02009-02-15 02:54:03 -0800822static int pirq_entries[MAX_PIRQS] = {
823 [0 ... MAX_PIRQS - 1] = -1
824};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826static int __init ioapic_pirq_setup(char *str)
827{
828 int i, max;
829 int ints[MAX_PIRQS+1];
830
831 get_options(str, ARRAY_SIZE(ints), ints);
832
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 apic_printk(APIC_VERBOSE, KERN_INFO
834 "PIRQ redirection, working around broken MP-BIOS.\n");
835 max = MAX_PIRQS;
836 if (ints[0] < MAX_PIRQS)
837 max = ints[0];
838
839 for (i = 0; i < max; i++) {
840 apic_printk(APIC_VERBOSE, KERN_DEBUG
841 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
842 /*
843 * PIRQs are mapped upside down, usually.
844 */
845 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
846 }
847 return 1;
848}
849
850__setup("pirq=", ioapic_pirq_setup);
Ingo Molnar54168ed2008-08-20 09:07:45 +0200851#endif /* CONFIG_X86_32 */
852
853#ifdef CONFIG_INTR_REMAP
Fenghua Yub24696b2009-03-27 14:22:44 -0700854struct IO_APIC_route_entry **alloc_ioapic_entries(void)
855{
856 int apic;
857 struct IO_APIC_route_entry **ioapic_entries;
858
859 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
860 GFP_ATOMIC);
861 if (!ioapic_entries)
862 return 0;
863
864 for (apic = 0; apic < nr_ioapics; apic++) {
865 ioapic_entries[apic] =
866 kzalloc(sizeof(struct IO_APIC_route_entry) *
867 nr_ioapic_registers[apic], GFP_ATOMIC);
868 if (!ioapic_entries[apic])
869 goto nomem;
870 }
871
872 return ioapic_entries;
873
874nomem:
875 while (--apic >= 0)
876 kfree(ioapic_entries[apic]);
877 kfree(ioapic_entries);
878
879 return 0;
880}
Ingo Molnar54168ed2008-08-20 09:07:45 +0200881
882/*
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700883 * Saves all the IO-APIC RTE's
Ingo Molnar54168ed2008-08-20 09:07:45 +0200884 */
Fenghua Yub24696b2009-03-27 14:22:44 -0700885int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
Ingo Molnar54168ed2008-08-20 09:07:45 +0200886{
Ingo Molnar54168ed2008-08-20 09:07:45 +0200887 int apic, pin;
888
Fenghua Yub24696b2009-03-27 14:22:44 -0700889 if (!ioapic_entries)
890 return -ENOMEM;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200891
892 for (apic = 0; apic < nr_ioapics; apic++) {
Fenghua Yub24696b2009-03-27 14:22:44 -0700893 if (!ioapic_entries[apic])
894 return -ENOMEM;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200895
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700896 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
Fenghua Yub24696b2009-03-27 14:22:44 -0700897 ioapic_entries[apic][pin] =
Ingo Molnar54168ed2008-08-20 09:07:45 +0200898 ioapic_read_entry(apic, pin);
Fenghua Yub24696b2009-03-27 14:22:44 -0700899 }
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400900
Ingo Molnar54168ed2008-08-20 09:07:45 +0200901 return 0;
902}
903
Fenghua Yub24696b2009-03-27 14:22:44 -0700904/*
905 * Mask all IO APIC entries.
906 */
907void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700908{
909 int apic, pin;
910
Fenghua Yub24696b2009-03-27 14:22:44 -0700911 if (!ioapic_entries)
912 return;
913
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700914 for (apic = 0; apic < nr_ioapics; apic++) {
Fenghua Yub24696b2009-03-27 14:22:44 -0700915 if (!ioapic_entries[apic])
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700916 break;
Fenghua Yub24696b2009-03-27 14:22:44 -0700917
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700918 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
919 struct IO_APIC_route_entry entry;
920
Fenghua Yub24696b2009-03-27 14:22:44 -0700921 entry = ioapic_entries[apic][pin];
Suresh Siddha05c3dc22009-03-16 17:05:03 -0700922 if (!entry.mask) {
923 entry.mask = 1;
924 ioapic_write_entry(apic, pin, entry);
925 }
926 }
927 }
928}
929
Fenghua Yub24696b2009-03-27 14:22:44 -0700930/*
931 * Restore IO APIC entries which was saved in ioapic_entries.
932 */
933int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
Ingo Molnar54168ed2008-08-20 09:07:45 +0200934{
935 int apic, pin;
936
Fenghua Yub24696b2009-03-27 14:22:44 -0700937 if (!ioapic_entries)
938 return -ENOMEM;
939
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400940 for (apic = 0; apic < nr_ioapics; apic++) {
Fenghua Yub24696b2009-03-27 14:22:44 -0700941 if (!ioapic_entries[apic])
942 return -ENOMEM;
943
Ingo Molnar54168ed2008-08-20 09:07:45 +0200944 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
945 ioapic_write_entry(apic, pin,
Fenghua Yub24696b2009-03-27 14:22:44 -0700946 ioapic_entries[apic][pin]);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +0400947 }
Fenghua Yub24696b2009-03-27 14:22:44 -0700948 return 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +0200949}
950
Fenghua Yub24696b2009-03-27 14:22:44 -0700951void reinit_intr_remapped_IO_APIC(int intr_remapping,
952 struct IO_APIC_route_entry **ioapic_entries)
953
Ingo Molnar54168ed2008-08-20 09:07:45 +0200954{
955 /*
956 * for now plain restore of previous settings.
957 * TBD: In the case of OS enabling interrupt-remapping,
958 * IO-APIC RTE's need to be setup to point to interrupt-remapping
959 * table entries. for now, do a plain restore, and wait for
960 * the setup_IO_APIC_irqs() to do proper initialization.
961 */
Fenghua Yub24696b2009-03-27 14:22:44 -0700962 restore_IO_APIC_setup(ioapic_entries);
963}
964
965void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
966{
967 int apic;
968
969 for (apic = 0; apic < nr_ioapics; apic++)
970 kfree(ioapic_entries[apic]);
971
972 kfree(ioapic_entries);
Ingo Molnar54168ed2008-08-20 09:07:45 +0200973}
974#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975
976/*
977 * Find the IRQ entry number of a certain pin.
978 */
979static int find_irq_entry(int apic, int pin, int type)
980{
981 int i;
982
983 for (i = 0; i < mp_irq_entries; i++)
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +0530984 if (mp_irqs[i].irqtype == type &&
985 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
986 mp_irqs[i].dstapic == MP_APIC_ALL) &&
987 mp_irqs[i].dstirq == pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 return i;
989
990 return -1;
991}
992
993/*
994 * Find the pin to which IRQ[irq] (ISA) is connected
995 */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -0800996static int __init find_isa_irq_pin(int irq, int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997{
998 int i;
999
1000 for (i = 0; i < mp_irq_entries; i++) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301001 int lbus = mp_irqs[i].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002
Alexey Starikovskiyd27e2b82008-03-20 14:54:18 +03001003 if (test_bit(lbus, mp_bus_not_pci) &&
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301004 (mp_irqs[i].irqtype == type) &&
1005 (mp_irqs[i].srcbusirq == irq))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301007 return mp_irqs[i].dstirq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008 }
1009 return -1;
1010}
1011
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08001012static int __init find_isa_irq_apic(int irq, int type)
1013{
1014 int i;
1015
1016 for (i = 0; i < mp_irq_entries; i++) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301017 int lbus = mp_irqs[i].srcbus;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08001018
Alexey Starikovskiy73b29612008-03-20 14:54:24 +03001019 if (test_bit(lbus, mp_bus_not_pci) &&
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301020 (mp_irqs[i].irqtype == type) &&
1021 (mp_irqs[i].srcbusirq == irq))
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08001022 break;
1023 }
1024 if (i < mp_irq_entries) {
1025 int apic;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001026 for(apic = 0; apic < nr_ioapics; apic++) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301027 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08001028 return apic;
1029 }
1030 }
1031
1032 return -1;
1033}
1034
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035/*
1036 * Find a specific PCI IRQ entry.
1037 * Not an __init, possibly needed by modules
1038 */
1039static int pin_2_irq(int idx, int apic, int pin);
1040
1041int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1042{
1043 int apic, i, best_guess = -1;
1044
Ingo Molnar54168ed2008-08-20 09:07:45 +02001045 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1046 bus, slot, pin);
Alexey Starikovskiyce6444d2008-05-19 19:47:09 +04001047 if (test_bit(bus, mp_bus_not_pci)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001048 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049 return -1;
1050 }
1051 for (i = 0; i < mp_irq_entries; i++) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301052 int lbus = mp_irqs[i].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053
1054 for (apic = 0; apic < nr_ioapics; apic++)
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301055 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1056 mp_irqs[i].dstapic == MP_APIC_ALL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 break;
1058
Alexey Starikovskiy47cab822008-03-20 14:54:30 +03001059 if (!test_bit(lbus, mp_bus_not_pci) &&
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301060 !mp_irqs[i].irqtype &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 (bus == lbus) &&
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301062 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1063 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064
1065 if (!(apic || IO_APIC_IRQ(irq)))
1066 continue;
1067
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301068 if (pin == (mp_irqs[i].srcbusirq & 3))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069 return irq;
1070 /*
1071 * Use the first all-but-pin matching entry as a
1072 * best-guess fuzzy result for broken mptables.
1073 */
1074 if (best_guess < 0)
1075 best_guess = irq;
1076 }
1077 }
1078 return best_guess;
1079}
Ingo Molnar54168ed2008-08-20 09:07:45 +02001080
Alexey Dobriyan129f6942005-06-23 00:08:33 -07001081EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001083#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084/*
1085 * EISA Edge/Level control register, ELCR
1086 */
1087static int EISA_ELCR(unsigned int irq)
1088{
Yinghai Lu99d093d2008-12-05 18:58:32 -08001089 if (irq < NR_IRQS_LEGACY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090 unsigned int port = 0x4d0 + (irq >> 3);
1091 return (inb(port) >> (irq & 7)) & 1;
1092 }
1093 apic_printk(APIC_VERBOSE, KERN_INFO
1094 "Broken MPtable reports ISA irq %d\n", irq);
1095 return 0;
1096}
Ingo Molnar54168ed2008-08-20 09:07:45 +02001097
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001098#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001100/* ISA interrupts are always polarity zero edge triggered,
1101 * when listed as conforming in the MP table. */
1102
1103#define default_ISA_trigger(idx) (0)
1104#define default_ISA_polarity(idx) (0)
1105
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106/* EISA interrupts are always polarity zero and can be edge or level
1107 * trigger depending on the ELCR value. If an interrupt is listed as
1108 * EISA conforming in the MP table, that means its trigger type must
1109 * be read in from the ELCR */
1110
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301111#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001112#define default_EISA_polarity(idx) default_ISA_polarity(idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113
1114/* PCI interrupts are always polarity one level triggered,
1115 * when listed as conforming in the MP table. */
1116
1117#define default_PCI_trigger(idx) (1)
1118#define default_PCI_polarity(idx) (1)
1119
1120/* MCA interrupts are always polarity zero level triggered,
1121 * when listed as conforming in the MP table. */
1122
1123#define default_MCA_trigger(idx) (1)
Alexey Starikovskiy67288012008-03-20 14:54:36 +03001124#define default_MCA_polarity(idx) default_ISA_polarity(idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125
Shaohua Li61fd47e2007-11-17 01:05:28 -05001126static int MPBIOS_polarity(int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001127{
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301128 int bus = mp_irqs[idx].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129 int polarity;
1130
1131 /*
1132 * Determine IRQ line polarity (high active or low active):
1133 */
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301134 switch (mp_irqs[idx].irqflag & 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001136 case 0: /* conforms, ie. bus-type dependent polarity */
1137 if (test_bit(bus, mp_bus_not_pci))
1138 polarity = default_ISA_polarity(idx);
1139 else
1140 polarity = default_PCI_polarity(idx);
1141 break;
1142 case 1: /* high active */
1143 {
1144 polarity = 0;
1145 break;
1146 }
1147 case 2: /* reserved */
1148 {
1149 printk(KERN_WARNING "broken BIOS!!\n");
1150 polarity = 1;
1151 break;
1152 }
1153 case 3: /* low active */
1154 {
1155 polarity = 1;
1156 break;
1157 }
1158 default: /* invalid */
1159 {
1160 printk(KERN_WARNING "broken BIOS!!\n");
1161 polarity = 1;
1162 break;
1163 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 }
1165 return polarity;
1166}
1167
1168static int MPBIOS_trigger(int idx)
1169{
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301170 int bus = mp_irqs[idx].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 int trigger;
1172
1173 /*
1174 * Determine IRQ trigger mode (edge or level sensitive):
1175 */
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301176 switch ((mp_irqs[idx].irqflag>>2) & 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001177 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001178 case 0: /* conforms, ie. bus-type dependent */
1179 if (test_bit(bus, mp_bus_not_pci))
1180 trigger = default_ISA_trigger(idx);
1181 else
1182 trigger = default_PCI_trigger(idx);
Alexey Starikovskiyc0a282c2008-03-20 14:55:02 +03001183#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001184 switch (mp_bus_id_to_type[bus]) {
1185 case MP_BUS_ISA: /* ISA pin */
1186 {
1187 /* set before the switch */
1188 break;
1189 }
1190 case MP_BUS_EISA: /* EISA pin */
1191 {
1192 trigger = default_EISA_trigger(idx);
1193 break;
1194 }
1195 case MP_BUS_PCI: /* PCI pin */
1196 {
1197 /* set before the switch */
1198 break;
1199 }
1200 case MP_BUS_MCA: /* MCA pin */
1201 {
1202 trigger = default_MCA_trigger(idx);
1203 break;
1204 }
1205 default:
1206 {
1207 printk(KERN_WARNING "broken BIOS!!\n");
1208 trigger = 1;
1209 break;
1210 }
1211 }
1212#endif
1213 break;
1214 case 1: /* edge */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001215 {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001216 trigger = 0;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001217 break;
1218 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001219 case 2: /* reserved */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001220 {
1221 printk(KERN_WARNING "broken BIOS!!\n");
1222 trigger = 1;
1223 break;
1224 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001225 case 3: /* level */
1226 {
1227 trigger = 1;
1228 break;
1229 }
1230 default: /* invalid */
1231 {
1232 printk(KERN_WARNING "broken BIOS!!\n");
1233 trigger = 0;
1234 break;
1235 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236 }
1237 return trigger;
1238}
1239
1240static inline int irq_polarity(int idx)
1241{
1242 return MPBIOS_polarity(idx);
1243}
1244
1245static inline int irq_trigger(int idx)
1246{
1247 return MPBIOS_trigger(idx);
1248}
1249
Yinghai Luefa25592008-08-19 20:50:36 -07001250int (*ioapic_renumber_irq)(int ioapic, int irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251static int pin_2_irq(int idx, int apic, int pin)
1252{
1253 int irq, i;
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301254 int bus = mp_irqs[idx].srcbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255
1256 /*
1257 * Debugging check, we are in big trouble if this message pops up!
1258 */
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301259 if (mp_irqs[idx].dstirq != pin)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1261
Ingo Molnar54168ed2008-08-20 09:07:45 +02001262 if (test_bit(bus, mp_bus_not_pci)) {
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05301263 irq = mp_irqs[idx].srcbusirq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001264 } else {
Alexey Starikovskiy643befe2008-03-20 14:54:49 +03001265 /*
1266 * PCI IRQs are mapped in order
1267 */
1268 i = irq = 0;
1269 while (i < apic)
1270 irq += nr_ioapic_registers[i++];
1271 irq += pin;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001272 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02001273 * For MPS mode, so far only needed by ES7000 platform
1274 */
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001275 if (ioapic_renumber_irq)
1276 irq = ioapic_renumber_irq(apic, irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001277 }
1278
Ingo Molnar54168ed2008-08-20 09:07:45 +02001279#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -07001280 /*
1281 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1282 */
1283 if ((pin >= 16) && (pin <= 23)) {
1284 if (pirq_entries[pin-16] != -1) {
1285 if (!pirq_entries[pin-16]) {
1286 apic_printk(APIC_VERBOSE, KERN_DEBUG
1287 "disabling PIRQ%d\n", pin-16);
1288 } else {
1289 irq = pirq_entries[pin-16];
1290 apic_printk(APIC_VERBOSE, KERN_DEBUG
1291 "using PIRQ%d -> IRQ %d\n",
1292 pin-16, irq);
1293 }
1294 }
1295 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001296#endif
1297
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298 return irq;
1299}
1300
Yinghai Lu497c9a12008-08-19 20:50:28 -07001301void lock_vector_lock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001303 /* Used to the online set of cpus does not change
1304 * during assign_irq_vector.
1305 */
1306 spin_lock(&vector_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001307}
1308
Yinghai Lu497c9a12008-08-19 20:50:28 -07001309void unlock_vector_lock(void)
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001310{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001311 spin_unlock(&vector_lock);
1312}
1313
Mike Travise7986732008-12-16 17:33:52 -08001314static int
1315__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001316{
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001317 /*
1318 * NOTE! The local APIC isn't very good at handling
1319 * multiple interrupts at the same interrupt level.
1320 * As the interrupt level is determined by taking the
1321 * vector number and shifting that right by 4, we
1322 * want to spread these out a bit so that they don't
1323 * all fall in the same interrupt level.
1324 *
1325 * Also, we've got to be careful not to trash gate
1326 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1327 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001328 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1329 unsigned int old_vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001330 int cpu, err;
1331 cpumask_var_t tmp_mask;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001332
Ingo Molnar54168ed2008-08-20 09:07:45 +02001333 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1334 return -EBUSY;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001335
Mike Travis22f65d32008-12-16 17:33:56 -08001336 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1337 return -ENOMEM;
Yinghai Lu3145e942008-12-05 18:58:34 -08001338
Ingo Molnar54168ed2008-08-20 09:07:45 +02001339 old_vector = cfg->vector;
1340 if (old_vector) {
Mike Travis22f65d32008-12-16 17:33:56 -08001341 cpumask_and(tmp_mask, mask, cpu_online_mask);
1342 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1343 if (!cpumask_empty(tmp_mask)) {
1344 free_cpumask_var(tmp_mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001345 return 0;
Mike Travis22f65d32008-12-16 17:33:56 -08001346 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001347 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07001348
Mike Travise7986732008-12-16 17:33:52 -08001349 /* Only try and allocate irqs on cpus that are present */
Mike Travis22f65d32008-12-16 17:33:56 -08001350 err = -ENOSPC;
1351 for_each_cpu_and(cpu, mask, cpu_online_mask) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02001352 int new_cpu;
1353 int vector, offset;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001354
Ingo Molnare2d40b12009-01-28 06:50:47 +01001355 apic->vector_allocation_domain(cpu, tmp_mask);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001356
Ingo Molnar54168ed2008-08-20 09:07:45 +02001357 vector = current_vector;
1358 offset = current_offset;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001359next:
Ingo Molnar54168ed2008-08-20 09:07:45 +02001360 vector += 8;
1361 if (vector >= first_system_vector) {
Mike Travise7986732008-12-16 17:33:52 -08001362 /* If out of vectors on large boxen, must share them. */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001363 offset = (offset + 1) % 8;
1364 vector = FIRST_DEVICE_VECTOR + offset;
Yinghai Lu7a959cf2008-08-19 20:50:32 -07001365 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02001366 if (unlikely(current_vector == vector))
1367 continue;
Yinghai Lub77b8812008-12-19 15:23:44 -08001368
1369 if (test_bit(vector, used_vectors))
Ingo Molnar54168ed2008-08-20 09:07:45 +02001370 goto next;
Yinghai Lub77b8812008-12-19 15:23:44 -08001371
Mike Travis22f65d32008-12-16 17:33:56 -08001372 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001373 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1374 goto next;
1375 /* Found one! */
1376 current_vector = vector;
1377 current_offset = offset;
1378 if (old_vector) {
1379 cfg->move_in_progress = 1;
Mike Travis22f65d32008-12-16 17:33:56 -08001380 cpumask_copy(cfg->old_domain, cfg->domain);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001381 }
Mike Travis22f65d32008-12-16 17:33:56 -08001382 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02001383 per_cpu(vector_irq, new_cpu)[vector] = irq;
1384 cfg->vector = vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001385 cpumask_copy(cfg->domain, tmp_mask);
1386 err = 0;
1387 break;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001388 }
Mike Travis22f65d32008-12-16 17:33:56 -08001389 free_cpumask_var(tmp_mask);
1390 return err;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001391}
1392
Mike Travise7986732008-12-16 17:33:52 -08001393static int
1394assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001395{
1396 int err;
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001397 unsigned long flags;
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001398
1399 spin_lock_irqsave(&vector_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -08001400 err = __assign_irq_vector(irq, cfg, mask);
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001401 spin_unlock_irqrestore(&vector_lock, flags);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001402 return err;
1403}
1404
Yinghai Lu3145e942008-12-05 18:58:34 -08001405static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001406{
Yinghai Lu497c9a12008-08-19 20:50:28 -07001407 int cpu, vector;
1408
Yinghai Lu497c9a12008-08-19 20:50:28 -07001409 BUG_ON(!cfg->vector);
1410
1411 vector = cfg->vector;
Mike Travis22f65d32008-12-16 17:33:56 -08001412 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001413 per_cpu(vector_irq, cpu)[vector] = -1;
1414
1415 cfg->vector = 0;
Mike Travis22f65d32008-12-16 17:33:56 -08001416 cpumask_clear(cfg->domain);
Matthew Wilcox0ca4b6b2008-11-20 14:09:33 -07001417
1418 if (likely(!cfg->move_in_progress))
1419 return;
Mike Travis22f65d32008-12-16 17:33:56 -08001420 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
Matthew Wilcox0ca4b6b2008-11-20 14:09:33 -07001421 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1422 vector++) {
1423 if (per_cpu(vector_irq, cpu)[vector] != irq)
1424 continue;
1425 per_cpu(vector_irq, cpu)[vector] = -1;
1426 break;
1427 }
1428 }
1429 cfg->move_in_progress = 0;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001430}
1431
1432void __setup_vector_irq(int cpu)
1433{
1434 /* Initialize vector_irq on a new cpu */
1435 /* This function must be called with vector_lock held */
1436 int irq, vector;
1437 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001438 struct irq_desc *desc;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001439
1440 /* Mark the inuse vectors */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001441 for_each_irq_desc(irq, desc) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001442 cfg = desc->chip_data;
Mike Travis22f65d32008-12-16 17:33:56 -08001443 if (!cpumask_test_cpu(cpu, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001444 continue;
1445 vector = cfg->vector;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001446 per_cpu(vector_irq, cpu)[vector] = irq;
1447 }
1448 /* Mark the free vectors */
1449 for (vector = 0; vector < NR_VECTORS; ++vector) {
1450 irq = per_cpu(vector_irq, cpu)[vector];
1451 if (irq < 0)
1452 continue;
1453
1454 cfg = irq_cfg(irq);
Mike Travis22f65d32008-12-16 17:33:56 -08001455 if (!cpumask_test_cpu(cpu, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001456 per_cpu(vector_irq, cpu)[vector] = -1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001457 }
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07001458}
Glauber Costa3fde6902008-05-28 20:34:19 -07001459
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07001460static struct irq_chip ioapic_chip;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001461static struct irq_chip ir_ioapic_chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462
Ingo Molnar54168ed2008-08-20 09:07:45 +02001463#define IOAPIC_AUTO -1
1464#define IOAPIC_EDGE 0
1465#define IOAPIC_LEVEL 1
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001467#ifdef CONFIG_X86_32
Yinghai Lu1d025192008-08-19 20:50:34 -07001468static inline int IO_APIC_irq_trigger(int irq)
1469{
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001470 int apic, idx, pin;
Yinghai Lu1d025192008-08-19 20:50:34 -07001471
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001472 for (apic = 0; apic < nr_ioapics; apic++) {
1473 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1474 idx = find_irq_entry(apic, pin, mp_INT);
1475 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1476 return irq_trigger(idx);
1477 }
1478 }
1479 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02001480 * nonexistent IRQs are edge default
1481 */
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001482 return 0;
Yinghai Lu1d025192008-08-19 20:50:34 -07001483}
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001484#else
1485static inline int IO_APIC_irq_trigger(int irq)
1486{
Ingo Molnar54168ed2008-08-20 09:07:45 +02001487 return 1;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001488}
1489#endif
Yinghai Lu1d025192008-08-19 20:50:34 -07001490
Yinghai Lu3145e942008-12-05 18:58:34 -08001491static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492{
Yinghai Lu199751d2008-08-19 20:50:27 -07001493
Jan Beulich6ebcc002006-06-26 13:56:46 +02001494 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001495 trigger == IOAPIC_LEVEL)
Yinghai Lu08678b02008-08-19 20:50:05 -07001496 desc->status |= IRQ_LEVEL;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001497 else
1498 desc->status &= ~IRQ_LEVEL;
1499
Ingo Molnar54168ed2008-08-20 09:07:45 +02001500 if (irq_remapped(irq)) {
1501 desc->status |= IRQ_MOVE_PCNTXT;
1502 if (trigger)
1503 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1504 handle_fasteoi_irq,
1505 "fasteoi");
1506 else
1507 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1508 handle_edge_irq, "edge");
1509 return;
1510 }
Suresh Siddha29b61be2009-03-16 17:05:02 -07001511
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001512 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1513 trigger == IOAPIC_LEVEL)
Ingo Molnara460e742006-10-17 00:10:03 -07001514 set_irq_chip_and_handler_name(irq, &ioapic_chip,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001515 handle_fasteoi_irq,
1516 "fasteoi");
Yinghai Lu047c8fd2008-08-19 20:50:41 -07001517 else
Ingo Molnara460e742006-10-17 00:10:03 -07001518 set_irq_chip_and_handler_name(irq, &ioapic_chip,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001519 handle_edge_irq, "edge");
Yinghai Lu497c9a12008-08-19 20:50:28 -07001520}
1521
Jeremy Fitzhardingeca97ab92009-02-09 12:05:47 -08001522int setup_ioapic_entry(int apic_id, int irq,
1523 struct IO_APIC_route_entry *entry,
1524 unsigned int destination, int trigger,
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001525 int polarity, int vector, int pin)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001526{
1527 /*
1528 * add it to the IO-APIC irq-routing table:
1529 */
1530 memset(entry,0,sizeof(*entry));
1531
Ingo Molnar54168ed2008-08-20 09:07:45 +02001532 if (intr_remapping_enabled) {
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001533 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001534 struct irte irte;
1535 struct IR_IO_APIC_route_entry *ir_entry =
1536 (struct IR_IO_APIC_route_entry *) entry;
1537 int index;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001538
Ingo Molnar54168ed2008-08-20 09:07:45 +02001539 if (!iommu)
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001540 panic("No mapping iommu for ioapic %d\n", apic_id);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001541
1542 index = alloc_irte(iommu, irq, 1);
1543 if (index < 0)
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001544 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001545
1546 memset(&irte, 0, sizeof(irte));
1547
1548 irte.present = 1;
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001549 irte.dst_mode = apic->irq_dest_mode;
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001550 /*
1551 * Trigger mode in the IRTE will always be edge, and the
1552 * actual level or edge trigger will be setup in the IO-APIC
1553 * RTE. This will help simplify level triggered irq migration.
1554 * For more details, see the comments above explainig IO-APIC
1555 * irq migration in the presence of interrupt-remapping.
1556 */
1557 irte.trigger_mode = 0;
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001558 irte.dlvry_mode = apic->irq_delivery_mode;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001559 irte.vector = vector;
1560 irte.dest_id = IRTE_DEST(destination);
1561
1562 modify_irte(irq, &irte);
1563
1564 ir_entry->index2 = (index >> 15) & 0x1;
1565 ir_entry->zero = 0;
1566 ir_entry->format = 1;
1567 ir_entry->index = (index & 0x7fff);
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001568 /*
1569 * IO-APIC RTE will be configured with virtual vector.
1570 * irq handler will do the explicit EOI to the io-apic.
1571 */
1572 ir_entry->vector = pin;
Suresh Siddha29b61be2009-03-16 17:05:02 -07001573 } else {
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001574 entry->delivery_mode = apic->irq_delivery_mode;
1575 entry->dest_mode = apic->irq_dest_mode;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001576 entry->dest = destination;
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001577 entry->vector = vector;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001578 }
1579
1580 entry->mask = 0; /* enable IRQ */
Yinghai Lu497c9a12008-08-19 20:50:28 -07001581 entry->trigger = trigger;
1582 entry->polarity = polarity;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001583
1584 /* Mask level triggered irqs.
1585 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1586 */
1587 if (trigger)
1588 entry->mask = 1;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001589 return 0;
1590}
1591
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001592static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
Ingo Molnar54168ed2008-08-20 09:07:45 +02001593 int trigger, int polarity)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001594{
1595 struct irq_cfg *cfg;
1596 struct IO_APIC_route_entry entry;
Mike Travis22f65d32008-12-16 17:33:56 -08001597 unsigned int dest;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001598
1599 if (!IO_APIC_IRQ(irq))
1600 return;
1601
Yinghai Lu3145e942008-12-05 18:58:34 -08001602 cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -07001603
Ingo Molnarfe402e12009-01-28 04:32:51 +01001604 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
Yinghai Lu497c9a12008-08-19 20:50:28 -07001605 return;
1606
Ingo Molnardebccb32009-01-28 15:20:18 +01001607 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
Yinghai Lu497c9a12008-08-19 20:50:28 -07001608
1609 apic_printk(APIC_VERBOSE,KERN_DEBUG
1610 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1611 "IRQ %d Mode:%i Active:%i)\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001612 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
Yinghai Lu497c9a12008-08-19 20:50:28 -07001613 irq, trigger, polarity);
1614
1615
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001616 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
Suresh Siddha0280f7c2009-03-16 17:05:01 -07001617 dest, trigger, polarity, cfg->vector, pin)) {
Yinghai Lu497c9a12008-08-19 20:50:28 -07001618 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001619 mp_ioapics[apic_id].apicid, pin);
Yinghai Lu3145e942008-12-05 18:58:34 -08001620 __clear_irq_vector(irq, cfg);
Yinghai Lu497c9a12008-08-19 20:50:28 -07001621 return;
1622 }
1623
Yinghai Lu3145e942008-12-05 18:58:34 -08001624 ioapic_register_intr(irq, desc, trigger);
Yinghai Lu99d093d2008-12-05 18:58:32 -08001625 if (irq < NR_IRQS_LEGACY)
Yinghai Lu497c9a12008-08-19 20:50:28 -07001626 disable_8259A_irq(irq);
1627
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001628 ioapic_write_entry(apic_id, pin, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629}
1630
1631static void __init setup_IO_APIC_irqs(void)
1632{
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001633 int apic_id, pin, idx, irq;
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001634 int notcon = 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001635 struct irq_desc *desc;
Yinghai Lu3145e942008-12-05 18:58:34 -08001636 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001637 int cpu = boot_cpu_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638
1639 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1640
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001641 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1642 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001643
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001644 idx = find_irq_entry(apic_id, pin, mp_INT);
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001645 if (idx == -1) {
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001646 if (!notcon) {
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001647 notcon = 1;
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001648 apic_printk(APIC_VERBOSE,
1649 KERN_DEBUG " %d-%d",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001650 mp_ioapics[apic_id].apicid, pin);
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001651 } else
1652 apic_printk(APIC_VERBOSE, " %d-%d",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001653 mp_ioapics[apic_id].apicid, pin);
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001654 continue;
1655 }
Cyrill Gorcunov56ffa1a2008-09-13 13:11:16 +04001656 if (notcon) {
1657 apic_printk(APIC_VERBOSE,
1658 " (apicid-pin) not connected\n");
1659 notcon = 0;
1660 }
Yinghai Lu20d225b2007-10-17 18:04:41 +02001661
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001662 irq = pin_2_irq(idx, apic_id, pin);
Ingo Molnar33a201f2009-01-28 07:17:26 +01001663
1664 /*
1665 * Skip the timer IRQ if there's a quirk handler
1666 * installed and if it returns 1:
1667 */
1668 if (apic->multi_timer_check &&
1669 apic->multi_timer_check(apic_id, irq))
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001670 continue;
Ingo Molnar33a201f2009-01-28 07:17:26 +01001671
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001672 desc = irq_to_desc_alloc_cpu(irq, cpu);
1673 if (!desc) {
1674 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1675 continue;
1676 }
Yinghai Lu3145e942008-12-05 18:58:34 -08001677 cfg = desc->chip_data;
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001678 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001679
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001680 setup_IO_APIC_irq(apic_id, pin, irq, desc,
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001681 irq_trigger(idx), irq_polarity(idx));
1682 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683 }
1684
Cyrill Gorcunov3c2cbd22008-09-06 14:15:33 +04001685 if (notcon)
1686 apic_printk(APIC_VERBOSE,
Cyrill Gorcunov2a554fb2008-09-08 19:38:06 +04001687 " (apicid-pin) not connected\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001688}
1689
1690/*
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001691 * Set up the timer pin, possibly with the 8259A-master behind.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001692 */
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001693static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001694 int vector)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001695{
1696 struct IO_APIC_route_entry entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697
Ingo Molnar54168ed2008-08-20 09:07:45 +02001698 if (intr_remapping_enabled)
1699 return;
Ingo Molnar54168ed2008-08-20 09:07:45 +02001700
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001701 memset(&entry, 0, sizeof(entry));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702
1703 /*
1704 * We use logical delivery to get the timer IRQ
1705 * to the first CPU.
1706 */
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001707 entry.dest_mode = apic->irq_dest_mode;
Yinghai Luf72dcca2009-02-08 16:18:03 -08001708 entry.mask = 0; /* don't mask IRQ for edge */
Ingo Molnardebccb32009-01-28 15:20:18 +01001709 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01001710 entry.delivery_mode = apic->irq_delivery_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001711 entry.polarity = 0;
1712 entry.trigger = 0;
1713 entry.vector = vector;
1714
1715 /*
1716 * The timer IRQ doesn't have to know that behind the
Maciej W. Rozyckif7633ce2008-05-27 21:19:34 +01001717 * scene we may have a 8259A-master in AEOI mode ...
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02001719 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001720
1721 /*
1722 * Add it to the IO-APIC irq-routing table:
1723 */
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01001724 ioapic_write_entry(apic_id, pin, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725}
1726
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001727
1728__apicdebuginit(void) print_IO_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001729{
1730 int apic, i;
1731 union IO_APIC_reg_00 reg_00;
1732 union IO_APIC_reg_01 reg_01;
1733 union IO_APIC_reg_02 reg_02;
1734 union IO_APIC_reg_03 reg_03;
1735 unsigned long flags;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001736 struct irq_cfg *cfg;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001737 struct irq_desc *desc;
Yinghai Lu8f09cd22008-08-19 20:50:51 -07001738 unsigned int irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739
1740 if (apic_verbosity == APIC_QUIET)
1741 return;
1742
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02001743 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744 for (i = 0; i < nr_ioapics; i++)
1745 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +05301746 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001747
1748 /*
1749 * We are a bit conservative about what we expect. We have to
1750 * know about every hardware change ASAP.
1751 */
1752 printk(KERN_INFO "testing the IO APIC.......................\n");
1753
1754 for (apic = 0; apic < nr_ioapics; apic++) {
1755
1756 spin_lock_irqsave(&ioapic_lock, flags);
1757 reg_00.raw = io_apic_read(apic, 0);
1758 reg_01.raw = io_apic_read(apic, 1);
1759 if (reg_01.bits.version >= 0x10)
1760 reg_02.raw = io_apic_read(apic, 2);
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02001761 if (reg_01.bits.version >= 0x20)
1762 reg_03.raw = io_apic_read(apic, 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001763 spin_unlock_irqrestore(&ioapic_lock, flags);
1764
Ingo Molnar54168ed2008-08-20 09:07:45 +02001765 printk("\n");
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +05301766 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1768 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1769 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1770 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001771
Ingo Molnar54168ed2008-08-20 09:07:45 +02001772 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001773 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001774
1775 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1776 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001777
1778 /*
1779 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1780 * but the value of reg_02 is read as the previous read register
1781 * value, so ignore it if reg_02 == reg_01.
1782 */
1783 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1784 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1785 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001786 }
1787
1788 /*
1789 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1790 * or reg_03, but the value of reg_0[23] is read as the previous read
1791 * register value, so ignore it if reg_03 == reg_0[12].
1792 */
1793 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1794 reg_03.raw != reg_01.raw) {
1795 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1796 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001797 }
1798
1799 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1800
Yinghai Lud83e94a2008-08-19 20:50:33 -07001801 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1802 " Stat Dmod Deli Vect: \n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803
1804 for (i = 0; i <= reg_01.bits.entries; i++) {
1805 struct IO_APIC_route_entry entry;
1806
Andi Kleencf4c6a22006-09-26 10:52:30 +02001807 entry = ioapic_read_entry(apic, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808
Ingo Molnar54168ed2008-08-20 09:07:45 +02001809 printk(KERN_DEBUG " %02x %03X ",
1810 i,
1811 entry.dest
1812 );
Linus Torvalds1da177e2005-04-16 15:20:36 -07001813
1814 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1815 entry.mask,
1816 entry.trigger,
1817 entry.irr,
1818 entry.polarity,
1819 entry.delivery_status,
1820 entry.dest_mode,
1821 entry.delivery_mode,
1822 entry.vector
1823 );
1824 }
1825 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001826 printk(KERN_DEBUG "IRQ to pin mappings:\n");
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001827 for_each_irq_desc(irq, desc) {
1828 struct irq_pin_list *entry;
1829
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08001830 cfg = desc->chip_data;
1831 entry = cfg->irq_2_pin;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001832 if (!entry)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001833 continue;
Yinghai Lu8f09cd22008-08-19 20:50:51 -07001834 printk(KERN_DEBUG "IRQ%d ", irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001835 for (;;) {
1836 printk("-> %d:%d", entry->apic, entry->pin);
1837 if (!entry->next)
1838 break;
Yinghai Lu0f978f42008-08-19 20:50:26 -07001839 entry = entry->next;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001840 }
1841 printk("\n");
1842 }
1843
1844 printk(KERN_INFO ".................................... done.\n");
1845
1846 return;
1847}
1848
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001849__apicdebuginit(void) print_APIC_bitfield(int base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001850{
1851 unsigned int v;
1852 int i, j;
1853
1854 if (apic_verbosity == APIC_QUIET)
1855 return;
1856
1857 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1858 for (i = 0; i < 8; i++) {
1859 v = apic_read(base + i*0x10);
1860 for (j = 0; j < 32; j++) {
1861 if (v & (1<<j))
1862 printk("1");
1863 else
1864 printk("0");
1865 }
1866 printk("\n");
1867 }
1868}
1869
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001870__apicdebuginit(void) print_local_APIC(void *dummy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001871{
1872 unsigned int v, ver, maxlvt;
Hiroshi Shimamoto7ab6af72008-07-30 17:36:48 -07001873 u64 icr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874
1875 if (apic_verbosity == APIC_QUIET)
1876 return;
1877
1878 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1879 smp_processor_id(), hard_smp_processor_id());
Andreas Herrmann66823112008-06-05 16:35:10 +02001880 v = apic_read(APIC_ID);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001881 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882 v = apic_read(APIC_LVR);
1883 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1884 ver = GET_APIC_VERSION(v);
Thomas Gleixnere05d7232007-02-16 01:27:58 -08001885 maxlvt = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886
1887 v = apic_read(APIC_TASKPRI);
1888 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1889
Ingo Molnar54168ed2008-08-20 09:07:45 +02001890 if (APIC_INTEGRATED(ver)) { /* !82489DX */
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001891 if (!APIC_XAPIC(ver)) {
1892 v = apic_read(APIC_ARBPRI);
1893 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1894 v & APIC_ARBPRI_MASK);
1895 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896 v = apic_read(APIC_PROCPRI);
1897 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1898 }
1899
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001900 /*
1901 * Remote read supported only in the 82489DX and local APIC for
1902 * Pentium processors.
1903 */
1904 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1905 v = apic_read(APIC_RRR);
1906 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1907 }
1908
Linus Torvalds1da177e2005-04-16 15:20:36 -07001909 v = apic_read(APIC_LDR);
1910 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
Yinghai Lua11b5ab2008-09-03 16:58:31 -07001911 if (!x2apic_enabled()) {
1912 v = apic_read(APIC_DFR);
1913 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1914 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001915 v = apic_read(APIC_SPIV);
1916 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1917
1918 printk(KERN_DEBUG "... APIC ISR field:\n");
1919 print_APIC_bitfield(APIC_ISR);
1920 printk(KERN_DEBUG "... APIC TMR field:\n");
1921 print_APIC_bitfield(APIC_TMR);
1922 printk(KERN_DEBUG "... APIC IRR field:\n");
1923 print_APIC_bitfield(APIC_IRR);
1924
Ingo Molnar54168ed2008-08-20 09:07:45 +02001925 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1926 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927 apic_write(APIC_ESR, 0);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001928
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929 v = apic_read(APIC_ESR);
1930 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1931 }
1932
Hiroshi Shimamoto7ab6af72008-07-30 17:36:48 -07001933 icr = apic_icr_read();
Ingo Molnar0c425ce2008-08-18 13:04:26 +02001934 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1935 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001936
1937 v = apic_read(APIC_LVTT);
1938 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1939
1940 if (maxlvt > 3) { /* PC is LVT#4. */
1941 v = apic_read(APIC_LVTPC);
1942 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1943 }
1944 v = apic_read(APIC_LVT0);
1945 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1946 v = apic_read(APIC_LVT1);
1947 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1948
1949 if (maxlvt > 2) { /* ERR is LVT#3. */
1950 v = apic_read(APIC_LVTERR);
1951 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1952 }
1953
1954 v = apic_read(APIC_TMICT);
1955 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1956 v = apic_read(APIC_TMCCT);
1957 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1958 v = apic_read(APIC_TDCR);
1959 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1960 printk("\n");
1961}
1962
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001963__apicdebuginit(void) print_all_local_APICs(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001964{
Yinghai Luffd5aae2008-08-19 20:50:50 -07001965 int cpu;
1966
1967 preempt_disable();
1968 for_each_online_cpu(cpu)
1969 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1970 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001971}
1972
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01001973__apicdebuginit(void) print_PIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001974{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001975 unsigned int v;
1976 unsigned long flags;
1977
1978 if (apic_verbosity == APIC_QUIET)
1979 return;
1980
1981 printk(KERN_DEBUG "\nprinting PIC contents\n");
1982
1983 spin_lock_irqsave(&i8259A_lock, flags);
1984
1985 v = inb(0xa1) << 8 | inb(0x21);
1986 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1987
1988 v = inb(0xa0) << 8 | inb(0x20);
1989 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1990
Ingo Molnar54168ed2008-08-20 09:07:45 +02001991 outb(0x0b,0xa0);
1992 outb(0x0b,0x20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001993 v = inb(0xa0) << 8 | inb(0x20);
Ingo Molnar54168ed2008-08-20 09:07:45 +02001994 outb(0x0a,0xa0);
1995 outb(0x0a,0x20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001996
1997 spin_unlock_irqrestore(&i8259A_lock, flags);
1998
1999 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
2000
2001 v = inb(0x4d1) << 8 | inb(0x4d0);
2002 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
2003}
2004
Maciej W. Rozycki32f71af2008-07-21 00:52:49 +01002005__apicdebuginit(int) print_all_ICs(void)
2006{
2007 print_PIC();
2008 print_all_local_APICs();
2009 print_IO_APIC();
2010
2011 return 0;
2012}
2013
2014fs_initcall(print_all_ICs);
2015
Linus Torvalds1da177e2005-04-16 15:20:36 -07002016
Yinghai Luefa25592008-08-19 20:50:36 -07002017/* Where if anywhere is the i8259 connect in external int mode */
2018static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
2019
Ingo Molnar54168ed2008-08-20 09:07:45 +02002020void __init enable_IO_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002021{
2022 union IO_APIC_reg_01 reg_01;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002023 int i8259_apic, i8259_pin;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002024 int apic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025 unsigned long flags;
2026
Linus Torvalds1da177e2005-04-16 15:20:36 -07002027 /*
2028 * The number of IO-APIC IRQ registers (== #pins):
2029 */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002030 for (apic = 0; apic < nr_ioapics; apic++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031 spin_lock_irqsave(&ioapic_lock, flags);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002032 reg_01.raw = io_apic_read(apic, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002033 spin_unlock_irqrestore(&ioapic_lock, flags);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002034 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2035 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002036 for(apic = 0; apic < nr_ioapics; apic++) {
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002037 int pin;
2038 /* See if any of the pins is in ExtINT mode */
Eric W. Biederman1008fdd2006-01-11 22:46:06 +01002039 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002040 struct IO_APIC_route_entry entry;
Andi Kleencf4c6a22006-09-26 10:52:30 +02002041 entry = ioapic_read_entry(apic, pin);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002042
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002043 /* If the interrupt line is enabled and in ExtInt mode
2044 * I have found the pin where the i8259 is connected.
2045 */
2046 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2047 ioapic_i8259.apic = apic;
2048 ioapic_i8259.pin = pin;
2049 goto found_i8259;
2050 }
2051 }
2052 }
2053 found_i8259:
2054 /* Look to see what if the MP table has reported the ExtINT */
2055 /* If we could not find the appropriate pin by looking at the ioapic
2056 * the i8259 probably is not connected the ioapic but give the
2057 * mptable a chance anyway.
2058 */
2059 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2060 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2061 /* Trust the MP table if nothing is setup in the hardware */
2062 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2063 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2064 ioapic_i8259.pin = i8259_pin;
2065 ioapic_i8259.apic = i8259_apic;
2066 }
2067 /* Complain if the MP table and the hardware disagree */
2068 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2069 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2070 {
2071 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002072 }
2073
2074 /*
2075 * Do not trust the IO-APIC being empty at bootup
2076 */
2077 clear_IO_APIC();
2078}
2079
2080/*
2081 * Not an __init, needed by the reboot code
2082 */
2083void disable_IO_APIC(void)
2084{
2085 /*
2086 * Clear the IO-APIC before rebooting:
2087 */
2088 clear_IO_APIC();
2089
Eric W. Biederman650927e2005-06-25 14:57:44 -07002090 /*
Karsten Wiese0b968d22005-09-09 12:59:04 +02002091 * If the i8259 is routed through an IOAPIC
Eric W. Biederman650927e2005-06-25 14:57:44 -07002092 * Put that IOAPIC in virtual wire mode
Karsten Wiese0b968d22005-09-09 12:59:04 +02002093 * so legacy interrupts can be delivered.
Suresh Siddha7c6d9f92009-03-16 17:04:59 -07002094 *
2095 * With interrupt-remapping, for now we will use virtual wire A mode,
2096 * as virtual wire B is little complex (need to configure both
2097 * IOAPIC RTE aswell as interrupt-remapping table entry).
2098 * As this gets called during crash dump, keep this simple for now.
Eric W. Biederman650927e2005-06-25 14:57:44 -07002099 */
Suresh Siddha7c6d9f92009-03-16 17:04:59 -07002100 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
Eric W. Biederman650927e2005-06-25 14:57:44 -07002101 struct IO_APIC_route_entry entry;
Eric W. Biederman650927e2005-06-25 14:57:44 -07002102
2103 memset(&entry, 0, sizeof(entry));
2104 entry.mask = 0; /* Enabled */
2105 entry.trigger = 0; /* Edge */
2106 entry.irr = 0;
2107 entry.polarity = 0; /* High */
2108 entry.delivery_status = 0;
2109 entry.dest_mode = 0; /* Physical */
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002110 entry.delivery_mode = dest_ExtINT; /* ExtInt */
Eric W. Biederman650927e2005-06-25 14:57:44 -07002111 entry.vector = 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002112 entry.dest = read_apic_id();
Eric W. Biederman650927e2005-06-25 14:57:44 -07002113
2114 /*
2115 * Add it to the IO-APIC irq-routing table:
2116 */
Andi Kleencf4c6a22006-09-26 10:52:30 +02002117 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
Eric W. Biederman650927e2005-06-25 14:57:44 -07002118 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002119
Suresh Siddha7c6d9f92009-03-16 17:04:59 -07002120 /*
2121 * Use virtual wire A mode when interrupt remapping is enabled.
2122 */
2123 disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002124}
2125
Ingo Molnar54168ed2008-08-20 09:07:45 +02002126#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -07002127/*
2128 * function to set the IO-APIC physical IDs based on the
2129 * values stored in the MPC table.
2130 *
2131 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2132 */
2133
Linus Torvalds1da177e2005-04-16 15:20:36 -07002134static void __init setup_ioapic_ids_from_mpc(void)
2135{
2136 union IO_APIC_reg_00 reg_00;
2137 physid_mask_t phys_id_present_map;
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002138 int apic_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002139 int i;
2140 unsigned char old_id;
2141 unsigned long flags;
2142
Yinghai Lua4dbc342008-07-25 02:14:28 -07002143 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
Yinghai Lud49c4282008-06-08 18:31:54 -07002144 return;
Yinghai Lud49c4282008-06-08 18:31:54 -07002145
Linus Torvalds1da177e2005-04-16 15:20:36 -07002146 /*
Natalie Protasevichca05fea2005-06-23 00:08:22 -07002147 * Don't check I/O APIC IDs for xAPIC systems. They have
2148 * no meaning without the serial APIC bus.
2149 */
Shaohua Li7c5c1e42006-03-23 02:59:53 -08002150 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2151 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
Natalie Protasevichca05fea2005-06-23 00:08:22 -07002152 return;
2153 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002154 * This is broken; anything with a real cpu count has to
2155 * circumvent this idiocy regardless.
2156 */
Ingo Molnard190cb82009-01-28 06:50:47 +01002157 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002158
2159 /*
2160 * Set the IOAPIC ID to the value stored in the MPC table.
2161 */
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002162 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002163
2164 /* Read the register 0 value */
2165 spin_lock_irqsave(&ioapic_lock, flags);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002166 reg_00.raw = io_apic_read(apic_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002167 spin_unlock_irqrestore(&ioapic_lock, flags);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002168
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002169 old_id = mp_ioapics[apic_id].apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002170
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002171 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002172 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002173 apic_id, mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002174 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2175 reg_00.bits.ID);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002176 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002177 }
2178
Linus Torvalds1da177e2005-04-16 15:20:36 -07002179 /*
2180 * Sanity check, is the ID really free? Every APIC in a
2181 * system must have a unique ID or we get lots of nice
2182 * 'stuck on smp_invalidate_needed IPI wait' messages.
2183 */
Ingo Molnard1d7cae2009-01-28 05:41:42 +01002184 if (apic->check_apicid_used(phys_id_present_map,
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002185 mp_ioapics[apic_id].apicid)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002186 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002187 apic_id, mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002188 for (i = 0; i < get_physical_broadcast(); i++)
2189 if (!physid_isset(i, phys_id_present_map))
2190 break;
2191 if (i >= get_physical_broadcast())
2192 panic("Max APIC ID exceeded!\n");
2193 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2194 i);
2195 physid_set(i, phys_id_present_map);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002196 mp_ioapics[apic_id].apicid = i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002197 } else {
2198 physid_mask_t tmp;
Ingo Molnar80587142009-01-28 06:50:47 +01002199 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002200 apic_printk(APIC_VERBOSE, "Setting %d in the "
2201 "phys_id_present_map\n",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002202 mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002203 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2204 }
2205
2206
2207 /*
2208 * We need to adjust the IRQ routing table
2209 * if the ID changed.
2210 */
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002211 if (old_id != mp_ioapics[apic_id].apicid)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002212 for (i = 0; i < mp_irq_entries; i++)
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05302213 if (mp_irqs[i].dstapic == old_id)
2214 mp_irqs[i].dstapic
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002215 = mp_ioapics[apic_id].apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002216
2217 /*
2218 * Read the right value from the MPC table and
2219 * write it into the ID register.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002220 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002221 apic_printk(APIC_VERBOSE, KERN_INFO
2222 "...changing IO-APIC physical APIC ID to %d ...",
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002223 mp_ioapics[apic_id].apicid);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002224
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002225 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002226 spin_lock_irqsave(&ioapic_lock, flags);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002227 io_apic_write(apic_id, 0, reg_00.raw);
Yinghai Lua2d332f2008-08-21 12:56:32 -07002228 spin_unlock_irqrestore(&ioapic_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002229
2230 /*
2231 * Sanity check
2232 */
2233 spin_lock_irqsave(&ioapic_lock, flags);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002234 reg_00.raw = io_apic_read(apic_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002235 spin_unlock_irqrestore(&ioapic_lock, flags);
Ingo Molnarc8d46cf2009-01-28 00:14:11 +01002236 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002237 printk("could not set ID!\n");
2238 else
2239 apic_printk(APIC_VERBOSE, " ok.\n");
2240 }
2241}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002242#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002243
Zachary Amsden7ce0bcf2007-02-13 13:26:21 +01002244int no_timer_check __initdata;
Zachary Amsden8542b202006-12-07 02:14:09 +01002245
2246static int __init notimercheck(char *s)
2247{
2248 no_timer_check = 1;
2249 return 1;
2250}
2251__setup("no_timer_check", notimercheck);
2252
Linus Torvalds1da177e2005-04-16 15:20:36 -07002253/*
2254 * There is a nasty bug in some older SMP boards, their mptable lies
2255 * about the timer IRQ. We do the following to work around the situation:
2256 *
2257 * - timer IRQ defaults to IO-APIC IRQ
2258 * - if this function detects that timer IRQs are defunct, then we fall
2259 * back to ISA timer IRQs
2260 */
Adrian Bunkf0a7a5c2007-07-21 17:10:29 +02002261static int __init timer_irq_works(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002262{
2263 unsigned long t1 = jiffies;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002264 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002265
Zachary Amsden8542b202006-12-07 02:14:09 +01002266 if (no_timer_check)
2267 return 1;
2268
Ingo Molnar4aae0702007-12-18 18:05:58 +01002269 local_save_flags(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002270 local_irq_enable();
2271 /* Let ten ticks pass... */
2272 mdelay((10 * 1000) / HZ);
Ingo Molnar4aae0702007-12-18 18:05:58 +01002273 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002274
2275 /*
2276 * Expect a few ticks at least, to be sure some possible
2277 * glue logic does not lock up after one or two first
2278 * ticks in a non-ExtINT mode. Also the local APIC
2279 * might have cached one ExtINT interrupt. Finally, at
2280 * least one tick may be lost due to delays.
2281 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002282
2283 /* jiffies wrap? */
Julia Lawall1d16b532008-01-30 13:32:19 +01002284 if (time_after(jiffies, t1 + 4))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002285 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002286 return 0;
2287}
2288
2289/*
2290 * In the SMP+IOAPIC case it might happen that there are an unspecified
2291 * number of pending IRQ events unhandled. These cases are very rare,
2292 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2293 * better to do it this way as thus we do not have to be aware of
2294 * 'pending' interrupts in the IRQ path, except at this point.
2295 */
2296/*
2297 * Edge triggered needs to resend any interrupt
2298 * that was delayed but this is now handled in the device
2299 * independent code.
2300 */
2301
2302/*
2303 * Starting up a edge-triggered IO-APIC interrupt is
2304 * nasty - we need to make sure that we get the edge.
2305 * If it is already asserted for some reason, we need
2306 * return 1 to indicate that is was pending.
2307 *
2308 * This is not complete - we should be able to fake
2309 * an edge even if it isn't on the 8259A...
2310 */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002311
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002312static unsigned int startup_ioapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002313{
2314 int was_pending = 0;
2315 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002316 struct irq_cfg *cfg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002317
2318 spin_lock_irqsave(&ioapic_lock, flags);
Yinghai Lu99d093d2008-12-05 18:58:32 -08002319 if (irq < NR_IRQS_LEGACY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002320 disable_8259A_irq(irq);
2321 if (i8259A_irq_pending(irq))
2322 was_pending = 1;
2323 }
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002324 cfg = irq_cfg(irq);
Yinghai Lu3145e942008-12-05 18:58:34 -08002325 __unmask_IO_APIC_irq(cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002326 spin_unlock_irqrestore(&ioapic_lock, flags);
2327
2328 return was_pending;
2329}
2330
Ingo Molnar54168ed2008-08-20 09:07:45 +02002331#ifdef CONFIG_X86_64
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07002332static int ioapic_retrigger_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002333{
Ingo Molnar54168ed2008-08-20 09:07:45 +02002334
2335 struct irq_cfg *cfg = irq_cfg(irq);
2336 unsigned long flags;
2337
2338 spin_lock_irqsave(&vector_lock, flags);
Ingo Molnardac5f412009-01-28 15:42:24 +01002339 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002340 spin_unlock_irqrestore(&vector_lock, flags);
Ingo Molnarc0ad90a2006-06-29 02:24:44 -07002341
2342 return 1;
2343}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002344#else
2345static int ioapic_retrigger_irq(unsigned int irq)
2346{
Ingo Molnardac5f412009-01-28 15:42:24 +01002347 apic->send_IPI_self(irq_cfg(irq)->vector);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002348
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002349 return 1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002350}
2351#endif
2352
2353/*
2354 * Level and edge triggered IO-APIC interrupts need different handling,
2355 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2356 * handled with the level-triggered descriptor, but that one has slightly
2357 * more overhead. Level-triggered interrupts cannot be handled with the
2358 * edge-triggered handler, without risking IRQ storms and other ugly
2359 * races.
2360 */
Ingo Molnarc0ad90a2006-06-29 02:24:44 -07002361
Yinghai Lu497c9a12008-08-19 20:50:28 -07002362#ifdef CONFIG_SMP
Ingo Molnar54168ed2008-08-20 09:07:45 +02002363
2364#ifdef CONFIG_INTR_REMAP
Ingo Molnar54168ed2008-08-20 09:07:45 +02002365
2366/*
2367 * Migrate the IO-APIC irq in the presence of intr-remapping.
2368 *
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002369 * For both level and edge triggered, irq migration is a simple atomic
2370 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
Ingo Molnar54168ed2008-08-20 09:07:45 +02002371 *
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002372 * For level triggered, we eliminate the io-apic RTE modification (with the
2373 * updated vector information), by using a virtual vector (io-apic pin number).
2374 * Real vector that is used for interrupting cpu will be coming from
2375 * the interrupt-remapping table entry.
Ingo Molnar54168ed2008-08-20 09:07:45 +02002376 */
Mike Travise7986732008-12-16 17:33:52 -08002377static void
2378migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002379{
2380 struct irq_cfg *cfg;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002381 struct irte irte;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002382 unsigned int dest;
Yinghai Lu3145e942008-12-05 18:58:34 -08002383 unsigned int irq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002384
Mike Travis22f65d32008-12-16 17:33:56 -08002385 if (!cpumask_intersects(mask, cpu_online_mask))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002386 return;
2387
Yinghai Lu3145e942008-12-05 18:58:34 -08002388 irq = desc->irq;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002389 if (get_irte(irq, &irte))
2390 return;
2391
Yinghai Lu3145e942008-12-05 18:58:34 -08002392 cfg = desc->chip_data;
2393 if (assign_irq_vector(irq, cfg, mask))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002394 return;
2395
Yinghai Lu3145e942008-12-05 18:58:34 -08002396 set_extra_move_desc(desc, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002397
Ingo Molnardebccb32009-01-28 15:20:18 +01002398 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002399
Ingo Molnar54168ed2008-08-20 09:07:45 +02002400 irte.vector = cfg->vector;
2401 irte.dest_id = IRTE_DEST(dest);
2402
2403 /*
2404 * Modified the IRTE and flushes the Interrupt entry cache.
2405 */
2406 modify_irte(irq, &irte);
2407
Mike Travis22f65d32008-12-16 17:33:56 -08002408 if (cfg->move_in_progress)
2409 send_cleanup_vector(cfg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002410
Mike Travis7f7ace02009-01-10 21:58:08 -08002411 cpumask_copy(desc->affinity, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002412}
2413
Ingo Molnar54168ed2008-08-20 09:07:45 +02002414/*
2415 * Migrates the IRQ destination in the process context.
2416 */
Rusty Russell968ea6d2008-12-13 21:55:51 +10302417static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2418 const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002419{
Yinghai Lu3145e942008-12-05 18:58:34 -08002420 migrate_ioapic_irq_desc(desc, mask);
2421}
Rusty Russell0de26522008-12-13 21:20:26 +10302422static void set_ir_ioapic_affinity_irq(unsigned int irq,
2423 const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02002424{
2425 struct irq_desc *desc = irq_to_desc(irq);
2426
Yinghai Lu3145e942008-12-05 18:58:34 -08002427 set_ir_ioapic_affinity_irq_desc(desc, mask);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002428}
Suresh Siddha29b61be2009-03-16 17:05:02 -07002429#else
2430static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2431 const struct cpumask *mask)
2432{
2433}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002434#endif
2435
Yinghai Lu497c9a12008-08-19 20:50:28 -07002436asmlinkage void smp_irq_move_cleanup_interrupt(void)
2437{
2438 unsigned vector, me;
Hiroshi Shimamoto8f2466f2008-12-08 19:19:07 -08002439
Yinghai Lu497c9a12008-08-19 20:50:28 -07002440 ack_APIC_irq();
Ingo Molnar54168ed2008-08-20 09:07:45 +02002441 exit_idle();
Yinghai Lu497c9a12008-08-19 20:50:28 -07002442 irq_enter();
2443
2444 me = smp_processor_id();
2445 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2446 unsigned int irq;
Suresh Siddha68a8ca52009-03-16 17:05:04 -07002447 unsigned int irr;
Yinghai Lu497c9a12008-08-19 20:50:28 -07002448 struct irq_desc *desc;
2449 struct irq_cfg *cfg;
2450 irq = __get_cpu_var(vector_irq)[vector];
2451
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002452 if (irq == -1)
2453 continue;
2454
Yinghai Lu497c9a12008-08-19 20:50:28 -07002455 desc = irq_to_desc(irq);
2456 if (!desc)
2457 continue;
2458
2459 cfg = irq_cfg(irq);
2460 spin_lock(&desc->lock);
2461 if (!cfg->move_cleanup_count)
2462 goto unlock;
2463
Mike Travis22f65d32008-12-16 17:33:56 -08002464 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
Yinghai Lu497c9a12008-08-19 20:50:28 -07002465 goto unlock;
2466
Suresh Siddha68a8ca52009-03-16 17:05:04 -07002467 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2468 /*
2469 * Check if the vector that needs to be cleanedup is
2470 * registered at the cpu's IRR. If so, then this is not
2471 * the best time to clean it up. Lets clean it up in the
2472 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2473 * to myself.
2474 */
2475 if (irr & (1 << (vector % 32))) {
2476 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2477 goto unlock;
2478 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07002479 __get_cpu_var(vector_irq)[vector] = -1;
2480 cfg->move_cleanup_count--;
2481unlock:
2482 spin_unlock(&desc->lock);
2483 }
2484
2485 irq_exit();
2486}
2487
Yinghai Lu3145e942008-12-05 18:58:34 -08002488static void irq_complete_move(struct irq_desc **descp)
Yinghai Lu497c9a12008-08-19 20:50:28 -07002489{
Yinghai Lu3145e942008-12-05 18:58:34 -08002490 struct irq_desc *desc = *descp;
2491 struct irq_cfg *cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -07002492 unsigned vector, me;
2493
Yinghai Lu48a1b102008-12-11 00:15:01 -08002494 if (likely(!cfg->move_in_progress)) {
2495#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2496 if (likely(!cfg->move_desc_pending))
2497 return;
2498
Yinghai Lub9098952008-12-19 13:48:34 -08002499 /* domain has not changed, but affinity did */
Yinghai Lu48a1b102008-12-11 00:15:01 -08002500 me = smp_processor_id();
Mike Travis7f7ace02009-01-10 21:58:08 -08002501 if (cpumask_test_cpu(me, desc->affinity)) {
Yinghai Lu48a1b102008-12-11 00:15:01 -08002502 *descp = desc = move_irq_desc(desc, me);
2503 /* get the new one */
2504 cfg = desc->chip_data;
2505 cfg->move_desc_pending = 0;
2506 }
2507#endif
Yinghai Lu497c9a12008-08-19 20:50:28 -07002508 return;
Yinghai Lu48a1b102008-12-11 00:15:01 -08002509 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07002510
2511 vector = ~get_irq_regs()->orig_ax;
2512 me = smp_processor_id();
Yinghai Lu10b888d2009-01-31 14:50:07 -08002513
2514 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
Yinghai Lu48a1b102008-12-11 00:15:01 -08002515#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2516 *descp = desc = move_irq_desc(desc, me);
2517 /* get the new one */
2518 cfg = desc->chip_data;
2519#endif
Mike Travis22f65d32008-12-16 17:33:56 -08002520 send_cleanup_vector(cfg);
Yinghai Lu10b888d2009-01-31 14:50:07 -08002521 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07002522}
2523#else
Yinghai Lu3145e942008-12-05 18:58:34 -08002524static inline void irq_complete_move(struct irq_desc **descp) {}
Yinghai Lu497c9a12008-08-19 20:50:28 -07002525#endif
Yinghai Lu3145e942008-12-05 18:58:34 -08002526
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002527static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2528{
2529 int apic, pin;
2530 struct irq_pin_list *entry;
2531
2532 entry = cfg->irq_2_pin;
2533 for (;;) {
2534
2535 if (!entry)
2536 break;
2537
2538 apic = entry->apic;
2539 pin = entry->pin;
2540 io_apic_eoi(apic, pin);
2541 entry = entry->next;
2542 }
2543}
2544
2545static void
2546eoi_ioapic_irq(struct irq_desc *desc)
2547{
2548 struct irq_cfg *cfg;
2549 unsigned long flags;
2550 unsigned int irq;
2551
2552 irq = desc->irq;
2553 cfg = desc->chip_data;
2554
2555 spin_lock_irqsave(&ioapic_lock, flags);
2556 __eoi_ioapic_irq(irq, cfg);
2557 spin_unlock_irqrestore(&ioapic_lock, flags);
2558}
2559
Weidong Han746cddd2009-04-10 17:17:17 +08002560#ifdef CONFIG_X86_X2APIC
Ingo Molnar54168ed2008-08-20 09:07:45 +02002561static void ack_x2apic_level(unsigned int irq)
2562{
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002563 struct irq_desc *desc = irq_to_desc(irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002564 ack_x2APIC_irq();
Suresh Siddha0280f7c2009-03-16 17:05:01 -07002565 eoi_ioapic_irq(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002566}
2567
2568static void ack_x2apic_edge(unsigned int irq)
2569{
2570 ack_x2APIC_irq();
2571}
2572#endif
Yinghai Lu497c9a12008-08-19 20:50:28 -07002573
Yinghai Lu1d025192008-08-19 20:50:34 -07002574static void ack_apic_edge(unsigned int irq)
2575{
Yinghai Lu3145e942008-12-05 18:58:34 -08002576 struct irq_desc *desc = irq_to_desc(irq);
2577
2578 irq_complete_move(&desc);
Yinghai Lu1d025192008-08-19 20:50:34 -07002579 move_native_irq(irq);
2580 ack_APIC_irq();
2581}
2582
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002583atomic_t irq_mis_count;
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002584
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002585static void ack_apic_level(unsigned int irq)
2586{
Yinghai Lu3145e942008-12-05 18:58:34 -08002587 struct irq_desc *desc = irq_to_desc(irq);
2588
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002589#ifdef CONFIG_X86_32
2590 unsigned long v;
2591 int i;
2592#endif
Yinghai Lu3145e942008-12-05 18:58:34 -08002593 struct irq_cfg *cfg;
Ingo Molnar54168ed2008-08-20 09:07:45 +02002594 int do_unmask_irq = 0;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002595
Yinghai Lu3145e942008-12-05 18:58:34 -08002596 irq_complete_move(&desc);
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002597#ifdef CONFIG_GENERIC_PENDING_IRQ
Ingo Molnar54168ed2008-08-20 09:07:45 +02002598 /* If we are moving the irq we need to mask it */
Yinghai Lu3145e942008-12-05 18:58:34 -08002599 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02002600 do_unmask_irq = 1;
Yinghai Lu3145e942008-12-05 18:58:34 -08002601 mask_IO_APIC_irq_desc(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002602 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002603#endif
2604
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002605#ifdef CONFIG_X86_32
2606 /*
2607 * It appears there is an erratum which affects at least version 0x11
2608 * of I/O APIC (that's the 82093AA and cores integrated into various
2609 * chipsets). Under certain conditions a level-triggered interrupt is
2610 * erroneously delivered as edge-triggered one but the respective IRR
2611 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2612 * message but it will never arrive and further interrupts are blocked
2613 * from the source. The exact reason is so far unknown, but the
2614 * phenomenon was observed when two consecutive interrupt requests
2615 * from a given source get delivered to the same CPU and the source is
2616 * temporarily disabled in between.
2617 *
2618 * A workaround is to simulate an EOI message manually. We achieve it
2619 * by setting the trigger mode to edge and then to level when the edge
2620 * trigger mode gets detected in the TMR of a local APIC for a
2621 * level-triggered interrupt. We mask the source for the time of the
2622 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2623 * The idea is from Manfred Spraul. --macro
2624 */
Yinghai Lu3145e942008-12-05 18:58:34 -08002625 cfg = desc->chip_data;
2626 i = cfg->vector;
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002627
2628 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2629#endif
2630
Ingo Molnar54168ed2008-08-20 09:07:45 +02002631 /*
2632 * We must acknowledge the irq before we move it or the acknowledge will
2633 * not propagate properly.
2634 */
2635 ack_APIC_irq();
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002636
Weidong Han746cddd2009-04-10 17:17:17 +08002637 if (irq_remapped(irq))
2638 eoi_ioapic_irq(desc);
2639
Ingo Molnar54168ed2008-08-20 09:07:45 +02002640 /* Now we can move and renable the irq */
2641 if (unlikely(do_unmask_irq)) {
2642 /* Only migrate the irq if the ack has been received.
2643 *
2644 * On rare occasions the broadcast level triggered ack gets
2645 * delayed going to ioapics, and if we reprogram the
2646 * vector while Remote IRR is still set the irq will never
2647 * fire again.
2648 *
2649 * To prevent this scenario we read the Remote IRR bit
2650 * of the ioapic. This has two effects.
2651 * - On any sane system the read of the ioapic will
2652 * flush writes (and acks) going to the ioapic from
2653 * this cpu.
2654 * - We get to see if the ACK has actually been delivered.
2655 *
2656 * Based on failed experiments of reprogramming the
2657 * ioapic entry from outside of irq context starting
2658 * with masking the ioapic entry and then polling until
2659 * Remote IRR was clear before reprogramming the
2660 * ioapic I don't trust the Remote IRR bit to be
2661 * completey accurate.
2662 *
2663 * However there appears to be no other way to plug
2664 * this race, so if the Remote IRR bit is not
2665 * accurate and is causing problems then it is a hardware bug
2666 * and you can go talk to the chipset vendor about it.
2667 */
Yinghai Lu3145e942008-12-05 18:58:34 -08002668 cfg = desc->chip_data;
2669 if (!io_apic_level_ack_pending(cfg))
Ingo Molnar54168ed2008-08-20 09:07:45 +02002670 move_masked_irq(irq);
Yinghai Lu3145e942008-12-05 18:58:34 -08002671 unmask_IO_APIC_irq_desc(desc);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002672 }
Yinghai Lu1d025192008-08-19 20:50:34 -07002673
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002674#ifdef CONFIG_X86_32
Yinghai Lu1d025192008-08-19 20:50:34 -07002675 if (!(v & (1 << (i & 0x1f)))) {
2676 atomic_inc(&irq_mis_count);
2677 spin_lock(&ioapic_lock);
Yinghai Lu3145e942008-12-05 18:58:34 -08002678 __mask_and_edge_IO_APIC_irq(cfg);
2679 __unmask_and_level_IO_APIC_irq(cfg);
Yinghai Lu1d025192008-08-19 20:50:34 -07002680 spin_unlock(&ioapic_lock);
2681 }
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002682#endif
Yinghai Lu3eb2cce2008-08-19 20:50:48 -07002683}
Yinghai Lu1d025192008-08-19 20:50:34 -07002684
Han, Weidongd0b03bd2009-04-03 17:15:50 +08002685#ifdef CONFIG_INTR_REMAP
2686static void ir_ack_apic_edge(unsigned int irq)
2687{
2688#ifdef CONFIG_X86_X2APIC
2689 if (x2apic_enabled())
2690 return ack_x2apic_edge(irq);
2691#endif
2692 return ack_apic_edge(irq);
2693}
2694
2695static void ir_ack_apic_level(unsigned int irq)
2696{
2697#ifdef CONFIG_X86_X2APIC
2698 if (x2apic_enabled())
2699 return ack_x2apic_level(irq);
2700#endif
2701 return ack_apic_level(irq);
2702}
2703#endif /* CONFIG_INTR_REMAP */
2704
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002705static struct irq_chip ioapic_chip __read_mostly = {
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002706 .name = "IO-APIC",
2707 .startup = startup_ioapic_irq,
2708 .mask = mask_IO_APIC_irq,
2709 .unmask = unmask_IO_APIC_irq,
2710 .ack = ack_apic_edge,
2711 .eoi = ack_apic_level,
Ashok Raj54d5d422005-09-06 15:16:15 -07002712#ifdef CONFIG_SMP
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002713 .set_affinity = set_ioapic_affinity_irq,
Ashok Raj54d5d422005-09-06 15:16:15 -07002714#endif
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07002715 .retrigger = ioapic_retrigger_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002716};
2717
Ingo Molnar54168ed2008-08-20 09:07:45 +02002718static struct irq_chip ir_ioapic_chip __read_mostly = {
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002719 .name = "IR-IO-APIC",
2720 .startup = startup_ioapic_irq,
2721 .mask = mask_IO_APIC_irq,
2722 .unmask = unmask_IO_APIC_irq,
Jaswinder Singh Rajputa1e38ca2009-03-23 02:11:25 +05302723#ifdef CONFIG_INTR_REMAP
Han, Weidongd0b03bd2009-04-03 17:15:50 +08002724 .ack = ir_ack_apic_edge,
2725 .eoi = ir_ack_apic_level,
Ingo Molnar54168ed2008-08-20 09:07:45 +02002726#ifdef CONFIG_SMP
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02002727 .set_affinity = set_ir_ioapic_affinity_irq,
Ingo Molnar54168ed2008-08-20 09:07:45 +02002728#endif
Jaswinder Singh Rajputa1e38ca2009-03-23 02:11:25 +05302729#endif
Ingo Molnar54168ed2008-08-20 09:07:45 +02002730 .retrigger = ioapic_retrigger_irq,
2731};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002732
2733static inline void init_IO_APIC_traps(void)
2734{
2735 int irq;
Yinghai Lu08678b02008-08-19 20:50:05 -07002736 struct irq_desc *desc;
Yinghai Luda51a822008-08-19 20:50:25 -07002737 struct irq_cfg *cfg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002738
2739 /*
2740 * NOTE! The local APIC isn't very good at handling
2741 * multiple interrupts at the same interrupt level.
2742 * As the interrupt level is determined by taking the
2743 * vector number and shifting that right by 4, we
2744 * want to spread these out a bit so that they don't
2745 * all fall in the same interrupt level.
2746 *
2747 * Also, we've got to be careful not to trash gate
2748 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2749 */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002750 for_each_irq_desc(irq, desc) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002751 cfg = desc->chip_data;
2752 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002753 /*
2754 * Hmm.. We don't have an entry for this,
2755 * so default to an old-fashioned 8259
2756 * interrupt if we can..
2757 */
Yinghai Lu99d093d2008-12-05 18:58:32 -08002758 if (irq < NR_IRQS_LEGACY)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002759 make_8259A_irq(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08002760 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07002761 /* Strange. Oh, well.. */
Yinghai Lu08678b02008-08-19 20:50:05 -07002762 desc->chip = &no_irq_chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002763 }
2764 }
2765}
2766
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002767/*
2768 * The local APIC irq-chip implementation:
2769 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002770
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002771static void mask_lapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002772{
2773 unsigned long v;
2774
2775 v = apic_read(APIC_LVT0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002776 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002777}
2778
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002779static void unmask_lapic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002780{
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002781 unsigned long v;
2782
2783 v = apic_read(APIC_LVT0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002784 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002785}
2786
Yinghai Lu3145e942008-12-05 18:58:34 -08002787static void ack_lapic_irq(unsigned int irq)
Yinghai Lu1d025192008-08-19 20:50:34 -07002788{
2789 ack_APIC_irq();
2790}
2791
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002792static struct irq_chip lapic_chip __read_mostly = {
Maciej W. Rozycki9a1c6192008-05-27 21:19:09 +01002793 .name = "local-APIC",
Ingo Molnarf5b9ed72006-10-04 02:16:26 -07002794 .mask = mask_lapic_irq,
2795 .unmask = unmask_lapic_irq,
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002796 .ack = ack_lapic_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002797};
2798
Yinghai Lu3145e942008-12-05 18:58:34 -08002799static void lapic_register_intr(int irq, struct irq_desc *desc)
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002800{
Yinghai Lu08678b02008-08-19 20:50:05 -07002801 desc->status &= ~IRQ_LEVEL;
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002802 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2803 "edge");
Maciej W. Rozyckic88ac1d2008-07-11 19:35:17 +01002804}
2805
Jan Beuliche9427102008-01-30 13:31:24 +01002806static void __init setup_nmi(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002807{
2808 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002809 * Dirty trick to enable the NMI watchdog ...
Linus Torvalds1da177e2005-04-16 15:20:36 -07002810 * We put the 8259A master into AEOI mode and
2811 * unmask on all local APICs LVT0 as NMI.
2812 *
2813 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2814 * is from Maciej W. Rozycki - so we do not have to EOI from
2815 * the NMI handler or the timer interrupt.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02002816 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002817 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2818
Jan Beuliche9427102008-01-30 13:31:24 +01002819 enable_NMI_through_LVT0();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002820
2821 apic_printk(APIC_VERBOSE, " done.\n");
2822}
2823
2824/*
2825 * This looks a bit hackish but it's about the only one way of sending
2826 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2827 * not support the ExtINT mode, unfortunately. We need to send these
2828 * cycles as some i82489DX-based boards have glue logic that keeps the
2829 * 8259A interrupt line asserted until INTA. --macro
2830 */
Jacek Luczak28acf282008-04-12 17:41:12 +02002831static inline void __init unlock_ExtINT_logic(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002832{
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002833 int apic, pin, i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002834 struct IO_APIC_route_entry entry0, entry1;
2835 unsigned char save_control, save_freq_select;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002836
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002837 pin = find_isa_irq_pin(8, mp_INT);
Adrian Bunk956fb532006-12-07 02:14:11 +01002838 if (pin == -1) {
2839 WARN_ON_ONCE(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002840 return;
Adrian Bunk956fb532006-12-07 02:14:11 +01002841 }
2842 apic = find_isa_irq_apic(8, mp_INT);
2843 if (apic == -1) {
2844 WARN_ON_ONCE(1);
2845 return;
2846 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002847
Andi Kleencf4c6a22006-09-26 10:52:30 +02002848 entry0 = ioapic_read_entry(apic, pin);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002849 clear_IO_APIC_pin(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002850
2851 memset(&entry1, 0, sizeof(entry1));
2852
2853 entry1.dest_mode = 0; /* physical delivery */
2854 entry1.mask = 0; /* unmask IRQ now */
Yinghai Lud83e94a2008-08-19 20:50:33 -07002855 entry1.dest = hard_smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002856 entry1.delivery_mode = dest_ExtINT;
2857 entry1.polarity = entry0.polarity;
2858 entry1.trigger = 0;
2859 entry1.vector = 0;
2860
Andi Kleencf4c6a22006-09-26 10:52:30 +02002861 ioapic_write_entry(apic, pin, entry1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002862
2863 save_control = CMOS_READ(RTC_CONTROL);
2864 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2865 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2866 RTC_FREQ_SELECT);
2867 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2868
2869 i = 100;
2870 while (i-- > 0) {
2871 mdelay(10);
2872 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2873 i -= 10;
2874 }
2875
2876 CMOS_WRITE(save_control, RTC_CONTROL);
2877 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002878 clear_IO_APIC_pin(apic, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002879
Andi Kleencf4c6a22006-09-26 10:52:30 +02002880 ioapic_write_entry(apic, pin, entry0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002881}
2882
Yinghai Luefa25592008-08-19 20:50:36 -07002883static int disable_timer_pin_1 __initdata;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002884/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
Ingo Molnar54168ed2008-08-20 09:07:45 +02002885static int __init disable_timer_pin_setup(char *arg)
Yinghai Luefa25592008-08-19 20:50:36 -07002886{
2887 disable_timer_pin_1 = 1;
2888 return 0;
2889}
Ingo Molnar54168ed2008-08-20 09:07:45 +02002890early_param("disable_timer_pin_1", disable_timer_pin_setup);
Yinghai Luefa25592008-08-19 20:50:36 -07002891
2892int timer_through_8259 __initdata;
2893
Linus Torvalds1da177e2005-04-16 15:20:36 -07002894/*
2895 * This code may look a bit paranoid, but it's supposed to cooperate with
2896 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2897 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2898 * fanatically on his truly buggy board.
Ingo Molnar54168ed2008-08-20 09:07:45 +02002899 *
2900 * FIXME: really need to revamp this for all platforms.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002901 */
Zachary Amsden8542b202006-12-07 02:14:09 +01002902static inline void __init check_timer(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002903{
Yinghai Lu3145e942008-12-05 18:58:34 -08002904 struct irq_desc *desc = irq_to_desc(0);
2905 struct irq_cfg *cfg = desc->chip_data;
2906 int cpu = boot_cpu_id;
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002907 int apic1, pin1, apic2, pin2;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002908 unsigned long flags;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07002909 int no_pin1 = 0;
Ingo Molnar4aae0702007-12-18 18:05:58 +01002910
2911 local_irq_save(flags);
Maciej W. Rozyckid4d25de2007-11-26 20:42:19 +01002912
Linus Torvalds1da177e2005-04-16 15:20:36 -07002913 /*
2914 * get/set the timer IRQ vector:
2915 */
2916 disable_8259A_irq(0);
Ingo Molnarfe402e12009-01-28 04:32:51 +01002917 assign_irq_vector(0, cfg, apic->target_cpus());
Linus Torvalds1da177e2005-04-16 15:20:36 -07002918
2919 /*
Maciej W. Rozyckid11d5792008-05-21 22:09:11 +01002920 * As IRQ0 is to be enabled in the 8259A, the virtual
2921 * wire has to be disabled in the local APIC. Also
2922 * timer interrupts need to be acknowledged manually in
2923 * the 8259A for the i82489DX when using the NMI
2924 * watchdog as that APIC treats NMIs as level-triggered.
2925 * The AEOI mode will finish them in the 8259A
2926 * automatically.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002927 */
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01002928 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002929 init_8259A(1);
Ingo Molnar54168ed2008-08-20 09:07:45 +02002930#ifdef CONFIG_X86_32
Yinghai Luf72dcca2009-02-08 16:18:03 -08002931 {
2932 unsigned int ver;
2933
2934 ver = apic_read(APIC_LVR);
2935 ver = GET_APIC_VERSION(ver);
2936 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2937 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002938#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002939
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002940 pin1 = find_isa_irq_pin(0, mp_INT);
2941 apic1 = find_isa_irq_apic(0, mp_INT);
2942 pin2 = ioapic_i8259.pin;
2943 apic2 = ioapic_i8259.apic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002944
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002945 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2946 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
Yinghai Lu497c9a12008-08-19 20:50:28 -07002947 cfg->vector, apic1, pin1, apic2, pin2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002948
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002949 /*
2950 * Some BIOS writers are clueless and report the ExtINTA
2951 * I/O APIC input from the cascaded 8259A as the timer
2952 * interrupt input. So just in case, if only one pin
2953 * was found above, try it both directly and through the
2954 * 8259A.
2955 */
2956 if (pin1 == -1) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02002957 if (intr_remapping_enabled)
2958 panic("BIOS bug: timer not connected to IO-APIC");
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002959 pin1 = pin2;
2960 apic1 = apic2;
2961 no_pin1 = 1;
2962 } else if (pin2 == -1) {
2963 pin2 = pin1;
2964 apic2 = apic1;
2965 }
2966
Linus Torvalds1da177e2005-04-16 15:20:36 -07002967 if (pin1 != -1) {
2968 /*
2969 * Ok, does IRQ0 through the IOAPIC work?
2970 */
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002971 if (no_pin1) {
Yinghai Lu3145e942008-12-05 18:58:34 -08002972 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
Yinghai Lu497c9a12008-08-19 20:50:28 -07002973 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
Yinghai Luf72dcca2009-02-08 16:18:03 -08002974 } else {
2975 /* for edge trigger, setup_IO_APIC_irq already
2976 * leave it unmasked.
2977 * so only need to unmask if it is level-trigger
2978 * do we really have level trigger timer?
2979 */
2980 int idx;
2981 idx = find_irq_entry(apic1, pin1, mp_INT);
2982 if (idx != -1 && irq_trigger(idx))
2983 unmask_IO_APIC_irq_desc(desc);
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002984 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002985 if (timer_irq_works()) {
2986 if (nmi_watchdog == NMI_IO_APIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002987 setup_nmi();
2988 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002989 }
Chuck Ebbert66759a02005-09-12 18:49:25 +02002990 if (disable_timer_pin_1 > 0)
2991 clear_IO_APIC_pin(0, pin1);
Ingo Molnar4aae0702007-12-18 18:05:58 +01002992 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002993 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02002994 if (intr_remapping_enabled)
2995 panic("timer doesn't work through Interrupt-remapped IO-APIC");
Yinghai Luf72dcca2009-02-08 16:18:03 -08002996 local_irq_disable();
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08002997 clear_IO_APIC_pin(apic1, pin1);
Maciej W. Rozycki691874f2008-05-27 21:19:51 +01002998 if (!no_pin1)
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01002999 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3000 "8254 timer not connected to IO-APIC\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003001
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003002 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3003 "(IRQ0) through the 8259A ...\n");
3004 apic_printk(APIC_QUIET, KERN_INFO
3005 "..... (found apic %d pin %d) ...\n", apic2, pin2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003006 /*
3007 * legacy devices should be connected to IO APIC #0
3008 */
Yinghai Lu3145e942008-12-05 18:58:34 -08003009 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003010 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
Maciej W. Rozyckiecd29472008-05-21 22:09:19 +01003011 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003012 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003013 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
Maciej W. Rozycki35542c52008-05-21 22:10:22 +01003014 timer_through_8259 = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003015 if (nmi_watchdog == NMI_IO_APIC) {
Maciej W. Rozycki60134eb2008-05-21 22:09:34 +01003016 disable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003017 setup_nmi();
Maciej W. Rozycki60134eb2008-05-21 22:09:34 +01003018 enable_8259A_irq(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003019 }
Ingo Molnar4aae0702007-12-18 18:05:58 +01003020 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003021 }
3022 /*
3023 * Cleanup, just in case ...
3024 */
Yinghai Luf72dcca2009-02-08 16:18:03 -08003025 local_irq_disable();
Maciej W. Rozyckiecd29472008-05-21 22:09:19 +01003026 disable_8259A_irq(0);
Eric W. Biedermanfcfd6362005-10-30 14:59:39 -08003027 clear_IO_APIC_pin(apic2, pin2);
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003028 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003029 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003030
3031 if (nmi_watchdog == NMI_IO_APIC) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003032 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3033 "through the IO-APIC - disabling NMI Watchdog!\n");
Cyrill Gorcunov067fa0f2008-05-29 22:32:30 +04003034 nmi_watchdog = NMI_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003035 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02003036#ifdef CONFIG_X86_32
Maciej W. Rozyckid11d5792008-05-21 22:09:11 +01003037 timer_ack = 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003038#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003039
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003040 apic_printk(APIC_QUIET, KERN_INFO
3041 "...trying to set up timer as Virtual Wire IRQ...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003042
Yinghai Lu3145e942008-12-05 18:58:34 -08003043 lapic_register_intr(0, desc);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003044 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003045 enable_8259A_irq(0);
3046
3047 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003048 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01003049 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003050 }
Yinghai Luf72dcca2009-02-08 16:18:03 -08003051 local_irq_disable();
Maciej W. Rozyckie67465f2008-05-21 22:09:26 +01003052 disable_8259A_irq(0);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003053 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003054 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003055
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003056 apic_printk(APIC_QUIET, KERN_INFO
3057 "...trying to set up timer as ExtINT IRQ...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003058
Linus Torvalds1da177e2005-04-16 15:20:36 -07003059 init_8259A(0);
3060 make_8259A_irq(0);
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01003061 apic_write(APIC_LVT0, APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003062
3063 unlock_ExtINT_logic();
3064
3065 if (timer_irq_works()) {
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003066 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01003067 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003068 }
Yinghai Luf72dcca2009-02-08 16:18:03 -08003069 local_irq_disable();
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003070 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003071 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
Maciej W. Rozycki49a66a02008-07-14 19:08:13 +01003072 "report. Then try booting with the 'noapic' option.\n");
Ingo Molnar4aae0702007-12-18 18:05:58 +01003073out:
3074 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003075}
3076
3077/*
Maciej W. Rozyckiaf174782008-07-11 19:35:23 +01003078 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3079 * to devices. However there may be an I/O APIC pin available for
3080 * this interrupt regardless. The pin may be left unconnected, but
3081 * typically it will be reused as an ExtINT cascade interrupt for
3082 * the master 8259A. In the MPS case such a pin will normally be
3083 * reported as an ExtINT interrupt in the MP table. With ACPI
3084 * there is no provision for ExtINT interrupts, and in the absence
3085 * of an override it would be treated as an ordinary ISA I/O APIC
3086 * interrupt, that is edge-triggered and unmasked by default. We
3087 * used to do this, but it caused problems on some systems because
3088 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3089 * the same ExtINT cascade interrupt to drive the local APIC of the
3090 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3091 * the I/O APIC in all cases now. No actual device should request
3092 * it anyway. --macro
Linus Torvalds1da177e2005-04-16 15:20:36 -07003093 */
3094#define PIC_IRQS (1 << PIC_CASCADE_IR)
3095
3096void __init setup_IO_APIC(void)
3097{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003098
Ingo Molnar54168ed2008-08-20 09:07:45 +02003099 /*
3100 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3101 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003102
Maciej W. Rozyckiaf174782008-07-11 19:35:23 +01003103 io_apic_irqs = ~PIC_IRQS;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003104
Ingo Molnar54168ed2008-08-20 09:07:45 +02003105 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003106 /*
Ingo Molnar54168ed2008-08-20 09:07:45 +02003107 * Set up IO-APIC IRQ routing.
3108 */
3109#ifdef CONFIG_X86_32
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003110 if (!acpi_ioapic)
3111 setup_ioapic_ids_from_mpc();
Ingo Molnar54168ed2008-08-20 09:07:45 +02003112#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003113 sync_Arb_IDs();
3114 setup_IO_APIC_irqs();
3115 init_IO_APIC_traps();
Linus Torvalds1e4c85f2005-10-31 19:16:17 -08003116 check_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -07003117}
3118
3119/*
Ingo Molnar54168ed2008-08-20 09:07:45 +02003120 * Called after all the initialization is done. If we didnt find any
3121 * APIC bugs then we can allow the modify fast path
Linus Torvalds1da177e2005-04-16 15:20:36 -07003122 */
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003123
Linus Torvalds1da177e2005-04-16 15:20:36 -07003124static int __init io_apic_bug_finalize(void)
3125{
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003126 if (sis_apic_bug == -1)
3127 sis_apic_bug = 0;
3128 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003129}
3130
3131late_initcall(io_apic_bug_finalize);
3132
3133struct sysfs_ioapic_data {
3134 struct sys_device dev;
3135 struct IO_APIC_route_entry entry[0];
3136};
Ingo Molnar54168ed2008-08-20 09:07:45 +02003137static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
Linus Torvalds1da177e2005-04-16 15:20:36 -07003138
Pavel Machek438510f2005-04-16 15:25:24 -07003139static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003140{
3141 struct IO_APIC_route_entry *entry;
3142 struct sysfs_ioapic_data *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003143 int i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003144
Linus Torvalds1da177e2005-04-16 15:20:36 -07003145 data = container_of(dev, struct sysfs_ioapic_data, dev);
3146 entry = data->entry;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003147 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3148 *entry = ioapic_read_entry(dev->id, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003149
3150 return 0;
3151}
3152
3153static int ioapic_resume(struct sys_device *dev)
3154{
3155 struct IO_APIC_route_entry *entry;
3156 struct sysfs_ioapic_data *data;
3157 unsigned long flags;
3158 union IO_APIC_reg_00 reg_00;
3159 int i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003160
Linus Torvalds1da177e2005-04-16 15:20:36 -07003161 data = container_of(dev, struct sysfs_ioapic_data, dev);
3162 entry = data->entry;
3163
3164 spin_lock_irqsave(&ioapic_lock, flags);
3165 reg_00.raw = io_apic_read(dev->id, 0);
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +05303166 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3167 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003168 io_apic_write(dev->id, 0, reg_00.raw);
3169 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003170 spin_unlock_irqrestore(&ioapic_lock, flags);
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003171 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
Andi Kleencf4c6a22006-09-26 10:52:30 +02003172 ioapic_write_entry(dev->id, i, entry[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003173
3174 return 0;
3175}
3176
3177static struct sysdev_class ioapic_sysdev_class = {
Kay Sieversaf5ca3f2007-12-20 02:09:39 +01003178 .name = "ioapic",
Linus Torvalds1da177e2005-04-16 15:20:36 -07003179 .suspend = ioapic_suspend,
3180 .resume = ioapic_resume,
3181};
3182
3183static int __init ioapic_init_sysfs(void)
3184{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003185 struct sys_device * dev;
3186 int i, size, error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003187
3188 error = sysdev_class_register(&ioapic_sysdev_class);
3189 if (error)
3190 return error;
3191
Ingo Molnar54168ed2008-08-20 09:07:45 +02003192 for (i = 0; i < nr_ioapics; i++ ) {
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003193 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
Linus Torvalds1da177e2005-04-16 15:20:36 -07003194 * sizeof(struct IO_APIC_route_entry);
Christophe Jaillet25556c12008-06-22 22:13:48 +02003195 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003196 if (!mp_ioapic_data[i]) {
3197 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3198 continue;
3199 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003200 dev = &mp_ioapic_data[i]->dev;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003201 dev->id = i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003202 dev->cls = &ioapic_sysdev_class;
3203 error = sysdev_register(dev);
3204 if (error) {
3205 kfree(mp_ioapic_data[i]);
3206 mp_ioapic_data[i] = NULL;
3207 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3208 continue;
3209 }
3210 }
3211
3212 return 0;
3213}
3214
3215device_initcall(ioapic_init_sysfs);
3216
Yinghai Luabcaa2b2009-02-08 16:18:03 -08003217static int nr_irqs_gsi = NR_IRQS_LEGACY;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003218/*
Eric W. Biederman95d77882006-10-04 02:17:01 -07003219 * Dynamic irq allocate and deallocation
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003220 */
Yinghai Lu199751d2008-08-19 20:50:27 -07003221unsigned int create_irq_nr(unsigned int irq_want)
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003222{
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003223 /* Allocate an unused irq */
Ingo Molnar54168ed2008-08-20 09:07:45 +02003224 unsigned int irq;
3225 unsigned int new;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003226 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003227 struct irq_cfg *cfg_new = NULL;
3228 int cpu = boot_cpu_id;
3229 struct irq_desc *desc_new = NULL;
Yinghai Lu199751d2008-08-19 20:50:27 -07003230
3231 irq = 0;
Yinghai Luabcaa2b2009-02-08 16:18:03 -08003232 if (irq_want < nr_irqs_gsi)
3233 irq_want = nr_irqs_gsi;
3234
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003235 spin_lock_irqsave(&vector_lock, flags);
Mike Travis95949492009-01-10 22:24:06 -08003236 for (new = irq_want; new < nr_irqs; new++) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003237 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3238 if (!desc_new) {
3239 printk(KERN_INFO "can not get irq_desc for %d\n", new);
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003240 continue;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003241 }
3242 cfg_new = desc_new->chip_data;
3243
3244 if (cfg_new->vector != 0)
3245 continue;
Ingo Molnarfe402e12009-01-28 04:32:51 +01003246 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
Eric W. Biedermanace80ab2006-10-04 02:16:47 -07003247 irq = new;
3248 break;
3249 }
3250 spin_unlock_irqrestore(&vector_lock, flags);
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003251
Yinghai Lu199751d2008-08-19 20:50:27 -07003252 if (irq > 0) {
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003253 dynamic_irq_init(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003254 /* restore it, in case dynamic_irq_init clear it */
3255 if (desc_new)
3256 desc_new->chip_data = cfg_new;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003257 }
3258 return irq;
3259}
3260
Yinghai Lu199751d2008-08-19 20:50:27 -07003261int create_irq(void)
3262{
Yinghai Lube5d5352008-12-05 18:58:33 -08003263 unsigned int irq_want;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003264 int irq;
3265
Yinghai Lube5d5352008-12-05 18:58:33 -08003266 irq_want = nr_irqs_gsi;
3267 irq = create_irq_nr(irq_want);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003268
3269 if (irq == 0)
3270 irq = -1;
3271
3272 return irq;
Yinghai Lu199751d2008-08-19 20:50:27 -07003273}
3274
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003275void destroy_irq(unsigned int irq)
3276{
3277 unsigned long flags;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003278 struct irq_cfg *cfg;
3279 struct irq_desc *desc;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003280
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003281 /* store it, in case dynamic_irq_cleanup clear it */
3282 desc = irq_to_desc(irq);
3283 cfg = desc->chip_data;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003284 dynamic_irq_cleanup(irq);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003285 /* connect back irq_cfg */
3286 if (desc)
3287 desc->chip_data = cfg;
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003288
Ingo Molnar54168ed2008-08-20 09:07:45 +02003289 free_irte(irq);
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003290 spin_lock_irqsave(&vector_lock, flags);
Yinghai Lu3145e942008-12-05 18:58:34 -08003291 __clear_irq_vector(irq, cfg);
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003292 spin_unlock_irqrestore(&vector_lock, flags);
3293}
Eric W. Biederman3fc471e2006-10-04 02:16:39 -07003294
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003295/*
Simon Arlott27b46d72007-10-20 01:13:56 +02003296 * MSI message composition
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003297 */
3298#ifdef CONFIG_PCI_MSI
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003299static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003300{
Yinghai Lu497c9a12008-08-19 20:50:28 -07003301 struct irq_cfg *cfg;
3302 int err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003303 unsigned dest;
3304
Jan Beulichf1182632009-01-14 12:27:35 +00003305 if (disable_apic)
3306 return -ENXIO;
3307
Yinghai Lu3145e942008-12-05 18:58:34 -08003308 cfg = irq_cfg(irq);
Ingo Molnarfe402e12009-01-28 04:32:51 +01003309 err = assign_irq_vector(irq, cfg, apic->target_cpus());
Yinghai Lu497c9a12008-08-19 20:50:28 -07003310 if (err)
3311 return err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003312
Ingo Molnardebccb32009-01-28 15:20:18 +01003313 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003314
Ingo Molnar54168ed2008-08-20 09:07:45 +02003315 if (irq_remapped(irq)) {
3316 struct irte irte;
3317 int ir_index;
3318 u16 sub_handle;
Yinghai Lu497c9a12008-08-19 20:50:28 -07003319
Ingo Molnar54168ed2008-08-20 09:07:45 +02003320 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3321 BUG_ON(ir_index == -1);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003322
Ingo Molnar54168ed2008-08-20 09:07:45 +02003323 memset (&irte, 0, sizeof(irte));
3324
3325 irte.present = 1;
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003326 irte.dst_mode = apic->irq_dest_mode;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003327 irte.trigger_mode = 0; /* edge */
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003328 irte.dlvry_mode = apic->irq_delivery_mode;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003329 irte.vector = cfg->vector;
3330 irte.dest_id = IRTE_DEST(dest);
3331
3332 modify_irte(irq, &irte);
3333
3334 msg->address_hi = MSI_ADDR_BASE_HI;
3335 msg->data = sub_handle;
3336 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3337 MSI_ADDR_IR_SHV |
3338 MSI_ADDR_IR_INDEX1(ir_index) |
3339 MSI_ADDR_IR_INDEX2(ir_index);
Suresh Siddha29b61be2009-03-16 17:05:02 -07003340 } else {
Suresh Siddha9d783ba2009-03-16 17:04:55 -07003341 if (x2apic_enabled())
3342 msg->address_hi = MSI_ADDR_BASE_HI |
3343 MSI_ADDR_EXT_DEST_ID(dest);
3344 else
3345 msg->address_hi = MSI_ADDR_BASE_HI;
3346
Ingo Molnar54168ed2008-08-20 09:07:45 +02003347 msg->address_lo =
3348 MSI_ADDR_BASE_LO |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003349 ((apic->irq_dest_mode == 0) ?
Ingo Molnar54168ed2008-08-20 09:07:45 +02003350 MSI_ADDR_DEST_MODE_PHYSICAL:
3351 MSI_ADDR_DEST_MODE_LOGICAL) |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003352 ((apic->irq_delivery_mode != dest_LowestPrio) ?
Ingo Molnar54168ed2008-08-20 09:07:45 +02003353 MSI_ADDR_REDIRECTION_CPU:
3354 MSI_ADDR_REDIRECTION_LOWPRI) |
3355 MSI_ADDR_DEST_ID(dest);
3356
3357 msg->data =
3358 MSI_DATA_TRIGGER_EDGE |
3359 MSI_DATA_LEVEL_ASSERT |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003360 ((apic->irq_delivery_mode != dest_LowestPrio) ?
Ingo Molnar54168ed2008-08-20 09:07:45 +02003361 MSI_DATA_DELIVERY_FIXED:
3362 MSI_DATA_DELIVERY_LOWPRI) |
3363 MSI_DATA_VECTOR(cfg->vector);
3364 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07003365 return err;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003366}
3367
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003368#ifdef CONFIG_SMP
Rusty Russell0de26522008-12-13 21:20:26 +10303369static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003370{
Yinghai Lu3145e942008-12-05 18:58:34 -08003371 struct irq_desc *desc = irq_to_desc(irq);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003372 struct irq_cfg *cfg;
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003373 struct msi_msg msg;
3374 unsigned int dest;
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003375
Mike Travis22f65d32008-12-16 17:33:56 -08003376 dest = set_desc_affinity(desc, mask);
3377 if (dest == BAD_APICID)
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003378 return;
3379
Yinghai Lu3145e942008-12-05 18:58:34 -08003380 cfg = desc->chip_data;
Yinghai Lu497c9a12008-08-19 20:50:28 -07003381
Yinghai Lu3145e942008-12-05 18:58:34 -08003382 read_msi_msg_desc(desc, &msg);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003383
3384 msg.data &= ~MSI_DATA_VECTOR_MASK;
Yinghai Lu497c9a12008-08-19 20:50:28 -07003385 msg.data |= MSI_DATA_VECTOR(cfg->vector);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003386 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3387 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3388
Yinghai Lu3145e942008-12-05 18:58:34 -08003389 write_msi_msg_desc(desc, &msg);
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003390}
Ingo Molnar54168ed2008-08-20 09:07:45 +02003391#ifdef CONFIG_INTR_REMAP
3392/*
3393 * Migrate the MSI irq to another cpumask. This migration is
3394 * done in the process context using interrupt-remapping hardware.
3395 */
Mike Travise7986732008-12-16 17:33:52 -08003396static void
3397ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003398{
Yinghai Lu3145e942008-12-05 18:58:34 -08003399 struct irq_desc *desc = irq_to_desc(irq);
Ingo Molnara7883de2008-12-19 00:59:09 +01003400 struct irq_cfg *cfg = desc->chip_data;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003401 unsigned int dest;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003402 struct irte irte;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003403
3404 if (get_irte(irq, &irte))
3405 return;
3406
Mike Travis22f65d32008-12-16 17:33:56 -08003407 dest = set_desc_affinity(desc, mask);
3408 if (dest == BAD_APICID)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003409 return;
3410
Ingo Molnar54168ed2008-08-20 09:07:45 +02003411 irte.vector = cfg->vector;
3412 irte.dest_id = IRTE_DEST(dest);
3413
3414 /*
3415 * atomically update the IRTE with the new destination and vector.
3416 */
3417 modify_irte(irq, &irte);
3418
3419 /*
3420 * After this point, all the interrupts will start arriving
3421 * at the new destination. So, time to cleanup the previous
3422 * vector allocation.
3423 */
Mike Travis22f65d32008-12-16 17:33:56 -08003424 if (cfg->move_in_progress)
3425 send_cleanup_vector(cfg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003426}
Yinghai Lu3145e942008-12-05 18:58:34 -08003427
Ingo Molnar54168ed2008-08-20 09:07:45 +02003428#endif
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003429#endif /* CONFIG_SMP */
3430
3431/*
3432 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3433 * which implement the MSI or MSI-X Capability Structure.
3434 */
3435static struct irq_chip msi_chip = {
3436 .name = "PCI-MSI",
3437 .unmask = unmask_msi_irq,
3438 .mask = mask_msi_irq,
Yinghai Lu1d025192008-08-19 20:50:34 -07003439 .ack = ack_apic_edge,
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003440#ifdef CONFIG_SMP
3441 .set_affinity = set_msi_irq_affinity,
3442#endif
3443 .retrigger = ioapic_retrigger_irq,
3444};
3445
Ingo Molnar54168ed2008-08-20 09:07:45 +02003446static struct irq_chip msi_ir_chip = {
3447 .name = "IR-PCI-MSI",
3448 .unmask = unmask_msi_irq,
3449 .mask = mask_msi_irq,
Jaswinder Singh Rajputa1e38ca2009-03-23 02:11:25 +05303450#ifdef CONFIG_INTR_REMAP
Han, Weidongd0b03bd2009-04-03 17:15:50 +08003451 .ack = ir_ack_apic_edge,
Ingo Molnar54168ed2008-08-20 09:07:45 +02003452#ifdef CONFIG_SMP
3453 .set_affinity = ir_set_msi_irq_affinity,
3454#endif
Jaswinder Singh Rajputa1e38ca2009-03-23 02:11:25 +05303455#endif
Ingo Molnar54168ed2008-08-20 09:07:45 +02003456 .retrigger = ioapic_retrigger_irq,
3457};
3458
3459/*
3460 * Map the PCI dev to the corresponding remapping hardware unit
3461 * and allocate 'nvec' consecutive interrupt-remapping table entries
3462 * in it.
3463 */
3464static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3465{
3466 struct intel_iommu *iommu;
3467 int index;
3468
3469 iommu = map_dev_to_ir(dev);
3470 if (!iommu) {
3471 printk(KERN_ERR
3472 "Unable to map PCI %s to iommu\n", pci_name(dev));
3473 return -ENOENT;
3474 }
3475
3476 index = alloc_irte(iommu, irq, nvec);
3477 if (index < 0) {
3478 printk(KERN_ERR
3479 "Unable to allocate %d IRTE for PCI %s\n", nvec,
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02003480 pci_name(dev));
Ingo Molnar54168ed2008-08-20 09:07:45 +02003481 return -ENOSPC;
3482 }
3483 return index;
3484}
Yinghai Lu1d025192008-08-19 20:50:34 -07003485
Yinghai Lu3145e942008-12-05 18:58:34 -08003486static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
Yinghai Lu1d025192008-08-19 20:50:34 -07003487{
3488 int ret;
3489 struct msi_msg msg;
3490
3491 ret = msi_compose_msg(dev, irq, &msg);
3492 if (ret < 0)
3493 return ret;
3494
Yinghai Lu3145e942008-12-05 18:58:34 -08003495 set_irq_msi(irq, msidesc);
Yinghai Lu1d025192008-08-19 20:50:34 -07003496 write_msi_msg(irq, &msg);
3497
Ingo Molnar54168ed2008-08-20 09:07:45 +02003498 if (irq_remapped(irq)) {
3499 struct irq_desc *desc = irq_to_desc(irq);
3500 /*
3501 * irq migration in process context
3502 */
3503 desc->status |= IRQ_MOVE_PCNTXT;
3504 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3505 } else
Ingo Molnar54168ed2008-08-20 09:07:45 +02003506 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
Yinghai Lu1d025192008-08-19 20:50:34 -07003507
Yinghai Luc81bba42008-09-25 11:53:11 -07003508 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3509
Yinghai Lu1d025192008-08-19 20:50:34 -07003510 return 0;
3511}
3512
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003513int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3514{
Ingo Molnar54168ed2008-08-20 09:07:45 +02003515 unsigned int irq;
3516 int ret, sub_handle;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003517 struct msi_desc *msidesc;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003518 unsigned int irq_want;
Dmitri Vorobiev1cc18522009-03-22 19:11:09 +02003519 struct intel_iommu *iommu = NULL;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003520 int index = 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003521
Matthew Wilcox1c8d7b02009-03-17 08:54:10 -04003522 /* x86 doesn't support multiple MSI yet */
3523 if (type == PCI_CAP_ID_MSI && nvec > 1)
3524 return 1;
3525
Yinghai Lube5d5352008-12-05 18:58:33 -08003526 irq_want = nr_irqs_gsi;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003527 sub_handle = 0;
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003528 list_for_each_entry(msidesc, &dev->msi_list, list) {
3529 irq = create_irq_nr(irq_want);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003530 if (irq == 0)
3531 return -1;
Yinghai Luf1ee5542009-02-08 16:18:03 -08003532 irq_want = irq + 1;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003533 if (!intr_remapping_enabled)
3534 goto no_ir;
3535
3536 if (!sub_handle) {
3537 /*
3538 * allocate the consecutive block of IRTE's
3539 * for 'nvec'
3540 */
3541 index = msi_alloc_irte(dev, irq, nvec);
3542 if (index < 0) {
3543 ret = index;
3544 goto error;
3545 }
3546 } else {
3547 iommu = map_dev_to_ir(dev);
3548 if (!iommu) {
3549 ret = -ENOENT;
3550 goto error;
3551 }
3552 /*
3553 * setup the mapping between the irq and the IRTE
3554 * base index, the sub_handle pointing to the
3555 * appropriate interrupt remap table entry.
3556 */
3557 set_irte_irq(irq, iommu, index, sub_handle);
3558 }
3559no_ir:
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003560 ret = setup_msi_irq(dev, msidesc, irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003561 if (ret < 0)
3562 goto error;
3563 sub_handle++;
3564 }
3565 return 0;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003566
3567error:
Ingo Molnar54168ed2008-08-20 09:07:45 +02003568 destroy_irq(irq);
3569 return ret;
Yinghai Lu047c8fd2008-08-19 20:50:41 -07003570}
3571
Eric W. Biederman3b7d1922006-10-04 02:16:59 -07003572void arch_teardown_msi_irq(unsigned int irq)
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003573{
Eric W. Biedermanf7feaca2007-01-28 12:56:37 -07003574 destroy_irq(irq);
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003575}
3576
Suresh Siddha9d783ba2009-03-16 17:04:55 -07003577#if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003578#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -08003579static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003580{
Yinghai Lu3145e942008-12-05 18:58:34 -08003581 struct irq_desc *desc = irq_to_desc(irq);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003582 struct irq_cfg *cfg;
3583 struct msi_msg msg;
3584 unsigned int dest;
Eric W. Biederman2d3fcc12006-10-04 02:16:43 -07003585
Mike Travis22f65d32008-12-16 17:33:56 -08003586 dest = set_desc_affinity(desc, mask);
3587 if (dest == BAD_APICID)
Ingo Molnar54168ed2008-08-20 09:07:45 +02003588 return;
3589
Yinghai Lu3145e942008-12-05 18:58:34 -08003590 cfg = desc->chip_data;
Ingo Molnar54168ed2008-08-20 09:07:45 +02003591
3592 dmar_msi_read(irq, &msg);
3593
3594 msg.data &= ~MSI_DATA_VECTOR_MASK;
3595 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3596 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3597 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3598
3599 dmar_msi_write(irq, &msg);
Ingo Molnar54168ed2008-08-20 09:07:45 +02003600}
Yinghai Lu3145e942008-12-05 18:58:34 -08003601
Ingo Molnar54168ed2008-08-20 09:07:45 +02003602#endif /* CONFIG_SMP */
3603
3604struct irq_chip dmar_msi_type = {
3605 .name = "DMAR_MSI",
3606 .unmask = dmar_msi_unmask,
3607 .mask = dmar_msi_mask,
3608 .ack = ack_apic_edge,
3609#ifdef CONFIG_SMP
3610 .set_affinity = dmar_msi_set_affinity,
3611#endif
3612 .retrigger = ioapic_retrigger_irq,
3613};
3614
3615int arch_setup_dmar_msi(unsigned int irq)
3616{
3617 int ret;
3618 struct msi_msg msg;
3619
3620 ret = msi_compose_msg(NULL, irq, &msg);
3621 if (ret < 0)
3622 return ret;
3623 dmar_msi_write(irq, &msg);
3624 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3625 "edge");
3626 return 0;
3627}
3628#endif
3629
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003630#ifdef CONFIG_HPET_TIMER
3631
3632#ifdef CONFIG_SMP
Mike Travis22f65d32008-12-16 17:33:56 -08003633static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003634{
Yinghai Lu3145e942008-12-05 18:58:34 -08003635 struct irq_desc *desc = irq_to_desc(irq);
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003636 struct irq_cfg *cfg;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003637 struct msi_msg msg;
3638 unsigned int dest;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003639
Mike Travis22f65d32008-12-16 17:33:56 -08003640 dest = set_desc_affinity(desc, mask);
3641 if (dest == BAD_APICID)
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003642 return;
3643
Yinghai Lu3145e942008-12-05 18:58:34 -08003644 cfg = desc->chip_data;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003645
3646 hpet_msi_read(irq, &msg);
3647
3648 msg.data &= ~MSI_DATA_VECTOR_MASK;
3649 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3650 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3651 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3652
3653 hpet_msi_write(irq, &msg);
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003654}
Yinghai Lu3145e942008-12-05 18:58:34 -08003655
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003656#endif /* CONFIG_SMP */
3657
Dmitri Vorobiev1cc18522009-03-22 19:11:09 +02003658static struct irq_chip hpet_msi_type = {
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003659 .name = "HPET_MSI",
3660 .unmask = hpet_msi_unmask,
3661 .mask = hpet_msi_mask,
3662 .ack = ack_apic_edge,
3663#ifdef CONFIG_SMP
3664 .set_affinity = hpet_msi_set_affinity,
3665#endif
3666 .retrigger = ioapic_retrigger_irq,
3667};
3668
3669int arch_setup_hpet_msi(unsigned int irq)
3670{
3671 int ret;
3672 struct msi_msg msg;
Pallipadi, Venkatesh6ec3cfe2009-04-13 15:20:58 -07003673 struct irq_desc *desc = irq_to_desc(irq);
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003674
3675 ret = msi_compose_msg(NULL, irq, &msg);
3676 if (ret < 0)
3677 return ret;
3678
3679 hpet_msi_write(irq, &msg);
Pallipadi, Venkatesh6ec3cfe2009-04-13 15:20:58 -07003680 desc->status |= IRQ_MOVE_PCNTXT;
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003681 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3682 "edge");
Yinghai Luc81bba42008-09-25 11:53:11 -07003683
venkatesh.pallipadi@intel.com58ac1e72008-09-05 18:02:17 -07003684 return 0;
3685}
3686#endif
3687
Ingo Molnar54168ed2008-08-20 09:07:45 +02003688#endif /* CONFIG_PCI_MSI */
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003689/*
3690 * Hypertransport interrupt support
3691 */
3692#ifdef CONFIG_HT_IRQ
3693
3694#ifdef CONFIG_SMP
3695
Yinghai Lu497c9a12008-08-19 20:50:28 -07003696static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003697{
Eric W. Biedermanec683072006-11-08 17:44:57 -08003698 struct ht_irq_msg msg;
3699 fetch_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003700
Yinghai Lu497c9a12008-08-19 20:50:28 -07003701 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
Eric W. Biedermanec683072006-11-08 17:44:57 -08003702 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003703
Yinghai Lu497c9a12008-08-19 20:50:28 -07003704 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
Eric W. Biedermanec683072006-11-08 17:44:57 -08003705 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003706
Eric W. Biedermanec683072006-11-08 17:44:57 -08003707 write_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003708}
3709
Mike Travis22f65d32008-12-16 17:33:56 -08003710static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003711{
Yinghai Lu3145e942008-12-05 18:58:34 -08003712 struct irq_desc *desc = irq_to_desc(irq);
Yinghai Lu497c9a12008-08-19 20:50:28 -07003713 struct irq_cfg *cfg;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003714 unsigned int dest;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003715
Mike Travis22f65d32008-12-16 17:33:56 -08003716 dest = set_desc_affinity(desc, mask);
3717 if (dest == BAD_APICID)
Yinghai Lu497c9a12008-08-19 20:50:28 -07003718 return;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003719
Yinghai Lu3145e942008-12-05 18:58:34 -08003720 cfg = desc->chip_data;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003721
Yinghai Lu497c9a12008-08-19 20:50:28 -07003722 target_ht_irq(irq, dest, cfg->vector);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003723}
Yinghai Lu3145e942008-12-05 18:58:34 -08003724
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003725#endif
3726
Aneesh Kumar K.Vc37e1082006-10-11 01:20:43 -07003727static struct irq_chip ht_irq_chip = {
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003728 .name = "PCI-HT",
3729 .mask = mask_ht_irq,
3730 .unmask = unmask_ht_irq,
Yinghai Lu1d025192008-08-19 20:50:34 -07003731 .ack = ack_apic_edge,
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003732#ifdef CONFIG_SMP
3733 .set_affinity = set_ht_irq_affinity,
3734#endif
3735 .retrigger = ioapic_retrigger_irq,
3736};
3737
3738int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3739{
Yinghai Lu497c9a12008-08-19 20:50:28 -07003740 struct irq_cfg *cfg;
3741 int err;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003742
Jan Beulichf1182632009-01-14 12:27:35 +00003743 if (disable_apic)
3744 return -ENXIO;
3745
Yinghai Lu3145e942008-12-05 18:58:34 -08003746 cfg = irq_cfg(irq);
Ingo Molnarfe402e12009-01-28 04:32:51 +01003747 err = assign_irq_vector(irq, cfg, apic->target_cpus());
Ingo Molnar54168ed2008-08-20 09:07:45 +02003748 if (!err) {
Eric W. Biedermanec683072006-11-08 17:44:57 -08003749 struct ht_irq_msg msg;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003750 unsigned dest;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003751
Ingo Molnardebccb32009-01-28 15:20:18 +01003752 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3753 apic->target_cpus());
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003754
Eric W. Biedermanec683072006-11-08 17:44:57 -08003755 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003756
Eric W. Biedermanec683072006-11-08 17:44:57 -08003757 msg.address_lo =
3758 HT_IRQ_LOW_BASE |
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003759 HT_IRQ_LOW_DEST_ID(dest) |
Yinghai Lu497c9a12008-08-19 20:50:28 -07003760 HT_IRQ_LOW_VECTOR(cfg->vector) |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003761 ((apic->irq_dest_mode == 0) ?
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003762 HT_IRQ_LOW_DM_PHYSICAL :
3763 HT_IRQ_LOW_DM_LOGICAL) |
3764 HT_IRQ_LOW_RQEOI_EDGE |
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003765 ((apic->irq_delivery_mode != dest_LowestPrio) ?
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003766 HT_IRQ_LOW_MT_FIXED :
3767 HT_IRQ_LOW_MT_ARBITRATED) |
3768 HT_IRQ_LOW_IRQ_MASKED;
3769
Eric W. Biedermanec683072006-11-08 17:44:57 -08003770 write_ht_irq_msg(irq, &msg);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003771
Ingo Molnara460e742006-10-17 00:10:03 -07003772 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3773 handle_edge_irq, "edge");
Yinghai Luc81bba42008-09-25 11:53:11 -07003774
3775 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003776 }
Yinghai Lu497c9a12008-08-19 20:50:28 -07003777 return err;
Eric W. Biederman8b955b02006-10-04 02:16:55 -07003778}
3779#endif /* CONFIG_HT_IRQ */
3780
Nick Piggin03b48632009-01-20 04:36:04 +01003781#ifdef CONFIG_X86_UV
Dean Nelson4173a0e2008-10-02 12:18:21 -05003782/*
3783 * Re-target the irq to the specified CPU and enable the specified MMR located
3784 * on the specified blade to allow the sending of MSIs to the specified CPU.
3785 */
3786int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3787 unsigned long mmr_offset)
3788{
Mike Travis22f65d32008-12-16 17:33:56 -08003789 const struct cpumask *eligible_cpu = cpumask_of(cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003790 struct irq_cfg *cfg;
3791 int mmr_pnode;
3792 unsigned long mmr_value;
3793 struct uv_IO_APIC_route_entry *entry;
3794 unsigned long flags;
3795 int err;
3796
Yinghai Lu3145e942008-12-05 18:58:34 -08003797 cfg = irq_cfg(irq);
3798
Mike Travise7986732008-12-16 17:33:52 -08003799 err = assign_irq_vector(irq, cfg, eligible_cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003800 if (err != 0)
3801 return err;
3802
3803 spin_lock_irqsave(&vector_lock, flags);
3804 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3805 irq_name);
3806 spin_unlock_irqrestore(&vector_lock, flags);
3807
Dean Nelson4173a0e2008-10-02 12:18:21 -05003808 mmr_value = 0;
3809 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3810 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3811
3812 entry->vector = cfg->vector;
Ingo Molnar9b5bc8d2009-01-28 04:09:58 +01003813 entry->delivery_mode = apic->irq_delivery_mode;
3814 entry->dest_mode = apic->irq_dest_mode;
Dean Nelson4173a0e2008-10-02 12:18:21 -05003815 entry->polarity = 0;
3816 entry->trigger = 0;
3817 entry->mask = 0;
Ingo Molnardebccb32009-01-28 15:20:18 +01003818 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
Dean Nelson4173a0e2008-10-02 12:18:21 -05003819
3820 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3821 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3822
3823 return irq;
3824}
3825
3826/*
3827 * Disable the specified MMR located on the specified blade so that MSIs are
3828 * longer allowed to be sent.
3829 */
3830void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3831{
3832 unsigned long mmr_value;
3833 struct uv_IO_APIC_route_entry *entry;
3834 int mmr_pnode;
3835
3836 mmr_value = 0;
3837 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3838 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3839
3840 entry->mask = 1;
3841
3842 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3843 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3844}
3845#endif /* CONFIG_X86_64 */
3846
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003847int __init io_apic_get_redir_entries (int ioapic)
3848{
3849 union IO_APIC_reg_01 reg_01;
3850 unsigned long flags;
3851
3852 spin_lock_irqsave(&ioapic_lock, flags);
3853 reg_01.raw = io_apic_read(ioapic, 1);
3854 spin_unlock_irqrestore(&ioapic_lock, flags);
3855
3856 return reg_01.bits.entries;
3857}
3858
Yinghai Lube5d5352008-12-05 18:58:33 -08003859void __init probe_nr_irqs_gsi(void)
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003860{
Yinghai Lube5d5352008-12-05 18:58:33 -08003861 int nr = 0;
3862
Yinghai Lucc6c5002009-02-08 16:18:03 -08003863 nr = acpi_probe_gsi();
3864 if (nr > nr_irqs_gsi) {
Yinghai Lube5d5352008-12-05 18:58:33 -08003865 nr_irqs_gsi = nr;
Yinghai Lucc6c5002009-02-08 16:18:03 -08003866 } else {
3867 /* for acpi=off or acpi is not compiled in */
3868 int idx;
3869
3870 nr = 0;
3871 for (idx = 0; idx < nr_ioapics; idx++)
3872 nr += io_apic_get_redir_entries(idx) + 1;
3873
3874 if (nr > nr_irqs_gsi)
3875 nr_irqs_gsi = nr;
3876 }
3877
3878 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
Yinghai Lu9d6a4d02008-08-19 20:50:52 -07003879}
3880
Yinghai Lu4a046d12009-01-12 17:39:24 -08003881#ifdef CONFIG_SPARSE_IRQ
3882int __init arch_probe_nr_irqs(void)
3883{
3884 int nr;
3885
Yinghai Luf1ee5542009-02-08 16:18:03 -08003886 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3887 nr_irqs = NR_VECTORS * nr_cpu_ids;
Yinghai Lu4a046d12009-01-12 17:39:24 -08003888
Yinghai Luf1ee5542009-02-08 16:18:03 -08003889 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3890#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3891 /*
3892 * for MSI and HT dyn irq
3893 */
3894 nr += nr_irqs_gsi * 16;
3895#endif
3896 if (nr < nr_irqs)
Yinghai Lu4a046d12009-01-12 17:39:24 -08003897 nr_irqs = nr;
3898
3899 return 0;
3900}
3901#endif
3902
Linus Torvalds1da177e2005-04-16 15:20:36 -07003903/* --------------------------------------------------------------------------
Ingo Molnar54168ed2008-08-20 09:07:45 +02003904 ACPI-based IOAPIC Configuration
Linus Torvalds1da177e2005-04-16 15:20:36 -07003905 -------------------------------------------------------------------------- */
3906
Len Brown888ba6c2005-08-24 12:07:20 -04003907#ifdef CONFIG_ACPI
Linus Torvalds1da177e2005-04-16 15:20:36 -07003908
Ingo Molnar54168ed2008-08-20 09:07:45 +02003909#ifdef CONFIG_X86_32
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003910int __init io_apic_get_unique_id(int ioapic, int apic_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003911{
3912 union IO_APIC_reg_00 reg_00;
3913 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3914 physid_mask_t tmp;
3915 unsigned long flags;
3916 int i = 0;
3917
3918 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003919 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3920 * buses (one for LAPICs, one for IOAPICs), where predecessors only
Linus Torvalds1da177e2005-04-16 15:20:36 -07003921 * supports up to 16 on one shared APIC bus.
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003922 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07003923 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3924 * advantage of new APIC bus architecture.
3925 */
3926
3927 if (physids_empty(apic_id_map))
Ingo Molnard190cb82009-01-28 06:50:47 +01003928 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003929
3930 spin_lock_irqsave(&ioapic_lock, flags);
3931 reg_00.raw = io_apic_read(ioapic, 0);
3932 spin_unlock_irqrestore(&ioapic_lock, flags);
3933
3934 if (apic_id >= get_physical_broadcast()) {
3935 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3936 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3937 apic_id = reg_00.bits.ID;
3938 }
3939
3940 /*
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003941 * Every APIC in a system must have a unique ID or we get lots of nice
Linus Torvalds1da177e2005-04-16 15:20:36 -07003942 * 'stuck on smp_invalidate_needed IPI wait' messages.
3943 */
Ingo Molnard1d7cae2009-01-28 05:41:42 +01003944 if (apic->check_apicid_used(apic_id_map, apic_id)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003945
3946 for (i = 0; i < get_physical_broadcast(); i++) {
Ingo Molnard1d7cae2009-01-28 05:41:42 +01003947 if (!apic->check_apicid_used(apic_id_map, i))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003948 break;
3949 }
3950
3951 if (i == get_physical_broadcast())
3952 panic("Max apic_id exceeded!\n");
3953
3954 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3955 "trying %d\n", ioapic, apic_id, i);
3956
3957 apic_id = i;
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003958 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003959
Ingo Molnar80587142009-01-28 06:50:47 +01003960 tmp = apic->apicid_to_cpu_present(apic_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003961 physids_or(apic_id_map, apic_id_map, tmp);
3962
3963 if (reg_00.bits.ID != apic_id) {
3964 reg_00.bits.ID = apic_id;
3965
3966 spin_lock_irqsave(&ioapic_lock, flags);
3967 io_apic_write(ioapic, 0, reg_00.raw);
3968 reg_00.raw = io_apic_read(ioapic, 0);
3969 spin_unlock_irqrestore(&ioapic_lock, flags);
3970
3971 /* Sanity check */
Andreas Deresch6070f9e2006-02-26 04:18:34 +01003972 if (reg_00.bits.ID != apic_id) {
3973 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3974 return -1;
3975 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003976 }
3977
3978 apic_printk(APIC_VERBOSE, KERN_INFO
3979 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3980
3981 return apic_id;
3982}
3983
Paolo Ciarrocchi36062442008-06-08 13:07:18 +02003984int __init io_apic_get_version(int ioapic)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003985{
3986 union IO_APIC_reg_01 reg_01;
3987 unsigned long flags;
3988
3989 spin_lock_irqsave(&ioapic_lock, flags);
3990 reg_01.raw = io_apic_read(ioapic, 1);
3991 spin_unlock_irqrestore(&ioapic_lock, flags);
3992
3993 return reg_01.bits.version;
3994}
Ingo Molnar54168ed2008-08-20 09:07:45 +02003995#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003996
Ingo Molnar54168ed2008-08-20 09:07:45 +02003997int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003998{
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08003999 struct irq_desc *desc;
4000 struct irq_cfg *cfg;
4001 int cpu = boot_cpu_id;
4002
Linus Torvalds1da177e2005-04-16 15:20:36 -07004003 if (!IO_APIC_IRQ(irq)) {
Ingo Molnar54168ed2008-08-20 09:07:45 +02004004 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07004005 ioapic);
4006 return -EINVAL;
4007 }
4008
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08004009 desc = irq_to_desc_alloc_cpu(irq, cpu);
4010 if (!desc) {
4011 printk(KERN_INFO "can not get irq_desc %d\n", irq);
4012 return 0;
4013 }
4014
Linus Torvalds1da177e2005-04-16 15:20:36 -07004015 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004016 * IRQs < 16 are already in the irq_2_pin[] map
4017 */
Yinghai Lu99d093d2008-12-05 18:58:32 -08004018 if (irq >= NR_IRQS_LEGACY) {
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08004019 cfg = desc->chip_data;
Yinghai Lu3145e942008-12-05 18:58:34 -08004020 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08004021 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004022
Yinghai Lu3145e942008-12-05 18:58:34 -08004023 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004024
4025 return 0;
4026}
4027
Ingo Molnar54168ed2008-08-20 09:07:45 +02004028
Shaohua Li61fd47e2007-11-17 01:05:28 -05004029int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4030{
4031 int i;
4032
4033 if (skip_ioapic_setup)
4034 return -1;
4035
4036 for (i = 0; i < mp_irq_entries; i++)
Jaswinder Singh Rajputc2c21742009-01-12 17:47:22 +05304037 if (mp_irqs[i].irqtype == mp_INT &&
4038 mp_irqs[i].srcbusirq == bus_irq)
Shaohua Li61fd47e2007-11-17 01:05:28 -05004039 break;
4040 if (i >= mp_irq_entries)
4041 return -1;
4042
4043 *trigger = irq_trigger(i);
4044 *polarity = irq_polarity(i);
4045 return 0;
4046}
4047
Len Brown888ba6c2005-08-24 12:07:20 -04004048#endif /* CONFIG_ACPI */
Rusty Russell1a3f2392006-09-26 10:52:32 +02004049
Yinghai Lu497c9a12008-08-19 20:50:28 -07004050/*
4051 * This function currently is only a helper for the i386 smp boot process where
4052 * we need to reprogram the ioredtbls to cater for the cpus which have come online
Ingo Molnarfe402e12009-01-28 04:32:51 +01004053 * so mask in all cases should simply be apic->target_cpus()
Yinghai Lu497c9a12008-08-19 20:50:28 -07004054 */
4055#ifdef CONFIG_SMP
4056void __init setup_ioapic_dest(void)
4057{
4058 int pin, ioapic, irq, irq_entry;
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004059 struct irq_desc *desc;
Yinghai Lu497c9a12008-08-19 20:50:28 -07004060 struct irq_cfg *cfg;
Mike Travis22f65d32008-12-16 17:33:56 -08004061 const struct cpumask *mask;
Yinghai Lu497c9a12008-08-19 20:50:28 -07004062
4063 if (skip_ioapic_setup == 1)
4064 return;
4065
4066 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4067 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4068 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4069 if (irq_entry == -1)
4070 continue;
4071 irq = pin_2_irq(irq_entry, ioapic, pin);
4072
4073 /* setup_IO_APIC_irqs could fail to get vector for some device
4074 * when you have too many devices, because at that time only boot
4075 * cpu is online.
4076 */
Yinghai Lu0b8f1ef2008-12-05 18:58:31 -08004077 desc = irq_to_desc(irq);
4078 cfg = desc->chip_data;
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004079 if (!cfg->vector) {
Yinghai Lu3145e942008-12-05 18:58:34 -08004080 setup_IO_APIC_irq(ioapic, pin, irq, desc,
Yinghai Lu497c9a12008-08-19 20:50:28 -07004081 irq_trigger(irq_entry),
4082 irq_polarity(irq_entry));
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004083 continue;
4084
4085 }
4086
4087 /*
4088 * Honour affinities which have been set in early boot
4089 */
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004090 if (desc->status &
4091 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
Mike Travis7f7ace02009-01-10 21:58:08 -08004092 mask = desc->affinity;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004093 else
Ingo Molnarfe402e12009-01-28 04:32:51 +01004094 mask = apic->target_cpus();
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004095
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004096 if (intr_remapping_enabled)
Yinghai Lu3145e942008-12-05 18:58:34 -08004097 set_ir_ioapic_affinity_irq_desc(desc, mask);
Thomas Gleixner6c2e9402008-11-07 12:33:49 +01004098 else
Yinghai Lu3145e942008-12-05 18:58:34 -08004099 set_ioapic_affinity_irq_desc(desc, mask);
Yinghai Lu497c9a12008-08-19 20:50:28 -07004100 }
4101
4102 }
4103}
4104#endif
4105
Ingo Molnar54168ed2008-08-20 09:07:45 +02004106#define IOAPIC_RESOURCE_NAME_SIZE 11
4107
4108static struct resource *ioapic_resources;
4109
4110static struct resource * __init ioapic_setup_resources(void)
4111{
4112 unsigned long n;
4113 struct resource *res;
4114 char *mem;
4115 int i;
4116
4117 if (nr_ioapics <= 0)
4118 return NULL;
4119
4120 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4121 n *= nr_ioapics;
4122
4123 mem = alloc_bootmem(n);
4124 res = (void *)mem;
4125
4126 if (mem != NULL) {
4127 mem += sizeof(struct resource) * nr_ioapics;
4128
4129 for (i = 0; i < nr_ioapics; i++) {
4130 res[i].name = mem;
4131 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4132 sprintf(mem, "IOAPIC %u", i);
4133 mem += IOAPIC_RESOURCE_NAME_SIZE;
4134 }
4135 }
4136
4137 ioapic_resources = res;
4138
4139 return res;
4140}
Ingo Molnar54168ed2008-08-20 09:07:45 +02004141
Yinghai Luf3294a32008-06-27 01:41:56 -07004142void __init ioapic_init_mappings(void)
4143{
4144 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004145 struct resource *ioapic_res;
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02004146 int i;
Yinghai Luf3294a32008-06-27 01:41:56 -07004147
Ingo Molnar54168ed2008-08-20 09:07:45 +02004148 ioapic_res = ioapic_setup_resources();
Yinghai Luf3294a32008-06-27 01:41:56 -07004149 for (i = 0; i < nr_ioapics; i++) {
4150 if (smp_found_config) {
Jaswinder Singh Rajputb5ba7e62009-01-12 17:46:17 +05304151 ioapic_phys = mp_ioapics[i].apicaddr;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004152#ifdef CONFIG_X86_32
Thomas Gleixnerd6c88a52008-10-15 15:27:23 +02004153 if (!ioapic_phys) {
4154 printk(KERN_ERR
4155 "WARNING: bogus zero IO-APIC "
4156 "address found in MPTABLE, "
4157 "disabling IO/APIC support!\n");
4158 smp_found_config = 0;
4159 skip_ioapic_setup = 1;
4160 goto fake_ioapic_page;
4161 }
Ingo Molnar54168ed2008-08-20 09:07:45 +02004162#endif
Yinghai Luf3294a32008-06-27 01:41:56 -07004163 } else {
Ingo Molnar54168ed2008-08-20 09:07:45 +02004164#ifdef CONFIG_X86_32
Yinghai Luf3294a32008-06-27 01:41:56 -07004165fake_ioapic_page:
Ingo Molnar54168ed2008-08-20 09:07:45 +02004166#endif
Yinghai Luf3294a32008-06-27 01:41:56 -07004167 ioapic_phys = (unsigned long)
Ingo Molnar54168ed2008-08-20 09:07:45 +02004168 alloc_bootmem_pages(PAGE_SIZE);
Yinghai Luf3294a32008-06-27 01:41:56 -07004169 ioapic_phys = __pa(ioapic_phys);
4170 }
4171 set_fixmap_nocache(idx, ioapic_phys);
Ingo Molnar54168ed2008-08-20 09:07:45 +02004172 apic_printk(APIC_VERBOSE,
4173 "mapped IOAPIC to %08lx (%08lx)\n",
4174 __fix_to_virt(idx), ioapic_phys);
Yinghai Luf3294a32008-06-27 01:41:56 -07004175 idx++;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004176
Ingo Molnar54168ed2008-08-20 09:07:45 +02004177 if (ioapic_res != NULL) {
4178 ioapic_res->start = ioapic_phys;
4179 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4180 ioapic_res++;
4181 }
Yinghai Luf3294a32008-06-27 01:41:56 -07004182 }
4183}
4184
Ingo Molnar54168ed2008-08-20 09:07:45 +02004185static int __init ioapic_insert_resources(void)
4186{
4187 int i;
4188 struct resource *r = ioapic_resources;
4189
4190 if (!r) {
Bartlomiej Zolnierkiewicz04c93ce2009-03-20 21:02:55 +01004191 if (nr_ioapics > 0) {
4192 printk(KERN_ERR
4193 "IO APIC resources couldn't be allocated.\n");
4194 return -1;
4195 }
4196 return 0;
Ingo Molnar54168ed2008-08-20 09:07:45 +02004197 }
4198
4199 for (i = 0; i < nr_ioapics; i++) {
4200 insert_resource(&iomem_resource, r);
4201 r++;
4202 }
4203
4204 return 0;
4205}
4206
4207/* Insert the IO APIC resources after PCI initialization has occured to handle
4208 * IO APICS that are mapped in on a BAR in PCI space. */
4209late_initcall(ioapic_insert_resources);