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nv-tegra.nvidia.com / linux-5.10 / eca05f0011de16f7a889e14dc36c7618d040884a / . / drivers / clk / rockchip / clk-rv1108.c
blob: 9c6bad0da14019b401382dbfdef273b187ac825b [file] [log] [blame]
Andy Yan7e2a9032017-03-17 18:18:38 +0100[diff] [blame]1/*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Shawn Lin <shawn.lin@rock-chips.com>
4 * Andy Yan <andy.yan@rock-chips.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/syscore_ops.h>
21#include <dt-bindings/clock/rv1108-cru.h>
22#include "clk.h"
23
24#define RV1108_GRF_SOC_STATUS0 0x480
25
26enum rv1108_plls {
27 apll, dpll, gpll,
28};
29
30static struct rockchip_pll_rate_table rv1108_pll_rates[] = {
31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
53 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
54 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
55 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
56 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
57 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
58 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
59 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
60 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
61 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
62 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
63 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
64 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
65 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
66 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
67 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
68 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
69 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
70 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
71 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
72 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
73 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
74 { /* sentinel */ },
75};
76
77#define RV1108_DIV_CORE_MASK 0xf
78#define RV1108_DIV_CORE_SHIFT 4
79
80#define RV1108_CLKSEL0(_core_peri_div) \
81 { \
82 .reg = RV1108_CLKSEL_CON(1), \
83 .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\
84 RV1108_DIV_CORE_SHIFT) \
85 }
86
87#define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \
88 { \
89 .prate = _prate, \
90 .divs = { \
91 RV1108_CLKSEL0(_core_peri_div), \
92 }, \
93 }
94
95static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
Elaine Zhangd00b4d92017-08-02 16:32:23 +0800[diff] [blame]96 RV1108_CPUCLK_RATE(1608000000, 7),
97 RV1108_CPUCLK_RATE(1512000000, 7),
98 RV1108_CPUCLK_RATE(1488000000, 5),
99 RV1108_CPUCLK_RATE(1416000000, 5),
100 RV1108_CPUCLK_RATE(1392000000, 5),
101 RV1108_CPUCLK_RATE(1296000000, 5),
102 RV1108_CPUCLK_RATE(1200000000, 5),
103 RV1108_CPUCLK_RATE(1104000000, 5),
104 RV1108_CPUCLK_RATE(1008000000, 5),
105 RV1108_CPUCLK_RATE(912000000, 5),
106 RV1108_CPUCLK_RATE(816000000, 3),
107 RV1108_CPUCLK_RATE(696000000, 3),
108 RV1108_CPUCLK_RATE(600000000, 3),
109 RV1108_CPUCLK_RATE(500000000, 3),
110 RV1108_CPUCLK_RATE(408000000, 1),
111 RV1108_CPUCLK_RATE(312000000, 1),
112 RV1108_CPUCLK_RATE(216000000, 1),
113 RV1108_CPUCLK_RATE(96000000, 1),
Andy Yan7e2a9032017-03-17 18:18:38 +0100[diff] [blame]114};
115
116static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
117 .core_reg = RV1108_CLKSEL_CON(0),
118 .div_core_shift = 0,
119 .div_core_mask = 0x1f,
120 .mux_core_alt = 1,
121 .mux_core_main = 0,
122 .mux_core_shift = 8,
Elaine Zhangd00b4d92017-08-02 16:32:23 +0800[diff] [blame]123 .mux_core_mask = 0x3,
Andy Yan7e2a9032017-03-17 18:18:38 +0100[diff] [blame]124};
125
126PNAME(mux_pll_p) = { "xin24m", "xin24m"};
127PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
128PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
129PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
130PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
131PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
132PNAME(mux_pll_src_4plls_p) = { "dpll", "hdmiphy", "gpll", "usb480m" };
133PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" };
134PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
135PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
136PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_dpll", "aclk_peri_src_gpll" };
137PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" };
138PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
139PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
140PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
141PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
142PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
143PNAME(mux_sclk_macphy_p) = { "sclk_macphy_pre", "ext_gmac" };
144PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
145PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" };
146PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "xin12m" };
147PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
148
149static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
150 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
Elaine Zhangeca05f02017-08-02 16:33:04 +0800[diff] [blame^]151 RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates),
Andy Yan7e2a9032017-03-17 18:18:38 +0100[diff] [blame]152 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
Elaine Zhangeca05f02017-08-02 16:33:04 +0800[diff] [blame^]153 RV1108_PLL_CON(11), 8, 1, 0, NULL),
Andy Yan7e2a9032017-03-17 18:18:38 +0100[diff] [blame]154 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
Elaine Zhangeca05f02017-08-02 16:33:04 +0800[diff] [blame^]155 RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates),
Andy Yan7e2a9032017-03-17 18:18:38 +0100[diff] [blame]156};
157
158#define MFLAGS CLK_MUX_HIWORD_MASK
159#define DFLAGS CLK_DIVIDER_HIWORD_MASK
160#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
161#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
162
163static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata =
164 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
165 RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
166
167static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata =
168 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
169 RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
170
171static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata =
172 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
173 RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
174
175static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata =
176 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT,
177 RV1108_CLKSEL_CON(5), 12, 2, MFLAGS);
178
179static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata =
180 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
181 RV1108_CLKSEL_CON(6), 12, 2, MFLAGS);
182
183static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata =
184 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
185 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
186
187static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
188 MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
189 RV1108_MISC_CON, 13, 2, MFLAGS),
190 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
191 RV1108_MISC_CON, 15, 2, MFLAGS),
192 /*
193 * Clock-Architecture Diagram 2
194 */
195
196 /* PD_CORE */
197 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
198 RV1108_CLKGATE_CON(0), 1, GFLAGS),
199 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
200 RV1108_CLKGATE_CON(0), 0, GFLAGS),
201 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
202 RV1108_CLKGATE_CON(0), 2, GFLAGS),
203 COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED,
204 RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
205 RV1108_CLKGATE_CON(0), 5, GFLAGS),
206 COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED,
207 RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
208 RV1108_CLKGATE_CON(0), 4, GFLAGS),
209 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
210 RV1108_CLKGATE_CON(11), 0, GFLAGS),
211 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
212 RV1108_CLKGATE_CON(11), 1, GFLAGS),
213
214 /* PD_RKVENC */
215
216 /* PD_RKVDEC */
217
218 /* PD_PMU_wrapper */
219 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
220 RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
221 RV1108_CLKGATE_CON(8), 12, GFLAGS),
222 GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
223 RV1108_CLKGATE_CON(10), 0, GFLAGS),
224 GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
225 RV1108_CLKGATE_CON(10), 1, GFLAGS),
226 GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
227 RV1108_CLKGATE_CON(10), 2, GFLAGS),
228 GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
229 RV1108_CLKGATE_CON(10), 3, GFLAGS),
230 GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED,
231 RV1108_CLKGATE_CON(10), 4, GFLAGS),
232 GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
233 RV1108_CLKGATE_CON(10), 5, GFLAGS),
234 GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
235 RV1108_CLKGATE_CON(10), 6, GFLAGS),
236 COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
237 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
238 RV1108_CLKGATE_CON(8), 15, GFLAGS),
239 COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
240 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
241 RV1108_CLKGATE_CON(8), 14, GFLAGS),
242 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
243 RV1108_CLKGATE_CON(8), 13, GFLAGS),
244
245 /*
246 * Clock-Architecture Diagram 4
247 */
248 COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
249 RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
250 RV1108_CLKGATE_CON(6), 0, GFLAGS),
251 GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED,
252 RV1108_CLKGATE_CON(17), 0, GFLAGS),
253 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
254 RV1108_CLKSEL_CON(29), 0, 5, DFLAGS,
255 RV1108_CLKGATE_CON(7), 2, GFLAGS),
256 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
257 RV1108_CLKSEL_CON(29), 8, 5, DFLAGS,
258 RV1108_CLKGATE_CON(7), 3, GFLAGS),
259
260 INVERTER(0, "pclk_vip", "ext_vip",
261 RV1108_CLKSEL_CON(31), 8, IFLAGS),
262 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED,
263 RV1108_CLKGATE_CON(7), 6, GFLAGS),
264 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED,
265 RV1108_CLKGATE_CON(18), 10, GFLAGS),
266 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED,
267 RV1108_CLKGATE_CON(6), 5, GFLAGS),
268 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
269 RV1108_CLKGATE_CON(6), 4, GFLAGS),
270 COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0,
271 RV1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS),
272
273 /*
274 * Clock-Architecture Diagram 5
275 */
276
277 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
278
279 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
280 RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
281 RV1108_CLKGATE_CON(2), 0, GFLAGS),
282 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
283 RV1108_CLKSEL_CON(8), 0,
284 RV1108_CLKGATE_CON(2), 1, GFLAGS,
285 &rv1108_i2s0_fracmux),
286 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
287 RV1108_CLKGATE_CON(2), 2, GFLAGS),
288 COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
289 RV1108_CLKSEL_CON(5), 15, 1, MFLAGS,
290 RV1108_CLKGATE_CON(2), 3, GFLAGS),
291
292 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
293 RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
294 RV1108_CLKGATE_CON(2), 4, GFLAGS),
295 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
296 RK2928_CLKSEL_CON(9), 0,
297 RK2928_CLKGATE_CON(2), 5, GFLAGS,
298 &rv1108_i2s1_fracmux),
299 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
300 RV1108_CLKGATE_CON(2), 6, GFLAGS),
301
302 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
303 RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
304 RV1108_CLKGATE_CON(3), 8, GFLAGS),
305 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
306 RV1108_CLKSEL_CON(10), 0,
307 RV1108_CLKGATE_CON(2), 9, GFLAGS,
308 &rv1108_i2s2_fracmux),
309 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
310 RV1108_CLKGATE_CON(2), 10, GFLAGS),
311
312 /* PD_BUS */
313 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
314 RV1108_CLKGATE_CON(1), 0, GFLAGS),
315 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
316 RV1108_CLKGATE_CON(1), 1, GFLAGS),
317 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
318 RV1108_CLKGATE_CON(1), 2, GFLAGS),
319 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
320 RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
321 COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0,
322 RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
323 RV1108_CLKGATE_CON(1), 4, GFLAGS),
324 COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0,
325 RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
326 RV1108_CLKGATE_CON(1), 5, GFLAGS),
327 GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED,
328 RV1108_CLKGATE_CON(1), 6, GFLAGS),
329 GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED,
330 RV1108_CLKGATE_CON(1), 7, GFLAGS),
331 GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED,
332 RV1108_CLKGATE_CON(1), 8, GFLAGS),
333 GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED,
334 RV1108_CLKGATE_CON(1), 9, GFLAGS),
335 GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED,
336 RV1108_CLKGATE_CON(1), 10, GFLAGS),
337 GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
338 RV1108_CLKGATE_CON(13), 4, GFLAGS),
339
340 COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
341 RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
342 RV1108_CLKGATE_CON(3), 1, GFLAGS),
343 COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
344 RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
345 RV1108_CLKGATE_CON(3), 3, GFLAGS),
346 COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
347 RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
348 RV1108_CLKGATE_CON(3), 5, GFLAGS),
349
350 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
351 RV1108_CLKSEL_CON(16), 0,
352 RV1108_CLKGATE_CON(3), 2, GFLAGS,
353 &rv1108_uart0_fracmux),
354 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
355 RV1108_CLKSEL_CON(17), 0,
356 RV1108_CLKGATE_CON(3), 4, GFLAGS,
357 &rv1108_uart1_fracmux),
358 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
359 RV1108_CLKSEL_CON(18), 0,
360 RV1108_CLKGATE_CON(3), 6, GFLAGS,
361 &rv1108_uart2_fracmux),
362 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED,
363 RV1108_CLKGATE_CON(13), 10, GFLAGS),
364 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
365 RV1108_CLKGATE_CON(13), 11, GFLAGS),
366 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
367 RV1108_CLKGATE_CON(13), 12, GFLAGS),
368
369 COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
370 RV1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS,
371 RV1108_CLKGATE_CON(3), 7, GFLAGS),
372 COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
373 RV1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS,
374 RV1108_CLKGATE_CON(3), 8, GFLAGS),
375 COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
376 RV1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS,
377 RV1108_CLKGATE_CON(3), 9, GFLAGS),
378 GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
379 RV1108_CLKGATE_CON(13), 0, GFLAGS),
380 GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
381 RV1108_CLKGATE_CON(13), 1, GFLAGS),
382 GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
383 RV1108_CLKGATE_CON(13), 2, GFLAGS),
384 COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
385 RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
386 RV1108_CLKGATE_CON(3), 10, GFLAGS),
387 GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
388 RV1108_CLKGATE_CON(13), 6, GFLAGS),
389 GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED,
390 RV1108_CLKGATE_CON(13), 3, GFLAGS),
391 GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
392 RV1108_CLKGATE_CON(13), 7, GFLAGS),
393 GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
394 RV1108_CLKGATE_CON(13), 8, GFLAGS),
395 GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
396 RV1108_CLKGATE_CON(13), 9, GFLAGS),
397
398 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
399 RV1108_CLKGATE_CON(14), 0, GFLAGS),
400
401 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
402 RV1108_CLKGATE_CON(12), 2, GFLAGS),
403 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED,
404 RV1108_CLKGATE_CON(12), 3, GFLAGS),
405 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED,
406 RV1108_CLKGATE_CON(12), 1, GFLAGS),
407
408 /* PD_DDR */
409 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
410 RV1108_CLKGATE_CON(0), 8, GFLAGS),
411 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
412 RV1108_CLKGATE_CON(0), 9, GFLAGS),
413 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
414 RV1108_CLKGATE_CON(0), 10, GFLAGS),
415 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
416 RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
417 DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
418 RV1108_CLKGATE_CON(10), 9, GFLAGS),
419 GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED,
420 RV1108_CLKGATE_CON(12), 4, GFLAGS),
421 GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED,
422 RV1108_CLKGATE_CON(12), 5, GFLAGS),
423 GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED,
424 RV1108_CLKGATE_CON(12), 6, GFLAGS),
425 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
426 RV1108_CLKGATE_CON(0), 11, GFLAGS),
427
428 /*
429 * Clock-Architecture Diagram 6
430 */
431
432 /* PD_PERI */
433 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
434 RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
435 RV1108_CLKGATE_CON(4), 5, GFLAGS),
436 GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
437 RV1108_CLKGATE_CON(15), 13, GFLAGS),
438 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
439 RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
440 RV1108_CLKGATE_CON(4), 4, GFLAGS),
441 GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
442 RV1108_CLKGATE_CON(15), 12, GFLAGS),
443
444 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
445 RV1108_CLKGATE_CON(4), 1, GFLAGS),
446 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
447 RV1108_CLKGATE_CON(4), 2, GFLAGS),
448 COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED,
449 RV1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS,
450 RV1108_CLKGATE_CON(15), 11, GFLAGS),
451
452 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
453 RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
454 RV1108_CLKGATE_CON(5), 0, GFLAGS),
455
456 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
457 RV1108_CLKSEL_CON(25), 10, 2, MFLAGS,
458 RV1108_CLKGATE_CON(5), 2, GFLAGS),
459 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
460 RV1108_CLKSEL_CON(26), 0, 8, DFLAGS),
461
462 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
463 RV1108_CLKSEL_CON(25), 12, 2, MFLAGS,
464 RV1108_CLKGATE_CON(5), 1, GFLAGS),
465 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
466 RK2928_CLKSEL_CON(26), 8, 8, DFLAGS),
467 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS),
468 GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS),
469 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
470
471 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
472 RV1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS,
473 RV1108_CLKGATE_CON(5), 3, GFLAGS),
474 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
475
476 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
477 RV1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS,
478 RV1108_CLKGATE_CON(5), 4, GFLAGS),
479 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
480
481 COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0,
482 RV1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS,
483 RV1108_CLKGATE_CON(4), 10, GFLAGS),
484 MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT,
485 RV1108_CLKSEL_CON(24), 8, 2, MFLAGS),
486 GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
487 GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
488 GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
489
490 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
491 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
492
493 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1),
494 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1),
495
496 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1),
497 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1),
498};
499
500static const char *const rv1108_critical_clocks[] __initconst = {
501 "aclk_core",
502 "aclk_bus_src_gpll",
503 "aclk_periph",
504 "hclk_periph",
505 "pclk_periph",
506};
507
508static void __init rv1108_clk_init(struct device_node *np)
509{
510 struct rockchip_clk_provider *ctx;
511 void __iomem *reg_base;
512
513 reg_base = of_iomap(np, 0);
514 if (!reg_base) {
515 pr_err("%s: could not map cru region\n", __func__);
516 return;
517 }
518
519 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
520 if (IS_ERR(ctx)) {
521 pr_err("%s: rockchip clk init failed\n", __func__);
522 iounmap(reg_base);
523 return;
524 }
525
526 rockchip_clk_register_plls(ctx, rv1108_pll_clks,
527 ARRAY_SIZE(rv1108_pll_clks),
528 RV1108_GRF_SOC_STATUS0);
529 rockchip_clk_register_branches(ctx, rv1108_clk_branches,
530 ARRAY_SIZE(rv1108_clk_branches));
531 rockchip_clk_protect_critical(rv1108_critical_clocks,
532 ARRAY_SIZE(rv1108_critical_clocks));
533
534 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
535 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
536 &rv1108_cpuclk_data, rv1108_cpuclk_rates,
537 ARRAY_SIZE(rv1108_cpuclk_rates));
538
539 rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0),
540 ROCKCHIP_SOFTRST_HIWORD_MASK);
541
542 rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL);
543
544 rockchip_clk_of_add_provider(np, ctx);
545}
546CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init);