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nv-tegra.nvidia.com / linux-5.10 / de86a33253d07675abbb1fa294ffb4f3df6f219e / . / sound / soc / codecs / rt5659.c
blob: ef3a44d6386bd764a78ba034d45446b9bb58dc2c [file] [log] [blame]
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1/*
2 * rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver
3 *
4 * Copyright 2015 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
Nicolin Chenc6f87692016-07-28 14:57:16 -0700[diff] [blame]12#include <linux/clk.h>
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <linux/acpi.h>
22#include <linux/gpio.h>
23#include <linux/gpio/consumer.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/jack.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <sound/rt5659.h>
33
34#include "rl6231.h"
35#include "rt5659.h"
36
37static const struct reg_default rt5659_reg[] = {
38 { 0x0000, 0x0000 },
39 { 0x0001, 0x4848 },
40 { 0x0002, 0x8080 },
41 { 0x0003, 0xc8c8 },
42 { 0x0004, 0xc80a },
43 { 0x0005, 0x0000 },
44 { 0x0006, 0x0000 },
45 { 0x0007, 0x0103 },
46 { 0x0008, 0x0080 },
47 { 0x0009, 0x0000 },
48 { 0x000a, 0x0000 },
49 { 0x000c, 0x0000 },
50 { 0x000d, 0x0000 },
51 { 0x000f, 0x0808 },
52 { 0x0010, 0x3080 },
53 { 0x0011, 0x4a00 },
54 { 0x0012, 0x4e00 },
55 { 0x0015, 0x42c1 },
56 { 0x0016, 0x0000 },
57 { 0x0018, 0x000b },
58 { 0x0019, 0xafaf },
59 { 0x001a, 0xafaf },
60 { 0x001b, 0x0011 },
61 { 0x001c, 0x2f2f },
62 { 0x001d, 0x2f2f },
63 { 0x001e, 0x2f2f },
64 { 0x001f, 0x0000 },
65 { 0x0020, 0x0000 },
66 { 0x0021, 0x0000 },
67 { 0x0022, 0x5757 },
68 { 0x0023, 0x0039 },
69 { 0x0026, 0xc060 },
70 { 0x0027, 0xd8d8 },
71 { 0x0029, 0x8080 },
72 { 0x002a, 0xaaaa },
73 { 0x002b, 0xaaaa },
74 { 0x002c, 0x00af },
75 { 0x002d, 0x0000 },
76 { 0x002f, 0x1002 },
77 { 0x0031, 0x5000 },
78 { 0x0032, 0x0000 },
79 { 0x0033, 0x0000 },
80 { 0x0034, 0x0000 },
81 { 0x0035, 0x0000 },
82 { 0x0036, 0x0000 },
83 { 0x003a, 0x0000 },
84 { 0x003b, 0x0000 },
85 { 0x003c, 0x007f },
86 { 0x003d, 0x0000 },
87 { 0x003e, 0x007f },
88 { 0x0040, 0x0808 },
89 { 0x0046, 0x001f },
90 { 0x0047, 0x001f },
91 { 0x0048, 0x0003 },
92 { 0x0049, 0xe061 },
93 { 0x004a, 0x0000 },
94 { 0x004b, 0x031f },
95 { 0x004d, 0x0000 },
96 { 0x004e, 0x001f },
97 { 0x004f, 0x0000 },
98 { 0x0050, 0x001f },
99 { 0x0052, 0xf000 },
100 { 0x0053, 0x0111 },
101 { 0x0054, 0x0064 },
102 { 0x0055, 0x0080 },
103 { 0x0056, 0xef0e },
104 { 0x0057, 0xf0f0 },
105 { 0x0058, 0xef0e },
106 { 0x0059, 0xf0f0 },
107 { 0x005a, 0xef0e },
108 { 0x005b, 0xf0f0 },
109 { 0x005c, 0xf000 },
110 { 0x005d, 0x0000 },
111 { 0x005e, 0x1f2c },
112 { 0x005f, 0x1f2c },
113 { 0x0060, 0x2717 },
114 { 0x0061, 0x0000 },
115 { 0x0062, 0x0000 },
116 { 0x0063, 0x003e },
117 { 0x0064, 0x0000 },
118 { 0x0065, 0x0000 },
119 { 0x0066, 0x0000 },
120 { 0x0067, 0x0000 },
121 { 0x006a, 0x0000 },
122 { 0x006b, 0x0000 },
123 { 0x006c, 0x0000 },
124 { 0x006e, 0x0000 },
125 { 0x006f, 0x0000 },
126 { 0x0070, 0x8000 },
127 { 0x0071, 0x8000 },
128 { 0x0072, 0x8000 },
129 { 0x0073, 0x1110 },
130 { 0x0074, 0xfe00 },
131 { 0x0075, 0x2409 },
132 { 0x0076, 0x000a },
133 { 0x0077, 0x00f0 },
134 { 0x0078, 0x0000 },
135 { 0x0079, 0x0000 },
136 { 0x007a, 0x0123 },
137 { 0x007b, 0x8003 },
138 { 0x0080, 0x0000 },
139 { 0x0081, 0x0000 },
140 { 0x0082, 0x0000 },
141 { 0x0083, 0x0000 },
142 { 0x0084, 0x0000 },
143 { 0x0085, 0x0000 },
144 { 0x0086, 0x0008 },
145 { 0x0087, 0x0000 },
146 { 0x0088, 0x0000 },
147 { 0x0089, 0x0000 },
148 { 0x008a, 0x0000 },
149 { 0x008b, 0x0000 },
150 { 0x008c, 0x0003 },
151 { 0x008e, 0x0000 },
152 { 0x008f, 0x1000 },
153 { 0x0090, 0x0646 },
154 { 0x0091, 0x0c16 },
155 { 0x0092, 0x0073 },
156 { 0x0093, 0x0000 },
157 { 0x0094, 0x0080 },
158 { 0x0097, 0x0000 },
159 { 0x0098, 0x0000 },
160 { 0x0099, 0x0000 },
161 { 0x009a, 0x0000 },
162 { 0x009b, 0x0000 },
163 { 0x009c, 0x007f },
164 { 0x009d, 0x0000 },
165 { 0x009e, 0x007f },
166 { 0x009f, 0x0000 },
167 { 0x00a0, 0x0060 },
168 { 0x00a1, 0x90a1 },
169 { 0x00ae, 0x2000 },
170 { 0x00af, 0x0000 },
171 { 0x00b0, 0x2000 },
172 { 0x00b1, 0x0000 },
173 { 0x00b2, 0x0000 },
174 { 0x00b6, 0x0000 },
175 { 0x00b7, 0x0000 },
176 { 0x00b8, 0x0000 },
177 { 0x00b9, 0x0000 },
178 { 0x00ba, 0x0000 },
179 { 0x00bb, 0x0000 },
180 { 0x00be, 0x0000 },
181 { 0x00bf, 0x0000 },
182 { 0x00c0, 0x0000 },
183 { 0x00c1, 0x0000 },
184 { 0x00c2, 0x0000 },
185 { 0x00c3, 0x0000 },
186 { 0x00c4, 0x0003 },
187 { 0x00c5, 0x0000 },
188 { 0x00cb, 0xa02f },
189 { 0x00cc, 0x0000 },
190 { 0x00cd, 0x0e02 },
191 { 0x00d6, 0x0000 },
192 { 0x00d7, 0x2244 },
193 { 0x00d9, 0x0809 },
194 { 0x00da, 0x0000 },
195 { 0x00db, 0x0008 },
196 { 0x00dc, 0x00c0 },
197 { 0x00dd, 0x6724 },
198 { 0x00de, 0x3131 },
199 { 0x00df, 0x0008 },
200 { 0x00e0, 0x4000 },
201 { 0x00e1, 0x3131 },
202 { 0x00e4, 0x400c },
203 { 0x00e5, 0x8031 },
204 { 0x00ea, 0xb320 },
205 { 0x00eb, 0x0000 },
206 { 0x00ec, 0xb300 },
207 { 0x00ed, 0x0000 },
208 { 0x00f0, 0x0000 },
209 { 0x00f1, 0x0202 },
210 { 0x00f2, 0x0ddd },
211 { 0x00f3, 0x0ddd },
212 { 0x00f4, 0x0ddd },
213 { 0x00f6, 0x0000 },
214 { 0x00f7, 0x0000 },
215 { 0x00f8, 0x0000 },
216 { 0x00f9, 0x0000 },
217 { 0x00fa, 0x8000 },
218 { 0x00fb, 0x0000 },
219 { 0x00fc, 0x0000 },
220 { 0x00fd, 0x0001 },
221 { 0x00fe, 0x10ec },
222 { 0x00ff, 0x6311 },
223 { 0x0100, 0xaaaa },
224 { 0x010a, 0xaaaa },
225 { 0x010b, 0x00a0 },
226 { 0x010c, 0xaeae },
227 { 0x010d, 0xaaaa },
228 { 0x010e, 0xaaa8 },
229 { 0x010f, 0xa0aa },
230 { 0x0110, 0xe02a },
231 { 0x0111, 0xa702 },
232 { 0x0112, 0xaaaa },
233 { 0x0113, 0x2800 },
234 { 0x0116, 0x0000 },
235 { 0x0117, 0x0f00 },
236 { 0x011a, 0x0020 },
237 { 0x011b, 0x0011 },
238 { 0x011c, 0x0150 },
239 { 0x011d, 0x0000 },
240 { 0x011e, 0x0000 },
241 { 0x011f, 0x0000 },
242 { 0x0120, 0x0000 },
243 { 0x0121, 0x009b },
244 { 0x0122, 0x5014 },
245 { 0x0123, 0x0421 },
246 { 0x0124, 0x7cea },
247 { 0x0125, 0x0420 },
248 { 0x0126, 0x5550 },
249 { 0x0132, 0x0000 },
250 { 0x0133, 0x0000 },
251 { 0x0137, 0x5055 },
252 { 0x0138, 0x3700 },
253 { 0x0139, 0x79a1 },
254 { 0x013a, 0x2020 },
255 { 0x013b, 0x2020 },
256 { 0x013c, 0x2005 },
257 { 0x013e, 0x1f00 },
258 { 0x013f, 0x0000 },
259 { 0x0145, 0x0002 },
260 { 0x0146, 0x0000 },
261 { 0x0147, 0x0000 },
262 { 0x0148, 0x0000 },
263 { 0x0150, 0x1813 },
264 { 0x0151, 0x0690 },
265 { 0x0152, 0x1c17 },
266 { 0x0153, 0x6883 },
267 { 0x0154, 0xd3ce },
268 { 0x0155, 0x352d },
269 { 0x0156, 0x00eb },
270 { 0x0157, 0x3717 },
271 { 0x0158, 0x4c6a },
272 { 0x0159, 0xe41b },
273 { 0x015a, 0x2a13 },
274 { 0x015b, 0xb600 },
275 { 0x015c, 0xc730 },
276 { 0x015d, 0x35d4 },
277 { 0x015e, 0x00bf },
278 { 0x0160, 0x0ec0 },
279 { 0x0161, 0x0020 },
280 { 0x0162, 0x0080 },
281 { 0x0163, 0x0800 },
282 { 0x0164, 0x0000 },
283 { 0x0165, 0x0000 },
284 { 0x0166, 0x0000 },
285 { 0x0167, 0x001f },
286 { 0x0170, 0x4e80 },
287 { 0x0171, 0x0020 },
288 { 0x0172, 0x0080 },
289 { 0x0173, 0x0800 },
290 { 0x0174, 0x000c },
291 { 0x0175, 0x0000 },
292 { 0x0190, 0x3300 },
293 { 0x0191, 0x2200 },
294 { 0x0192, 0x0000 },
295 { 0x01b0, 0x4b38 },
296 { 0x01b1, 0x0000 },
297 { 0x01b2, 0x0000 },
298 { 0x01b3, 0x0000 },
299 { 0x01c0, 0x0045 },
300 { 0x01c1, 0x0540 },
301 { 0x01c2, 0x0000 },
302 { 0x01c3, 0x0030 },
303 { 0x01c7, 0x0000 },
304 { 0x01c8, 0x5757 },
305 { 0x01c9, 0x5757 },
306 { 0x01ca, 0x5757 },
307 { 0x01cb, 0x5757 },
308 { 0x01cc, 0x5757 },
309 { 0x01cd, 0x5757 },
310 { 0x01ce, 0x006f },
311 { 0x01da, 0x0000 },
312 { 0x01db, 0x0000 },
313 { 0x01de, 0x7d00 },
314 { 0x01df, 0x10c0 },
315 { 0x01e0, 0x06a1 },
316 { 0x01e1, 0x0000 },
317 { 0x01e2, 0x0000 },
318 { 0x01e3, 0x0000 },
319 { 0x01e4, 0x0001 },
320 { 0x01e6, 0x0000 },
321 { 0x01e7, 0x0000 },
322 { 0x01e8, 0x0000 },
323 { 0x01ea, 0x0000 },
324 { 0x01eb, 0x0000 },
325 { 0x01ec, 0x0000 },
326 { 0x01ed, 0x0000 },
327 { 0x01ee, 0x0000 },
328 { 0x01ef, 0x0000 },
329 { 0x01f0, 0x0000 },
330 { 0x01f1, 0x0000 },
331 { 0x01f2, 0x0000 },
332 { 0x01f6, 0x1e04 },
333 { 0x01f7, 0x01a1 },
334 { 0x01f8, 0x0000 },
335 { 0x01f9, 0x0000 },
336 { 0x01fa, 0x0002 },
337 { 0x01fb, 0x0000 },
338 { 0x01fc, 0x0000 },
339 { 0x01fd, 0x0000 },
340 { 0x01fe, 0x0000 },
341 { 0x0200, 0x066c },
342 { 0x0201, 0x7fff },
343 { 0x0202, 0x7fff },
344 { 0x0203, 0x0000 },
345 { 0x0204, 0x0000 },
346 { 0x0205, 0x0000 },
347 { 0x0206, 0x0000 },
348 { 0x0207, 0x0000 },
349 { 0x0208, 0x0000 },
350 { 0x0256, 0x0000 },
351 { 0x0257, 0x0000 },
352 { 0x0258, 0x0000 },
353 { 0x0259, 0x0000 },
354 { 0x025a, 0x0000 },
355 { 0x025b, 0x3333 },
356 { 0x025c, 0x3333 },
357 { 0x025d, 0x3333 },
358 { 0x025e, 0x0000 },
359 { 0x025f, 0x0000 },
360 { 0x0260, 0x0000 },
361 { 0x0261, 0x0022 },
362 { 0x0262, 0x0300 },
363 { 0x0265, 0x1e80 },
364 { 0x0266, 0x0131 },
365 { 0x0267, 0x0003 },
366 { 0x0268, 0x0000 },
367 { 0x0269, 0x0000 },
368 { 0x026a, 0x0000 },
369 { 0x026b, 0x0000 },
370 { 0x026c, 0x0000 },
371 { 0x026d, 0x0000 },
372 { 0x026e, 0x0000 },
373 { 0x026f, 0x0000 },
374 { 0x0270, 0x0000 },
375 { 0x0271, 0x0000 },
376 { 0x0272, 0x0000 },
377 { 0x0273, 0x0000 },
378 { 0x0280, 0x0000 },
379 { 0x0281, 0x0000 },
380 { 0x0282, 0x0418 },
381 { 0x0283, 0x7fff },
382 { 0x0284, 0x7000 },
383 { 0x0290, 0x01d0 },
384 { 0x0291, 0x0100 },
385 { 0x02fa, 0x0000 },
386 { 0x02fb, 0x0000 },
387 { 0x02fc, 0x0000 },
388 { 0x0300, 0x001f },
389 { 0x0301, 0x032c },
390 { 0x0302, 0x5f21 },
391 { 0x0303, 0x4000 },
392 { 0x0304, 0x4000 },
393 { 0x0305, 0x0600 },
394 { 0x0306, 0x8000 },
395 { 0x0307, 0x0700 },
396 { 0x0308, 0x001f },
397 { 0x0309, 0x032c },
398 { 0x030a, 0x5f21 },
399 { 0x030b, 0x4000 },
400 { 0x030c, 0x4000 },
401 { 0x030d, 0x0600 },
402 { 0x030e, 0x8000 },
403 { 0x030f, 0x0700 },
404 { 0x0310, 0x4560 },
405 { 0x0311, 0xa4a8 },
406 { 0x0312, 0x7418 },
407 { 0x0313, 0x0000 },
408 { 0x0314, 0x0006 },
409 { 0x0315, 0x00ff },
410 { 0x0316, 0xc400 },
411 { 0x0317, 0x4560 },
412 { 0x0318, 0xa4a8 },
413 { 0x0319, 0x7418 },
414 { 0x031a, 0x0000 },
415 { 0x031b, 0x0006 },
416 { 0x031c, 0x00ff },
417 { 0x031d, 0xc400 },
418 { 0x0320, 0x0f20 },
419 { 0x0321, 0x8700 },
420 { 0x0322, 0x7dc2 },
421 { 0x0323, 0xa178 },
422 { 0x0324, 0x5383 },
423 { 0x0325, 0x7dc2 },
424 { 0x0326, 0xa178 },
425 { 0x0327, 0x5383 },
426 { 0x0328, 0x003e },
427 { 0x0329, 0x02c1 },
428 { 0x032a, 0xd37d },
429 { 0x0330, 0x00a6 },
430 { 0x0331, 0x04c3 },
431 { 0x0332, 0x27c8 },
432 { 0x0333, 0xbf50 },
433 { 0x0334, 0x0045 },
434 { 0x0335, 0x2007 },
435 { 0x0336, 0x7418 },
436 { 0x0337, 0x0501 },
437 { 0x0338, 0x0000 },
438 { 0x0339, 0x0010 },
439 { 0x033a, 0x1010 },
440 { 0x0340, 0x0800 },
441 { 0x0341, 0x0800 },
442 { 0x0342, 0x0800 },
443 { 0x0343, 0x0800 },
444 { 0x0344, 0x0000 },
445 { 0x0345, 0x0000 },
446 { 0x0346, 0x0000 },
447 { 0x0347, 0x0000 },
448 { 0x0348, 0x0000 },
449 { 0x0349, 0x0000 },
450 { 0x034a, 0x0000 },
451 { 0x034b, 0x0000 },
452 { 0x034c, 0x0000 },
453 { 0x034d, 0x0000 },
454 { 0x034e, 0x0000 },
455 { 0x034f, 0x0000 },
456 { 0x0350, 0x0000 },
457 { 0x0351, 0x0000 },
458 { 0x0352, 0x0000 },
459 { 0x0353, 0x0000 },
460 { 0x0354, 0x0000 },
461 { 0x0355, 0x0000 },
462 { 0x0356, 0x0000 },
463 { 0x0357, 0x0000 },
464 { 0x0358, 0x0000 },
465 { 0x0359, 0x0000 },
466 { 0x035a, 0x0000 },
467 { 0x035b, 0x0000 },
468 { 0x035c, 0x0000 },
469 { 0x035d, 0x0000 },
470 { 0x035e, 0x2000 },
471 { 0x035f, 0x0000 },
472 { 0x0360, 0x2000 },
473 { 0x0361, 0x2000 },
474 { 0x0362, 0x0000 },
475 { 0x0363, 0x2000 },
476 { 0x0364, 0x0200 },
477 { 0x0365, 0x0000 },
478 { 0x0366, 0x0000 },
479 { 0x0367, 0x0000 },
480 { 0x0368, 0x0000 },
481 { 0x0369, 0x0000 },
482 { 0x036a, 0x0000 },
483 { 0x036b, 0x0000 },
484 { 0x036c, 0x0000 },
485 { 0x036d, 0x0000 },
486 { 0x036e, 0x0200 },
487 { 0x036f, 0x0000 },
488 { 0x0370, 0x0000 },
489 { 0x0371, 0x0000 },
490 { 0x0372, 0x0000 },
491 { 0x0373, 0x0000 },
492 { 0x0374, 0x0000 },
493 { 0x0375, 0x0000 },
494 { 0x0376, 0x0000 },
495 { 0x0377, 0x0000 },
496 { 0x03d0, 0x0000 },
497 { 0x03d1, 0x0000 },
498 { 0x03d2, 0x0000 },
499 { 0x03d3, 0x0000 },
500 { 0x03d4, 0x2000 },
501 { 0x03d5, 0x2000 },
502 { 0x03d6, 0x0000 },
503 { 0x03d7, 0x0000 },
504 { 0x03d8, 0x2000 },
505 { 0x03d9, 0x2000 },
506 { 0x03da, 0x2000 },
507 { 0x03db, 0x2000 },
508 { 0x03dc, 0x0000 },
509 { 0x03dd, 0x0000 },
510 { 0x03de, 0x0000 },
511 { 0x03df, 0x2000 },
512 { 0x03e0, 0x0000 },
513 { 0x03e1, 0x0000 },
514 { 0x03e2, 0x0000 },
515 { 0x03e3, 0x0000 },
516 { 0x03e4, 0x0000 },
517 { 0x03e5, 0x0000 },
518 { 0x03e6, 0x0000 },
519 { 0x03e7, 0x0000 },
520 { 0x03e8, 0x0000 },
521 { 0x03e9, 0x0000 },
522 { 0x03ea, 0x0000 },
523 { 0x03eb, 0x0000 },
524 { 0x03ec, 0x0000 },
525 { 0x03ed, 0x0000 },
526 { 0x03ee, 0x0000 },
527 { 0x03ef, 0x0000 },
528 { 0x03f0, 0x0800 },
529 { 0x03f1, 0x0800 },
530 { 0x03f2, 0x0800 },
531 { 0x03f3, 0x0800 },
532};
533
534static bool rt5659_volatile_register(struct device *dev, unsigned int reg)
535{
536 switch (reg) {
537 case RT5659_RESET:
538 case RT5659_EJD_CTRL_2:
539 case RT5659_SILENCE_CTRL:
540 case RT5659_DAC2_DIG_VOL:
541 case RT5659_HP_IMP_GAIN_2:
542 case RT5659_PDM_OUT_CTRL:
543 case RT5659_PDM_DATA_CTRL_1:
544 case RT5659_PDM_DATA_CTRL_4:
545 case RT5659_HAPTIC_GEN_CTRL_1:
546 case RT5659_HAPTIC_GEN_CTRL_3:
547 case RT5659_HAPTIC_LPF_CTRL_3:
548 case RT5659_CLK_DET:
549 case RT5659_MICBIAS_1:
550 case RT5659_ASRC_11:
551 case RT5659_ADC_EQ_CTRL_1:
552 case RT5659_DAC_EQ_CTRL_1:
553 case RT5659_INT_ST_1:
554 case RT5659_INT_ST_2:
555 case RT5659_GPIO_STA:
556 case RT5659_SINE_GEN_CTRL_1:
557 case RT5659_IL_CMD_1:
558 case RT5659_4BTN_IL_CMD_1:
559 case RT5659_PSV_IL_CMD_1:
560 case RT5659_AJD1_CTRL:
561 case RT5659_AJD2_AJD3_CTRL:
562 case RT5659_JD_CTRL_3:
563 case RT5659_VENDOR_ID:
564 case RT5659_VENDOR_ID_1:
565 case RT5659_DEVICE_ID:
566 case RT5659_MEMORY_TEST:
567 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
568 case RT5659_VOL_TEST:
569 case RT5659_STO_NG2_CTRL_1:
570 case RT5659_STO_NG2_CTRL_5:
571 case RT5659_STO_NG2_CTRL_6:
572 case RT5659_STO_NG2_CTRL_7:
573 case RT5659_MONO_NG2_CTRL_1:
574 case RT5659_MONO_NG2_CTRL_5:
575 case RT5659_MONO_NG2_CTRL_6:
576 case RT5659_HP_IMP_SENS_CTRL_1:
577 case RT5659_HP_IMP_SENS_CTRL_3:
578 case RT5659_HP_IMP_SENS_CTRL_4:
579 case RT5659_HP_CALIB_CTRL_1:
580 case RT5659_HP_CALIB_CTRL_9:
581 case RT5659_HP_CALIB_STA_1:
582 case RT5659_HP_CALIB_STA_2:
583 case RT5659_HP_CALIB_STA_3:
584 case RT5659_HP_CALIB_STA_4:
585 case RT5659_HP_CALIB_STA_5:
586 case RT5659_HP_CALIB_STA_6:
587 case RT5659_HP_CALIB_STA_7:
588 case RT5659_HP_CALIB_STA_8:
589 case RT5659_HP_CALIB_STA_9:
590 case RT5659_MONO_AMP_CALIB_CTRL_1:
591 case RT5659_MONO_AMP_CALIB_CTRL_3:
592 case RT5659_MONO_AMP_CALIB_STA_1:
593 case RT5659_MONO_AMP_CALIB_STA_2:
594 case RT5659_MONO_AMP_CALIB_STA_3:
595 case RT5659_MONO_AMP_CALIB_STA_4:
596 case RT5659_SPK_PWR_LMT_STA_1:
597 case RT5659_SPK_PWR_LMT_STA_2:
598 case RT5659_SPK_PWR_LMT_STA_3:
599 case RT5659_SPK_PWR_LMT_STA_4:
600 case RT5659_SPK_PWR_LMT_STA_5:
601 case RT5659_SPK_PWR_LMT_STA_6:
602 case RT5659_SPK_DC_CAILB_CTRL_1:
603 case RT5659_SPK_DC_CAILB_STA_1:
604 case RT5659_SPK_DC_CAILB_STA_2:
605 case RT5659_SPK_DC_CAILB_STA_3:
606 case RT5659_SPK_DC_CAILB_STA_4:
607 case RT5659_SPK_DC_CAILB_STA_5:
608 case RT5659_SPK_DC_CAILB_STA_6:
609 case RT5659_SPK_DC_CAILB_STA_7:
610 case RT5659_SPK_DC_CAILB_STA_8:
611 case RT5659_SPK_DC_CAILB_STA_9:
612 case RT5659_SPK_DC_CAILB_STA_10:
613 case RT5659_SPK_VDD_STA_1:
614 case RT5659_SPK_VDD_STA_2:
615 case RT5659_SPK_DC_DET_CTRL_1:
616 case RT5659_PURE_DC_DET_CTRL_1:
617 case RT5659_PURE_DC_DET_CTRL_2:
618 case RT5659_DRC1_PRIV_1:
619 case RT5659_DRC1_PRIV_4:
620 case RT5659_DRC1_PRIV_5:
621 case RT5659_DRC1_PRIV_6:
622 case RT5659_DRC1_PRIV_7:
623 case RT5659_DRC2_PRIV_1:
624 case RT5659_DRC2_PRIV_4:
625 case RT5659_DRC2_PRIV_5:
626 case RT5659_DRC2_PRIV_6:
627 case RT5659_DRC2_PRIV_7:
628 case RT5659_ALC_PGA_STA_1:
629 case RT5659_ALC_PGA_STA_2:
630 case RT5659_ALC_PGA_STA_3:
631 return true;
632 default:
633 return false;
634 }
635}
636
637static bool rt5659_readable_register(struct device *dev, unsigned int reg)
638{
639 switch (reg) {
640 case RT5659_RESET:
641 case RT5659_SPO_VOL:
642 case RT5659_HP_VOL:
643 case RT5659_LOUT:
644 case RT5659_MONO_OUT:
645 case RT5659_HPL_GAIN:
646 case RT5659_HPR_GAIN:
647 case RT5659_MONO_GAIN:
648 case RT5659_SPDIF_CTRL_1:
649 case RT5659_SPDIF_CTRL_2:
650 case RT5659_CAL_BST_CTRL:
651 case RT5659_IN1_IN2:
652 case RT5659_IN3_IN4:
653 case RT5659_INL1_INR1_VOL:
654 case RT5659_EJD_CTRL_1:
655 case RT5659_EJD_CTRL_2:
656 case RT5659_EJD_CTRL_3:
657 case RT5659_SILENCE_CTRL:
658 case RT5659_PSV_CTRL:
659 case RT5659_SIDETONE_CTRL:
660 case RT5659_DAC1_DIG_VOL:
661 case RT5659_DAC2_DIG_VOL:
662 case RT5659_DAC_CTRL:
663 case RT5659_STO1_ADC_DIG_VOL:
664 case RT5659_MONO_ADC_DIG_VOL:
665 case RT5659_STO2_ADC_DIG_VOL:
666 case RT5659_STO1_BOOST:
667 case RT5659_MONO_BOOST:
668 case RT5659_STO2_BOOST:
669 case RT5659_HP_IMP_GAIN_1:
670 case RT5659_HP_IMP_GAIN_2:
671 case RT5659_STO1_ADC_MIXER:
672 case RT5659_MONO_ADC_MIXER:
673 case RT5659_AD_DA_MIXER:
674 case RT5659_STO_DAC_MIXER:
675 case RT5659_MONO_DAC_MIXER:
676 case RT5659_DIG_MIXER:
677 case RT5659_A_DAC_MUX:
678 case RT5659_DIG_INF23_DATA:
679 case RT5659_PDM_OUT_CTRL:
680 case RT5659_PDM_DATA_CTRL_1:
681 case RT5659_PDM_DATA_CTRL_2:
682 case RT5659_PDM_DATA_CTRL_3:
683 case RT5659_PDM_DATA_CTRL_4:
684 case RT5659_SPDIF_CTRL:
685 case RT5659_REC1_GAIN:
686 case RT5659_REC1_L1_MIXER:
687 case RT5659_REC1_L2_MIXER:
688 case RT5659_REC1_R1_MIXER:
689 case RT5659_REC1_R2_MIXER:
690 case RT5659_CAL_REC:
691 case RT5659_REC2_L1_MIXER:
692 case RT5659_REC2_L2_MIXER:
693 case RT5659_REC2_R1_MIXER:
694 case RT5659_REC2_R2_MIXER:
695 case RT5659_SPK_L_MIXER:
696 case RT5659_SPK_R_MIXER:
697 case RT5659_SPO_AMP_GAIN:
698 case RT5659_ALC_BACK_GAIN:
699 case RT5659_MONOMIX_GAIN:
700 case RT5659_MONOMIX_IN_GAIN:
701 case RT5659_OUT_L_GAIN:
702 case RT5659_OUT_L_MIXER:
703 case RT5659_OUT_R_GAIN:
704 case RT5659_OUT_R_MIXER:
705 case RT5659_LOUT_MIXER:
706 case RT5659_HAPTIC_GEN_CTRL_1:
707 case RT5659_HAPTIC_GEN_CTRL_2:
708 case RT5659_HAPTIC_GEN_CTRL_3:
709 case RT5659_HAPTIC_GEN_CTRL_4:
710 case RT5659_HAPTIC_GEN_CTRL_5:
711 case RT5659_HAPTIC_GEN_CTRL_6:
712 case RT5659_HAPTIC_GEN_CTRL_7:
713 case RT5659_HAPTIC_GEN_CTRL_8:
714 case RT5659_HAPTIC_GEN_CTRL_9:
715 case RT5659_HAPTIC_GEN_CTRL_10:
716 case RT5659_HAPTIC_GEN_CTRL_11:
717 case RT5659_HAPTIC_LPF_CTRL_1:
718 case RT5659_HAPTIC_LPF_CTRL_2:
719 case RT5659_HAPTIC_LPF_CTRL_3:
720 case RT5659_PWR_DIG_1:
721 case RT5659_PWR_DIG_2:
722 case RT5659_PWR_ANLG_1:
723 case RT5659_PWR_ANLG_2:
724 case RT5659_PWR_ANLG_3:
725 case RT5659_PWR_MIXER:
726 case RT5659_PWR_VOL:
727 case RT5659_PRIV_INDEX:
728 case RT5659_CLK_DET:
729 case RT5659_PRIV_DATA:
730 case RT5659_PRE_DIV_1:
731 case RT5659_PRE_DIV_2:
732 case RT5659_I2S1_SDP:
733 case RT5659_I2S2_SDP:
734 case RT5659_I2S3_SDP:
735 case RT5659_ADDA_CLK_1:
736 case RT5659_ADDA_CLK_2:
737 case RT5659_DMIC_CTRL_1:
738 case RT5659_DMIC_CTRL_2:
739 case RT5659_TDM_CTRL_1:
740 case RT5659_TDM_CTRL_2:
741 case RT5659_TDM_CTRL_3:
742 case RT5659_TDM_CTRL_4:
743 case RT5659_TDM_CTRL_5:
744 case RT5659_GLB_CLK:
745 case RT5659_PLL_CTRL_1:
746 case RT5659_PLL_CTRL_2:
747 case RT5659_ASRC_1:
748 case RT5659_ASRC_2:
749 case RT5659_ASRC_3:
750 case RT5659_ASRC_4:
751 case RT5659_ASRC_5:
752 case RT5659_ASRC_6:
753 case RT5659_ASRC_7:
754 case RT5659_ASRC_8:
755 case RT5659_ASRC_9:
756 case RT5659_ASRC_10:
757 case RT5659_DEPOP_1:
758 case RT5659_DEPOP_2:
759 case RT5659_DEPOP_3:
760 case RT5659_HP_CHARGE_PUMP_1:
761 case RT5659_HP_CHARGE_PUMP_2:
762 case RT5659_MICBIAS_1:
763 case RT5659_MICBIAS_2:
764 case RT5659_ASRC_11:
765 case RT5659_ASRC_12:
766 case RT5659_ASRC_13:
767 case RT5659_REC_M1_M2_GAIN_CTRL:
768 case RT5659_RC_CLK_CTRL:
769 case RT5659_CLASSD_CTRL_1:
770 case RT5659_CLASSD_CTRL_2:
771 case RT5659_ADC_EQ_CTRL_1:
772 case RT5659_ADC_EQ_CTRL_2:
773 case RT5659_DAC_EQ_CTRL_1:
774 case RT5659_DAC_EQ_CTRL_2:
775 case RT5659_DAC_EQ_CTRL_3:
776 case RT5659_IRQ_CTRL_1:
777 case RT5659_IRQ_CTRL_2:
778 case RT5659_IRQ_CTRL_3:
779 case RT5659_IRQ_CTRL_4:
780 case RT5659_IRQ_CTRL_5:
781 case RT5659_IRQ_CTRL_6:
782 case RT5659_INT_ST_1:
783 case RT5659_INT_ST_2:
784 case RT5659_GPIO_CTRL_1:
785 case RT5659_GPIO_CTRL_2:
786 case RT5659_GPIO_CTRL_3:
787 case RT5659_GPIO_CTRL_4:
788 case RT5659_GPIO_CTRL_5:
789 case RT5659_GPIO_STA:
790 case RT5659_SINE_GEN_CTRL_1:
791 case RT5659_SINE_GEN_CTRL_2:
792 case RT5659_SINE_GEN_CTRL_3:
793 case RT5659_HP_AMP_DET_CTRL_1:
794 case RT5659_HP_AMP_DET_CTRL_2:
795 case RT5659_SV_ZCD_1:
796 case RT5659_SV_ZCD_2:
797 case RT5659_IL_CMD_1:
798 case RT5659_IL_CMD_2:
799 case RT5659_IL_CMD_3:
800 case RT5659_IL_CMD_4:
801 case RT5659_4BTN_IL_CMD_1:
802 case RT5659_4BTN_IL_CMD_2:
803 case RT5659_4BTN_IL_CMD_3:
804 case RT5659_PSV_IL_CMD_1:
805 case RT5659_PSV_IL_CMD_2:
806 case RT5659_ADC_STO1_HP_CTRL_1:
807 case RT5659_ADC_STO1_HP_CTRL_2:
808 case RT5659_ADC_MONO_HP_CTRL_1:
809 case RT5659_ADC_MONO_HP_CTRL_2:
810 case RT5659_AJD1_CTRL:
811 case RT5659_AJD2_AJD3_CTRL:
812 case RT5659_JD1_THD:
813 case RT5659_JD2_THD:
814 case RT5659_JD3_THD:
815 case RT5659_JD_CTRL_1:
816 case RT5659_JD_CTRL_2:
817 case RT5659_JD_CTRL_3:
818 case RT5659_JD_CTRL_4:
819 case RT5659_DIG_MISC:
820 case RT5659_DUMMY_2:
821 case RT5659_DUMMY_3:
822 case RT5659_VENDOR_ID:
823 case RT5659_VENDOR_ID_1:
824 case RT5659_DEVICE_ID:
825 case RT5659_DAC_ADC_DIG_VOL:
826 case RT5659_BIAS_CUR_CTRL_1:
827 case RT5659_BIAS_CUR_CTRL_2:
828 case RT5659_BIAS_CUR_CTRL_3:
829 case RT5659_BIAS_CUR_CTRL_4:
830 case RT5659_BIAS_CUR_CTRL_5:
831 case RT5659_BIAS_CUR_CTRL_6:
832 case RT5659_BIAS_CUR_CTRL_7:
833 case RT5659_BIAS_CUR_CTRL_8:
834 case RT5659_BIAS_CUR_CTRL_9:
835 case RT5659_BIAS_CUR_CTRL_10:
836 case RT5659_MEMORY_TEST:
837 case RT5659_VREF_REC_OP_FB_CAP_CTRL:
838 case RT5659_CLASSD_0:
839 case RT5659_CLASSD_1:
840 case RT5659_CLASSD_2:
841 case RT5659_CLASSD_3:
842 case RT5659_CLASSD_4:
843 case RT5659_CLASSD_5:
844 case RT5659_CLASSD_6:
845 case RT5659_CLASSD_7:
846 case RT5659_CLASSD_8:
847 case RT5659_CLASSD_9:
848 case RT5659_CLASSD_10:
849 case RT5659_CHARGE_PUMP_1:
850 case RT5659_CHARGE_PUMP_2:
851 case RT5659_DIG_IN_CTRL_1:
852 case RT5659_DIG_IN_CTRL_2:
853 case RT5659_PAD_DRIVING_CTRL:
854 case RT5659_SOFT_RAMP_DEPOP:
855 case RT5659_PLL:
856 case RT5659_CHOP_DAC:
857 case RT5659_CHOP_ADC:
858 case RT5659_CALIB_ADC_CTRL:
859 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
860 case RT5659_VOL_TEST:
861 case RT5659_TEST_MODE_CTRL_1:
862 case RT5659_TEST_MODE_CTRL_2:
863 case RT5659_TEST_MODE_CTRL_3:
864 case RT5659_TEST_MODE_CTRL_4:
865 case RT5659_BASSBACK_CTRL:
866 case RT5659_MP3_PLUS_CTRL_1:
867 case RT5659_MP3_PLUS_CTRL_2:
868 case RT5659_MP3_HPF_A1:
869 case RT5659_MP3_HPF_A2:
870 case RT5659_MP3_HPF_H0:
871 case RT5659_MP3_LPF_H0:
872 case RT5659_3D_SPK_CTRL:
873 case RT5659_3D_SPK_COEF_1:
874 case RT5659_3D_SPK_COEF_2:
875 case RT5659_3D_SPK_COEF_3:
876 case RT5659_3D_SPK_COEF_4:
877 case RT5659_3D_SPK_COEF_5:
878 case RT5659_3D_SPK_COEF_6:
879 case RT5659_3D_SPK_COEF_7:
880 case RT5659_STO_NG2_CTRL_1:
881 case RT5659_STO_NG2_CTRL_2:
882 case RT5659_STO_NG2_CTRL_3:
883 case RT5659_STO_NG2_CTRL_4:
884 case RT5659_STO_NG2_CTRL_5:
885 case RT5659_STO_NG2_CTRL_6:
886 case RT5659_STO_NG2_CTRL_7:
887 case RT5659_STO_NG2_CTRL_8:
888 case RT5659_MONO_NG2_CTRL_1:
889 case RT5659_MONO_NG2_CTRL_2:
890 case RT5659_MONO_NG2_CTRL_3:
891 case RT5659_MONO_NG2_CTRL_4:
892 case RT5659_MONO_NG2_CTRL_5:
893 case RT5659_MONO_NG2_CTRL_6:
894 case RT5659_MID_HP_AMP_DET:
895 case RT5659_LOW_HP_AMP_DET:
896 case RT5659_LDO_CTRL:
897 case RT5659_HP_DECROSS_CTRL_1:
898 case RT5659_HP_DECROSS_CTRL_2:
899 case RT5659_HP_DECROSS_CTRL_3:
900 case RT5659_HP_DECROSS_CTRL_4:
901 case RT5659_HP_IMP_SENS_CTRL_1:
902 case RT5659_HP_IMP_SENS_CTRL_2:
903 case RT5659_HP_IMP_SENS_CTRL_3:
904 case RT5659_HP_IMP_SENS_CTRL_4:
905 case RT5659_HP_IMP_SENS_MAP_1:
906 case RT5659_HP_IMP_SENS_MAP_2:
907 case RT5659_HP_IMP_SENS_MAP_3:
908 case RT5659_HP_IMP_SENS_MAP_4:
909 case RT5659_HP_IMP_SENS_MAP_5:
910 case RT5659_HP_IMP_SENS_MAP_6:
911 case RT5659_HP_IMP_SENS_MAP_7:
912 case RT5659_HP_IMP_SENS_MAP_8:
913 case RT5659_HP_LOGIC_CTRL_1:
914 case RT5659_HP_LOGIC_CTRL_2:
915 case RT5659_HP_CALIB_CTRL_1:
916 case RT5659_HP_CALIB_CTRL_2:
917 case RT5659_HP_CALIB_CTRL_3:
918 case RT5659_HP_CALIB_CTRL_4:
919 case RT5659_HP_CALIB_CTRL_5:
920 case RT5659_HP_CALIB_CTRL_6:
921 case RT5659_HP_CALIB_CTRL_7:
922 case RT5659_HP_CALIB_CTRL_9:
923 case RT5659_HP_CALIB_CTRL_10:
924 case RT5659_HP_CALIB_CTRL_11:
925 case RT5659_HP_CALIB_STA_1:
926 case RT5659_HP_CALIB_STA_2:
927 case RT5659_HP_CALIB_STA_3:
928 case RT5659_HP_CALIB_STA_4:
929 case RT5659_HP_CALIB_STA_5:
930 case RT5659_HP_CALIB_STA_6:
931 case RT5659_HP_CALIB_STA_7:
932 case RT5659_HP_CALIB_STA_8:
933 case RT5659_HP_CALIB_STA_9:
934 case RT5659_MONO_AMP_CALIB_CTRL_1:
935 case RT5659_MONO_AMP_CALIB_CTRL_2:
936 case RT5659_MONO_AMP_CALIB_CTRL_3:
937 case RT5659_MONO_AMP_CALIB_CTRL_4:
938 case RT5659_MONO_AMP_CALIB_CTRL_5:
939 case RT5659_MONO_AMP_CALIB_STA_1:
940 case RT5659_MONO_AMP_CALIB_STA_2:
941 case RT5659_MONO_AMP_CALIB_STA_3:
942 case RT5659_MONO_AMP_CALIB_STA_4:
943 case RT5659_SPK_PWR_LMT_CTRL_1:
944 case RT5659_SPK_PWR_LMT_CTRL_2:
945 case RT5659_SPK_PWR_LMT_CTRL_3:
946 case RT5659_SPK_PWR_LMT_STA_1:
947 case RT5659_SPK_PWR_LMT_STA_2:
948 case RT5659_SPK_PWR_LMT_STA_3:
949 case RT5659_SPK_PWR_LMT_STA_4:
950 case RT5659_SPK_PWR_LMT_STA_5:
951 case RT5659_SPK_PWR_LMT_STA_6:
952 case RT5659_FLEX_SPK_BST_CTRL_1:
953 case RT5659_FLEX_SPK_BST_CTRL_2:
954 case RT5659_FLEX_SPK_BST_CTRL_3:
955 case RT5659_FLEX_SPK_BST_CTRL_4:
956 case RT5659_SPK_EX_LMT_CTRL_1:
957 case RT5659_SPK_EX_LMT_CTRL_2:
958 case RT5659_SPK_EX_LMT_CTRL_3:
959 case RT5659_SPK_EX_LMT_CTRL_4:
960 case RT5659_SPK_EX_LMT_CTRL_5:
961 case RT5659_SPK_EX_LMT_CTRL_6:
962 case RT5659_SPK_EX_LMT_CTRL_7:
963 case RT5659_ADJ_HPF_CTRL_1:
964 case RT5659_ADJ_HPF_CTRL_2:
965 case RT5659_SPK_DC_CAILB_CTRL_1:
966 case RT5659_SPK_DC_CAILB_CTRL_2:
967 case RT5659_SPK_DC_CAILB_CTRL_3:
968 case RT5659_SPK_DC_CAILB_CTRL_4:
969 case RT5659_SPK_DC_CAILB_CTRL_5:
970 case RT5659_SPK_DC_CAILB_STA_1:
971 case RT5659_SPK_DC_CAILB_STA_2:
972 case RT5659_SPK_DC_CAILB_STA_3:
973 case RT5659_SPK_DC_CAILB_STA_4:
974 case RT5659_SPK_DC_CAILB_STA_5:
975 case RT5659_SPK_DC_CAILB_STA_6:
976 case RT5659_SPK_DC_CAILB_STA_7:
977 case RT5659_SPK_DC_CAILB_STA_8:
978 case RT5659_SPK_DC_CAILB_STA_9:
979 case RT5659_SPK_DC_CAILB_STA_10:
980 case RT5659_SPK_VDD_STA_1:
981 case RT5659_SPK_VDD_STA_2:
982 case RT5659_SPK_DC_DET_CTRL_1:
983 case RT5659_SPK_DC_DET_CTRL_2:
984 case RT5659_SPK_DC_DET_CTRL_3:
985 case RT5659_PURE_DC_DET_CTRL_1:
986 case RT5659_PURE_DC_DET_CTRL_2:
987 case RT5659_DUMMY_4:
988 case RT5659_DUMMY_5:
989 case RT5659_DUMMY_6:
990 case RT5659_DRC1_CTRL_1:
991 case RT5659_DRC1_CTRL_2:
992 case RT5659_DRC1_CTRL_3:
993 case RT5659_DRC1_CTRL_4:
994 case RT5659_DRC1_CTRL_5:
995 case RT5659_DRC1_CTRL_6:
996 case RT5659_DRC1_HARD_LMT_CTRL_1:
997 case RT5659_DRC1_HARD_LMT_CTRL_2:
998 case RT5659_DRC2_CTRL_1:
999 case RT5659_DRC2_CTRL_2:
1000 case RT5659_DRC2_CTRL_3:
1001 case RT5659_DRC2_CTRL_4:
1002 case RT5659_DRC2_CTRL_5:
1003 case RT5659_DRC2_CTRL_6:
1004 case RT5659_DRC2_HARD_LMT_CTRL_1:
1005 case RT5659_DRC2_HARD_LMT_CTRL_2:
1006 case RT5659_DRC1_PRIV_1:
1007 case RT5659_DRC1_PRIV_2:
1008 case RT5659_DRC1_PRIV_3:
1009 case RT5659_DRC1_PRIV_4:
1010 case RT5659_DRC1_PRIV_5:
1011 case RT5659_DRC1_PRIV_6:
1012 case RT5659_DRC1_PRIV_7:
1013 case RT5659_DRC2_PRIV_1:
1014 case RT5659_DRC2_PRIV_2:
1015 case RT5659_DRC2_PRIV_3:
1016 case RT5659_DRC2_PRIV_4:
1017 case RT5659_DRC2_PRIV_5:
1018 case RT5659_DRC2_PRIV_6:
1019 case RT5659_DRC2_PRIV_7:
1020 case RT5659_MULTI_DRC_CTRL:
1021 case RT5659_CROSS_OVER_1:
1022 case RT5659_CROSS_OVER_2:
1023 case RT5659_CROSS_OVER_3:
1024 case RT5659_CROSS_OVER_4:
1025 case RT5659_CROSS_OVER_5:
1026 case RT5659_CROSS_OVER_6:
1027 case RT5659_CROSS_OVER_7:
1028 case RT5659_CROSS_OVER_8:
1029 case RT5659_CROSS_OVER_9:
1030 case RT5659_CROSS_OVER_10:
1031 case RT5659_ALC_PGA_CTRL_1:
1032 case RT5659_ALC_PGA_CTRL_2:
1033 case RT5659_ALC_PGA_CTRL_3:
1034 case RT5659_ALC_PGA_CTRL_4:
1035 case RT5659_ALC_PGA_CTRL_5:
1036 case RT5659_ALC_PGA_CTRL_6:
1037 case RT5659_ALC_PGA_CTRL_7:
1038 case RT5659_ALC_PGA_CTRL_8:
1039 case RT5659_ALC_PGA_STA_1:
1040 case RT5659_ALC_PGA_STA_2:
1041 case RT5659_ALC_PGA_STA_3:
1042 case RT5659_DAC_L_EQ_PRE_VOL:
1043 case RT5659_DAC_R_EQ_PRE_VOL:
1044 case RT5659_DAC_L_EQ_POST_VOL:
1045 case RT5659_DAC_R_EQ_POST_VOL:
1046 case RT5659_DAC_L_EQ_LPF1_A1:
1047 case RT5659_DAC_L_EQ_LPF1_H0:
1048 case RT5659_DAC_R_EQ_LPF1_A1:
1049 case RT5659_DAC_R_EQ_LPF1_H0:
1050 case RT5659_DAC_L_EQ_BPF2_A1:
1051 case RT5659_DAC_L_EQ_BPF2_A2:
1052 case RT5659_DAC_L_EQ_BPF2_H0:
1053 case RT5659_DAC_R_EQ_BPF2_A1:
1054 case RT5659_DAC_R_EQ_BPF2_A2:
1055 case RT5659_DAC_R_EQ_BPF2_H0:
1056 case RT5659_DAC_L_EQ_BPF3_A1:
1057 case RT5659_DAC_L_EQ_BPF3_A2:
1058 case RT5659_DAC_L_EQ_BPF3_H0:
1059 case RT5659_DAC_R_EQ_BPF3_A1:
1060 case RT5659_DAC_R_EQ_BPF3_A2:
1061 case RT5659_DAC_R_EQ_BPF3_H0:
1062 case RT5659_DAC_L_EQ_BPF4_A1:
1063 case RT5659_DAC_L_EQ_BPF4_A2:
1064 case RT5659_DAC_L_EQ_BPF4_H0:
1065 case RT5659_DAC_R_EQ_BPF4_A1:
1066 case RT5659_DAC_R_EQ_BPF4_A2:
1067 case RT5659_DAC_R_EQ_BPF4_H0:
1068 case RT5659_DAC_L_EQ_HPF1_A1:
1069 case RT5659_DAC_L_EQ_HPF1_H0:
1070 case RT5659_DAC_R_EQ_HPF1_A1:
1071 case RT5659_DAC_R_EQ_HPF1_H0:
1072 case RT5659_DAC_L_EQ_HPF2_A1:
1073 case RT5659_DAC_L_EQ_HPF2_A2:
1074 case RT5659_DAC_L_EQ_HPF2_H0:
1075 case RT5659_DAC_R_EQ_HPF2_A1:
1076 case RT5659_DAC_R_EQ_HPF2_A2:
1077 case RT5659_DAC_R_EQ_HPF2_H0:
1078 case RT5659_DAC_L_BI_EQ_BPF1_H0_1:
1079 case RT5659_DAC_L_BI_EQ_BPF1_H0_2:
1080 case RT5659_DAC_L_BI_EQ_BPF1_B1_1:
1081 case RT5659_DAC_L_BI_EQ_BPF1_B1_2:
1082 case RT5659_DAC_L_BI_EQ_BPF1_B2_1:
1083 case RT5659_DAC_L_BI_EQ_BPF1_B2_2:
1084 case RT5659_DAC_L_BI_EQ_BPF1_A1_1:
1085 case RT5659_DAC_L_BI_EQ_BPF1_A1_2:
1086 case RT5659_DAC_L_BI_EQ_BPF1_A2_1:
1087 case RT5659_DAC_L_BI_EQ_BPF1_A2_2:
1088 case RT5659_DAC_R_BI_EQ_BPF1_H0_1:
1089 case RT5659_DAC_R_BI_EQ_BPF1_H0_2:
1090 case RT5659_DAC_R_BI_EQ_BPF1_B1_1:
1091 case RT5659_DAC_R_BI_EQ_BPF1_B1_2:
1092 case RT5659_DAC_R_BI_EQ_BPF1_B2_1:
1093 case RT5659_DAC_R_BI_EQ_BPF1_B2_2:
1094 case RT5659_DAC_R_BI_EQ_BPF1_A1_1:
1095 case RT5659_DAC_R_BI_EQ_BPF1_A1_2:
1096 case RT5659_DAC_R_BI_EQ_BPF1_A2_1:
1097 case RT5659_DAC_R_BI_EQ_BPF1_A2_2:
1098 case RT5659_ADC_L_EQ_LPF1_A1:
1099 case RT5659_ADC_R_EQ_LPF1_A1:
1100 case RT5659_ADC_L_EQ_LPF1_H0:
1101 case RT5659_ADC_R_EQ_LPF1_H0:
1102 case RT5659_ADC_L_EQ_BPF1_A1:
1103 case RT5659_ADC_R_EQ_BPF1_A1:
1104 case RT5659_ADC_L_EQ_BPF1_A2:
1105 case RT5659_ADC_R_EQ_BPF1_A2:
1106 case RT5659_ADC_L_EQ_BPF1_H0:
1107 case RT5659_ADC_R_EQ_BPF1_H0:
1108 case RT5659_ADC_L_EQ_BPF2_A1:
1109 case RT5659_ADC_R_EQ_BPF2_A1:
1110 case RT5659_ADC_L_EQ_BPF2_A2:
1111 case RT5659_ADC_R_EQ_BPF2_A2:
1112 case RT5659_ADC_L_EQ_BPF2_H0:
1113 case RT5659_ADC_R_EQ_BPF2_H0:
1114 case RT5659_ADC_L_EQ_BPF3_A1:
1115 case RT5659_ADC_R_EQ_BPF3_A1:
1116 case RT5659_ADC_L_EQ_BPF3_A2:
1117 case RT5659_ADC_R_EQ_BPF3_A2:
1118 case RT5659_ADC_L_EQ_BPF3_H0:
1119 case RT5659_ADC_R_EQ_BPF3_H0:
1120 case RT5659_ADC_L_EQ_BPF4_A1:
1121 case RT5659_ADC_R_EQ_BPF4_A1:
1122 case RT5659_ADC_L_EQ_BPF4_A2:
1123 case RT5659_ADC_R_EQ_BPF4_A2:
1124 case RT5659_ADC_L_EQ_BPF4_H0:
1125 case RT5659_ADC_R_EQ_BPF4_H0:
1126 case RT5659_ADC_L_EQ_HPF1_A1:
1127 case RT5659_ADC_R_EQ_HPF1_A1:
1128 case RT5659_ADC_L_EQ_HPF1_H0:
1129 case RT5659_ADC_R_EQ_HPF1_H0:
1130 case RT5659_ADC_L_EQ_PRE_VOL:
1131 case RT5659_ADC_R_EQ_PRE_VOL:
1132 case RT5659_ADC_L_EQ_POST_VOL:
1133 case RT5659_ADC_R_EQ_POST_VOL:
1134 return true;
1135 default:
1136 return false;
1137 }
1138}
1139
1140static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0);
1141static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
1142static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
1143static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
1144static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
1145static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1146static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
1147
1148/* Interface data select */
1149static const char * const rt5659_data_select[] = {
1150 "L/R", "R/L", "L/L", "R/R"
1151};
1152
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1153static SOC_ENUM_SINGLE_DECL(rt5659_if1_01_adc_enum,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1154 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT01_SFT, rt5659_data_select);
1155
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1156static SOC_ENUM_SINGLE_DECL(rt5659_if1_23_adc_enum,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1157 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT23_SFT, rt5659_data_select);
1158
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1159static SOC_ENUM_SINGLE_DECL(rt5659_if1_45_adc_enum,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1160 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT45_SFT, rt5659_data_select);
1161
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1162static SOC_ENUM_SINGLE_DECL(rt5659_if1_67_adc_enum,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1163 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT67_SFT, rt5659_data_select);
1164
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1165static SOC_ENUM_SINGLE_DECL(rt5659_if2_dac_enum,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1166 RT5659_DIG_INF23_DATA, RT5659_IF2_DAC_SEL_SFT, rt5659_data_select);
1167
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1168static SOC_ENUM_SINGLE_DECL(rt5659_if2_adc_enum,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1169 RT5659_DIG_INF23_DATA, RT5659_IF2_ADC_SEL_SFT, rt5659_data_select);
1170
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1171static SOC_ENUM_SINGLE_DECL(rt5659_if3_dac_enum,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1172 RT5659_DIG_INF23_DATA, RT5659_IF3_DAC_SEL_SFT, rt5659_data_select);
1173
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1174static SOC_ENUM_SINGLE_DECL(rt5659_if3_adc_enum,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1175 RT5659_DIG_INF23_DATA, RT5659_IF3_ADC_SEL_SFT, rt5659_data_select);
1176
1177static const struct snd_kcontrol_new rt5659_if1_01_adc_swap_mux =
1178 SOC_DAPM_ENUM("IF1 01 ADC Swap Source", rt5659_if1_01_adc_enum);
1179
1180static const struct snd_kcontrol_new rt5659_if1_23_adc_swap_mux =
1181 SOC_DAPM_ENUM("IF1 23 ADC1 Swap Source", rt5659_if1_23_adc_enum);
1182
1183static const struct snd_kcontrol_new rt5659_if1_45_adc_swap_mux =
1184 SOC_DAPM_ENUM("IF1 45 ADC1 Swap Source", rt5659_if1_45_adc_enum);
1185
1186static const struct snd_kcontrol_new rt5659_if1_67_adc_swap_mux =
1187 SOC_DAPM_ENUM("IF1 67 ADC1 Swap Source", rt5659_if1_67_adc_enum);
1188
1189static const struct snd_kcontrol_new rt5659_if2_dac_swap_mux =
1190 SOC_DAPM_ENUM("IF2 DAC Swap Source", rt5659_if2_dac_enum);
1191
1192static const struct snd_kcontrol_new rt5659_if2_adc_swap_mux =
1193 SOC_DAPM_ENUM("IF2 ADC Swap Source", rt5659_if2_adc_enum);
1194
1195static const struct snd_kcontrol_new rt5659_if3_dac_swap_mux =
1196 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5659_if3_dac_enum);
1197
1198static const struct snd_kcontrol_new rt5659_if3_adc_swap_mux =
1199 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5659_if3_adc_enum);
1200
1201static const char * const rt5659_asrc_clk_src[] = {
1202 "clk_sysy_div_out", "clk_i2s1_track", "clk_i2s2_track",
1203 "clk_i2s3_track", "clk_sys2", "clk_sys3"
1204};
1205
1206static unsigned int rt5659_asrc_clk_map_values[] = {
1207 0, 1, 2, 3, 5, 6,
1208};
1209
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1210static SOC_VALUE_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1211 rt5659_da_sto_asrc_enum, RT5659_ASRC_2, RT5659_DA_STO_T_SFT, 0x7,
1212 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1213
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1214static SOC_VALUE_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1215 rt5659_da_monol_asrc_enum, RT5659_ASRC_2, RT5659_DA_MONO_L_T_SFT, 0x7,
1216 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1217
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1218static SOC_VALUE_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1219 rt5659_da_monor_asrc_enum, RT5659_ASRC_2, RT5659_DA_MONO_R_T_SFT, 0x7,
1220 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1221
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1222static SOC_VALUE_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1223 rt5659_ad_sto1_asrc_enum, RT5659_ASRC_2, RT5659_AD_STO1_T_SFT, 0x7,
1224 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1225
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1226static SOC_VALUE_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1227 rt5659_ad_sto2_asrc_enum, RT5659_ASRC_3, RT5659_AD_STO2_T_SFT, 0x7,
1228 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1229
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1230static SOC_VALUE_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1231 rt5659_ad_monol_asrc_enum, RT5659_ASRC_3, RT5659_AD_MONO_L_T_SFT, 0x7,
1232 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1233
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1234static SOC_VALUE_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1235 rt5659_ad_monor_asrc_enum, RT5659_ASRC_3, RT5659_AD_MONO_R_T_SFT, 0x7,
1236 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1237
1238static int rt5659_hp_vol_put(struct snd_kcontrol *kcontrol,
1239 struct snd_ctl_elem_value *ucontrol)
1240{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1241 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1242 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1243
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1244 if (snd_soc_component_read32(component, RT5659_STO_NG2_CTRL_1) & RT5659_NG2_EN) {
1245 snd_soc_component_update_bits(component, RT5659_STO_NG2_CTRL_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1246 RT5659_NG2_EN_MASK, RT5659_NG2_DIS);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1247 snd_soc_component_update_bits(component, RT5659_STO_NG2_CTRL_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1248 RT5659_NG2_EN_MASK, RT5659_NG2_EN);
1249 }
1250
1251 return ret;
1252}
1253
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1254static void rt5659_enable_push_button_irq(struct snd_soc_component *component,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1255 bool enable)
1256{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1257 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1258
1259 if (enable) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1260 snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, 0x000b);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1261
1262 /* MICBIAS1 and Mic Det Power for button detect*/
1263 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1264 snd_soc_dapm_force_enable_pin(dapm,
1265 "Mic Det Power");
1266 snd_soc_dapm_sync(dapm);
1267
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1268 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_2,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1269 RT5659_PWR_MB1, RT5659_PWR_MB1);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1270 snd_soc_component_update_bits(component, RT5659_PWR_VOL,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1271 RT5659_PWR_MIC_DET, RT5659_PWR_MIC_DET);
1272
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1273 snd_soc_component_update_bits(component, RT5659_IRQ_CTRL_2,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1274 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1275 snd_soc_component_update_bits(component, RT5659_4BTN_IL_CMD_2,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1276 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN);
1277 } else {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1278 snd_soc_component_update_bits(component, RT5659_4BTN_IL_CMD_2,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1279 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_DIS);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1280 snd_soc_component_update_bits(component, RT5659_IRQ_CTRL_2,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1281 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_DIS);
1282 /* MICBIAS1 and Mic Det Power for button detect*/
1283 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1284 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1285 snd_soc_dapm_sync(dapm);
1286 }
1287}
1288
1289/**
1290 * rt5659_headset_detect - Detect headset.
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1291 * @component: SoC audio component device.
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1292 * @jack_insert: Jack insert or not.
1293 *
1294 * Detect whether is headset or not when jack inserted.
1295 *
1296 * Returns detect status.
1297 */
1298
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1299static int rt5659_headset_detect(struct snd_soc_component *component, int jack_insert)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1300{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1301 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1302 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1303 int reg_63;
1304
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1305 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1306
1307 if (jack_insert) {
1308 snd_soc_dapm_force_enable_pin(dapm,
1309 "Mic Det Power");
1310 snd_soc_dapm_sync(dapm);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1311 reg_63 = snd_soc_component_read32(component, RT5659_PWR_ANLG_1);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1312
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1313 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1314 RT5659_PWR_VREF2 | RT5659_PWR_MB,
1315 RT5659_PWR_VREF2 | RT5659_PWR_MB);
1316 msleep(20);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1317 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1318 RT5659_PWR_FV2, RT5659_PWR_FV2);
1319
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1320 snd_soc_component_write(component, RT5659_EJD_CTRL_2, 0x4160);
1321 snd_soc_component_update_bits(component, RT5659_EJD_CTRL_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1322 0x20, 0x0);
1323 msleep(20);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1324 snd_soc_component_update_bits(component, RT5659_EJD_CTRL_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1325 0x20, 0x20);
1326
1327 while (i < 5) {
1328 msleep(sleep_time[i]);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1329 val = snd_soc_component_read32(component, RT5659_EJD_CTRL_2) & 0x0003;
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1330 i++;
1331 if (val == 0x1 || val == 0x2 || val == 0x3)
1332 break;
1333 }
1334
1335 switch (val) {
1336 case 1:
1337 rt5659->jack_type = SND_JACK_HEADSET;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1338 rt5659_enable_push_button_irq(component, true);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1339 break;
1340 default:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1341 snd_soc_component_write(component, RT5659_PWR_ANLG_1, reg_63);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1342 rt5659->jack_type = SND_JACK_HEADPHONE;
1343 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1344 snd_soc_dapm_sync(dapm);
1345 break;
1346 }
1347 } else {
1348 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1349 snd_soc_dapm_sync(dapm);
1350 if (rt5659->jack_type == SND_JACK_HEADSET)
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1351 rt5659_enable_push_button_irq(component, false);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1352 rt5659->jack_type = 0;
1353 }
1354
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1355 dev_dbg(component->dev, "jack_type = %d\n", rt5659->jack_type);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1356 return rt5659->jack_type;
1357}
1358
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1359static int rt5659_button_detect(struct snd_soc_component *component)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1360{
1361 int btn_type, val;
1362
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1363 val = snd_soc_component_read32(component, RT5659_4BTN_IL_CMD_1);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1364 btn_type = val & 0xfff0;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1365 snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, val);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1366
1367 return btn_type;
1368}
1369
1370static irqreturn_t rt5659_irq(int irq, void *data)
1371{
1372 struct rt5659_priv *rt5659 = data;
1373
1374 queue_delayed_work(system_power_efficient_wq,
1375 &rt5659->jack_detect_work, msecs_to_jiffies(250));
1376
1377 return IRQ_HANDLED;
1378}
1379
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1380int rt5659_set_jack_detect(struct snd_soc_component *component,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1381 struct snd_soc_jack *hs_jack)
1382{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1383 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1384
1385 rt5659->hs_jack = hs_jack;
1386
1387 rt5659_irq(0, rt5659);
1388
1389 return 0;
1390}
1391EXPORT_SYMBOL_GPL(rt5659_set_jack_detect);
1392
1393static void rt5659_jack_detect_work(struct work_struct *work)
1394{
1395 struct rt5659_priv *rt5659 =
1396 container_of(work, struct rt5659_priv, jack_detect_work.work);
1397 int val, btn_type, report = 0;
1398
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1399 if (!rt5659->component)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1400 return;
1401
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1402 val = snd_soc_component_read32(rt5659->component, RT5659_INT_ST_1) & 0x0080;
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1403 if (!val) {
1404 /* jack in */
1405 if (rt5659->jack_type == 0) {
1406 /* jack was out, report jack type */
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1407 report = rt5659_headset_detect(rt5659->component, 1);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1408 } else {
1409 /* jack is already in, report button event */
1410 report = SND_JACK_HEADSET;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1411 btn_type = rt5659_button_detect(rt5659->component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1412 /**
1413 * rt5659 can report three kinds of button behavior,
1414 * one click, double click and hold. However,
1415 * currently we will report button pressed/released
1416 * event. So all the three button behaviors are
1417 * treated as button pressed.
1418 */
1419 switch (btn_type) {
1420 case 0x8000:
1421 case 0x4000:
1422 case 0x2000:
1423 report |= SND_JACK_BTN_0;
1424 break;
1425 case 0x1000:
1426 case 0x0800:
1427 case 0x0400:
1428 report |= SND_JACK_BTN_1;
1429 break;
1430 case 0x0200:
1431 case 0x0100:
1432 case 0x0080:
1433 report |= SND_JACK_BTN_2;
1434 break;
1435 case 0x0040:
1436 case 0x0020:
1437 case 0x0010:
1438 report |= SND_JACK_BTN_3;
1439 break;
1440 case 0x0000: /* unpressed */
1441 break;
1442 default:
1443 btn_type = 0;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1444 dev_err(rt5659->component->dev,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1445 "Unexpected button code 0x%04x\n",
1446 btn_type);
1447 break;
1448 }
1449
1450 /* button release or spurious interrput*/
1451 if (btn_type == 0)
1452 report = rt5659->jack_type;
1453 }
1454 } else {
1455 /* jack out */
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1456 report = rt5659_headset_detect(rt5659->component, 0);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1457 }
1458
1459 snd_soc_jack_report(rt5659->hs_jack, report, SND_JACK_HEADSET |
1460 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1461 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1462}
1463
oder_chiou@realtek.com041e74b2018-02-05 18:29:56 +0800[diff] [blame]1464static void rt5659_jack_detect_intel_hd_header(struct work_struct *work)
1465{
1466 struct rt5659_priv *rt5659 =
1467 container_of(work, struct rt5659_priv, jack_detect_work.work);
1468 unsigned int value;
1469 bool hp_flag, mic_flag;
1470
1471 if (!rt5659->hs_jack)
1472 return;
1473
1474 /* headphone jack */
1475 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value);
1476 hp_flag = (!(value & 0x8)) ? true : false;
1477
1478 if (hp_flag != rt5659->hda_hp_plugged) {
1479 rt5659->hda_hp_plugged = hp_flag;
1480
1481 if (hp_flag) {
1482 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
1483 0x10, 0x0);
1484 rt5659->jack_type |= SND_JACK_HEADPHONE;
1485 } else {
1486 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
1487 0x10, 0x10);
1488 rt5659->jack_type = rt5659->jack_type &
1489 (~SND_JACK_HEADPHONE);
1490 }
1491
1492 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type,
1493 SND_JACK_HEADPHONE);
1494 }
1495
1496 /* mic jack */
1497 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
1498 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value);
1499 mic_flag = (value & 0x2000) ? true : false;
1500
1501 if (mic_flag != rt5659->hda_mic_plugged) {
1502 rt5659->hda_mic_plugged = mic_flag;
1503 if (mic_flag) {
1504 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
1505 0x2, 0x2);
1506 rt5659->jack_type |= SND_JACK_MICROPHONE;
1507 } else {
1508 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
1509 0x2, 0x0);
1510 rt5659->jack_type = rt5659->jack_type
1511 & (~SND_JACK_MICROPHONE);
1512 }
1513
1514 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type,
1515 SND_JACK_MICROPHONE);
1516 }
1517}
1518
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1519static const struct snd_kcontrol_new rt5659_snd_controls[] = {
1520 /* Speaker Output Volume */
1521 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5659_SPO_VOL,
1522 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
1523
1524 /* Headphone Output Volume */
1525 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5659_HPL_GAIN,
1526 RT5659_HPR_GAIN, RT5659_G_HP_SFT, 31, 1, snd_soc_get_volsw,
1527 rt5659_hp_vol_put, hp_vol_tlv),
1528
1529 /* Mono Output Volume */
1530 SOC_SINGLE_TLV("Mono Playback Volume", RT5659_MONO_OUT,
1531 RT5659_L_VOL_SFT, 39, 1, out_vol_tlv),
1532
1533 /* Output Volume */
1534 SOC_DOUBLE_TLV("OUT Playback Volume", RT5659_LOUT,
1535 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
1536
1537 /* DAC Digital Volume */
1538 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5659_DAC1_DIG_VOL,
1539 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
1540 SOC_DOUBLE("DAC1 Playback Switch", RT5659_AD_DA_MIXER,
1541 RT5659_M_DAC1_L_SFT, RT5659_M_DAC1_R_SFT, 1, 1),
1542
1543 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5659_DAC2_DIG_VOL,
1544 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
1545 SOC_DOUBLE("DAC2 Playback Switch", RT5659_DAC_CTRL,
1546 RT5659_M_DAC2_L_VOL_SFT, RT5659_M_DAC2_R_VOL_SFT, 1, 1),
1547
1548 /* IN1/IN2/IN3/IN4 Volume */
1549 SOC_SINGLE_TLV("IN1 Boost Volume", RT5659_IN1_IN2,
1550 RT5659_BST1_SFT, 69, 0, in_bst_tlv),
1551 SOC_SINGLE_TLV("IN2 Boost Volume", RT5659_IN1_IN2,
1552 RT5659_BST2_SFT, 69, 0, in_bst_tlv),
1553 SOC_SINGLE_TLV("IN3 Boost Volume", RT5659_IN3_IN4,
1554 RT5659_BST3_SFT, 69, 0, in_bst_tlv),
1555 SOC_SINGLE_TLV("IN4 Boost Volume", RT5659_IN3_IN4,
1556 RT5659_BST4_SFT, 69, 0, in_bst_tlv),
1557
1558 /* INL/INR Volume Control */
1559 SOC_DOUBLE_TLV("IN Capture Volume", RT5659_INL1_INR1_VOL,
1560 RT5659_INL_VOL_SFT, RT5659_INR_VOL_SFT, 31, 1, in_vol_tlv),
1561
1562 /* ADC Digital Volume Control */
1563 SOC_DOUBLE("STO1 ADC Capture Switch", RT5659_STO1_ADC_DIG_VOL,
1564 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1565 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5659_STO1_ADC_DIG_VOL,
1566 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1567 SOC_DOUBLE("Mono ADC Capture Switch", RT5659_MONO_ADC_DIG_VOL,
1568 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1569 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5659_MONO_ADC_DIG_VOL,
1570 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1571 SOC_DOUBLE("STO2 ADC Capture Switch", RT5659_STO2_ADC_DIG_VOL,
1572 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1573 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5659_STO2_ADC_DIG_VOL,
1574 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1575
1576 /* ADC Boost Volume Control */
1577 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5659_STO1_BOOST,
1578 RT5659_STO1_ADC_L_BST_SFT, RT5659_STO1_ADC_R_BST_SFT,
1579 3, 0, adc_bst_tlv),
1580
1581 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5659_MONO_BOOST,
1582 RT5659_MONO_ADC_L_BST_SFT, RT5659_MONO_ADC_R_BST_SFT,
1583 3, 0, adc_bst_tlv),
1584
1585 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5659_STO2_BOOST,
1586 RT5659_STO2_ADC_L_BST_SFT, RT5659_STO2_ADC_R_BST_SFT,
1587 3, 0, adc_bst_tlv),
1588
1589 SOC_SINGLE("DAC IF1 DAC1 L Data Switch", RT5659_TDM_CTRL_4, 12, 7, 0),
1590 SOC_SINGLE("DAC IF1 DAC1 R Data Switch", RT5659_TDM_CTRL_4, 8, 7, 0),
1591 SOC_SINGLE("DAC IF1 DAC2 L Data Switch", RT5659_TDM_CTRL_4, 4, 7, 0),
1592 SOC_SINGLE("DAC IF1 DAC2 R Data Switch", RT5659_TDM_CTRL_4, 0, 7, 0),
1593};
1594
1595/**
1596 * set_dmic_clk - Set parameter of dmic.
1597 *
1598 * @w: DAPM widget.
1599 * @kcontrol: The kcontrol of this widget.
1600 * @event: Event id.
1601 *
1602 * Choose dmic clock between 1MHz and 3MHz.
1603 * It is better for clock to approximate 3MHz.
1604 */
1605static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1606 struct snd_kcontrol *kcontrol, int event)
1607{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1608 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1609 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1610 int pd, idx = -EINVAL;
1611
1612 pd = rl6231_get_pre_div(rt5659->regmap,
1613 RT5659_ADDA_CLK_1, RT5659_I2S_PD1_SFT);
1614 idx = rl6231_calc_dmic_clk(rt5659->sysclk / pd);
1615
1616 if (idx < 0)
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1617 dev_err(component->dev, "Failed to set DMIC clock\n");
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1618 else {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1619 snd_soc_component_update_bits(component, RT5659_DMIC_CTRL_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1620 RT5659_DMIC_CLK_MASK, idx << RT5659_DMIC_CLK_SFT);
1621 }
1622 return idx;
1623}
1624
1625static int set_adc_clk(struct snd_soc_dapm_widget *w,
1626 struct snd_kcontrol *kcontrol, int event)
1627{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1628 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1629
1630 switch (event) {
1631 case SND_SOC_DAPM_POST_PMU:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1632 snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1633 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK,
1634 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK);
1635 break;
1636
1637 case SND_SOC_DAPM_PRE_PMD:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1638 snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1639 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK, 0);
1640 break;
1641
1642 default:
1643 return 0;
1644 }
1645
1646 return 0;
1647
1648}
1649
1650static int rt5659_charge_pump_event(struct snd_soc_dapm_widget *w,
1651 struct snd_kcontrol *kcontrol, int event)
1652{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1653 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1654
1655 switch (event) {
1656 case SND_SOC_DAPM_PRE_PMU:
1657 /* Depop */
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1658 snd_soc_component_write(component, RT5659_DEPOP_1, 0x0009);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1659 break;
1660 case SND_SOC_DAPM_POST_PMD:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1661 snd_soc_component_write(component, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1662 break;
1663 default:
1664 return 0;
1665 }
1666
1667 return 0;
1668}
1669
1670static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1671 struct snd_soc_dapm_widget *sink)
1672{
1673 unsigned int val;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1674 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1675
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1676 val = snd_soc_component_read32(component, RT5659_GLB_CLK);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1677 val &= RT5659_SCLK_SRC_MASK;
1678 if (val == RT5659_SCLK_SRC_PLL1)
1679 return 1;
1680 else
1681 return 0;
1682}
1683
1684static int is_using_asrc(struct snd_soc_dapm_widget *w,
1685 struct snd_soc_dapm_widget *sink)
1686{
1687 unsigned int reg, shift, val;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1688 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1689
1690 switch (w->shift) {
1691 case RT5659_ADC_MONO_R_ASRC_SFT:
1692 reg = RT5659_ASRC_3;
1693 shift = RT5659_AD_MONO_R_T_SFT;
1694 break;
1695 case RT5659_ADC_MONO_L_ASRC_SFT:
1696 reg = RT5659_ASRC_3;
1697 shift = RT5659_AD_MONO_L_T_SFT;
1698 break;
1699 case RT5659_ADC_STO1_ASRC_SFT:
1700 reg = RT5659_ASRC_2;
1701 shift = RT5659_AD_STO1_T_SFT;
1702 break;
1703 case RT5659_DAC_MONO_R_ASRC_SFT:
1704 reg = RT5659_ASRC_2;
1705 shift = RT5659_DA_MONO_R_T_SFT;
1706 break;
1707 case RT5659_DAC_MONO_L_ASRC_SFT:
1708 reg = RT5659_ASRC_2;
1709 shift = RT5659_DA_MONO_L_T_SFT;
1710 break;
1711 case RT5659_DAC_STO_ASRC_SFT:
1712 reg = RT5659_ASRC_2;
1713 shift = RT5659_DA_STO_T_SFT;
1714 break;
1715 default:
1716 return 0;
1717 }
1718
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1719 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1720 switch (val) {
1721 case 1:
1722 case 2:
1723 case 3:
1724 /* I2S_Pre_Div1 should be 1 in asrc mode */
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]1725 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1726 RT5659_I2S_PD1_MASK, RT5659_I2S_PD1_2);
1727 return 1;
1728 default:
1729 return 0;
1730 }
1731
1732}
1733
1734/* Digital Mixer */
1735static const struct snd_kcontrol_new rt5659_sto1_adc_l_mix[] = {
1736 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
1737 RT5659_M_STO1_ADC_L1_SFT, 1, 1),
1738 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
1739 RT5659_M_STO1_ADC_L2_SFT, 1, 1),
1740};
1741
1742static const struct snd_kcontrol_new rt5659_sto1_adc_r_mix[] = {
1743 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
1744 RT5659_M_STO1_ADC_R1_SFT, 1, 1),
1745 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
1746 RT5659_M_STO1_ADC_R2_SFT, 1, 1),
1747};
1748
1749static const struct snd_kcontrol_new rt5659_mono_adc_l_mix[] = {
1750 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
1751 RT5659_M_MONO_ADC_L1_SFT, 1, 1),
1752 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
1753 RT5659_M_MONO_ADC_L2_SFT, 1, 1),
1754};
1755
1756static const struct snd_kcontrol_new rt5659_mono_adc_r_mix[] = {
1757 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
1758 RT5659_M_MONO_ADC_R1_SFT, 1, 1),
1759 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
1760 RT5659_M_MONO_ADC_R2_SFT, 1, 1),
1761};
1762
1763static const struct snd_kcontrol_new rt5659_dac_l_mix[] = {
1764 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1765 RT5659_M_ADCMIX_L_SFT, 1, 1),
1766 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
1767 RT5659_M_DAC1_L_SFT, 1, 1),
1768};
1769
1770static const struct snd_kcontrol_new rt5659_dac_r_mix[] = {
1771 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1772 RT5659_M_ADCMIX_R_SFT, 1, 1),
1773 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
1774 RT5659_M_DAC1_R_SFT, 1, 1),
1775};
1776
1777static const struct snd_kcontrol_new rt5659_sto_dac_l_mix[] = {
1778 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
1779 RT5659_M_DAC_L1_STO_L_SFT, 1, 1),
1780 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
1781 RT5659_M_DAC_R1_STO_L_SFT, 1, 1),
1782 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
1783 RT5659_M_DAC_L2_STO_L_SFT, 1, 1),
1784 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
1785 RT5659_M_DAC_R2_STO_L_SFT, 1, 1),
1786};
1787
1788static const struct snd_kcontrol_new rt5659_sto_dac_r_mix[] = {
1789 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
1790 RT5659_M_DAC_L1_STO_R_SFT, 1, 1),
1791 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
1792 RT5659_M_DAC_R1_STO_R_SFT, 1, 1),
1793 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
1794 RT5659_M_DAC_L2_STO_R_SFT, 1, 1),
1795 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
1796 RT5659_M_DAC_R2_STO_R_SFT, 1, 1),
1797};
1798
1799static const struct snd_kcontrol_new rt5659_mono_dac_l_mix[] = {
1800 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
1801 RT5659_M_DAC_L1_MONO_L_SFT, 1, 1),
1802 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
1803 RT5659_M_DAC_R1_MONO_L_SFT, 1, 1),
1804 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
1805 RT5659_M_DAC_L2_MONO_L_SFT, 1, 1),
1806 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
1807 RT5659_M_DAC_R2_MONO_L_SFT, 1, 1),
1808};
1809
1810static const struct snd_kcontrol_new rt5659_mono_dac_r_mix[] = {
1811 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
1812 RT5659_M_DAC_L1_MONO_R_SFT, 1, 1),
1813 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
1814 RT5659_M_DAC_R1_MONO_R_SFT, 1, 1),
1815 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
1816 RT5659_M_DAC_L2_MONO_R_SFT, 1, 1),
1817 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
1818 RT5659_M_DAC_R2_MONO_R_SFT, 1, 1),
1819};
1820
1821/* Analog Input Mixer */
1822static const struct snd_kcontrol_new rt5659_rec1_l_mix[] = {
1823 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC1_L2_MIXER,
1824 RT5659_M_SPKVOLL_RM1_L_SFT, 1, 1),
1825 SOC_DAPM_SINGLE("INL Switch", RT5659_REC1_L2_MIXER,
1826 RT5659_M_INL_RM1_L_SFT, 1, 1),
1827 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_L2_MIXER,
1828 RT5659_M_BST4_RM1_L_SFT, 1, 1),
1829 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_L2_MIXER,
1830 RT5659_M_BST3_RM1_L_SFT, 1, 1),
1831 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_L2_MIXER,
1832 RT5659_M_BST2_RM1_L_SFT, 1, 1),
1833 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_L2_MIXER,
1834 RT5659_M_BST1_RM1_L_SFT, 1, 1),
1835};
1836
1837static const struct snd_kcontrol_new rt5659_rec1_r_mix[] = {
1838 SOC_DAPM_SINGLE("HPOVOLR Switch", RT5659_REC1_L2_MIXER,
1839 RT5659_M_HPOVOLR_RM1_R_SFT, 1, 1),
1840 SOC_DAPM_SINGLE("INR Switch", RT5659_REC1_R2_MIXER,
1841 RT5659_M_INR_RM1_R_SFT, 1, 1),
1842 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_R2_MIXER,
1843 RT5659_M_BST4_RM1_R_SFT, 1, 1),
1844 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_R2_MIXER,
1845 RT5659_M_BST3_RM1_R_SFT, 1, 1),
1846 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_R2_MIXER,
1847 RT5659_M_BST2_RM1_R_SFT, 1, 1),
1848 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_R2_MIXER,
1849 RT5659_M_BST1_RM1_R_SFT, 1, 1),
1850};
1851
1852static const struct snd_kcontrol_new rt5659_rec2_l_mix[] = {
1853 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC2_L2_MIXER,
1854 RT5659_M_SPKVOL_RM2_L_SFT, 1, 1),
1855 SOC_DAPM_SINGLE("OUTVOLL Switch", RT5659_REC2_L2_MIXER,
1856 RT5659_M_OUTVOLL_RM2_L_SFT, 1, 1),
1857 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_L2_MIXER,
1858 RT5659_M_BST4_RM2_L_SFT, 1, 1),
1859 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_L2_MIXER,
1860 RT5659_M_BST3_RM2_L_SFT, 1, 1),
1861 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_L2_MIXER,
1862 RT5659_M_BST2_RM2_L_SFT, 1, 1),
1863 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_L2_MIXER,
1864 RT5659_M_BST1_RM2_L_SFT, 1, 1),
1865};
1866
1867static const struct snd_kcontrol_new rt5659_rec2_r_mix[] = {
1868 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_REC2_R2_MIXER,
1869 RT5659_M_MONOVOL_RM2_R_SFT, 1, 1),
1870 SOC_DAPM_SINGLE("OUTVOLR Switch", RT5659_REC2_R2_MIXER,
1871 RT5659_M_OUTVOLR_RM2_R_SFT, 1, 1),
1872 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_R2_MIXER,
1873 RT5659_M_BST4_RM2_R_SFT, 1, 1),
1874 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_R2_MIXER,
1875 RT5659_M_BST3_RM2_R_SFT, 1, 1),
1876 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_R2_MIXER,
1877 RT5659_M_BST2_RM2_R_SFT, 1, 1),
1878 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_R2_MIXER,
1879 RT5659_M_BST1_RM2_R_SFT, 1, 1),
1880};
1881
1882static const struct snd_kcontrol_new rt5659_spk_l_mix[] = {
1883 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPK_L_MIXER,
1884 RT5659_M_DAC_L2_SM_L_SFT, 1, 1),
1885 SOC_DAPM_SINGLE("BST1 Switch", RT5659_SPK_L_MIXER,
1886 RT5659_M_BST1_SM_L_SFT, 1, 1),
1887 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_L_MIXER,
1888 RT5659_M_IN_L_SM_L_SFT, 1, 1),
1889 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_L_MIXER,
1890 RT5659_M_IN_R_SM_L_SFT, 1, 1),
1891 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_L_MIXER,
1892 RT5659_M_BST3_SM_L_SFT, 1, 1),
1893};
1894
1895static const struct snd_kcontrol_new rt5659_spk_r_mix[] = {
1896 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPK_R_MIXER,
1897 RT5659_M_DAC_R2_SM_R_SFT, 1, 1),
1898 SOC_DAPM_SINGLE("BST4 Switch", RT5659_SPK_R_MIXER,
1899 RT5659_M_BST4_SM_R_SFT, 1, 1),
1900 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_R_MIXER,
1901 RT5659_M_IN_L_SM_R_SFT, 1, 1),
1902 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_R_MIXER,
1903 RT5659_M_IN_R_SM_R_SFT, 1, 1),
1904 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_R_MIXER,
1905 RT5659_M_BST3_SM_R_SFT, 1, 1),
1906};
1907
1908static const struct snd_kcontrol_new rt5659_monovol_mix[] = {
1909 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
1910 RT5659_M_DAC_L2_MM_SFT, 1, 1),
1911 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONOMIX_IN_GAIN,
1912 RT5659_M_DAC_R2_MM_SFT, 1, 1),
1913 SOC_DAPM_SINGLE("BST1 Switch", RT5659_MONOMIX_IN_GAIN,
1914 RT5659_M_BST1_MM_SFT, 1, 1),
1915 SOC_DAPM_SINGLE("BST2 Switch", RT5659_MONOMIX_IN_GAIN,
1916 RT5659_M_BST2_MM_SFT, 1, 1),
1917 SOC_DAPM_SINGLE("BST3 Switch", RT5659_MONOMIX_IN_GAIN,
1918 RT5659_M_BST3_MM_SFT, 1, 1),
1919};
1920
1921static const struct snd_kcontrol_new rt5659_out_l_mix[] = {
1922 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_OUT_L_MIXER,
1923 RT5659_M_DAC_L2_OM_L_SFT, 1, 1),
1924 SOC_DAPM_SINGLE("INL Switch", RT5659_OUT_L_MIXER,
1925 RT5659_M_IN_L_OM_L_SFT, 1, 1),
1926 SOC_DAPM_SINGLE("BST1 Switch", RT5659_OUT_L_MIXER,
1927 RT5659_M_BST1_OM_L_SFT, 1, 1),
1928 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_L_MIXER,
1929 RT5659_M_BST2_OM_L_SFT, 1, 1),
1930 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_L_MIXER,
1931 RT5659_M_BST3_OM_L_SFT, 1, 1),
1932};
1933
1934static const struct snd_kcontrol_new rt5659_out_r_mix[] = {
1935 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_OUT_R_MIXER,
1936 RT5659_M_DAC_R2_OM_R_SFT, 1, 1),
1937 SOC_DAPM_SINGLE("INR Switch", RT5659_OUT_R_MIXER,
1938 RT5659_M_IN_R_OM_R_SFT, 1, 1),
1939 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_R_MIXER,
1940 RT5659_M_BST2_OM_R_SFT, 1, 1),
1941 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_R_MIXER,
1942 RT5659_M_BST3_OM_R_SFT, 1, 1),
1943 SOC_DAPM_SINGLE("BST4 Switch", RT5659_OUT_R_MIXER,
1944 RT5659_M_BST4_OM_R_SFT, 1, 1),
1945};
1946
1947static const struct snd_kcontrol_new rt5659_spo_l_mix[] = {
1948 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPO_AMP_GAIN,
1949 RT5659_M_DAC_L2_SPKOMIX_SFT, 1, 0),
1950 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5659_SPO_AMP_GAIN,
1951 RT5659_M_SPKVOLL_SPKOMIX_SFT, 1, 0),
1952};
1953
1954static const struct snd_kcontrol_new rt5659_spo_r_mix[] = {
1955 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPO_AMP_GAIN,
1956 RT5659_M_DAC_R2_SPKOMIX_SFT, 1, 0),
1957 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5659_SPO_AMP_GAIN,
1958 RT5659_M_SPKVOLR_SPKOMIX_SFT, 1, 0),
1959};
1960
1961static const struct snd_kcontrol_new rt5659_mono_mix[] = {
1962 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
1963 RT5659_M_DAC_L2_MA_SFT, 1, 1),
1964 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_MONOMIX_IN_GAIN,
1965 RT5659_M_MONOVOL_MA_SFT, 1, 1),
1966};
1967
1968static const struct snd_kcontrol_new rt5659_lout_l_mix[] = {
1969 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_LOUT_MIXER,
1970 RT5659_M_DAC_L2_LM_SFT, 1, 1),
1971 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5659_LOUT_MIXER,
1972 RT5659_M_OV_L_LM_SFT, 1, 1),
1973};
1974
1975static const struct snd_kcontrol_new rt5659_lout_r_mix[] = {
1976 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_LOUT_MIXER,
1977 RT5659_M_DAC_R2_LM_SFT, 1, 1),
1978 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5659_LOUT_MIXER,
1979 RT5659_M_OV_R_LM_SFT, 1, 1),
1980};
1981
1982/*DAC L2, DAC R2*/
1983/*MX-1B [6:4], MX-1B [2:0]*/
1984static const char * const rt5659_dac2_src[] = {
1985 "IF1 DAC2", "IF2 DAC", "IF3 DAC", "Mono ADC MIX"
1986};
1987
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1988static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1989 rt5659_dac_l2_enum, RT5659_DAC_CTRL,
1990 RT5659_DAC_L2_SEL_SFT, rt5659_dac2_src);
1991
1992static const struct snd_kcontrol_new rt5659_dac_l2_mux =
1993 SOC_DAPM_ENUM("DAC L2 Source", rt5659_dac_l2_enum);
1994
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]1995static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]1996 rt5659_dac_r2_enum, RT5659_DAC_CTRL,
1997 RT5659_DAC_R2_SEL_SFT, rt5659_dac2_src);
1998
1999static const struct snd_kcontrol_new rt5659_dac_r2_mux =
2000 SOC_DAPM_ENUM("DAC R2 Source", rt5659_dac_r2_enum);
2001
2002
2003/* STO1 ADC1 Source */
2004/* MX-26 [13] */
2005static const char * const rt5659_sto1_adc1_src[] = {
2006 "DAC MIX", "ADC"
2007};
2008
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2009static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2010 rt5659_sto1_adc1_enum, RT5659_STO1_ADC_MIXER,
2011 RT5659_STO1_ADC1_SRC_SFT, rt5659_sto1_adc1_src);
2012
2013static const struct snd_kcontrol_new rt5659_sto1_adc1_mux =
2014 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5659_sto1_adc1_enum);
2015
2016/* STO1 ADC Source */
2017/* MX-26 [12] */
2018static const char * const rt5659_sto1_adc_src[] = {
2019 "ADC1", "ADC2"
2020};
2021
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2022static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2023 rt5659_sto1_adc_enum, RT5659_STO1_ADC_MIXER,
2024 RT5659_STO1_ADC_SRC_SFT, rt5659_sto1_adc_src);
2025
2026static const struct snd_kcontrol_new rt5659_sto1_adc_mux =
2027 SOC_DAPM_ENUM("Stereo1 ADC Source", rt5659_sto1_adc_enum);
2028
2029/* STO1 ADC2 Source */
2030/* MX-26 [11] */
2031static const char * const rt5659_sto1_adc2_src[] = {
2032 "DAC MIX", "DMIC"
2033};
2034
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2035static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2036 rt5659_sto1_adc2_enum, RT5659_STO1_ADC_MIXER,
2037 RT5659_STO1_ADC2_SRC_SFT, rt5659_sto1_adc2_src);
2038
2039static const struct snd_kcontrol_new rt5659_sto1_adc2_mux =
2040 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5659_sto1_adc2_enum);
2041
2042/* STO1 DMIC Source */
2043/* MX-26 [8] */
2044static const char * const rt5659_sto1_dmic_src[] = {
2045 "DMIC1", "DMIC2"
2046};
2047
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2048static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2049 rt5659_sto1_dmic_enum, RT5659_STO1_ADC_MIXER,
2050 RT5659_STO1_DMIC_SRC_SFT, rt5659_sto1_dmic_src);
2051
2052static const struct snd_kcontrol_new rt5659_sto1_dmic_mux =
2053 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5659_sto1_dmic_enum);
2054
2055
2056/* MONO ADC L2 Source */
2057/* MX-27 [12] */
2058static const char * const rt5659_mono_adc_l2_src[] = {
2059 "Mono DAC MIXL", "DMIC"
2060};
2061
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2062static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2063 rt5659_mono_adc_l2_enum, RT5659_MONO_ADC_MIXER,
2064 RT5659_MONO_ADC_L2_SRC_SFT, rt5659_mono_adc_l2_src);
2065
2066static const struct snd_kcontrol_new rt5659_mono_adc_l2_mux =
2067 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5659_mono_adc_l2_enum);
2068
2069
2070/* MONO ADC L1 Source */
2071/* MX-27 [11] */
2072static const char * const rt5659_mono_adc_l1_src[] = {
2073 "Mono DAC MIXL", "ADC"
2074};
2075
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2076static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2077 rt5659_mono_adc_l1_enum, RT5659_MONO_ADC_MIXER,
2078 RT5659_MONO_ADC_L1_SRC_SFT, rt5659_mono_adc_l1_src);
2079
2080static const struct snd_kcontrol_new rt5659_mono_adc_l1_mux =
2081 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5659_mono_adc_l1_enum);
2082
2083/* MONO ADC L Source, MONO ADC R Source*/
2084/* MX-27 [10:9], MX-27 [2:1] */
2085static const char * const rt5659_mono_adc_src[] = {
2086 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2087};
2088
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2089static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2090 rt5659_mono_adc_l_enum, RT5659_MONO_ADC_MIXER,
2091 RT5659_MONO_ADC_L_SRC_SFT, rt5659_mono_adc_src);
2092
2093static const struct snd_kcontrol_new rt5659_mono_adc_l_mux =
2094 SOC_DAPM_ENUM("Mono ADC L Source", rt5659_mono_adc_l_enum);
2095
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2096static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2097 rt5659_mono_adcr_enum, RT5659_MONO_ADC_MIXER,
2098 RT5659_MONO_ADC_R_SRC_SFT, rt5659_mono_adc_src);
2099
2100static const struct snd_kcontrol_new rt5659_mono_adc_r_mux =
2101 SOC_DAPM_ENUM("Mono ADC R Source", rt5659_mono_adcr_enum);
2102
2103/* MONO DMIC L Source */
2104/* MX-27 [8] */
2105static const char * const rt5659_mono_dmic_l_src[] = {
2106 "DMIC1 L", "DMIC2 L"
2107};
2108
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2109static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2110 rt5659_mono_dmic_l_enum, RT5659_MONO_ADC_MIXER,
2111 RT5659_MONO_DMIC_L_SRC_SFT, rt5659_mono_dmic_l_src);
2112
2113static const struct snd_kcontrol_new rt5659_mono_dmic_l_mux =
2114 SOC_DAPM_ENUM("Mono DMIC L Source", rt5659_mono_dmic_l_enum);
2115
2116/* MONO ADC R2 Source */
2117/* MX-27 [4] */
2118static const char * const rt5659_mono_adc_r2_src[] = {
2119 "Mono DAC MIXR", "DMIC"
2120};
2121
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2122static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2123 rt5659_mono_adc_r2_enum, RT5659_MONO_ADC_MIXER,
2124 RT5659_MONO_ADC_R2_SRC_SFT, rt5659_mono_adc_r2_src);
2125
2126static const struct snd_kcontrol_new rt5659_mono_adc_r2_mux =
2127 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5659_mono_adc_r2_enum);
2128
2129/* MONO ADC R1 Source */
2130/* MX-27 [3] */
2131static const char * const rt5659_mono_adc_r1_src[] = {
2132 "Mono DAC MIXR", "ADC"
2133};
2134
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2135static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2136 rt5659_mono_adc_r1_enum, RT5659_MONO_ADC_MIXER,
2137 RT5659_MONO_ADC_R1_SRC_SFT, rt5659_mono_adc_r1_src);
2138
2139static const struct snd_kcontrol_new rt5659_mono_adc_r1_mux =
2140 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5659_mono_adc_r1_enum);
2141
2142/* MONO DMIC R Source */
2143/* MX-27 [0] */
2144static const char * const rt5659_mono_dmic_r_src[] = {
2145 "DMIC1 R", "DMIC2 R"
2146};
2147
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2148static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2149 rt5659_mono_dmic_r_enum, RT5659_MONO_ADC_MIXER,
2150 RT5659_MONO_DMIC_R_SRC_SFT, rt5659_mono_dmic_r_src);
2151
2152static const struct snd_kcontrol_new rt5659_mono_dmic_r_mux =
2153 SOC_DAPM_ENUM("Mono DMIC R Source", rt5659_mono_dmic_r_enum);
2154
2155
2156/* DAC R1 Source, DAC L1 Source*/
2157/* MX-29 [11:10], MX-29 [9:8]*/
2158static const char * const rt5659_dac1_src[] = {
2159 "IF1 DAC1", "IF2 DAC", "IF3 DAC"
2160};
2161
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2162static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2163 rt5659_dac_r1_enum, RT5659_AD_DA_MIXER,
2164 RT5659_DAC1_R_SEL_SFT, rt5659_dac1_src);
2165
2166static const struct snd_kcontrol_new rt5659_dac_r1_mux =
2167 SOC_DAPM_ENUM("DAC R1 Source", rt5659_dac_r1_enum);
2168
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2169static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2170 rt5659_dac_l1_enum, RT5659_AD_DA_MIXER,
2171 RT5659_DAC1_L_SEL_SFT, rt5659_dac1_src);
2172
2173static const struct snd_kcontrol_new rt5659_dac_l1_mux =
2174 SOC_DAPM_ENUM("DAC L1 Source", rt5659_dac_l1_enum);
2175
2176/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2177/* MX-2C [6], MX-2C [4]*/
2178static const char * const rt5659_dig_dac_mix_src[] = {
2179 "Stereo DAC Mixer", "Mono DAC Mixer"
2180};
2181
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2182static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2183 rt5659_dig_dac_mixl_enum, RT5659_DIG_MIXER,
2184 RT5659_DAC_MIX_L_SFT, rt5659_dig_dac_mix_src);
2185
2186static const struct snd_kcontrol_new rt5659_dig_dac_mixl_mux =
2187 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5659_dig_dac_mixl_enum);
2188
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2189static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2190 rt5659_dig_dac_mixr_enum, RT5659_DIG_MIXER,
2191 RT5659_DAC_MIX_R_SFT, rt5659_dig_dac_mix_src);
2192
2193static const struct snd_kcontrol_new rt5659_dig_dac_mixr_mux =
2194 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5659_dig_dac_mixr_enum);
2195
2196/* Analog DAC L1 Source, Analog DAC R1 Source*/
2197/* MX-2D [3], MX-2D [2]*/
2198static const char * const rt5659_alg_dac1_src[] = {
2199 "DAC", "Stereo DAC Mixer"
2200};
2201
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2202static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2203 rt5659_alg_dac_l1_enum, RT5659_A_DAC_MUX,
2204 RT5659_A_DACL1_SFT, rt5659_alg_dac1_src);
2205
2206static const struct snd_kcontrol_new rt5659_alg_dac_l1_mux =
2207 SOC_DAPM_ENUM("Analog DACL1 Source", rt5659_alg_dac_l1_enum);
2208
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2209static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2210 rt5659_alg_dac_r1_enum, RT5659_A_DAC_MUX,
2211 RT5659_A_DACR1_SFT, rt5659_alg_dac1_src);
2212
2213static const struct snd_kcontrol_new rt5659_alg_dac_r1_mux =
2214 SOC_DAPM_ENUM("Analog DACR1 Source", rt5659_alg_dac_r1_enum);
2215
2216/* Analog DAC LR Source, Analog DAC R2 Source*/
2217/* MX-2D [1], MX-2D [0]*/
2218static const char * const rt5659_alg_dac2_src[] = {
2219 "Stereo DAC Mixer", "Mono DAC Mixer"
2220};
2221
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2222static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2223 rt5659_alg_dac_l2_enum, RT5659_A_DAC_MUX,
2224 RT5659_A_DACL2_SFT, rt5659_alg_dac2_src);
2225
2226static const struct snd_kcontrol_new rt5659_alg_dac_l2_mux =
2227 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5659_alg_dac_l2_enum);
2228
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2229static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2230 rt5659_alg_dac_r2_enum, RT5659_A_DAC_MUX,
2231 RT5659_A_DACR2_SFT, rt5659_alg_dac2_src);
2232
2233static const struct snd_kcontrol_new rt5659_alg_dac_r2_mux =
2234 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5659_alg_dac_r2_enum);
2235
2236/* Interface2 ADC Data Input*/
2237/* MX-2F [13:12] */
2238static const char * const rt5659_if2_adc_in_src[] = {
2239 "IF_ADC1", "IF_ADC2", "DAC_REF", "IF_ADC3"
2240};
2241
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2242static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2243 rt5659_if2_adc_in_enum, RT5659_DIG_INF23_DATA,
2244 RT5659_IF2_ADC_IN_SFT, rt5659_if2_adc_in_src);
2245
2246static const struct snd_kcontrol_new rt5659_if2_adc_in_mux =
2247 SOC_DAPM_ENUM("IF2 ADC IN Source", rt5659_if2_adc_in_enum);
2248
2249/* Interface3 ADC Data Input*/
2250/* MX-2F [1:0] */
2251static const char * const rt5659_if3_adc_in_src[] = {
2252 "IF_ADC1", "IF_ADC2", "DAC_REF", "Stereo2_ADC_L/R"
2253};
2254
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2255static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2256 rt5659_if3_adc_in_enum, RT5659_DIG_INF23_DATA,
2257 RT5659_IF3_ADC_IN_SFT, rt5659_if3_adc_in_src);
2258
2259static const struct snd_kcontrol_new rt5659_if3_adc_in_mux =
2260 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5659_if3_adc_in_enum);
2261
2262/* PDM 1 L/R*/
2263/* MX-31 [15] [13] */
2264static const char * const rt5659_pdm_src[] = {
2265 "Mono DAC", "Stereo DAC"
2266};
2267
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2268static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2269 rt5659_pdm_l_enum, RT5659_PDM_OUT_CTRL,
2270 RT5659_PDM1_L_SFT, rt5659_pdm_src);
2271
2272static const struct snd_kcontrol_new rt5659_pdm_l_mux =
2273 SOC_DAPM_ENUM("PDM L Source", rt5659_pdm_l_enum);
2274
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2275static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2276 rt5659_pdm_r_enum, RT5659_PDM_OUT_CTRL,
2277 RT5659_PDM1_R_SFT, rt5659_pdm_src);
2278
2279static const struct snd_kcontrol_new rt5659_pdm_r_mux =
2280 SOC_DAPM_ENUM("PDM R Source", rt5659_pdm_r_enum);
2281
2282/* SPDIF Output source*/
2283/* MX-36 [1:0] */
2284static const char * const rt5659_spdif_src[] = {
2285 "IF1_DAC1", "IF1_DAC2", "IF2_DAC", "IF3_DAC"
2286};
2287
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2288static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2289 rt5659_spdif_enum, RT5659_SPDIF_CTRL,
2290 RT5659_SPDIF_SEL_SFT, rt5659_spdif_src);
2291
2292static const struct snd_kcontrol_new rt5659_spdif_mux =
2293 SOC_DAPM_ENUM("SPDIF Source", rt5659_spdif_enum);
2294
2295/* I2S1 TDM ADCDAT Source */
2296/* MX-78[4:0] */
2297static const char * const rt5659_rx_adc_data_src[] = {
2298 "AD1:AD2:DAC:NUL", "AD1:AD2:NUL:DAC", "AD1:DAC:AD2:NUL",
2299 "AD1:DAC:NUL:AD2", "AD1:NUL:DAC:AD2", "AD1:NUL:AD2:DAC",
2300 "AD2:AD1:DAC:NUL", "AD2:AD1:NUL:DAC", "AD2:DAC:AD1:NUL",
2301 "AD2:DAC:NUL:AD1", "AD2:NUL:DAC:AD1", "AD1:NUL:AD1:DAC",
2302 "DAC:AD1:AD2:NUL", "DAC:AD1:NUL:AD2", "DAC:AD2:AD1:NUL",
2303 "DAC:AD2:NUL:AD1", "DAC:NUL:DAC:AD2", "DAC:NUL:AD2:DAC",
2304 "NUL:AD1:AD2:DAC", "NUL:AD1:DAC:AD2", "NUL:AD2:AD1:DAC",
2305 "NUL:AD2:DAC:AD1", "NUL:DAC:DAC:AD2", "NUL:DAC:AD2:DAC"
2306};
2307
Nicholas Mc Guireeae39b52017-01-12 14:15:03 +0100[diff] [blame]2308static SOC_ENUM_SINGLE_DECL(
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2309 rt5659_rx_adc_data_enum, RT5659_TDM_CTRL_2,
2310 RT5659_ADCDAT_SRC_SFT, rt5659_rx_adc_data_src);
2311
2312static const struct snd_kcontrol_new rt5659_rx_adc_dac_mux =
2313 SOC_DAPM_ENUM("TDM ADCDAT Source", rt5659_rx_adc_data_enum);
2314
2315/* Out Volume Switch */
2316static const struct snd_kcontrol_new spkvol_l_switch =
2317 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_L_SFT, 1, 1);
2318
2319static const struct snd_kcontrol_new spkvol_r_switch =
2320 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_R_SFT, 1, 1);
2321
2322static const struct snd_kcontrol_new monovol_switch =
2323 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_VOL_L_SFT, 1, 1);
2324
2325static const struct snd_kcontrol_new outvol_l_switch =
2326 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_L_SFT, 1, 1);
2327
2328static const struct snd_kcontrol_new outvol_r_switch =
2329 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_R_SFT, 1, 1);
2330
2331/* Out Switch */
2332static const struct snd_kcontrol_new spo_switch =
2333 SOC_DAPM_SINGLE("Switch", RT5659_CLASSD_2, RT5659_M_RF_DIG_SFT, 1, 1);
2334
2335static const struct snd_kcontrol_new mono_switch =
2336 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_L_MUTE_SFT, 1, 1);
2337
2338static const struct snd_kcontrol_new hpo_l_switch =
2339 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_L_MUTE_SFT, 1, 1);
2340
2341static const struct snd_kcontrol_new hpo_r_switch =
2342 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_R_MUTE_SFT, 1, 1);
2343
2344static const struct snd_kcontrol_new lout_l_switch =
2345 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_L_MUTE_SFT, 1, 1);
2346
2347static const struct snd_kcontrol_new lout_r_switch =
2348 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_R_MUTE_SFT, 1, 1);
2349
2350static const struct snd_kcontrol_new pdm_l_switch =
2351 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_L_SFT, 1,
2352 1);
2353
2354static const struct snd_kcontrol_new pdm_r_switch =
2355 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_R_SFT, 1,
2356 1);
2357
2358static int rt5659_spk_event(struct snd_soc_dapm_widget *w,
2359 struct snd_kcontrol *kcontrol, int event)
2360{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2361 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2362
2363 switch (event) {
2364 case SND_SOC_DAPM_PRE_PMU:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2365 snd_soc_component_update_bits(component, RT5659_CLASSD_CTRL_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2366 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_EN);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2367 snd_soc_component_update_bits(component, RT5659_CLASSD_2,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2368 RT5659_M_RI_DIG, RT5659_M_RI_DIG);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2369 snd_soc_component_write(component, RT5659_CLASSD_1, 0x0803);
2370 snd_soc_component_write(component, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2371 break;
2372
2373 case SND_SOC_DAPM_POST_PMD:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2374 snd_soc_component_write(component, RT5659_CLASSD_1, 0x0011);
2375 snd_soc_component_update_bits(component, RT5659_CLASSD_2,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2376 RT5659_M_RI_DIG, 0x0);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2377 snd_soc_component_write(component, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
2378 snd_soc_component_update_bits(component, RT5659_CLASSD_CTRL_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2379 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_DIS);
2380 break;
2381
2382 default:
2383 return 0;
2384 }
2385
2386 return 0;
2387
2388}
2389
2390static int rt5659_mono_event(struct snd_soc_dapm_widget *w,
2391 struct snd_kcontrol *kcontrol, int event)
2392{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2393 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2394
2395 switch (event) {
2396 case SND_SOC_DAPM_PRE_PMU:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2397 snd_soc_component_write(component, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2398 break;
2399
2400 case SND_SOC_DAPM_POST_PMD:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2401 snd_soc_component_write(component, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2402 break;
2403
2404 default:
2405 return 0;
2406 }
2407
2408 return 0;
2409
2410}
2411
2412static int rt5659_hp_event(struct snd_soc_dapm_widget *w,
2413 struct snd_kcontrol *kcontrol, int event)
2414{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2415 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2416
2417 switch (event) {
2418 case SND_SOC_DAPM_POST_PMU:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2419 snd_soc_component_write(component, RT5659_HP_CHARGE_PUMP_1, 0x0e1e);
2420 snd_soc_component_update_bits(component, RT5659_DEPOP_1, 0x0010, 0x0010);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2421 break;
2422
2423 case SND_SOC_DAPM_PRE_PMD:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]2424 snd_soc_component_write(component, RT5659_DEPOP_1, 0x0000);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2425 break;
2426
2427 default:
2428 return 0;
2429 }
2430
2431 return 0;
2432}
2433
2434static int set_dmic_power(struct snd_soc_dapm_widget *w,
2435 struct snd_kcontrol *kcontrol, int event)
2436{
2437 switch (event) {
2438 case SND_SOC_DAPM_POST_PMU:
2439 /*Add delay to avoid pop noise*/
2440 msleep(450);
2441 break;
2442
2443 default:
2444 return 0;
2445 }
2446
2447 return 0;
2448}
2449
2450static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = {
2451 SND_SOC_DAPM_SUPPLY("LDO2", RT5659_PWR_ANLG_3, RT5659_PWR_LDO2_BIT, 0,
2452 NULL, 0),
2453 SND_SOC_DAPM_SUPPLY("PLL", RT5659_PWR_ANLG_3, RT5659_PWR_PLL_BIT, 0,
2454 NULL, 0),
2455 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5659_PWR_VOL,
2456 RT5659_PWR_MIC_DET_BIT, 0, NULL, 0),
2457 SND_SOC_DAPM_SUPPLY("Mono Vref", RT5659_PWR_ANLG_1,
2458 RT5659_PWR_VREF3_BIT, 0, NULL, 0),
2459
2460 /* ASRC */
2461 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5659_ASRC_1,
2462 RT5659_I2S1_ASRC_SFT, 0, NULL, 0),
2463 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5659_ASRC_1,
2464 RT5659_I2S2_ASRC_SFT, 0, NULL, 0),
2465 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5659_ASRC_1,
2466 RT5659_I2S3_ASRC_SFT, 0, NULL, 0),
2467 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5659_ASRC_1,
2468 RT5659_DAC_STO_ASRC_SFT, 0, NULL, 0),
2469 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5659_ASRC_1,
2470 RT5659_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2471 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5659_ASRC_1,
2472 RT5659_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2473 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5659_ASRC_1,
2474 RT5659_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2475 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5659_ASRC_1,
2476 RT5659_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2477 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5659_ASRC_1,
2478 RT5659_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2479
2480 /* Input Side */
2481 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5659_PWR_ANLG_2, RT5659_PWR_MB1_BIT,
2482 0, NULL, 0),
2483 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5659_PWR_ANLG_2, RT5659_PWR_MB2_BIT,
2484 0, NULL, 0),
2485 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5659_PWR_ANLG_2, RT5659_PWR_MB3_BIT,
2486 0, NULL, 0),
2487
2488 /* Input Lines */
2489 SND_SOC_DAPM_INPUT("DMIC L1"),
2490 SND_SOC_DAPM_INPUT("DMIC R1"),
2491 SND_SOC_DAPM_INPUT("DMIC L2"),
2492 SND_SOC_DAPM_INPUT("DMIC R2"),
2493
2494 SND_SOC_DAPM_INPUT("IN1P"),
2495 SND_SOC_DAPM_INPUT("IN1N"),
2496 SND_SOC_DAPM_INPUT("IN2P"),
2497 SND_SOC_DAPM_INPUT("IN2N"),
2498 SND_SOC_DAPM_INPUT("IN3P"),
2499 SND_SOC_DAPM_INPUT("IN3N"),
2500 SND_SOC_DAPM_INPUT("IN4P"),
2501 SND_SOC_DAPM_INPUT("IN4N"),
2502
2503 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2504 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2505
2506 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2507 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2508 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5659_DMIC_CTRL_1,
2509 RT5659_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2510 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5659_DMIC_CTRL_1,
2511 RT5659_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2512
2513 /* Boost */
2514 SND_SOC_DAPM_PGA("BST1", RT5659_PWR_ANLG_2,
2515 RT5659_PWR_BST1_P_BIT, 0, NULL, 0),
2516 SND_SOC_DAPM_PGA("BST2", RT5659_PWR_ANLG_2,
2517 RT5659_PWR_BST2_P_BIT, 0, NULL, 0),
2518 SND_SOC_DAPM_PGA("BST3", RT5659_PWR_ANLG_2,
2519 RT5659_PWR_BST3_P_BIT, 0, NULL, 0),
2520 SND_SOC_DAPM_PGA("BST4", RT5659_PWR_ANLG_2,
2521 RT5659_PWR_BST4_P_BIT, 0, NULL, 0),
2522 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5659_PWR_ANLG_2,
2523 RT5659_PWR_BST1_BIT, 0, NULL, 0),
2524 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5659_PWR_ANLG_2,
2525 RT5659_PWR_BST2_BIT, 0, NULL, 0),
2526 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5659_PWR_ANLG_2,
2527 RT5659_PWR_BST3_BIT, 0, NULL, 0),
2528 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5659_PWR_ANLG_2,
2529 RT5659_PWR_BST4_BIT, 0, NULL, 0),
2530
2531
2532 /* Input Volume */
2533 SND_SOC_DAPM_PGA("INL VOL", RT5659_PWR_VOL, RT5659_PWR_IN_L_BIT,
2534 0, NULL, 0),
2535 SND_SOC_DAPM_PGA("INR VOL", RT5659_PWR_VOL, RT5659_PWR_IN_R_BIT,
2536 0, NULL, 0),
2537
2538 /* REC Mixer */
2539 SND_SOC_DAPM_MIXER("RECMIX1L", RT5659_PWR_MIXER, RT5659_PWR_RM1_L_BIT,
2540 0, rt5659_rec1_l_mix, ARRAY_SIZE(rt5659_rec1_l_mix)),
2541 SND_SOC_DAPM_MIXER("RECMIX1R", RT5659_PWR_MIXER, RT5659_PWR_RM1_R_BIT,
2542 0, rt5659_rec1_r_mix, ARRAY_SIZE(rt5659_rec1_r_mix)),
2543 SND_SOC_DAPM_MIXER("RECMIX2L", RT5659_PWR_MIXER, RT5659_PWR_RM2_L_BIT,
2544 0, rt5659_rec2_l_mix, ARRAY_SIZE(rt5659_rec2_l_mix)),
2545 SND_SOC_DAPM_MIXER("RECMIX2R", RT5659_PWR_MIXER, RT5659_PWR_RM2_R_BIT,
2546 0, rt5659_rec2_r_mix, ARRAY_SIZE(rt5659_rec2_r_mix)),
2547
2548 /* ADCs */
2549 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2550 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2551 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2552 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2553
2554 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5659_PWR_DIG_1,
2555 RT5659_PWR_ADC_L1_BIT, 0, NULL, 0),
2556 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5659_PWR_DIG_1,
2557 RT5659_PWR_ADC_R1_BIT, 0, NULL, 0),
2558 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5659_PWR_DIG_2,
2559 RT5659_PWR_ADC_L2_BIT, 0, NULL, 0),
2560 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_2,
2561 RT5659_PWR_ADC_R2_BIT, 0, NULL, 0),
2562 SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc_clk,
2563 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2564 SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc_clk,
2565 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2566
2567 /* ADC Mux */
2568 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2569 &rt5659_sto1_dmic_mux),
2570 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2571 &rt5659_sto1_dmic_mux),
2572 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2573 &rt5659_sto1_adc1_mux),
2574 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2575 &rt5659_sto1_adc1_mux),
2576 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2577 &rt5659_sto1_adc2_mux),
2578 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2579 &rt5659_sto1_adc2_mux),
2580 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2581 &rt5659_sto1_adc_mux),
2582 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2583 &rt5659_sto1_adc_mux),
2584 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2585 &rt5659_mono_adc_l2_mux),
2586 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2587 &rt5659_mono_adc_r2_mux),
2588 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2589 &rt5659_mono_adc_l1_mux),
2590 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2591 &rt5659_mono_adc_r1_mux),
2592 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2593 &rt5659_mono_dmic_l_mux),
2594 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2595 &rt5659_mono_dmic_r_mux),
2596 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2597 &rt5659_mono_adc_l_mux),
2598 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2599 &rt5659_mono_adc_r_mux),
2600 /* ADC Mixer */
2601 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5659_PWR_DIG_2,
2602 RT5659_PWR_ADC_S1F_BIT, 0, NULL, 0),
2603 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5659_PWR_DIG_2,
2604 RT5659_PWR_ADC_S2F_BIT, 0, NULL, 0),
2605 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM,
2606 0, 0, rt5659_sto1_adc_l_mix,
2607 ARRAY_SIZE(rt5659_sto1_adc_l_mix)),
2608 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM,
2609 0, 0, rt5659_sto1_adc_r_mix,
2610 ARRAY_SIZE(rt5659_sto1_adc_r_mix)),
2611 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5659_PWR_DIG_2,
2612 RT5659_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2613 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5659_MONO_ADC_DIG_VOL,
2614 RT5659_L_MUTE_SFT, 1, rt5659_mono_adc_l_mix,
2615 ARRAY_SIZE(rt5659_mono_adc_l_mix)),
2616 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5659_PWR_DIG_2,
2617 RT5659_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2618 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5659_MONO_ADC_DIG_VOL,
2619 RT5659_R_MUTE_SFT, 1, rt5659_mono_adc_r_mix,
2620 ARRAY_SIZE(rt5659_mono_adc_r_mix)),
2621
2622 /* ADC PGA */
2623 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2624 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2625 SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2626 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2627 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2628 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2629 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2630 SND_SOC_DAPM_PGA("Stereo2 ADC LR", SND_SOC_NOPM, 0, 0, NULL, 0),
2631
2632 SND_SOC_DAPM_PGA("Stereo1 ADC Volume L", RT5659_STO1_ADC_DIG_VOL,
2633 RT5659_L_MUTE_SFT, 1, NULL, 0),
2634 SND_SOC_DAPM_PGA("Stereo1 ADC Volume R", RT5659_STO1_ADC_DIG_VOL,
2635 RT5659_R_MUTE_SFT, 1, NULL, 0),
2636
2637 /* Digital Interface */
2638 SND_SOC_DAPM_SUPPLY("I2S1", RT5659_PWR_DIG_1, RT5659_PWR_I2S1_BIT,
2639 0, NULL, 0),
2640 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2641 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2642 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2643 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2644 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2645 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2646 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2647 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2648 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2649 SND_SOC_DAPM_SUPPLY("I2S2", RT5659_PWR_DIG_1, RT5659_PWR_I2S2_BIT, 0,
2650 NULL, 0),
2651 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2652 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2653 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2654 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2655 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2656 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2657 SND_SOC_DAPM_SUPPLY("I2S3", RT5659_PWR_DIG_1, RT5659_PWR_I2S3_BIT, 0,
2658 NULL, 0),
2659 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2660 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2661 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2662 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2663 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2664 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2665
2666 /* Digital Interface Select */
2667 SND_SOC_DAPM_PGA("TDM AD1:AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2668 SND_SOC_DAPM_PGA("TDM AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2669 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
2670 &rt5659_rx_adc_dac_mux),
2671 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
2672 &rt5659_if2_adc_in_mux),
2673 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2674 &rt5659_if3_adc_in_mux),
2675 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2676 &rt5659_if1_01_adc_swap_mux),
2677 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2678 &rt5659_if1_23_adc_swap_mux),
2679 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2680 &rt5659_if1_45_adc_swap_mux),
2681 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2682 &rt5659_if1_67_adc_swap_mux),
2683 SND_SOC_DAPM_MUX("IF2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2684 &rt5659_if2_dac_swap_mux),
2685 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2686 &rt5659_if2_adc_swap_mux),
2687 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2688 &rt5659_if3_dac_swap_mux),
2689 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2690 &rt5659_if3_adc_swap_mux),
2691
2692 /* Audio Interface */
2693 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2694 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2695 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2696 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2697 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2698 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2699
2700 /* Output Side */
2701 /* DAC mixer before sound effect */
2702 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2703 rt5659_dac_l_mix, ARRAY_SIZE(rt5659_dac_l_mix)),
2704 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2705 rt5659_dac_r_mix, ARRAY_SIZE(rt5659_dac_r_mix)),
2706
2707 /* DAC channel Mux */
2708 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l1_mux),
2709 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r1_mux),
2710 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l2_mux),
2711 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r2_mux),
2712
2713 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
2714 &rt5659_alg_dac_l1_mux),
2715 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
2716 &rt5659_alg_dac_r1_mux),
2717 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
2718 &rt5659_alg_dac_l2_mux),
2719 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
2720 &rt5659_alg_dac_r2_mux),
2721
2722 /* DAC Mixer */
2723 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5659_PWR_DIG_2,
2724 RT5659_PWR_DAC_S1F_BIT, 0, NULL, 0),
2725 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5659_PWR_DIG_2,
2726 RT5659_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2727 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5659_PWR_DIG_2,
2728 RT5659_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2729 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2730 rt5659_sto_dac_l_mix, ARRAY_SIZE(rt5659_sto_dac_l_mix)),
2731 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2732 rt5659_sto_dac_r_mix, ARRAY_SIZE(rt5659_sto_dac_r_mix)),
2733 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2734 rt5659_mono_dac_l_mix, ARRAY_SIZE(rt5659_mono_dac_l_mix)),
2735 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2736 rt5659_mono_dac_r_mix, ARRAY_SIZE(rt5659_mono_dac_r_mix)),
2737 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
2738 &rt5659_dig_dac_mixl_mux),
2739 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
2740 &rt5659_dig_dac_mixr_mux),
2741
2742 /* DACs */
2743 SND_SOC_DAPM_SUPPLY_S("DAC L1 Power", 1, RT5659_PWR_DIG_1,
2744 RT5659_PWR_DAC_L1_BIT, 0, NULL, 0),
2745 SND_SOC_DAPM_SUPPLY_S("DAC R1 Power", 1, RT5659_PWR_DIG_1,
2746 RT5659_PWR_DAC_R1_BIT, 0, NULL, 0),
2747 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
2748 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
2749
2750 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5659_PWR_DIG_1,
2751 RT5659_PWR_DAC_L2_BIT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5659_PWR_DIG_1,
2753 RT5659_PWR_DAC_R2_BIT, 0, NULL, 0),
2754 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
2755 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
2756 SND_SOC_DAPM_PGA("DAC_REF", SND_SOC_NOPM, 0, 0, NULL, 0),
2757
2758 /* OUT Mixer */
2759 SND_SOC_DAPM_MIXER("SPK MIXL", RT5659_PWR_MIXER, RT5659_PWR_SM_L_BIT,
2760 0, rt5659_spk_l_mix, ARRAY_SIZE(rt5659_spk_l_mix)),
2761 SND_SOC_DAPM_MIXER("SPK MIXR", RT5659_PWR_MIXER, RT5659_PWR_SM_R_BIT,
2762 0, rt5659_spk_r_mix, ARRAY_SIZE(rt5659_spk_r_mix)),
2763 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5659_PWR_MIXER, RT5659_PWR_MM_BIT,
2764 0, rt5659_monovol_mix, ARRAY_SIZE(rt5659_monovol_mix)),
2765 SND_SOC_DAPM_MIXER("OUT MIXL", RT5659_PWR_MIXER, RT5659_PWR_OM_L_BIT,
2766 0, rt5659_out_l_mix, ARRAY_SIZE(rt5659_out_l_mix)),
2767 SND_SOC_DAPM_MIXER("OUT MIXR", RT5659_PWR_MIXER, RT5659_PWR_OM_R_BIT,
2768 0, rt5659_out_r_mix, ARRAY_SIZE(rt5659_out_r_mix)),
2769
2770 /* Output Volume */
2771 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5659_PWR_VOL, RT5659_PWR_SV_L_BIT, 0,
2772 &spkvol_l_switch),
2773 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5659_PWR_VOL, RT5659_PWR_SV_R_BIT, 0,
2774 &spkvol_r_switch),
2775 SND_SOC_DAPM_SWITCH("MONOVOL", RT5659_PWR_VOL, RT5659_PWR_MV_BIT, 0,
2776 &monovol_switch),
2777 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5659_PWR_VOL, RT5659_PWR_OV_L_BIT, 0,
2778 &outvol_l_switch),
2779 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5659_PWR_VOL, RT5659_PWR_OV_R_BIT, 0,
2780 &outvol_r_switch),
2781
2782 /* SPO/MONO/HPO/LOUT */
2783 SND_SOC_DAPM_MIXER("SPO L MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_l_mix,
2784 ARRAY_SIZE(rt5659_spo_l_mix)),
2785 SND_SOC_DAPM_MIXER("SPO R MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_r_mix,
2786 ARRAY_SIZE(rt5659_spo_r_mix)),
2787 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5659_mono_mix,
2788 ARRAY_SIZE(rt5659_mono_mix)),
2789 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_l_mix,
2790 ARRAY_SIZE(rt5659_lout_l_mix)),
2791 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_r_mix,
2792 ARRAY_SIZE(rt5659_lout_r_mix)),
2793
2794 SND_SOC_DAPM_PGA_S("SPK Amp", 1, RT5659_PWR_DIG_1, RT5659_PWR_CLS_D_BIT,
2795 0, rt5659_spk_event, SND_SOC_DAPM_POST_PMD |
2796 SND_SOC_DAPM_PRE_PMU),
2797 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_MA_BIT,
2798 0, rt5659_mono_event, SND_SOC_DAPM_POST_PMD |
2799 SND_SOC_DAPM_PRE_PMU),
2800 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5659_hp_event,
2801 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
Bard Liaod1e84302017-10-16 19:15:13 +0800[diff] [blame]2802 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_LM_BIT,
2803 0, NULL, 0),
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2804
2805 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
2806 rt5659_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2807 SND_SOC_DAPM_POST_PMD),
2808
2809 SND_SOC_DAPM_SWITCH("SPO Playback", SND_SOC_NOPM, 0, 0, &spo_switch),
2810 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
2811 &mono_switch),
2812 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
2813 &hpo_l_switch),
2814 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
2815 &hpo_r_switch),
2816 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
2817 &lout_l_switch),
2818 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
2819 &lout_r_switch),
2820 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
2821 &pdm_l_switch),
2822 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
2823 &pdm_r_switch),
2824
2825 /* PDM */
2826 SND_SOC_DAPM_SUPPLY("PDM Power", RT5659_PWR_DIG_2,
2827 RT5659_PWR_PDM1_BIT, 0, NULL, 0),
2828 SND_SOC_DAPM_MUX("PDM L Mux", RT5659_PDM_OUT_CTRL,
2829 RT5659_M_PDM1_L_SFT, 1, &rt5659_pdm_l_mux),
2830 SND_SOC_DAPM_MUX("PDM R Mux", RT5659_PDM_OUT_CTRL,
2831 RT5659_M_PDM1_R_SFT, 1, &rt5659_pdm_r_mux),
2832
2833 /* SPDIF */
2834 SND_SOC_DAPM_MUX("SPDIF Mux", SND_SOC_NOPM, 0, 0, &rt5659_spdif_mux),
2835
2836 SND_SOC_DAPM_SUPPLY("SYS CLK DET", RT5659_CLK_DET, 3, 0, NULL, 0),
2837 SND_SOC_DAPM_SUPPLY("CLKDET", RT5659_CLK_DET, 0, 0, NULL, 0),
2838
2839 /* Output Lines */
2840 SND_SOC_DAPM_OUTPUT("HPOL"),
2841 SND_SOC_DAPM_OUTPUT("HPOR"),
2842 SND_SOC_DAPM_OUTPUT("SPOL"),
2843 SND_SOC_DAPM_OUTPUT("SPOR"),
2844 SND_SOC_DAPM_OUTPUT("LOUTL"),
2845 SND_SOC_DAPM_OUTPUT("LOUTR"),
2846 SND_SOC_DAPM_OUTPUT("MONOOUT"),
2847 SND_SOC_DAPM_OUTPUT("PDML"),
2848 SND_SOC_DAPM_OUTPUT("PDMR"),
2849 SND_SOC_DAPM_OUTPUT("SPDIF"),
2850};
2851
2852static const struct snd_soc_dapm_route rt5659_dapm_routes[] = {
2853 /*PLL*/
2854 { "ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2855 { "ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll },
2856 { "ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2857 { "ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2858 { "DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2859 { "DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2860 { "DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2861
2862 /*ASRC*/
2863 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2864 { "ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc },
2865 { "ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc },
2866 { "DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc },
2867 { "DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc },
2868 { "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
2869
2870 { "SYS CLK DET", NULL, "CLKDET" },
2871
2872 { "I2S1", NULL, "I2S1 ASRC" },
2873 { "I2S2", NULL, "I2S2 ASRC" },
2874 { "I2S3", NULL, "I2S3 ASRC" },
2875
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]2876 { "DMIC1", NULL, "DMIC L1" },
2877 { "DMIC1", NULL, "DMIC R1" },
2878 { "DMIC2", NULL, "DMIC L2" },
2879 { "DMIC2", NULL, "DMIC R2" },
2880
2881 { "BST1", NULL, "IN1P" },
2882 { "BST1", NULL, "IN1N" },
2883 { "BST1", NULL, "BST1 Power" },
2884 { "BST2", NULL, "IN2P" },
2885 { "BST2", NULL, "IN2N" },
2886 { "BST2", NULL, "BST2 Power" },
2887 { "BST3", NULL, "IN3P" },
2888 { "BST3", NULL, "IN3N" },
2889 { "BST3", NULL, "BST3 Power" },
2890 { "BST4", NULL, "IN4P" },
2891 { "BST4", NULL, "IN4N" },
2892 { "BST4", NULL, "BST4 Power" },
2893
2894 { "INL VOL", NULL, "IN2P" },
2895 { "INR VOL", NULL, "IN2N" },
2896
2897 { "RECMIX1L", "SPKVOLL Switch", "SPKVOL L" },
2898 { "RECMIX1L", "INL Switch", "INL VOL" },
2899 { "RECMIX1L", "BST4 Switch", "BST4" },
2900 { "RECMIX1L", "BST3 Switch", "BST3" },
2901 { "RECMIX1L", "BST2 Switch", "BST2" },
2902 { "RECMIX1L", "BST1 Switch", "BST1" },
2903
2904 { "RECMIX1R", "HPOVOLR Switch", "HPO R Playback" },
2905 { "RECMIX1R", "INR Switch", "INR VOL" },
2906 { "RECMIX1R", "BST4 Switch", "BST4" },
2907 { "RECMIX1R", "BST3 Switch", "BST3" },
2908 { "RECMIX1R", "BST2 Switch", "BST2" },
2909 { "RECMIX1R", "BST1 Switch", "BST1" },
2910
2911 { "RECMIX2L", "SPKVOLL Switch", "SPKVOL L" },
2912 { "RECMIX2L", "OUTVOLL Switch", "OUTVOL L" },
2913 { "RECMIX2L", "BST4 Switch", "BST4" },
2914 { "RECMIX2L", "BST3 Switch", "BST3" },
2915 { "RECMIX2L", "BST2 Switch", "BST2" },
2916 { "RECMIX2L", "BST1 Switch", "BST1" },
2917
2918 { "RECMIX2R", "MONOVOL Switch", "MONOVOL" },
2919 { "RECMIX2R", "OUTVOLR Switch", "OUTVOL R" },
2920 { "RECMIX2R", "BST4 Switch", "BST4" },
2921 { "RECMIX2R", "BST3 Switch", "BST3" },
2922 { "RECMIX2R", "BST2 Switch", "BST2" },
2923 { "RECMIX2R", "BST1 Switch", "BST1" },
2924
2925 { "ADC1 L", NULL, "RECMIX1L" },
2926 { "ADC1 L", NULL, "ADC1 L Power" },
2927 { "ADC1 L", NULL, "ADC1 clock" },
2928 { "ADC1 R", NULL, "RECMIX1R" },
2929 { "ADC1 R", NULL, "ADC1 R Power" },
2930 { "ADC1 R", NULL, "ADC1 clock" },
2931
2932 { "ADC2 L", NULL, "RECMIX2L" },
2933 { "ADC2 L", NULL, "ADC2 L Power" },
2934 { "ADC2 L", NULL, "ADC2 clock" },
2935 { "ADC2 R", NULL, "RECMIX2R" },
2936 { "ADC2 R", NULL, "ADC2 R Power" },
2937 { "ADC2 R", NULL, "ADC2 clock" },
2938
2939 { "DMIC L1", NULL, "DMIC CLK" },
2940 { "DMIC L1", NULL, "DMIC1 Power" },
2941 { "DMIC R1", NULL, "DMIC CLK" },
2942 { "DMIC R1", NULL, "DMIC1 Power" },
2943 { "DMIC L2", NULL, "DMIC CLK" },
2944 { "DMIC L2", NULL, "DMIC2 Power" },
2945 { "DMIC R2", NULL, "DMIC CLK" },
2946 { "DMIC R2", NULL, "DMIC2 Power" },
2947
2948 { "Stereo1 DMIC L Mux", "DMIC1", "DMIC L1" },
2949 { "Stereo1 DMIC L Mux", "DMIC2", "DMIC L2" },
2950
2951 { "Stereo1 DMIC R Mux", "DMIC1", "DMIC R1" },
2952 { "Stereo1 DMIC R Mux", "DMIC2", "DMIC R2" },
2953
2954 { "Mono DMIC L Mux", "DMIC1 L", "DMIC L1" },
2955 { "Mono DMIC L Mux", "DMIC2 L", "DMIC L2" },
2956
2957 { "Mono DMIC R Mux", "DMIC1 R", "DMIC R1" },
2958 { "Mono DMIC R Mux", "DMIC2 R", "DMIC R2" },
2959
2960 { "Stereo1 ADC L Mux", "ADC1", "ADC1 L" },
2961 { "Stereo1 ADC L Mux", "ADC2", "ADC2 L" },
2962 { "Stereo1 ADC R Mux", "ADC1", "ADC1 R" },
2963 { "Stereo1 ADC R Mux", "ADC2", "ADC2 R" },
2964
2965 { "Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux" },
2966 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2967 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux" },
2968 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2969
2970 { "Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux" },
2971 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2972 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux" },
2973 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2974
2975 { "Mono ADC L Mux", "ADC1 L", "ADC1 L" },
2976 { "Mono ADC L Mux", "ADC1 R", "ADC1 R" },
2977 { "Mono ADC L Mux", "ADC2 L", "ADC2 L" },
2978 { "Mono ADC L Mux", "ADC2 R", "ADC2 R" },
2979
2980 { "Mono ADC R Mux", "ADC1 L", "ADC1 L" },
2981 { "Mono ADC R Mux", "ADC1 R", "ADC1 R" },
2982 { "Mono ADC R Mux", "ADC2 L", "ADC2 L" },
2983 { "Mono ADC R Mux", "ADC2 R", "ADC2 R" },
2984
2985 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2986 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2987 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2988 { "Mono ADC L1 Mux", "ADC", "Mono ADC L Mux" },
2989
2990 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2991 { "Mono ADC R1 Mux", "ADC", "Mono ADC R Mux" },
2992 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2993 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2994
2995 { "Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2996 { "Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2997 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
2998
2999 { "Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
3000 { "Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
3001 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
3002
3003 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
3004 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
3005 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
3006
3007 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
3008 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
3009 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
3010
3011 { "Stereo1 ADC Volume L", NULL, "Stereo1 ADC MIXL" },
3012 { "Stereo1 ADC Volume R", NULL, "Stereo1 ADC MIXR" },
3013
3014 { "IF_ADC1", NULL, "Stereo1 ADC Volume L" },
3015 { "IF_ADC1", NULL, "Stereo1 ADC Volume R" },
3016 { "IF_ADC2", NULL, "Mono ADC MIXL" },
3017 { "IF_ADC2", NULL, "Mono ADC MIXR" },
3018
3019 { "TDM AD1:AD2:DAC", NULL, "IF_ADC1" },
3020 { "TDM AD1:AD2:DAC", NULL, "IF_ADC2" },
3021 { "TDM AD1:AD2:DAC", NULL, "DAC_REF" },
3022 { "TDM AD2:DAC", NULL, "IF_ADC2" },
3023 { "TDM AD2:DAC", NULL, "DAC_REF" },
3024 { "TDM Data Mux", "AD1:AD2:DAC:NUL", "TDM AD1:AD2:DAC" },
3025 { "TDM Data Mux", "AD1:AD2:NUL:DAC", "TDM AD1:AD2:DAC" },
3026 { "TDM Data Mux", "AD1:DAC:AD2:NUL", "TDM AD1:AD2:DAC" },
3027 { "TDM Data Mux", "AD1:DAC:NUL:AD2", "TDM AD1:AD2:DAC" },
3028 { "TDM Data Mux", "AD1:NUL:DAC:AD2", "TDM AD1:AD2:DAC" },
3029 { "TDM Data Mux", "AD1:NUL:AD2:DAC", "TDM AD1:AD2:DAC" },
3030 { "TDM Data Mux", "AD2:AD1:DAC:NUL", "TDM AD1:AD2:DAC" },
3031 { "TDM Data Mux", "AD2:AD1:NUL:DAC", "TDM AD1:AD2:DAC" },
3032 { "TDM Data Mux", "AD2:DAC:AD1:NUL", "TDM AD1:AD2:DAC" },
3033 { "TDM Data Mux", "AD2:DAC:NUL:AD1", "TDM AD1:AD2:DAC" },
3034 { "TDM Data Mux", "AD2:NUL:DAC:AD1", "TDM AD1:AD2:DAC" },
3035 { "TDM Data Mux", "AD1:NUL:AD1:DAC", "TDM AD1:AD2:DAC" },
3036 { "TDM Data Mux", "DAC:AD1:AD2:NUL", "TDM AD1:AD2:DAC" },
3037 { "TDM Data Mux", "DAC:AD1:NUL:AD2", "TDM AD1:AD2:DAC" },
3038 { "TDM Data Mux", "DAC:AD2:AD1:NUL", "TDM AD1:AD2:DAC" },
3039 { "TDM Data Mux", "DAC:AD2:NUL:AD1", "TDM AD1:AD2:DAC" },
3040 { "TDM Data Mux", "DAC:NUL:DAC:AD2", "TDM AD2:DAC" },
3041 { "TDM Data Mux", "DAC:NUL:AD2:DAC", "TDM AD2:DAC" },
3042 { "TDM Data Mux", "NUL:AD1:AD2:DAC", "TDM AD1:AD2:DAC" },
3043 { "TDM Data Mux", "NUL:AD1:DAC:AD2", "TDM AD1:AD2:DAC" },
3044 { "TDM Data Mux", "NUL:AD2:AD1:DAC", "TDM AD1:AD2:DAC" },
3045 { "TDM Data Mux", "NUL:AD2:DAC:AD1", "TDM AD1:AD2:DAC" },
3046 { "TDM Data Mux", "NUL:DAC:DAC:AD2", "TDM AD2:DAC" },
3047 { "TDM Data Mux", "NUL:DAC:AD2:DAC", "TDM AD2:DAC" },
3048 { "IF1 01 ADC Swap Mux", "L/R", "TDM Data Mux" },
3049 { "IF1 01 ADC Swap Mux", "R/L", "TDM Data Mux" },
3050 { "IF1 01 ADC Swap Mux", "L/L", "TDM Data Mux" },
3051 { "IF1 01 ADC Swap Mux", "R/R", "TDM Data Mux" },
3052 { "IF1 23 ADC Swap Mux", "L/R", "TDM Data Mux" },
3053 { "IF1 23 ADC Swap Mux", "R/L", "TDM Data Mux" },
3054 { "IF1 23 ADC Swap Mux", "L/L", "TDM Data Mux" },
3055 { "IF1 23 ADC Swap Mux", "R/R", "TDM Data Mux" },
3056 { "IF1 45 ADC Swap Mux", "L/R", "TDM Data Mux" },
3057 { "IF1 45 ADC Swap Mux", "R/L", "TDM Data Mux" },
3058 { "IF1 45 ADC Swap Mux", "L/L", "TDM Data Mux" },
3059 { "IF1 45 ADC Swap Mux", "R/R", "TDM Data Mux" },
3060 { "IF1 67 ADC Swap Mux", "L/R", "TDM Data Mux" },
3061 { "IF1 67 ADC Swap Mux", "R/L", "TDM Data Mux" },
3062 { "IF1 67 ADC Swap Mux", "L/L", "TDM Data Mux" },
3063 { "IF1 67 ADC Swap Mux", "R/R", "TDM Data Mux" },
3064 { "IF1 ADC", NULL, "IF1 01 ADC Swap Mux" },
3065 { "IF1 ADC", NULL, "IF1 23 ADC Swap Mux" },
3066 { "IF1 ADC", NULL, "IF1 45 ADC Swap Mux" },
3067 { "IF1 ADC", NULL, "IF1 67 ADC Swap Mux" },
3068 { "IF1 ADC", NULL, "I2S1" },
3069
3070 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
3071 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
3072 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
3073 { "IF2 ADC Mux", "DAC_REF", "DAC_REF" },
3074 { "IF2 ADC", NULL, "IF2 ADC Mux"},
3075 { "IF2 ADC", NULL, "I2S2" },
3076
3077 { "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" },
3078 { "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" },
3079 { "IF3 ADC Mux", "Stereo2_ADC_L/R", "Stereo2 ADC LR" },
3080 { "IF3 ADC Mux", "DAC_REF", "DAC_REF" },
3081 { "IF3 ADC", NULL, "IF3 ADC Mux"},
3082 { "IF3 ADC", NULL, "I2S3" },
3083
3084 { "AIF1TX", NULL, "IF1 ADC" },
3085 { "IF2 ADC Swap Mux", "L/R", "IF2 ADC" },
3086 { "IF2 ADC Swap Mux", "R/L", "IF2 ADC" },
3087 { "IF2 ADC Swap Mux", "L/L", "IF2 ADC" },
3088 { "IF2 ADC Swap Mux", "R/R", "IF2 ADC" },
3089 { "AIF2TX", NULL, "IF2 ADC Swap Mux" },
3090 { "IF3 ADC Swap Mux", "L/R", "IF3 ADC" },
3091 { "IF3 ADC Swap Mux", "R/L", "IF3 ADC" },
3092 { "IF3 ADC Swap Mux", "L/L", "IF3 ADC" },
3093 { "IF3 ADC Swap Mux", "R/R", "IF3 ADC" },
3094 { "AIF3TX", NULL, "IF3 ADC Swap Mux" },
3095
3096 { "IF1 DAC1", NULL, "AIF1RX" },
3097 { "IF1 DAC2", NULL, "AIF1RX" },
3098 { "IF2 DAC Swap Mux", "L/R", "AIF2RX" },
3099 { "IF2 DAC Swap Mux", "R/L", "AIF2RX" },
3100 { "IF2 DAC Swap Mux", "L/L", "AIF2RX" },
3101 { "IF2 DAC Swap Mux", "R/R", "AIF2RX" },
3102 { "IF2 DAC", NULL, "IF2 DAC Swap Mux" },
3103 { "IF3 DAC Swap Mux", "L/R", "AIF3RX" },
3104 { "IF3 DAC Swap Mux", "R/L", "AIF3RX" },
3105 { "IF3 DAC Swap Mux", "L/L", "AIF3RX" },
3106 { "IF3 DAC Swap Mux", "R/R", "AIF3RX" },
3107 { "IF3 DAC", NULL, "IF3 DAC Swap Mux" },
3108
3109 { "IF1 DAC1", NULL, "I2S1" },
3110 { "IF1 DAC2", NULL, "I2S1" },
3111 { "IF2 DAC", NULL, "I2S2" },
3112 { "IF3 DAC", NULL, "I2S3" },
3113
3114 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
3115 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
3116 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
3117 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
3118 { "IF2 DAC L", NULL, "IF2 DAC" },
3119 { "IF2 DAC R", NULL, "IF2 DAC" },
3120 { "IF3 DAC L", NULL, "IF3 DAC" },
3121 { "IF3 DAC R", NULL, "IF3 DAC" },
3122
3123 { "DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L" },
3124 { "DAC L1 Mux", "IF2 DAC", "IF2 DAC L" },
3125 { "DAC L1 Mux", "IF3 DAC", "IF3 DAC L" },
3126 { "DAC L1 Mux", NULL, "DAC Stereo1 Filter" },
3127
3128 { "DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R" },
3129 { "DAC R1 Mux", "IF2 DAC", "IF2 DAC R" },
3130 { "DAC R1 Mux", "IF3 DAC", "IF3 DAC R" },
3131 { "DAC R1 Mux", NULL, "DAC Stereo1 Filter" },
3132
3133 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC Volume L" },
3134 { "DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux" },
3135 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC Volume R" },
3136 { "DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux" },
3137
3138 { "DAC_REF", NULL, "DAC1 MIXL" },
3139 { "DAC_REF", NULL, "DAC1 MIXR" },
3140
3141 { "DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L" },
3142 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
3143 { "DAC L2 Mux", "IF3 DAC", "IF3 DAC L" },
3144 { "DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL" },
3145 { "DAC L2 Mux", NULL, "DAC Mono Left Filter" },
3146
3147 { "DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R" },
3148 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
3149 { "DAC R2 Mux", "IF3 DAC", "IF3 DAC R" },
3150 { "DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR" },
3151 { "DAC R2 Mux", NULL, "DAC Mono Right Filter" },
3152
3153 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
3154 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
3155 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3156 { "Stereo DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3157
3158 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
3159 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
3160 { "Stereo DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3161 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3162
3163 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
3164 { "Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
3165 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3166 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3167 { "Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
3168 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
3169 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3170 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3171
3172 { "DAC MIXL", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3173 { "DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL" },
3174 { "DAC MIXR", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3175 { "DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR" },
3176
3177 { "DAC L1 Source", NULL, "DAC L1 Power" },
3178 { "DAC L1 Source", "DAC", "DAC1 MIXL" },
3179 { "DAC L1 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3180 { "DAC R1 Source", NULL, "DAC R1 Power" },
3181 { "DAC R1 Source", "DAC", "DAC1 MIXR" },
3182 { "DAC R1 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3183 { "DAC L2 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3184 { "DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL" },
3185 { "DAC L2 Source", NULL, "DAC L2 Power" },
3186 { "DAC R2 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3187 { "DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR" },
3188 { "DAC R2 Source", NULL, "DAC R2 Power" },
3189
3190 { "DAC L1", NULL, "DAC L1 Source" },
3191 { "DAC R1", NULL, "DAC R1 Source" },
3192 { "DAC L2", NULL, "DAC L2 Source" },
3193 { "DAC R2", NULL, "DAC R2 Source" },
3194
3195 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
3196 { "SPK MIXL", "BST1 Switch", "BST1" },
3197 { "SPK MIXL", "INL Switch", "INL VOL" },
3198 { "SPK MIXL", "INR Switch", "INR VOL" },
3199 { "SPK MIXL", "BST3 Switch", "BST3" },
3200 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
3201 { "SPK MIXR", "BST4 Switch", "BST4" },
3202 { "SPK MIXR", "INL Switch", "INL VOL" },
3203 { "SPK MIXR", "INR Switch", "INR VOL" },
3204 { "SPK MIXR", "BST3 Switch", "BST3" },
3205
3206 { "MONOVOL MIX", "DAC L2 Switch", "DAC L2" },
3207 { "MONOVOL MIX", "DAC R2 Switch", "DAC R2" },
3208 { "MONOVOL MIX", "BST1 Switch", "BST1" },
3209 { "MONOVOL MIX", "BST2 Switch", "BST2" },
3210 { "MONOVOL MIX", "BST3 Switch", "BST3" },
3211
3212 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
3213 { "OUT MIXL", "INL Switch", "INL VOL" },
3214 { "OUT MIXL", "BST1 Switch", "BST1" },
3215 { "OUT MIXL", "BST2 Switch", "BST2" },
3216 { "OUT MIXL", "BST3 Switch", "BST3" },
3217 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
3218 { "OUT MIXR", "INR Switch", "INR VOL" },
3219 { "OUT MIXR", "BST2 Switch", "BST2" },
3220 { "OUT MIXR", "BST3 Switch", "BST3" },
3221 { "OUT MIXR", "BST4 Switch", "BST4" },
3222
3223 { "SPKVOL L", "Switch", "SPK MIXL" },
3224 { "SPKVOL R", "Switch", "SPK MIXR" },
3225 { "SPO L MIX", "DAC L2 Switch", "DAC L2" },
3226 { "SPO L MIX", "SPKVOL L Switch", "SPKVOL L" },
3227 { "SPO R MIX", "DAC R2 Switch", "DAC R2" },
3228 { "SPO R MIX", "SPKVOL R Switch", "SPKVOL R" },
3229 { "SPK Amp", NULL, "SPO L MIX" },
3230 { "SPK Amp", NULL, "SPO R MIX" },
3231 { "SPK Amp", NULL, "SYS CLK DET" },
3232 { "SPO Playback", "Switch", "SPK Amp" },
3233 { "SPOL", NULL, "SPO Playback" },
3234 { "SPOR", NULL, "SPO Playback" },
3235
3236 { "MONOVOL", "Switch", "MONOVOL MIX" },
3237 { "Mono MIX", "DAC L2 Switch", "DAC L2" },
3238 { "Mono MIX", "MONOVOL Switch", "MONOVOL" },
3239 { "Mono Amp", NULL, "Mono MIX" },
3240 { "Mono Amp", NULL, "Mono Vref" },
3241 { "Mono Amp", NULL, "SYS CLK DET" },
3242 { "Mono Playback", "Switch", "Mono Amp" },
3243 { "MONOOUT", NULL, "Mono Playback" },
3244
3245 { "HP Amp", NULL, "DAC L1" },
3246 { "HP Amp", NULL, "DAC R1" },
3247 { "HP Amp", NULL, "Charge Pump" },
3248 { "HP Amp", NULL, "SYS CLK DET" },
3249 { "HPO L Playback", "Switch", "HP Amp"},
3250 { "HPO R Playback", "Switch", "HP Amp"},
3251 { "HPOL", NULL, "HPO L Playback" },
3252 { "HPOR", NULL, "HPO R Playback" },
3253
3254 { "OUTVOL L", "Switch", "OUT MIXL" },
3255 { "OUTVOL R", "Switch", "OUT MIXR" },
3256 { "LOUT L MIX", "DAC L2 Switch", "DAC L2" },
3257 { "LOUT L MIX", "OUTVOL L Switch", "OUTVOL L" },
3258 { "LOUT R MIX", "DAC R2 Switch", "DAC R2" },
3259 { "LOUT R MIX", "OUTVOL R Switch", "OUTVOL R" },
3260 { "LOUT Amp", NULL, "LOUT L MIX" },
3261 { "LOUT Amp", NULL, "LOUT R MIX" },
Bard Liaoa6189d32017-10-16 19:15:14 +0800[diff] [blame]3262 { "LOUT Amp", NULL, "Charge Pump" },
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3263 { "LOUT Amp", NULL, "SYS CLK DET" },
3264 { "LOUT L Playback", "Switch", "LOUT Amp" },
3265 { "LOUT R Playback", "Switch", "LOUT Amp" },
3266 { "LOUTL", NULL, "LOUT L Playback" },
3267 { "LOUTR", NULL, "LOUT R Playback" },
3268
3269 { "PDM L Mux", "Mono DAC", "Mono DAC MIXL" },
3270 { "PDM L Mux", "Stereo DAC", "Stereo DAC MIXL" },
3271 { "PDM L Mux", NULL, "PDM Power" },
3272 { "PDM R Mux", "Mono DAC", "Mono DAC MIXR" },
3273 { "PDM R Mux", "Stereo DAC", "Stereo DAC MIXR" },
3274 { "PDM R Mux", NULL, "PDM Power" },
3275 { "PDM L Playback", "Switch", "PDM L Mux" },
3276 { "PDM R Playback", "Switch", "PDM R Mux" },
3277 { "PDML", NULL, "PDM L Playback" },
3278 { "PDMR", NULL, "PDM R Playback" },
3279
3280 { "SPDIF Mux", "IF3_DAC", "IF3 DAC" },
3281 { "SPDIF Mux", "IF2_DAC", "IF2 DAC" },
3282 { "SPDIF Mux", "IF1_DAC2", "IF1 DAC2" },
3283 { "SPDIF Mux", "IF1_DAC1", "IF1 DAC1" },
3284 { "SPDIF", NULL, "SPDIF Mux" },
3285};
3286
3287static int rt5659_hw_params(struct snd_pcm_substream *substream,
3288 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3289{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3290 struct snd_soc_component *component = dai->component;
3291 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3292 unsigned int val_len = 0, val_clk, mask_clk;
3293 int pre_div, frame_size;
3294
3295 rt5659->lrck[dai->id] = params_rate(params);
3296 pre_div = rl6231_get_clk_info(rt5659->sysclk, rt5659->lrck[dai->id]);
3297 if (pre_div < 0) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3298 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3299 rt5659->lrck[dai->id], dai->id);
3300 return -EINVAL;
3301 }
3302 frame_size = snd_soc_params_to_frame_size(params);
3303 if (frame_size < 0) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3304 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3305 return -EINVAL;
3306 }
3307
3308 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
3309 rt5659->lrck[dai->id], pre_div, dai->id);
3310
3311 switch (params_width(params)) {
3312 case 16:
3313 break;
3314 case 20:
3315 val_len |= RT5659_I2S_DL_20;
3316 break;
3317 case 24:
3318 val_len |= RT5659_I2S_DL_24;
3319 break;
3320 case 8:
3321 val_len |= RT5659_I2S_DL_8;
3322 break;
3323 default:
3324 return -EINVAL;
3325 }
3326
3327 switch (dai->id) {
3328 case RT5659_AIF1:
3329 mask_clk = RT5659_I2S_PD1_MASK;
3330 val_clk = pre_div << RT5659_I2S_PD1_SFT;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3331 snd_soc_component_update_bits(component, RT5659_I2S1_SDP,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3332 RT5659_I2S_DL_MASK, val_len);
3333 break;
3334 case RT5659_AIF2:
3335 mask_clk = RT5659_I2S_PD2_MASK;
3336 val_clk = pre_div << RT5659_I2S_PD2_SFT;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3337 snd_soc_component_update_bits(component, RT5659_I2S2_SDP,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3338 RT5659_I2S_DL_MASK, val_len);
3339 break;
3340 case RT5659_AIF3:
3341 mask_clk = RT5659_I2S_PD3_MASK;
3342 val_clk = pre_div << RT5659_I2S_PD3_SFT;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3343 snd_soc_component_update_bits(component, RT5659_I2S3_SDP,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3344 RT5659_I2S_DL_MASK, val_len);
3345 break;
3346 default:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3347 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3348 return -EINVAL;
3349 }
3350
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3351 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, mask_clk, val_clk);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3352
3353 switch (rt5659->lrck[dai->id]) {
3354 case 192000:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3355 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3356 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_32);
3357 break;
3358 case 96000:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3359 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3360 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_64);
3361 break;
3362 default:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3363 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3364 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_128);
3365 break;
3366 }
3367
3368 return 0;
3369}
3370
3371static int rt5659_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3372{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3373 struct snd_soc_component *component = dai->component;
3374 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3375 unsigned int reg_val = 0;
3376
3377 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3378 case SND_SOC_DAIFMT_CBM_CFM:
3379 rt5659->master[dai->id] = 1;
3380 break;
3381 case SND_SOC_DAIFMT_CBS_CFS:
3382 reg_val |= RT5659_I2S_MS_S;
3383 rt5659->master[dai->id] = 0;
3384 break;
3385 default:
3386 return -EINVAL;
3387 }
3388
3389 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3390 case SND_SOC_DAIFMT_NB_NF:
3391 break;
3392 case SND_SOC_DAIFMT_IB_NF:
3393 reg_val |= RT5659_I2S_BP_INV;
3394 break;
3395 default:
3396 return -EINVAL;
3397 }
3398
3399 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3400 case SND_SOC_DAIFMT_I2S:
3401 break;
3402 case SND_SOC_DAIFMT_LEFT_J:
3403 reg_val |= RT5659_I2S_DF_LEFT;
3404 break;
3405 case SND_SOC_DAIFMT_DSP_A:
3406 reg_val |= RT5659_I2S_DF_PCM_A;
3407 break;
3408 case SND_SOC_DAIFMT_DSP_B:
3409 reg_val |= RT5659_I2S_DF_PCM_B;
3410 break;
3411 default:
3412 return -EINVAL;
3413 }
3414
3415 switch (dai->id) {
3416 case RT5659_AIF1:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3417 snd_soc_component_update_bits(component, RT5659_I2S1_SDP,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3418 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3419 RT5659_I2S_DF_MASK, reg_val);
3420 break;
3421 case RT5659_AIF2:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3422 snd_soc_component_update_bits(component, RT5659_I2S2_SDP,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3423 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3424 RT5659_I2S_DF_MASK, reg_val);
3425 break;
3426 case RT5659_AIF3:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3427 snd_soc_component_update_bits(component, RT5659_I2S3_SDP,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3428 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3429 RT5659_I2S_DF_MASK, reg_val);
3430 break;
3431 default:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3432 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3433 return -EINVAL;
3434 }
3435 return 0;
3436}
3437
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3438static int rt5659_set_component_sysclk(struct snd_soc_component *component, int clk_id,
Bard Liaofe01e5e2017-10-16 19:15:15 +0800[diff] [blame]3439 int source, unsigned int freq, int dir)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3440{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3441 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3442 unsigned int reg_val = 0;
3443
3444 if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src)
3445 return 0;
3446
3447 switch (clk_id) {
3448 case RT5659_SCLK_S_MCLK:
3449 reg_val |= RT5659_SCLK_SRC_MCLK;
3450 break;
3451 case RT5659_SCLK_S_PLL1:
3452 reg_val |= RT5659_SCLK_SRC_PLL1;
3453 break;
3454 case RT5659_SCLK_S_RCCLK:
3455 reg_val |= RT5659_SCLK_SRC_RCCLK;
3456 break;
3457 default:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3458 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3459 return -EINVAL;
3460 }
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3461 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3462 RT5659_SCLK_SRC_MASK, reg_val);
3463 rt5659->sysclk = freq;
3464 rt5659->sysclk_src = clk_id;
3465
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3466 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
Bard Liaofe01e5e2017-10-16 19:15:15 +0800[diff] [blame]3467 freq, clk_id);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3468
3469 return 0;
3470}
3471
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3472static int rt5659_set_component_pll(struct snd_soc_component *component, int pll_id,
Bard Liaoc8a04b52017-10-16 19:15:16 +0800[diff] [blame]3473 int source, unsigned int freq_in,
3474 unsigned int freq_out)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3475{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3476 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3477 struct rl6231_pll_code pll_code;
3478 int ret;
3479
Bard Liaoc8a04b52017-10-16 19:15:16 +0800[diff] [blame]3480 if (source == rt5659->pll_src && freq_in == rt5659->pll_in &&
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3481 freq_out == rt5659->pll_out)
3482 return 0;
3483
3484 if (!freq_in || !freq_out) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3485 dev_dbg(component->dev, "PLL disabled\n");
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3486
3487 rt5659->pll_in = 0;
3488 rt5659->pll_out = 0;
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3489 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3490 RT5659_SCLK_SRC_MASK, RT5659_SCLK_SRC_MCLK);
3491 return 0;
3492 }
3493
Bard Liaoc8a04b52017-10-16 19:15:16 +0800[diff] [blame]3494 switch (source) {
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3495 case RT5659_PLL1_S_MCLK:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3496 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3497 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_MCLK);
3498 break;
3499 case RT5659_PLL1_S_BCLK1:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3500 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3501 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK1);
3502 break;
3503 case RT5659_PLL1_S_BCLK2:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3504 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3505 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK2);
3506 break;
3507 case RT5659_PLL1_S_BCLK3:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3508 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3509 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK3);
3510 break;
3511 default:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3512 dev_err(component->dev, "Unknown PLL source %d\n", source);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3513 return -EINVAL;
3514 }
3515
3516 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
3517 if (ret < 0) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3518 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3519 return ret;
3520 }
3521
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3522 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3523 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3524 pll_code.n_code, pll_code.k_code);
3525
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3526 snd_soc_component_write(component, RT5659_PLL_CTRL_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3527 pll_code.n_code << RT5659_PLL_N_SFT | pll_code.k_code);
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3528 snd_soc_component_write(component, RT5659_PLL_CTRL_2,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3529 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5659_PLL_M_SFT |
3530 pll_code.m_bp << RT5659_PLL_M_BP_SFT);
3531
3532 rt5659->pll_in = freq_in;
3533 rt5659->pll_out = freq_out;
Bard Liaoc8a04b52017-10-16 19:15:16 +0800[diff] [blame]3534 rt5659->pll_src = source;
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3535
3536 return 0;
3537}
3538
3539static int rt5659_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3540 unsigned int rx_mask, int slots, int slot_width)
3541{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3542 struct snd_soc_component *component = dai->component;
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3543 unsigned int val = 0;
3544
3545 if (rx_mask || tx_mask)
3546 val |= (1 << 15);
3547
3548 switch (slots) {
3549 case 4:
3550 val |= (1 << 10);
3551 val |= (1 << 8);
3552 break;
3553 case 6:
3554 val |= (2 << 10);
3555 val |= (2 << 8);
3556 break;
3557 case 8:
3558 val |= (3 << 10);
3559 val |= (3 << 8);
3560 break;
3561 case 2:
3562 break;
3563 default:
3564 return -EINVAL;
3565 }
3566
3567 switch (slot_width) {
3568 case 20:
3569 val |= (1 << 6);
3570 val |= (1 << 4);
3571 break;
3572 case 24:
3573 val |= (2 << 6);
3574 val |= (2 << 4);
3575 break;
3576 case 32:
3577 val |= (3 << 6);
3578 val |= (3 << 4);
3579 break;
3580 case 16:
3581 break;
3582 default:
3583 return -EINVAL;
3584 }
3585
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3586 snd_soc_component_update_bits(component, RT5659_TDM_CTRL_1, 0x8ff0, val);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3587
3588 return 0;
3589}
3590
3591static int rt5659_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3592{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3593 struct snd_soc_component *component = dai->component;
3594 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3595
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3596 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3597
3598 rt5659->bclk[dai->id] = ratio;
3599
3600 if (ratio == 64) {
3601 switch (dai->id) {
3602 case RT5659_AIF2:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3603 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3604 RT5659_I2S_BCLK_MS2_MASK,
3605 RT5659_I2S_BCLK_MS2_64);
3606 break;
3607 case RT5659_AIF3:
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3608 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3609 RT5659_I2S_BCLK_MS3_MASK,
3610 RT5659_I2S_BCLK_MS3_64);
3611 break;
3612 }
3613 }
3614
3615 return 0;
3616}
3617
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3618static int rt5659_set_bias_level(struct snd_soc_component *component,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3619 enum snd_soc_bias_level level)
3620{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3621 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3622 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Nicolin Chenc6f87692016-07-28 14:57:16 -0700[diff] [blame]3623 int ret;
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3624
3625 switch (level) {
3626 case SND_SOC_BIAS_PREPARE:
3627 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
3628 RT5659_DIG_GATE_CTRL, RT5659_DIG_GATE_CTRL);
3629 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
3630 RT5659_PWR_LDO, RT5659_PWR_LDO);
3631 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3632 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2,
3633 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2);
3634 msleep(20);
3635 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3636 RT5659_PWR_FV1 | RT5659_PWR_FV2,
3637 RT5659_PWR_FV1 | RT5659_PWR_FV2);
3638 break;
3639
Nicolin Chenc6f87692016-07-28 14:57:16 -0700[diff] [blame]3640 case SND_SOC_BIAS_STANDBY:
3641 if (dapm->bias_level == SND_SOC_BIAS_OFF) {
3642 ret = clk_prepare_enable(rt5659->mclk);
3643 if (ret) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3644 dev_err(component->dev,
Nicolin Chenc6f87692016-07-28 14:57:16 -0700[diff] [blame]3645 "failed to enable MCLK: %d\n", ret);
3646 return ret;
3647 }
3648 }
3649 break;
3650
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3651 case SND_SOC_BIAS_OFF:
3652 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
3653 RT5659_PWR_LDO, 0);
3654 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3655 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2
3656 | RT5659_PWR_FV1 | RT5659_PWR_FV2,
3657 RT5659_PWR_MB | RT5659_PWR_VREF2);
3658 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
3659 RT5659_DIG_GATE_CTRL, 0);
Nicolin Chenc6f87692016-07-28 14:57:16 -0700[diff] [blame]3660 clk_disable_unprepare(rt5659->mclk);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3661 break;
3662
3663 default:
3664 break;
3665 }
3666
3667 return 0;
3668}
3669
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3670static int rt5659_probe(struct snd_soc_component *component)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3671{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3672 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3673
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3674 rt5659->component = component;
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3675
3676 return 0;
3677}
3678
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3679static void rt5659_remove(struct snd_soc_component *component)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3680{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3681 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3682
3683 regmap_write(rt5659->regmap, RT5659_RESET, 0);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3684}
3685
3686#ifdef CONFIG_PM
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3687static int rt5659_suspend(struct snd_soc_component *component)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3688{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3689 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3690
3691 regcache_cache_only(rt5659->regmap, true);
3692 regcache_mark_dirty(rt5659->regmap);
3693 return 0;
3694}
3695
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3696static int rt5659_resume(struct snd_soc_component *component)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3697{
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3698 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3699
3700 regcache_cache_only(rt5659->regmap, false);
3701 regcache_sync(rt5659->regmap);
3702
3703 return 0;
3704}
3705#else
3706#define rt5659_suspend NULL
3707#define rt5659_resume NULL
3708#endif
3709
3710#define RT5659_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3711#define RT5659_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3712 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3713
3714static const struct snd_soc_dai_ops rt5659_aif_dai_ops = {
3715 .hw_params = rt5659_hw_params,
3716 .set_fmt = rt5659_set_dai_fmt,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3717 .set_tdm_slot = rt5659_set_tdm_slot,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3718 .set_bclk_ratio = rt5659_set_bclk_ratio,
3719};
3720
3721static struct snd_soc_dai_driver rt5659_dai[] = {
3722 {
3723 .name = "rt5659-aif1",
3724 .id = RT5659_AIF1,
3725 .playback = {
3726 .stream_name = "AIF1 Playback",
3727 .channels_min = 1,
3728 .channels_max = 2,
3729 .rates = RT5659_STEREO_RATES,
3730 .formats = RT5659_FORMATS,
3731 },
3732 .capture = {
3733 .stream_name = "AIF1 Capture",
3734 .channels_min = 1,
3735 .channels_max = 2,
3736 .rates = RT5659_STEREO_RATES,
3737 .formats = RT5659_FORMATS,
3738 },
3739 .ops = &rt5659_aif_dai_ops,
3740 },
3741 {
3742 .name = "rt5659-aif2",
3743 .id = RT5659_AIF2,
3744 .playback = {
3745 .stream_name = "AIF2 Playback",
3746 .channels_min = 1,
3747 .channels_max = 2,
3748 .rates = RT5659_STEREO_RATES,
3749 .formats = RT5659_FORMATS,
3750 },
3751 .capture = {
3752 .stream_name = "AIF2 Capture",
3753 .channels_min = 1,
3754 .channels_max = 2,
3755 .rates = RT5659_STEREO_RATES,
3756 .formats = RT5659_FORMATS,
3757 },
3758 .ops = &rt5659_aif_dai_ops,
3759 },
3760 {
3761 .name = "rt5659-aif3",
3762 .id = RT5659_AIF3,
3763 .playback = {
3764 .stream_name = "AIF3 Playback",
3765 .channels_min = 1,
3766 .channels_max = 2,
3767 .rates = RT5659_STEREO_RATES,
3768 .formats = RT5659_FORMATS,
3769 },
3770 .capture = {
3771 .stream_name = "AIF3 Capture",
3772 .channels_min = 1,
3773 .channels_max = 2,
3774 .rates = RT5659_STEREO_RATES,
3775 .formats = RT5659_FORMATS,
3776 },
3777 .ops = &rt5659_aif_dai_ops,
3778 },
3779};
3780
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3781static const struct snd_soc_component_driver soc_component_dev_rt5659 = {
3782 .probe = rt5659_probe,
3783 .remove = rt5659_remove,
3784 .suspend = rt5659_suspend,
3785 .resume = rt5659_resume,
3786 .set_bias_level = rt5659_set_bias_level,
3787 .controls = rt5659_snd_controls,
3788 .num_controls = ARRAY_SIZE(rt5659_snd_controls),
3789 .dapm_widgets = rt5659_dapm_widgets,
3790 .num_dapm_widgets = ARRAY_SIZE(rt5659_dapm_widgets),
3791 .dapm_routes = rt5659_dapm_routes,
3792 .num_dapm_routes = ARRAY_SIZE(rt5659_dapm_routes),
3793 .set_sysclk = rt5659_set_component_sysclk,
3794 .set_pll = rt5659_set_component_pll,
3795 .use_pmdown_time = 1,
3796 .endianness = 1,
3797 .non_legacy_dai_naming = 1,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3798};
3799
3800
3801static const struct regmap_config rt5659_regmap = {
3802 .reg_bits = 16,
3803 .val_bits = 16,
3804 .max_register = 0x0400,
3805 .volatile_reg = rt5659_volatile_register,
3806 .readable_reg = rt5659_readable_register,
3807 .cache_type = REGCACHE_RBTREE,
3808 .reg_defaults = rt5659_reg,
3809 .num_reg_defaults = ARRAY_SIZE(rt5659_reg),
3810};
3811
3812static const struct i2c_device_id rt5659_i2c_id[] = {
3813 { "rt5658", 0 },
3814 { "rt5659", 0 },
3815 { }
3816};
3817MODULE_DEVICE_TABLE(i2c, rt5659_i2c_id);
3818
3819static int rt5659_parse_dt(struct rt5659_priv *rt5659, struct device *dev)
3820{
3821 rt5659->pdata.in1_diff = device_property_read_bool(dev,
3822 "realtek,in1-differential");
3823 rt5659->pdata.in3_diff = device_property_read_bool(dev,
3824 "realtek,in3-differential");
3825 rt5659->pdata.in4_diff = device_property_read_bool(dev,
3826 "realtek,in4-differential");
3827
3828
3829 device_property_read_u32(dev, "realtek,dmic1-data-pin",
3830 &rt5659->pdata.dmic1_data_pin);
3831 device_property_read_u32(dev, "realtek,dmic2-data-pin",
3832 &rt5659->pdata.dmic2_data_pin);
3833 device_property_read_u32(dev, "realtek,jd-src",
3834 &rt5659->pdata.jd_src);
3835
3836 return 0;
3837}
3838
3839static void rt5659_calibrate(struct rt5659_priv *rt5659)
3840{
3841 int value, count;
3842
3843 /* Calibrate HPO Start */
3844 /* Fine tune HP Performance */
3845 regmap_write(rt5659->regmap, RT5659_BIAS_CUR_CTRL_8, 0xa502);
3846 regmap_write(rt5659->regmap, RT5659_CHOP_DAC, 0x3030);
3847
3848 regmap_write(rt5659->regmap, RT5659_PRE_DIV_1, 0xef00);
3849 regmap_write(rt5659->regmap, RT5659_PRE_DIV_2, 0xeffc);
3850 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0280);
3851 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0001);
3852 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x8000);
3853
3854 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xaa7e);
3855 msleep(60);
3856 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe7e);
3857 msleep(50);
3858 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0004);
3859 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0400);
3860 msleep(50);
3861 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0080);
3862 usleep_range(10000, 10005);
3863 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0009);
3864 msleep(50);
3865 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0f80);
3866 msleep(50);
3867 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0e16);
3868 msleep(50);
3869
3870 /* Enalbe K ADC Power And Clock */
3871 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0505);
3872 msleep(50);
3873 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0184);
3874 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x3c05);
3875 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c1);
3876
3877 /* K Headphone */
3878 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3879 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x5100);
3880 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0014);
3881 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0xd100);
3882 msleep(60);
3883
3884 /* Manual K ADC Offset */
3885 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3886 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4900);
3887 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0016);
3888 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
3889 0x8000, 0x8000);
3890
3891 count = 0;
3892 while (true) {
3893 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
3894 if (value & 0x8000)
3895 usleep_range(10000, 10005);
3896 else
3897 break;
3898
3899 if (count > 30) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3900 dev_err(rt5659->component->dev,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3901 "HP Calibration 1 Failure\n");
3902 return;
3903 }
3904
3905 count++;
3906 }
3907
3908 /* Manual K Internal Path Offset */
3909 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3910 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x0000);
3911 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4500);
3912 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x001f);
3913 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
3914 0x8000, 0x8000);
3915
3916 count = 0;
3917 while (true) {
3918 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
3919 if (value & 0x8000)
3920 usleep_range(10000, 10005);
3921 else
3922 break;
3923
3924 if (count > 85) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3925 dev_err(rt5659->component->dev,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3926 "HP Calibration 2 Failure\n");
3927 return;
3928 }
3929
3930 count++;
3931 }
3932
3933 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0000);
3934 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
3935 /* Calibrate HPO End */
3936
3937 /* Calibrate SPO Start */
3938 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
3939 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0260);
3940 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x3000);
3941 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0xc000);
3942 regmap_write(rt5659->regmap, RT5659_A_DAC_MUX, 0x000c);
3943 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x8000);
3944 regmap_write(rt5659->regmap, RT5659_SPO_VOL, 0x0808);
3945 regmap_write(rt5659->regmap, RT5659_SPK_L_MIXER, 0x001e);
3946 regmap_write(rt5659->regmap, RT5659_SPK_R_MIXER, 0x001e);
3947 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0803);
3948 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0554);
3949 regmap_write(rt5659->regmap, RT5659_SPO_AMP_GAIN, 0x1103);
3950
3951 /* Enalbe K ADC Power And Clock */
3952 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0909);
3953 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x0001,
3954 0x0001);
3955
3956 /* Start Calibration */
3957 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
3958 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x0021);
3959 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 0x3e80);
3960 regmap_update_bits(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1,
3961 0x8000, 0x8000);
3962
3963 count = 0;
3964 while (true) {
3965 regmap_read(rt5659->regmap,
3966 RT5659_SPK_DC_CAILB_CTRL_1, &value);
3967 if (value & 0x8000)
3968 usleep_range(10000, 10005);
3969 else
3970 break;
3971
3972 if (count > 10) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]3973 dev_err(rt5659->component->dev,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]3974 "SPK Calibration Failure\n");
3975 return;
3976 }
3977
3978 count++;
3979 }
3980 /* Calibrate SPO End */
3981
3982 /* Calibrate MONO Start */
3983 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0000);
3984 regmap_write(rt5659->regmap, RT5659_MONOMIX_IN_GAIN, 0x021f);
3985 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0x480a);
3986 /* MONO NG2 GAIN 5dB */
3987 regmap_write(rt5659->regmap, RT5659_MONO_GAIN, 0x0003);
3988 regmap_write(rt5659->regmap, RT5659_MONO_NG2_CTRL_5, 0x0009);
3989
3990 /* Start Calibration */
3991 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x000f);
3992 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
3993 regmap_update_bits(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
3994 0x8000, 0x8000);
3995
3996 count = 0;
3997 while (true) {
3998 regmap_read(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
3999 &value);
4000 if (value & 0x8000)
4001 usleep_range(10000, 10005);
4002 else
4003 break;
4004
4005 if (count > 35) {
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]4006 dev_err(rt5659->component->dev,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4007 "Mono Calibration Failure\n");
4008 return;
4009 }
4010
4011 count++;
4012 }
4013
4014 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
4015 /* Calibrate MONO End */
4016
4017 /* Power Off */
4018 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0808);
4019 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0000);
4020 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x2005);
4021 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
4022 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0000);
4023 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0011);
4024 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0150);
4025 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe3e);
4026 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0xc80a);
4027 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
4028 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x0000);
4029 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0x0000);
4030 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0000);
4031 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0000);
4032 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0x003e);
4033 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0060);
4034 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
4035 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x0000);
4036 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0080);
4037 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x8080);
4038 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
4039}
4040
oder_chiou@realtek.com041e74b2018-02-05 18:29:56 +0800[diff] [blame]4041void rt5659_intel_hd_header_probe_setup(struct rt5659_priv *rt5659)
4042{
4043 int value;
4044
4045 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value);
4046 if (!(value & 0x8)) {
4047 rt5659->hda_hp_plugged = true;
4048 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
4049 0x10, 0x0);
4050 } else {
4051 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
4052 0x10, 0x10);
4053 }
4054
4055 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
4056 RT5659_PWR_VREF2 | RT5659_PWR_MB,
4057 RT5659_PWR_VREF2 | RT5659_PWR_MB);
4058 msleep(20);
4059 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
4060 RT5659_PWR_FV2, RT5659_PWR_FV2);
4061
4062 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_3, RT5659_PWR_LDO2,
4063 RT5659_PWR_LDO2);
4064 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_2, RT5659_PWR_MB1,
4065 RT5659_PWR_MB1);
4066 regmap_update_bits(rt5659->regmap, RT5659_PWR_VOL, RT5659_PWR_MIC_DET,
4067 RT5659_PWR_MIC_DET);
4068 msleep(20);
4069
4070 regmap_update_bits(rt5659->regmap, RT5659_4BTN_IL_CMD_2,
4071 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN);
4072 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
4073 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value);
4074 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
4075
4076 if (value & 0x2000) {
4077 rt5659->hda_mic_plugged = true;
4078 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
4079 0x2, 0x2);
4080 } else {
4081 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
4082 0x2, 0x0);
4083 }
4084
4085 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
4086 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN);
4087}
4088
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4089static int rt5659_i2c_probe(struct i2c_client *i2c,
4090 const struct i2c_device_id *id)
4091{
4092 struct rt5659_platform_data *pdata = dev_get_platdata(&i2c->dev);
4093 struct rt5659_priv *rt5659;
4094 int ret;
4095 unsigned int val;
4096
4097 rt5659 = devm_kzalloc(&i2c->dev, sizeof(struct rt5659_priv),
4098 GFP_KERNEL);
4099
4100 if (rt5659 == NULL)
4101 return -ENOMEM;
4102
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4103 i2c_set_clientdata(i2c, rt5659);
4104
4105 if (pdata)
4106 rt5659->pdata = *pdata;
4107 else
4108 rt5659_parse_dt(rt5659, &i2c->dev);
4109
4110 rt5659->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, "ldo1-en",
4111 GPIOD_OUT_HIGH);
4112 if (IS_ERR(rt5659->gpiod_ldo1_en))
4113 dev_warn(&i2c->dev, "Request ldo1-en GPIO failed\n");
4114
4115 rt5659->gpiod_reset = devm_gpiod_get_optional(&i2c->dev, "reset",
4116 GPIOD_OUT_HIGH);
4117
4118 /* Sleep for 300 ms miniumum */
Nicholas Mc Guire11b4ad92017-01-12 14:14:20 +0100[diff] [blame]4119 msleep(300);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4120
4121 rt5659->regmap = devm_regmap_init_i2c(i2c, &rt5659_regmap);
4122 if (IS_ERR(rt5659->regmap)) {
4123 ret = PTR_ERR(rt5659->regmap);
4124 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4125 ret);
4126 return ret;
4127 }
4128
4129 regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val);
4130 if (val != DEVICE_ID) {
4131 dev_err(&i2c->dev,
4132 "Device with ID register %x is not rt5659\n", val);
4133 return -ENODEV;
4134 }
4135
4136 regmap_write(rt5659->regmap, RT5659_RESET, 0);
4137
Nicolin Chenc6f87692016-07-28 14:57:16 -0700[diff] [blame]4138 /* Check if MCLK provided */
4139 rt5659->mclk = devm_clk_get(&i2c->dev, "mclk");
4140 if (IS_ERR(rt5659->mclk)) {
4141 if (PTR_ERR(rt5659->mclk) != -ENOENT)
4142 return PTR_ERR(rt5659->mclk);
4143 /* Otherwise mark the mclk pointer to NULL */
4144 rt5659->mclk = NULL;
4145 }
4146
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4147 rt5659_calibrate(rt5659);
4148
4149 /* line in diff mode*/
4150 if (rt5659->pdata.in1_diff)
4151 regmap_update_bits(rt5659->regmap, RT5659_IN1_IN2,
4152 RT5659_IN1_DF_MASK, RT5659_IN1_DF_MASK);
4153 if (rt5659->pdata.in3_diff)
4154 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
4155 RT5659_IN3_DF_MASK, RT5659_IN3_DF_MASK);
4156 if (rt5659->pdata.in4_diff)
4157 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
4158 RT5659_IN4_DF_MASK, RT5659_IN4_DF_MASK);
4159
4160 /* DMIC pin*/
4161 if (rt5659->pdata.dmic1_data_pin != RT5659_DMIC1_NULL ||
4162 rt5659->pdata.dmic2_data_pin != RT5659_DMIC2_NULL) {
4163 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4164 RT5659_GP2_PIN_MASK, RT5659_GP2_PIN_DMIC1_SCL);
4165
4166 switch (rt5659->pdata.dmic1_data_pin) {
4167 case RT5659_DMIC1_DATA_IN2N:
4168 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4169 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_IN2N);
4170 break;
4171
4172 case RT5659_DMIC1_DATA_GPIO5:
4173 regmap_update_bits(rt5659->regmap,
4174 RT5659_GPIO_CTRL_3,
4175 RT5659_I2S2_PIN_MASK,
4176 RT5659_I2S2_PIN_GPIO);
4177 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4178 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO5);
4179 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4180 RT5659_GP5_PIN_MASK, RT5659_GP5_PIN_DMIC1_SDA);
4181 break;
4182
4183 case RT5659_DMIC1_DATA_GPIO9:
4184 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4185 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO9);
4186 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4187 RT5659_GP9_PIN_MASK, RT5659_GP9_PIN_DMIC1_SDA);
4188 break;
4189
4190 case RT5659_DMIC1_DATA_GPIO11:
4191 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4192 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO11);
4193 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4194 RT5659_GP11_PIN_MASK,
4195 RT5659_GP11_PIN_DMIC1_SDA);
4196 break;
4197
4198 default:
4199 dev_dbg(&i2c->dev, "no DMIC1\n");
4200 break;
4201 }
4202
4203 switch (rt5659->pdata.dmic2_data_pin) {
4204 case RT5659_DMIC2_DATA_IN2P:
4205 regmap_update_bits(rt5659->regmap,
4206 RT5659_DMIC_CTRL_1,
4207 RT5659_DMIC_2_DP_MASK,
4208 RT5659_DMIC_2_DP_IN2P);
4209 break;
4210
4211 case RT5659_DMIC2_DATA_GPIO6:
4212 regmap_update_bits(rt5659->regmap,
4213 RT5659_DMIC_CTRL_1,
4214 RT5659_DMIC_2_DP_MASK,
4215 RT5659_DMIC_2_DP_GPIO6);
4216 regmap_update_bits(rt5659->regmap,
4217 RT5659_GPIO_CTRL_1,
4218 RT5659_GP6_PIN_MASK,
4219 RT5659_GP6_PIN_DMIC2_SDA);
4220 break;
4221
4222 case RT5659_DMIC2_DATA_GPIO10:
4223 regmap_update_bits(rt5659->regmap,
4224 RT5659_DMIC_CTRL_1,
4225 RT5659_DMIC_2_DP_MASK,
4226 RT5659_DMIC_2_DP_GPIO10);
4227 regmap_update_bits(rt5659->regmap,
4228 RT5659_GPIO_CTRL_1,
4229 RT5659_GP10_PIN_MASK,
4230 RT5659_GP10_PIN_DMIC2_SDA);
4231 break;
4232
4233 case RT5659_DMIC2_DATA_GPIO12:
4234 regmap_update_bits(rt5659->regmap,
4235 RT5659_DMIC_CTRL_1,
4236 RT5659_DMIC_2_DP_MASK,
4237 RT5659_DMIC_2_DP_GPIO12);
4238 regmap_update_bits(rt5659->regmap,
4239 RT5659_GPIO_CTRL_1,
4240 RT5659_GP12_PIN_MASK,
4241 RT5659_GP12_PIN_DMIC2_SDA);
4242 break;
4243
4244 default:
4245 dev_dbg(&i2c->dev, "no DMIC2\n");
4246 break;
4247
4248 }
4249 } else {
4250 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4251 RT5659_GP2_PIN_MASK | RT5659_GP5_PIN_MASK |
4252 RT5659_GP9_PIN_MASK | RT5659_GP11_PIN_MASK |
4253 RT5659_GP6_PIN_MASK | RT5659_GP10_PIN_MASK |
4254 RT5659_GP12_PIN_MASK,
4255 RT5659_GP2_PIN_GPIO2 | RT5659_GP5_PIN_GPIO5 |
4256 RT5659_GP9_PIN_GPIO9 | RT5659_GP11_PIN_GPIO11 |
4257 RT5659_GP6_PIN_GPIO6 | RT5659_GP10_PIN_GPIO10 |
4258 RT5659_GP12_PIN_GPIO12);
4259 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4260 RT5659_DMIC_1_DP_MASK | RT5659_DMIC_2_DP_MASK,
4261 RT5659_DMIC_1_DP_IN2N | RT5659_DMIC_2_DP_IN2P);
4262 }
4263
4264 switch (rt5659->pdata.jd_src) {
4265 case RT5659_JD3:
4266 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0xa880);
4267 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x9000);
4268 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_1, 0xc800);
4269 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
4270 RT5659_PWR_MB, RT5659_PWR_MB);
4271 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_2, 0x0001);
4272 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_2, 0x0040);
oder_chiou@realtek.com041e74b2018-02-05 18:29:56 +0800[diff] [blame]4273 INIT_DELAYED_WORK(&rt5659->jack_detect_work,
4274 rt5659_jack_detect_work);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4275 break;
oder_chiou@realtek.com041e74b2018-02-05 18:29:56 +0800[diff] [blame]4276 case RT5659_JD_HDA_HEADER:
4277 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_3, 0x8000);
4278 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x0900);
4279 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0x70c0);
4280 regmap_write(rt5659->regmap, RT5659_JD_CTRL_1, 0x2000);
4281 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_1, 0x0040);
4282 INIT_DELAYED_WORK(&rt5659->jack_detect_work,
4283 rt5659_jack_detect_intel_hd_header);
4284 rt5659_intel_hd_header_probe_setup(rt5659);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4285 break;
4286 default:
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4287 break;
4288 }
4289
Axel Lin1ca2cf82016-01-12 15:55:17 +0800[diff] [blame]4290 if (i2c->irq) {
4291 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4292 rt5659_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4293 | IRQF_ONESHOT, "rt5659", rt5659);
4294 if (ret)
4295 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4296
Nicolin Chen38d16f72016-08-24 12:03:39 -0700[diff] [blame]4297 /* Enable IRQ output for GPIO1 pin any way */
4298 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4299 RT5659_GP1_PIN_MASK, RT5659_GP1_PIN_IRQ);
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4300 }
4301
Kuninori Morimotode86a332018-01-29 03:45:50 +0000[diff] [blame^]4302 return devm_snd_soc_register_component(&i2c->dev,
4303 &soc_component_dev_rt5659,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4304 rt5659_dai, ARRAY_SIZE(rt5659_dai));
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4305}
4306
Axel Linc62db3d2016-01-12 15:53:46 +0800[diff] [blame]4307static void rt5659_i2c_shutdown(struct i2c_client *client)
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4308{
4309 struct rt5659_priv *rt5659 = i2c_get_clientdata(client);
4310
4311 regmap_write(rt5659->regmap, RT5659_RESET, 0);
4312}
4313
Arnd Bergmann2256b8d2016-01-20 12:46:24 +0100[diff] [blame]4314#ifdef CONFIG_OF
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4315static const struct of_device_id rt5659_of_match[] = {
4316 { .compatible = "realtek,rt5658", },
4317 { .compatible = "realtek,rt5659", },
Arnd Bergmann2256b8d2016-01-20 12:46:24 +0100[diff] [blame]4318 { },
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4319};
Arnd Bergmann2256b8d2016-01-20 12:46:24 +0100[diff] [blame]4320MODULE_DEVICE_TABLE(of, rt5659_of_match);
4321#endif
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4322
Arnd Bergmann2256b8d2016-01-20 12:46:24 +0100[diff] [blame]4323#ifdef CONFIG_ACPI
Arvind Yadavf36544a2017-07-23 22:53:26 +0530[diff] [blame]4324static const struct acpi_device_id rt5659_acpi_match[] = {
Arnd Bergmann2256b8d2016-01-20 12:46:24 +0100[diff] [blame]4325 { "10EC5658", 0, },
4326 { "10EC5659", 0, },
4327 { },
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4328};
4329MODULE_DEVICE_TABLE(acpi, rt5659_acpi_match);
Arnd Bergmann2256b8d2016-01-20 12:46:24 +0100[diff] [blame]4330#endif
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4331
Nicholas Mc Guire0230f082017-01-12 14:14:41 +0100[diff] [blame]4332static struct i2c_driver rt5659_i2c_driver = {
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4333 .driver = {
4334 .name = "rt5659",
Arnd Bergmann2256b8d2016-01-20 12:46:24 +0100[diff] [blame]4335 .of_match_table = of_match_ptr(rt5659_of_match),
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4336 .acpi_match_table = ACPI_PTR(rt5659_acpi_match),
4337 },
4338 .probe = rt5659_i2c_probe,
Bard Liaod3cb2de2015-11-09 14:47:34 +0800[diff] [blame]4339 .shutdown = rt5659_i2c_shutdown,
4340 .id_table = rt5659_i2c_id,
4341};
4342module_i2c_driver(rt5659_i2c_driver);
4343
4344MODULE_DESCRIPTION("ASoC RT5659 driver");
4345MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4346MODULE_LICENSE("GPL v2");