Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 1 | /* |
| 2 | * NVDIMM Firmware Interface Table - NFIT |
| 3 | * |
| 4 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of version 2 of the GNU General Public License as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | * General Public License for more details. |
| 14 | */ |
| 15 | #ifndef __NFIT_H__ |
| 16 | #define __NFIT_H__ |
Dan Williams | 7ae0fa43 | 2016-02-19 12:16:34 -0800 | [diff] [blame] | 17 | #include <linux/workqueue.h> |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 18 | #include <linux/libnvdimm.h> |
Vishal Verma | 6839a6d | 2016-07-23 21:51:21 -0700 | [diff] [blame] | 19 | #include <linux/ndctl.h> |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 20 | #include <linux/types.h> |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 21 | #include <linux/acpi.h> |
| 22 | #include <acpi/acuuid.h> |
| 23 | |
Dan Williams | 31eca76 | 2016-04-28 16:23:43 -0700 | [diff] [blame] | 24 | /* ACPI 6.1 */ |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 25 | #define UUID_NFIT_BUS "2f10e7a4-9e91-11e4-89d3-123b93f75cba" |
Dan Williams | 31eca76 | 2016-04-28 16:23:43 -0700 | [diff] [blame] | 26 | |
Dan Williams | 11e1427 | 2017-10-20 15:39:43 -0700 | [diff] [blame] | 27 | /* http://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf */ |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 28 | #define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66" |
Dan Williams | 31eca76 | 2016-04-28 16:23:43 -0700 | [diff] [blame] | 29 | |
| 30 | /* https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/ */ |
| 31 | #define UUID_NFIT_DIMM_N_HPE1 "9002c334-acf3-4c0e-9642-a235f0d53bc6" |
| 32 | #define UUID_NFIT_DIMM_N_HPE2 "5008664b-b758-41a0-a03c-27c2f2d04f7e" |
| 33 | |
stuart hayes | e02fb72 | 2016-05-26 11:38:41 -0500 | [diff] [blame] | 34 | /* https://msdn.microsoft.com/library/windows/hardware/mt604741 */ |
| 35 | #define UUID_NFIT_DIMM_N_MSFT "1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05" |
| 36 | |
Dan Williams | 5813882 | 2015-06-23 20:08:34 -0400 | [diff] [blame] | 37 | #define ACPI_NFIT_MEM_FAILED_MASK (ACPI_NFIT_MEM_SAVE_FAILED \ |
| 38 | | ACPI_NFIT_MEM_RESTORE_FAILED | ACPI_NFIT_MEM_FLUSH_FAILED \ |
Dan Williams | 1499934 | 2017-04-13 19:46:36 -0700 | [diff] [blame] | 39 | | ACPI_NFIT_MEM_NOT_ARMED | ACPI_NFIT_MEM_MAP_FAILED) |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 40 | |
Dan Williams | 11e1427 | 2017-10-20 15:39:43 -0700 | [diff] [blame] | 41 | #define NVDIMM_FAMILY_MAX NVDIMM_FAMILY_MSFT |
| 42 | |
Dan Williams | b9b1504 | 2017-10-29 12:13:07 -0700 | [diff] [blame] | 43 | #define NVDIMM_STANDARD_CMDMASK \ |
| 44 | (1 << ND_CMD_SMART | 1 << ND_CMD_SMART_THRESHOLD | 1 << ND_CMD_DIMM_FLAGS \ |
| 45 | | 1 << ND_CMD_GET_CONFIG_SIZE | 1 << ND_CMD_GET_CONFIG_DATA \ |
| 46 | | 1 << ND_CMD_SET_CONFIG_DATA | 1 << ND_CMD_VENDOR_EFFECT_LOG_SIZE \ |
| 47 | | 1 << ND_CMD_VENDOR_EFFECT_LOG | 1 << ND_CMD_VENDOR) |
| 48 | |
Dan Williams | 11e1427 | 2017-10-20 15:39:43 -0700 | [diff] [blame] | 49 | /* |
| 50 | * Command numbers that the kernel needs to know about to handle |
| 51 | * non-default DSM revision ids |
| 52 | */ |
| 53 | enum nvdimm_family_cmds { |
Dan Williams | 79ab67e | 2017-11-15 10:10:48 -0800 | [diff] [blame] | 54 | NVDIMM_INTEL_LATCH_SHUTDOWN = 10, |
Dan Williams | 11e1427 | 2017-10-20 15:39:43 -0700 | [diff] [blame] | 55 | NVDIMM_INTEL_GET_MODES = 11, |
| 56 | NVDIMM_INTEL_GET_FWINFO = 12, |
| 57 | NVDIMM_INTEL_START_FWUPDATE = 13, |
| 58 | NVDIMM_INTEL_SEND_FWUPDATE = 14, |
| 59 | NVDIMM_INTEL_FINISH_FWUPDATE = 15, |
| 60 | NVDIMM_INTEL_QUERY_FWUPDATE = 16, |
| 61 | NVDIMM_INTEL_SET_THRESHOLD = 17, |
| 62 | NVDIMM_INTEL_INJECT_ERROR = 18, |
| 63 | }; |
| 64 | |
| 65 | #define NVDIMM_INTEL_CMDMASK \ |
| 66 | (NVDIMM_STANDARD_CMDMASK | 1 << NVDIMM_INTEL_GET_MODES \ |
| 67 | | 1 << NVDIMM_INTEL_GET_FWINFO | 1 << NVDIMM_INTEL_START_FWUPDATE \ |
| 68 | | 1 << NVDIMM_INTEL_SEND_FWUPDATE | 1 << NVDIMM_INTEL_FINISH_FWUPDATE \ |
| 69 | | 1 << NVDIMM_INTEL_QUERY_FWUPDATE | 1 << NVDIMM_INTEL_SET_THRESHOLD \ |
Dan Williams | 79ab67e | 2017-11-15 10:10:48 -0800 | [diff] [blame] | 70 | | 1 << NVDIMM_INTEL_INJECT_ERROR | 1 << NVDIMM_INTEL_LATCH_SHUTDOWN) |
Dan Williams | 11e1427 | 2017-10-20 15:39:43 -0700 | [diff] [blame] | 71 | |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 72 | enum nfit_uuids { |
Dan Williams | 31eca76 | 2016-04-28 16:23:43 -0700 | [diff] [blame] | 73 | /* for simplicity alias the uuid index with the family id */ |
| 74 | NFIT_DEV_DIMM = NVDIMM_FAMILY_INTEL, |
| 75 | NFIT_DEV_DIMM_N_HPE1 = NVDIMM_FAMILY_HPE1, |
| 76 | NFIT_DEV_DIMM_N_HPE2 = NVDIMM_FAMILY_HPE2, |
stuart hayes | e02fb72 | 2016-05-26 11:38:41 -0500 | [diff] [blame] | 77 | NFIT_DEV_DIMM_N_MSFT = NVDIMM_FAMILY_MSFT, |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 78 | NFIT_SPA_VOLATILE, |
| 79 | NFIT_SPA_PM, |
| 80 | NFIT_SPA_DCR, |
| 81 | NFIT_SPA_BDW, |
| 82 | NFIT_SPA_VDISK, |
| 83 | NFIT_SPA_VCD, |
| 84 | NFIT_SPA_PDISK, |
| 85 | NFIT_SPA_PCD, |
| 86 | NFIT_DEV_BUS, |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 87 | NFIT_UUID_MAX, |
| 88 | }; |
| 89 | |
Dan Williams | 30ec5fd | 2016-04-28 18:35:23 -0700 | [diff] [blame] | 90 | /* |
Dan Williams | 1bcbf42 | 2016-06-29 11:19:32 -0700 | [diff] [blame] | 91 | * Region format interface codes are stored with the interface as the |
| 92 | * LSB and the function as the MSB. |
Dan Williams | 30ec5fd | 2016-04-28 18:35:23 -0700 | [diff] [blame] | 93 | */ |
Dan Williams | 1bcbf42 | 2016-06-29 11:19:32 -0700 | [diff] [blame] | 94 | #define NFIT_FIC_BYTE cpu_to_le16(0x101) /* byte-addressable energy backed */ |
| 95 | #define NFIT_FIC_BLK cpu_to_le16(0x201) /* block-addressable non-energy backed */ |
| 96 | #define NFIT_FIC_BYTEN cpu_to_le16(0x301) /* byte-addressable non-energy backed */ |
Dan Williams | be26f9a | 2016-02-01 17:48:42 -0800 | [diff] [blame] | 97 | |
Ross Zwisler | f0f2c07 | 2015-07-10 11:06:14 -0600 | [diff] [blame] | 98 | enum { |
Dan Williams | aef2533 | 2016-02-12 17:01:11 -0800 | [diff] [blame] | 99 | NFIT_BLK_READ_FLUSH = 1, |
| 100 | NFIT_BLK_DCR_LATCH = 2, |
| 101 | NFIT_ARS_STATUS_DONE = 0, |
| 102 | NFIT_ARS_STATUS_BUSY = 1 << 16, |
| 103 | NFIT_ARS_STATUS_NONE = 2 << 16, |
| 104 | NFIT_ARS_STATUS_INTR = 3 << 16, |
| 105 | NFIT_ARS_START_BUSY = 6, |
| 106 | NFIT_ARS_CAP_NONE = 1, |
| 107 | NFIT_ARS_F_OVERFLOW = 1, |
Dan Williams | 1cf03c0 | 2016-02-17 13:01:23 -0800 | [diff] [blame] | 108 | NFIT_ARS_TIMEOUT = 90, |
Ross Zwisler | f0f2c07 | 2015-07-10 11:06:14 -0600 | [diff] [blame] | 109 | }; |
| 110 | |
Vishal Verma | c09f121 | 2016-08-19 14:40:58 -0600 | [diff] [blame] | 111 | enum nfit_root_notifiers { |
| 112 | NFIT_NOTIFY_UPDATE = 0x80, |
Toshi Kani | 56b47fe | 2017-06-08 12:36:57 -0600 | [diff] [blame] | 113 | NFIT_NOTIFY_UC_MEMORY_ERROR = 0x81, |
Vishal Verma | c09f121 | 2016-08-19 14:40:58 -0600 | [diff] [blame] | 114 | }; |
| 115 | |
Dan Williams | ba9c8dd | 2016-08-22 19:28:37 -0700 | [diff] [blame] | 116 | enum nfit_dimm_notifiers { |
| 117 | NFIT_NOTIFY_DIMM_HEALTH = 0x81, |
| 118 | }; |
| 119 | |
Dan Williams | 14c73f9 | 2018-04-02 15:40:30 -0700 | [diff] [blame] | 120 | enum nfit_ars_state { |
Dan Williams | d3abaf4 | 2018-10-13 20:32:17 -0700 | [diff] [blame^] | 121 | ARS_REQ_SHORT, |
| 122 | ARS_REQ_LONG, |
Dan Williams | 14c73f9 | 2018-04-02 15:40:30 -0700 | [diff] [blame] | 123 | ARS_FAILED, |
| 124 | }; |
| 125 | |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 126 | struct nfit_spa { |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 127 | struct list_head list; |
Dan Williams | 1cf03c0 | 2016-02-17 13:01:23 -0800 | [diff] [blame] | 128 | struct nd_region *nd_region; |
Dan Williams | 14c73f9 | 2018-04-02 15:40:30 -0700 | [diff] [blame] | 129 | unsigned long ars_state; |
Dan Williams | 1cf03c0 | 2016-02-17 13:01:23 -0800 | [diff] [blame] | 130 | u32 clear_err_unit; |
| 131 | u32 max_ars; |
Dan Williams | 3193204 | 2016-07-14 17:22:48 -0700 | [diff] [blame] | 132 | struct acpi_nfit_system_address spa[0]; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | struct nfit_dcr { |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 136 | struct list_head list; |
Dan Williams | 3193204 | 2016-07-14 17:22:48 -0700 | [diff] [blame] | 137 | struct acpi_nfit_control_region dcr[0]; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | struct nfit_bdw { |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 141 | struct list_head list; |
Dan Williams | 3193204 | 2016-07-14 17:22:48 -0700 | [diff] [blame] | 142 | struct acpi_nfit_data_region bdw[0]; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 143 | }; |
| 144 | |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 145 | struct nfit_idt { |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 146 | struct list_head list; |
Dan Williams | 3193204 | 2016-07-14 17:22:48 -0700 | [diff] [blame] | 147 | struct acpi_nfit_interleave idt[0]; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 148 | }; |
| 149 | |
Ross Zwisler | c2ad295 | 2015-07-10 11:06:13 -0600 | [diff] [blame] | 150 | struct nfit_flush { |
Ross Zwisler | c2ad295 | 2015-07-10 11:06:13 -0600 | [diff] [blame] | 151 | struct list_head list; |
Dan Williams | 3193204 | 2016-07-14 17:22:48 -0700 | [diff] [blame] | 152 | struct acpi_nfit_flush_address flush[0]; |
Ross Zwisler | c2ad295 | 2015-07-10 11:06:13 -0600 | [diff] [blame] | 153 | }; |
| 154 | |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 155 | struct nfit_memdev { |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 156 | struct list_head list; |
Dan Williams | 3193204 | 2016-07-14 17:22:48 -0700 | [diff] [blame] | 157 | struct acpi_nfit_memory_map memdev[0]; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 158 | }; |
| 159 | |
Dan Williams | 6f07f86 | 2018-09-26 10:48:38 -0700 | [diff] [blame] | 160 | enum nfit_mem_flags { |
| 161 | NFIT_MEM_LSR, |
| 162 | NFIT_MEM_LSW, |
Dan Williams | 0ead111 | 2018-09-26 10:47:15 -0700 | [diff] [blame] | 163 | NFIT_MEM_DIRTY, |
| 164 | NFIT_MEM_DIRTY_COUNT, |
Dan Williams | 6f07f86 | 2018-09-26 10:48:38 -0700 | [diff] [blame] | 165 | }; |
| 166 | |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 167 | /* assembled tables for a given dimm/memory-device */ |
| 168 | struct nfit_mem { |
Dan Williams | e6dfb2d | 2015-04-25 03:56:17 -0400 | [diff] [blame] | 169 | struct nvdimm *nvdimm; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 170 | struct acpi_nfit_memory_map *memdev_dcr; |
| 171 | struct acpi_nfit_memory_map *memdev_pmem; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 172 | struct acpi_nfit_memory_map *memdev_bdw; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 173 | struct acpi_nfit_control_region *dcr; |
| 174 | struct acpi_nfit_data_region *bdw; |
| 175 | struct acpi_nfit_system_address *spa_dcr; |
| 176 | struct acpi_nfit_system_address *spa_bdw; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 177 | struct acpi_nfit_interleave *idt_dcr; |
| 178 | struct acpi_nfit_interleave *idt_bdw; |
Dan Williams | ba9c8dd | 2016-08-22 19:28:37 -0700 | [diff] [blame] | 179 | struct kernfs_node *flags_attr; |
Ross Zwisler | c2ad295 | 2015-07-10 11:06:13 -0600 | [diff] [blame] | 180 | struct nfit_flush *nfit_flush; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 181 | struct list_head list; |
Dan Williams | 62232e45 | 2015-06-08 14:27:06 -0400 | [diff] [blame] | 182 | struct acpi_device *adev; |
Dan Williams | 8cc6ddf | 2016-04-05 15:26:50 -0700 | [diff] [blame] | 183 | struct acpi_nfit_desc *acpi_desc; |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 184 | struct resource *flush_wpq; |
Dan Williams | 62232e45 | 2015-06-08 14:27:06 -0400 | [diff] [blame] | 185 | unsigned long dsm_mask; |
Dan Williams | 6f07f86 | 2018-09-26 10:48:38 -0700 | [diff] [blame] | 186 | unsigned long flags; |
Dan Williams | 0ead111 | 2018-09-26 10:47:15 -0700 | [diff] [blame] | 187 | u32 dirty_shutdown; |
Dan Williams | 31eca76 | 2016-04-28 16:23:43 -0700 | [diff] [blame] | 188 | int family; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 189 | }; |
| 190 | |
| 191 | struct acpi_nfit_desc { |
| 192 | struct nvdimm_bus_descriptor nd_desc; |
Linda Knippers | 6b577c9 | 2015-11-20 19:05:49 -0500 | [diff] [blame] | 193 | struct acpi_table_header acpi_header; |
Vishal Verma | 2098516 | 2015-10-27 16:58:27 -0600 | [diff] [blame] | 194 | struct mutex init_mutex; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 195 | struct list_head memdevs; |
Ross Zwisler | c2ad295 | 2015-07-10 11:06:13 -0600 | [diff] [blame] | 196 | struct list_head flushes; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 197 | struct list_head dimms; |
| 198 | struct list_head spas; |
| 199 | struct list_head dcrs; |
| 200 | struct list_head bdws; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 201 | struct list_head idts; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 202 | struct nvdimm_bus *nvdimm_bus; |
| 203 | struct device *dev; |
Toshi Kani | 8079003 | 2017-06-29 20:41:30 -0600 | [diff] [blame] | 204 | u8 ars_start_flags; |
Dan Williams | 1cf03c0 | 2016-02-17 13:01:23 -0800 | [diff] [blame] | 205 | struct nd_cmd_ars_status *ars_status; |
Dan Williams | d3abaf4 | 2018-10-13 20:32:17 -0700 | [diff] [blame^] | 206 | struct nfit_spa *scrub_spa; |
Dan Williams | bc6ba80 | 2018-04-05 16:18:55 -0700 | [diff] [blame] | 207 | struct delayed_work dwork; |
Vishal Verma | 6839a6d | 2016-07-23 21:51:21 -0700 | [diff] [blame] | 208 | struct list_head list; |
Vishal Verma | 37b137f | 2016-07-23 21:51:42 -0700 | [diff] [blame] | 209 | struct kernfs_node *scrub_count_state; |
Dan Williams | 459d0dd | 2018-04-05 01:25:02 -0700 | [diff] [blame] | 210 | unsigned int max_ars; |
Vishal Verma | 37b137f | 2016-07-23 21:51:42 -0700 | [diff] [blame] | 211 | unsigned int scrub_count; |
Vishal Verma | 9ffd635 | 2016-09-30 17:19:29 -0600 | [diff] [blame] | 212 | unsigned int scrub_mode; |
Dan Williams | 33cc2c9 | 2018-07-05 14:58:49 -0700 | [diff] [blame] | 213 | unsigned int scrub_busy:1; |
Dan Williams | 7ae0fa43 | 2016-02-19 12:16:34 -0800 | [diff] [blame] | 214 | unsigned int cancel:1; |
Dan Williams | e3654ec | 2016-04-28 16:17:07 -0700 | [diff] [blame] | 215 | unsigned long dimm_cmd_force_en; |
| 216 | unsigned long bus_cmd_force_en; |
Yasunori Goto | b37b3fd | 2017-09-22 16:47:40 +0900 | [diff] [blame] | 217 | unsigned long bus_nfit_cmd_force_en; |
Dave Jiang | 06e8ccd | 2018-01-31 12:45:38 -0700 | [diff] [blame] | 218 | unsigned int platform_cap; |
Dan Williams | bc6ba80 | 2018-04-05 16:18:55 -0700 | [diff] [blame] | 219 | unsigned int scrub_tmo; |
Dan Williams | 6bc7561 | 2015-06-17 17:23:32 -0400 | [diff] [blame] | 220 | int (*blk_do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
| 221 | void *iobuf, u64 len, int rw); |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 222 | }; |
| 223 | |
Vishal Verma | 9ffd635 | 2016-09-30 17:19:29 -0600 | [diff] [blame] | 224 | enum scrub_mode { |
| 225 | HW_ERROR_SCRUB_OFF, |
| 226 | HW_ERROR_SCRUB_ON, |
| 227 | }; |
| 228 | |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 229 | enum nd_blk_mmio_selector { |
| 230 | BDW, |
| 231 | DCR, |
| 232 | }; |
| 233 | |
Ross Zwisler | 67a3e8f | 2015-08-27 13:14:20 -0600 | [diff] [blame] | 234 | struct nd_blk_addr { |
| 235 | union { |
| 236 | void __iomem *base; |
Dan Williams | 7a9eb20 | 2016-06-03 18:06:47 -0700 | [diff] [blame] | 237 | void *aperture; |
Ross Zwisler | 67a3e8f | 2015-08-27 13:14:20 -0600 | [diff] [blame] | 238 | }; |
| 239 | }; |
| 240 | |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 241 | struct nfit_blk { |
| 242 | struct nfit_blk_mmio { |
Ross Zwisler | 67a3e8f | 2015-08-27 13:14:20 -0600 | [diff] [blame] | 243 | struct nd_blk_addr addr; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 244 | u64 size; |
| 245 | u64 base_offset; |
| 246 | u32 line_size; |
| 247 | u32 num_lines; |
| 248 | u32 table_size; |
| 249 | struct acpi_nfit_interleave *idt; |
| 250 | struct acpi_nfit_system_address *spa; |
| 251 | } mmio[2]; |
| 252 | struct nd_region *nd_region; |
| 253 | u64 bdw_offset; /* post interleave offset */ |
| 254 | u64 stat_offset; |
| 255 | u64 cmd_offset; |
Ross Zwisler | f0f2c07 | 2015-07-10 11:06:14 -0600 | [diff] [blame] | 256 | u32 dimm_flags; |
Ross Zwisler | c2ad295 | 2015-07-10 11:06:13 -0600 | [diff] [blame] | 257 | }; |
| 258 | |
Vishal Verma | 6839a6d | 2016-07-23 21:51:21 -0700 | [diff] [blame] | 259 | extern struct list_head acpi_descs; |
| 260 | extern struct mutex acpi_desc_lock; |
Dan Williams | d3abaf4 | 2018-10-13 20:32:17 -0700 | [diff] [blame^] | 261 | int acpi_nfit_ars_rescan(struct acpi_nfit_desc *acpi_desc, |
| 262 | enum nfit_ars_state req_type); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 263 | |
Vishal Verma | 6839a6d | 2016-07-23 21:51:21 -0700 | [diff] [blame] | 264 | #ifdef CONFIG_X86_MCE |
| 265 | void nfit_mce_register(void); |
| 266 | void nfit_mce_unregister(void); |
| 267 | #else |
| 268 | static inline void nfit_mce_register(void) |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 269 | { |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 270 | } |
Vishal Verma | 6839a6d | 2016-07-23 21:51:21 -0700 | [diff] [blame] | 271 | static inline void nfit_mce_unregister(void) |
| 272 | { |
| 273 | } |
| 274 | #endif |
| 275 | |
| 276 | int nfit_spa_type(struct acpi_nfit_system_address *spa); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 277 | |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 278 | static inline struct acpi_nfit_memory_map *__to_nfit_memdev( |
| 279 | struct nfit_mem *nfit_mem) |
| 280 | { |
| 281 | if (nfit_mem->memdev_dcr) |
| 282 | return nfit_mem->memdev_dcr; |
| 283 | return nfit_mem->memdev_pmem; |
| 284 | } |
Dan Williams | 45def22 | 2015-04-26 19:26:48 -0400 | [diff] [blame] | 285 | |
| 286 | static inline struct acpi_nfit_desc *to_acpi_desc( |
| 287 | struct nvdimm_bus_descriptor *nd_desc) |
| 288 | { |
| 289 | return container_of(nd_desc, struct acpi_nfit_desc, nd_desc); |
| 290 | } |
Dan Williams | 6bc7561 | 2015-06-17 17:23:32 -0400 | [diff] [blame] | 291 | |
Andy Shevchenko | 41c8bdb | 2017-06-05 19:40:42 +0300 | [diff] [blame] | 292 | const guid_t *to_nfit_uuid(enum nfit_uuids id); |
Dan Williams | e7a11b4 | 2016-07-14 16:19:55 -0700 | [diff] [blame] | 293 | int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, void *nfit, acpi_size sz); |
Dan Williams | fbabd82 | 2017-04-18 09:56:31 -0700 | [diff] [blame] | 294 | void acpi_nfit_shutdown(void *data); |
Dan Williams | c14a868 | 2016-08-18 22:15:04 -0700 | [diff] [blame] | 295 | void __acpi_nfit_notify(struct device *dev, acpi_handle handle, u32 event); |
Dan Williams | 231bf11 | 2016-08-22 19:23:25 -0700 | [diff] [blame] | 296 | void __acpi_nvdimm_notify(struct device *dev, u32 event); |
Dan Williams | a7de92d | 2016-12-05 13:43:25 -0800 | [diff] [blame] | 297 | int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm, |
| 298 | unsigned int cmd, void *buf, unsigned int buf_len, int *cmd_rc); |
Dan Williams | a61fe6f | 2016-02-19 12:29:32 -0800 | [diff] [blame] | 299 | void acpi_nfit_desc_init(struct acpi_nfit_desc *acpi_desc, struct device *dev); |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 300 | #endif /* __NFIT_H__ */ |