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nv-tegra.nvidia.com / linux-5.10 / d2912cb15bdda8ba4a5dd73396ad62641af2f520 / . / include / linux / platform_data / pxa_sdhci.h
blob: 899457cee425d33f82606f0b8c280003bc73d48d [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
Zhangfei Gaobfed3452011-06-20 22:11:52 +0800[diff] [blame]2/*
3 * include/linux/platform_data/pxa_sdhci.h
Zhangfei Gao536ac992010-09-20 10:51:28 -0400[diff] [blame]4 *
5 * Copyright 2010 Marvell
6 * Zhangfei Gao <zhangfei.gao@marvell.com>
7 *
8 * PXA Platform - SDHCI platform data definitions
Zhangfei Gao536ac992010-09-20 10:51:28 -0400[diff] [blame]9 */
10
Zhangfei Gaobfed3452011-06-20 22:11:52 +0800[diff] [blame]11#ifndef _PXA_SDHCI_H_
12#define _PXA_SDHCI_H_
Zhangfei Gao536ac992010-09-20 10:51:28 -0400[diff] [blame]13
14/* pxa specific flag */
15/* Require clock free running */
Zhangfei Gaoa702c8a2011-06-08 17:41:57 +0800[diff] [blame]16#define PXA_FLAG_ENABLE_CLOCK_GATING (1<<0)
17/* card always wired to host, like on-chip emmc */
18#define PXA_FLAG_CARD_PERMANENT (1<<1)
Philip Rakity15ec4462010-11-19 16:48:39 -0500[diff] [blame]19/* Board design supports 8-bit data on SD/SDIO BUS */
20#define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2)
21
Zhangfei Gao536ac992010-09-20 10:51:28 -0400[diff] [blame]22/*
23 * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
Zhangfei Gao536ac992010-09-20 10:51:28 -0400[diff] [blame]24 * @flags: flags for platform requirement
Zhangfei Gaoa702c8a2011-06-08 17:41:57 +0800[diff] [blame]25 * @clk_delay_cycles:
26 * mmp2: each step is roughly 100ps, 5bits width
27 * pxa910: each step is 1ns, 4bits width
28 * @clk_delay_sel: select clk_delay, used on pxa910
29 * 0: choose feedback clk
30 * 1: choose feedback clk + delay value
31 * 2: choose internal clk
32 * @clk_delay_enable: enable clk_delay or not, used on pxa910
Zhangfei Gaoa702c8a2011-06-08 17:41:57 +0800[diff] [blame]33 * @max_speed: the maximum speed supported
34 * @host_caps: Standard MMC host capabilities bit field.
35 * @quirks: quirks of platfrom
Kevin Liu7c52d7bb2012-10-17 19:04:48 +0800[diff] [blame]36 * @quirks2: quirks2 of platfrom
Zhangfei Gaoa702c8a2011-06-08 17:41:57 +0800[diff] [blame]37 * @pm_caps: pm_caps of platfrom
Zhangfei Gao536ac992010-09-20 10:51:28 -0400[diff] [blame]38 */
39struct sdhci_pxa_platdata {
Zhangfei Gao536ac992010-09-20 10:51:28 -0400[diff] [blame]40 unsigned int flags;
Zhangfei Gaoa702c8a2011-06-08 17:41:57 +0800[diff] [blame]41 unsigned int clk_delay_cycles;
42 unsigned int clk_delay_sel;
43 bool clk_delay_enable;
Zhangfei Gaoa702c8a2011-06-08 17:41:57 +0800[diff] [blame]44 unsigned int max_speed;
Lee Jones5f1a4dd2012-11-14 12:35:51 +0000[diff] [blame]45 u32 host_caps;
46 u32 host_caps2;
Zhangfei Gaoa702c8a2011-06-08 17:41:57 +0800[diff] [blame]47 unsigned int quirks;
Kevin Liu7c52d7bb2012-10-17 19:04:48 +0800[diff] [blame]48 unsigned int quirks2;
Zhangfei Gaoa702c8a2011-06-08 17:41:57 +0800[diff] [blame]49 unsigned int pm_caps;
50};
Zhangfei Gaobfed3452011-06-20 22:11:52 +0800[diff] [blame]51#endif /* _PXA_SDHCI_H_ */