blob: 274e5b4bc4ac85b550cd1fea015cfa7c20e5252e [file] [log] [blame]
Thomas Gleixner16216332019-05-19 15:51:31 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Sten Wang7a47dd72007-11-12 21:31:11 -08002/*
3 * RDC R6040 Fast Ethernet MAC support
4 *
5 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Copyright (C) 2007
Francois Romieu5ac5d612007-11-28 23:02:33 +01007 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
Florian Fainelli35566e92016-07-04 14:36:08 -07008 * Copyright (C) 2007-2012 Florian Fainelli <f.fainelli@gmail.com>
Sten Wang7a47dd72007-11-12 21:31:11 -08009*/
10
11#include <linux/kernel.h>
12#include <linux/module.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080013#include <linux/moduleparam.h>
14#include <linux/string.h>
15#include <linux/timer.h>
16#include <linux/errno.h>
17#include <linux/ioport.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080018#include <linux/interrupt.h>
19#include <linux/pci.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/skbuff.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080023#include <linux/delay.h>
24#include <linux/mii.h>
25#include <linux/ethtool.h>
26#include <linux/crc32.h>
27#include <linux/spinlock.h>
Jeff Garzik092427b2007-11-23 21:49:27 -050028#include <linux/bitops.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/uaccess.h>
Florian Fainelli38318612010-05-31 09:18:57 +000032#include <linux/phy.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080033
34#include <asm/processor.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080035
36#define DRV_NAME "r6040"
Florian Fainelli9da28042016-07-04 14:36:09 -070037#define DRV_VERSION "0.29"
38#define DRV_RELDATE "04Jul2016"
Sten Wang7a47dd72007-11-12 21:31:11 -080039
Sten Wang7a47dd72007-11-12 21:31:11 -080040/* Time in jiffies before concluding the transmitter is hung. */
Francois Romieu5ac5d612007-11-28 23:02:33 +010041#define TX_TIMEOUT (6000 * HZ / 1000)
Sten Wang7a47dd72007-11-12 21:31:11 -080042
43/* RDC MAC I/O Size */
44#define R6040_IO_SIZE 256
45
46/* MAX RDC MAC */
47#define MAX_MAC 2
48
49/* MAC registers */
50#define MCR0 0x00 /* Control register 0 */
Florian Fainelli4e16d6e2012-01-04 08:59:34 +000051#define MCR0_RCVEN 0x0002 /* Receive enable */
Shawn Linc60c9c72011-03-07 00:09:40 +000052#define MCR0_PROMISC 0x0020 /* Promiscuous mode */
53#define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
Florian Fainelli4e16d6e2012-01-04 08:59:34 +000054#define MCR0_XMTEN 0x1000 /* Transmission enable */
55#define MCR0_FD 0x8000 /* Full/Half duplex */
Sten Wang7a47dd72007-11-12 21:31:11 -080056#define MCR1 0x04 /* Control register 1 */
57#define MAC_RST 0x0001 /* Reset the MAC */
58#define MBCR 0x08 /* Bus control */
59#define MT_ICR 0x0C /* TX interrupt control */
60#define MR_ICR 0x10 /* RX interrupt control */
61#define MTPR 0x14 /* TX poll command register */
Florian Fainelli940ff7e2012-04-11 07:18:41 +000062#define TM2TX 0x0001 /* Trigger MAC to transmit */
Sten Wang7a47dd72007-11-12 21:31:11 -080063#define MR_BSR 0x18 /* RX buffer size */
64#define MR_DCR 0x1A /* RX descriptor control */
65#define MLSR 0x1C /* Last status */
Florian Fainelli8dd87a22012-04-11 07:18:40 +000066#define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
67#define TX_EXCEEDC 0x2000 /* Transmit exceed collision */
68#define TX_LATEC 0x4000 /* Transmit late collision */
Sten Wang7a47dd72007-11-12 21:31:11 -080069#define MMDIO 0x20 /* MDIO control register */
70#define MDIO_WRITE 0x4000 /* MDIO write */
71#define MDIO_READ 0x2000 /* MDIO read */
72#define MMRD 0x24 /* MDIO read data register */
73#define MMWD 0x28 /* MDIO write data register */
74#define MTD_SA0 0x2C /* TX descriptor start address 0 */
75#define MTD_SA1 0x30 /* TX descriptor start address 1 */
76#define MRD_SA0 0x34 /* RX descriptor start address 0 */
77#define MRD_SA1 0x38 /* RX descriptor start address 1 */
78#define MISR 0x3C /* Status register */
79#define MIER 0x40 /* INT enable register */
80#define MSK_INT 0x0000 /* Mask off interrupts */
Florian Fainelli3d254342008-07-13 14:28:27 +020081#define RX_FINISH 0x0001 /* RX finished */
82#define RX_NO_DESC 0x0002 /* No RX descriptor available */
83#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
84#define RX_EARLY 0x0008 /* RX early */
85#define TX_FINISH 0x0010 /* TX finished */
86#define TX_EARLY 0x0080 /* TX early */
87#define EVENT_OVRFL 0x0100 /* Event counter overflow */
88#define LINK_CHANGED 0x0200 /* PHY link changed */
Sten Wang7a47dd72007-11-12 21:31:11 -080089#define ME_CISR 0x44 /* Event counter INT status */
90#define ME_CIER 0x48 /* Event counter INT enable */
91#define MR_CNT 0x50 /* Successfully received packet counter */
92#define ME_CNT0 0x52 /* Event counter 0 */
93#define ME_CNT1 0x54 /* Event counter 1 */
94#define ME_CNT2 0x56 /* Event counter 2 */
95#define ME_CNT3 0x58 /* Event counter 3 */
96#define MT_CNT 0x5A /* Successfully transmit packet counter */
97#define ME_CNT4 0x5C /* Event counter 4 */
98#define MP_CNT 0x5E /* Pause frame counter register */
99#define MAR0 0x60 /* Hash table 0 */
100#define MAR1 0x62 /* Hash table 1 */
101#define MAR2 0x64 /* Hash table 2 */
102#define MAR3 0x66 /* Hash table 3 */
103#define MID_0L 0x68 /* Multicast address MID0 Low */
104#define MID_0M 0x6A /* Multicast address MID0 Medium */
105#define MID_0H 0x6C /* Multicast address MID0 High */
106#define MID_1L 0x70 /* MID1 Low */
107#define MID_1M 0x72 /* MID1 Medium */
108#define MID_1H 0x74 /* MID1 High */
109#define MID_2L 0x78 /* MID2 Low */
110#define MID_2M 0x7A /* MID2 Medium */
111#define MID_2H 0x7C /* MID2 High */
112#define MID_3L 0x80 /* MID3 Low */
113#define MID_3M 0x82 /* MID3 Medium */
114#define MID_3H 0x84 /* MID3 High */
115#define PHY_CC 0x88 /* PHY status change configuration register */
Florian Fainelli31171ae2012-04-11 07:18:42 +0000116#define SCEN 0x8000 /* PHY status change enable */
117#define PHYAD_SHIFT 8 /* PHY address shift */
118#define TMRDIV_SHIFT 0 /* Timer divider shift */
Sten Wang7a47dd72007-11-12 21:31:11 -0800119#define PHY_ST 0x8A /* PHY status register */
120#define MAC_SM 0xAC /* MAC status machine */
Florian Fainellie1477632012-01-04 08:59:36 +0000121#define MAC_SM_RST 0x0002 /* MAC status machine reset */
Sten Wang7a47dd72007-11-12 21:31:11 -0800122#define MAC_ID 0xBE /* Identifier register */
123
124#define TX_DCNT 0x80 /* TX descriptor count */
125#define RX_DCNT 0x80 /* RX descriptor count */
126#define MAX_BUF_SIZE 0x600
Francois Romieu6c323102007-11-28 22:31:00 +0100127#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
128#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
Sten Wang7a47dd72007-11-12 21:31:11 -0800129#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
Florian Fainelli3bcf8222010-04-07 16:50:58 -0700130#define MCAST_MAX 3 /* Max number multicast addresses to filter */
Sten Wang7a47dd72007-11-12 21:31:11 -0800131
Florian Fainelli2fa15bb2012-04-11 07:18:38 +0000132#define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */
133
Florian Fainelli32f565d2008-07-13 14:34:15 +0200134/* Descriptor status */
135#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
136#define DSC_RX_OK 0x4000 /* RX was successful */
137#define DSC_RX_ERR 0x0800 /* RX PHY error */
138#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
139#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
140#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
141#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
142#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
143#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
144#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
145#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
146#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
147#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
148
Sten Wang7a47dd72007-11-12 21:31:11 -0800149MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
150 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
Florian Fainelli35566e92016-07-04 14:36:08 -0700151 "Florian Fainelli <f.fainelli@gmail.com>");
Sten Wang7a47dd72007-11-12 21:31:11 -0800152MODULE_LICENSE("GPL");
153MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
Florian Fainellibc4de262009-04-08 15:50:43 -0700154MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
Sten Wang7a47dd72007-11-12 21:31:11 -0800155
Florian Fainelli3d254342008-07-13 14:28:27 +0200156/* RX and TX interrupts that we handle */
Florian Fainellie24ddf32008-07-13 14:35:32 +0200157#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
158#define TX_INTS (TX_FINISH)
159#define INT_MASK (RX_INTS | TX_INTS)
Sten Wang7a47dd72007-11-12 21:31:11 -0800160
161struct r6040_descriptor {
162 u16 status, len; /* 0-3 */
163 __le32 buf; /* 4-7 */
164 __le32 ndesc; /* 8-B */
165 u32 rev1; /* C-F */
166 char *vbufp; /* 10-13 */
167 struct r6040_descriptor *vndescp; /* 14-17 */
168 struct sk_buff *skb_ptr; /* 18-1B */
169 u32 rev2; /* 1C-1F */
Florian Fainelli853d5dc2012-01-04 08:59:37 +0000170} __aligned(32);
Sten Wang7a47dd72007-11-12 21:31:11 -0800171
172struct r6040_private {
173 spinlock_t lock; /* driver lock */
Sten Wang7a47dd72007-11-12 21:31:11 -0800174 struct pci_dev *pdev;
175 struct r6040_descriptor *rx_insert_ptr;
176 struct r6040_descriptor *rx_remove_ptr;
177 struct r6040_descriptor *tx_insert_ptr;
178 struct r6040_descriptor *tx_remove_ptr;
Francois Romieu6c323102007-11-28 22:31:00 +0100179 struct r6040_descriptor *rx_ring;
180 struct r6040_descriptor *tx_ring;
181 dma_addr_t rx_ring_dma;
182 dma_addr_t tx_ring_dma;
Florian Fainelli49f26722012-01-04 08:59:33 +0000183 u16 tx_free_desc;
Florian Fainelli0db0cfc2012-04-11 07:18:37 +0000184 u16 mcr0;
Sten Wang7a47dd72007-11-12 21:31:11 -0800185 struct net_device *dev;
Florian Fainelli38318612010-05-31 09:18:57 +0000186 struct mii_bus *mii_bus;
Sten Wang7a47dd72007-11-12 21:31:11 -0800187 struct napi_struct napi;
Sten Wang7a47dd72007-11-12 21:31:11 -0800188 void __iomem *base;
Florian Fainelli38318612010-05-31 09:18:57 +0000189 int old_link;
190 int old_duplex;
Sten Wang7a47dd72007-11-12 21:31:11 -0800191};
192
Bill Pembertonf1e24262012-12-03 09:23:30 -0500193static char version[] = DRV_NAME
Sten Wang7a47dd72007-11-12 21:31:11 -0800194 ": RDC R6040 NAPI net driver,"
Florian Fainelli9a48ce82009-01-08 11:00:52 -0800195 "version "DRV_VERSION " (" DRV_RELDATE ")";
Sten Wang7a47dd72007-11-12 21:31:11 -0800196
Sten Wang7a47dd72007-11-12 21:31:11 -0800197/* Read a word data from PHY Chip */
Florian Fainellic6e69bb2008-07-13 13:39:32 +0200198static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
Sten Wang7a47dd72007-11-12 21:31:11 -0800199{
Florian Fainelli2fa15bb2012-04-11 07:18:38 +0000200 int limit = MAC_DEF_TIMEOUT;
Sten Wang7a47dd72007-11-12 21:31:11 -0800201 u16 cmd;
202
203 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
204 /* Wait for the read bit to be cleared */
205 while (limit--) {
206 cmd = ioread16(ioaddr + MMDIO);
Joe Chou11e5e8f2008-12-22 19:38:17 -0800207 if (!(cmd & MDIO_READ))
Sten Wang7a47dd72007-11-12 21:31:11 -0800208 break;
Florian Fainelli4f8d9f3c2014-01-15 13:04:25 -0800209 udelay(1);
Sten Wang7a47dd72007-11-12 21:31:11 -0800210 }
211
Florian Fainelli09e7fae2013-03-06 00:41:32 +0000212 if (limit < 0)
213 return -ETIMEDOUT;
214
Sten Wang7a47dd72007-11-12 21:31:11 -0800215 return ioread16(ioaddr + MMRD);
216}
217
218/* Write a word data from PHY Chip */
Florian Fainelli09e7fae2013-03-06 00:41:32 +0000219static int r6040_phy_write(void __iomem *ioaddr,
Florian Fainelli2154c7042010-08-08 10:08:44 +0000220 int phy_addr, int reg, u16 val)
Sten Wang7a47dd72007-11-12 21:31:11 -0800221{
Florian Fainelli2fa15bb2012-04-11 07:18:38 +0000222 int limit = MAC_DEF_TIMEOUT;
Sten Wang7a47dd72007-11-12 21:31:11 -0800223 u16 cmd;
224
225 iowrite16(val, ioaddr + MMWD);
226 /* Write the command to the MDIO bus */
227 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
228 /* Wait for the write bit to be cleared */
229 while (limit--) {
230 cmd = ioread16(ioaddr + MMDIO);
Joe Chou11e5e8f2008-12-22 19:38:17 -0800231 if (!(cmd & MDIO_WRITE))
Sten Wang7a47dd72007-11-12 21:31:11 -0800232 break;
Florian Fainelli4f8d9f3c2014-01-15 13:04:25 -0800233 udelay(1);
Sten Wang7a47dd72007-11-12 21:31:11 -0800234 }
Florian Fainelli09e7fae2013-03-06 00:41:32 +0000235
236 return (limit < 0) ? -ETIMEDOUT : 0;
Sten Wang7a47dd72007-11-12 21:31:11 -0800237}
238
Florian Fainelli38318612010-05-31 09:18:57 +0000239static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
Sten Wang7a47dd72007-11-12 21:31:11 -0800240{
Florian Fainelli38318612010-05-31 09:18:57 +0000241 struct net_device *dev = bus->priv;
Sten Wang7a47dd72007-11-12 21:31:11 -0800242 struct r6040_private *lp = netdev_priv(dev);
243 void __iomem *ioaddr = lp->base;
244
Florian Fainelli38318612010-05-31 09:18:57 +0000245 return r6040_phy_read(ioaddr, phy_addr, reg);
Sten Wang7a47dd72007-11-12 21:31:11 -0800246}
247
Florian Fainelli38318612010-05-31 09:18:57 +0000248static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
249 int reg, u16 value)
Sten Wang7a47dd72007-11-12 21:31:11 -0800250{
Florian Fainelli38318612010-05-31 09:18:57 +0000251 struct net_device *dev = bus->priv;
Sten Wang7a47dd72007-11-12 21:31:11 -0800252 struct r6040_private *lp = netdev_priv(dev);
253 void __iomem *ioaddr = lp->base;
254
Florian Fainelli09e7fae2013-03-06 00:41:32 +0000255 return r6040_phy_write(ioaddr, phy_addr, reg, value);
Florian Fainelli38318612010-05-31 09:18:57 +0000256}
257
Florian Fainellib4f12552007-12-12 22:55:34 +0100258static void r6040_free_txbufs(struct net_device *dev)
259{
260 struct r6040_private *lp = netdev_priv(dev);
261 int i;
262
263 for (i = 0; i < TX_DCNT; i++) {
264 if (lp->tx_insert_ptr->skb_ptr) {
Al Viroed773b4a2008-03-16 22:43:06 +0000265 pci_unmap_single(lp->pdev,
266 le32_to_cpu(lp->tx_insert_ptr->buf),
Florian Fainellib4f12552007-12-12 22:55:34 +0100267 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
268 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
Florian Fainelli3b060be2008-09-24 21:16:40 +0200269 lp->tx_insert_ptr->skb_ptr = NULL;
Florian Fainellib4f12552007-12-12 22:55:34 +0100270 }
271 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
272 }
273}
274
275static void r6040_free_rxbufs(struct net_device *dev)
276{
277 struct r6040_private *lp = netdev_priv(dev);
278 int i;
279
280 for (i = 0; i < RX_DCNT; i++) {
281 if (lp->rx_insert_ptr->skb_ptr) {
Al Viroed773b4a2008-03-16 22:43:06 +0000282 pci_unmap_single(lp->pdev,
283 le32_to_cpu(lp->rx_insert_ptr->buf),
Florian Fainellib4f12552007-12-12 22:55:34 +0100284 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
285 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
286 lp->rx_insert_ptr->skb_ptr = NULL;
287 }
288 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
289 }
290}
291
Florian Fainellib4f12552007-12-12 22:55:34 +0100292static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
293 dma_addr_t desc_dma, int size)
294{
295 struct r6040_descriptor *desc = desc_ring;
296 dma_addr_t mapping = desc_dma;
297
298 while (size-- > 0) {
Julia Lawall3f6602a2008-06-23 23:12:31 +0200299 mapping += sizeof(*desc);
Florian Fainellib4f12552007-12-12 22:55:34 +0100300 desc->ndesc = cpu_to_le32(mapping);
301 desc->vndescp = desc + 1;
302 desc++;
303 }
304 desc--;
305 desc->ndesc = cpu_to_le32(desc_dma);
306 desc->vndescp = desc_ring;
307}
308
Florian Fainelli3d463412008-07-13 14:32:18 +0200309static void r6040_init_txbufs(struct net_device *dev)
Florian Fainellib4f12552007-12-12 22:55:34 +0100310{
311 struct r6040_private *lp = netdev_priv(dev);
Florian Fainellib4f12552007-12-12 22:55:34 +0100312
313 lp->tx_free_desc = TX_DCNT;
314
315 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
316 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
Florian Fainellib4f12552007-12-12 22:55:34 +0100317}
318
Florian Fainelli3d463412008-07-13 14:32:18 +0200319static int r6040_alloc_rxbufs(struct net_device *dev)
Florian Fainellib4f12552007-12-12 22:55:34 +0100320{
321 struct r6040_private *lp = netdev_priv(dev);
Florian Fainelli3d463412008-07-13 14:32:18 +0200322 struct r6040_descriptor *desc;
323 struct sk_buff *skb;
324 int rc;
Florian Fainellib4f12552007-12-12 22:55:34 +0100325
326 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
327 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
328
Florian Fainelli3d463412008-07-13 14:32:18 +0200329 /* Allocate skbs for the rx descriptors */
330 desc = lp->rx_ring;
331 do {
332 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
333 if (!skb) {
Florian Fainelli3d463412008-07-13 14:32:18 +0200334 rc = -ENOMEM;
335 goto err_exit;
336 }
337 desc->skb_ptr = skb;
338 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
Florian Fainelli2154c7042010-08-08 10:08:44 +0000339 desc->skb_ptr->data,
340 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
Florian Fainelli32f565d2008-07-13 14:34:15 +0200341 desc->status = DSC_OWNER_MAC;
Florian Fainelli3d463412008-07-13 14:32:18 +0200342 desc = desc->vndescp;
343 } while (desc != lp->rx_ring);
344
345 return 0;
346
347err_exit:
348 /* Deallocate all previously allocated skbs */
349 r6040_free_rxbufs(dev);
350 return rc;
Florian Fainellifec3a232008-07-13 14:29:20 +0200351}
Florian Fainellib4f12552007-12-12 22:55:34 +0100352
Florian Fainelli90f750a2012-04-11 07:18:36 +0000353static void r6040_reset_mac(struct r6040_private *lp)
Florian Fainellifec3a232008-07-13 14:29:20 +0200354{
Florian Fainellifec3a232008-07-13 14:29:20 +0200355 void __iomem *ioaddr = lp->base;
Florian Fainelli2fa15bb2012-04-11 07:18:38 +0000356 int limit = MAC_DEF_TIMEOUT;
Florian Fainellifec3a232008-07-13 14:29:20 +0200357 u16 cmd;
358
Florian Fainellifec3a232008-07-13 14:29:20 +0200359 iowrite16(MAC_RST, ioaddr + MCR1);
360 while (limit--) {
361 cmd = ioread16(ioaddr + MCR1);
Florian Fainelli58dbc692012-01-04 08:59:35 +0000362 if (cmd & MAC_RST)
Florian Fainellifec3a232008-07-13 14:29:20 +0200363 break;
364 }
Florian Fainelli90f750a2012-04-11 07:18:36 +0000365
Florian Fainellifec3a232008-07-13 14:29:20 +0200366 /* Reset internal state machine */
Florian Fainellie1477632012-01-04 08:59:36 +0000367 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
Florian Fainellifec3a232008-07-13 14:29:20 +0200368 iowrite16(0, ioaddr + MAC_SM);
Florian Fainellic1d69932008-09-03 16:50:03 +0200369 mdelay(5);
Florian Fainelli90f750a2012-04-11 07:18:36 +0000370}
371
372static void r6040_init_mac_regs(struct net_device *dev)
373{
374 struct r6040_private *lp = netdev_priv(dev);
375 void __iomem *ioaddr = lp->base;
376
377 /* Mask Off Interrupt */
378 iowrite16(MSK_INT, ioaddr + MIER);
379
380 /* Reset RDC MAC */
381 r6040_reset_mac(lp);
Florian Fainellifec3a232008-07-13 14:29:20 +0200382
383 /* MAC Bus Control Register */
384 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
385
386 /* Buffer Size Register */
387 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
388
389 /* Write TX ring start address */
390 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
391 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
392
393 /* Write RX ring start address */
Florian Fainellib4f12552007-12-12 22:55:34 +0100394 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
395 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
Florian Fainellifec3a232008-07-13 14:29:20 +0200396
397 /* Set interrupt waiting time and packet numbers */
Florian Fainelli31718de2008-07-13 14:35:00 +0200398 iowrite16(0, ioaddr + MT_ICR);
399 iowrite16(0, ioaddr + MR_ICR);
Florian Fainellifec3a232008-07-13 14:29:20 +0200400
401 /* Enable interrupts */
402 iowrite16(INT_MASK, ioaddr + MIER);
403
404 /* Enable TX and RX */
Florian Fainelli4e16d6e2012-01-04 08:59:34 +0000405 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
Florian Fainellifec3a232008-07-13 14:29:20 +0200406
407 /* Let TX poll the descriptors
408 * we may got called by r6040_tx_timeout which has left
409 * some unsent tx buffers */
Florian Fainelli940ff7e2012-04-11 07:18:41 +0000410 iowrite16(TM2TX, ioaddr + MTPR);
Florian Fainellib4f12552007-12-12 22:55:34 +0100411}
Sten Wang7a47dd72007-11-12 21:31:11 -0800412
Florian Fainelli106adf32007-12-12 23:01:33 +0100413static void r6040_tx_timeout(struct net_device *dev)
414{
415 struct r6040_private *priv = netdev_priv(dev);
416 void __iomem *ioaddr = priv->base;
417
Florian Fainelli7d53b802010-04-07 21:39:27 +0000418 netdev_warn(dev, "transmit timed out, int enable %4.4x "
Florian Fainelli38318612010-05-31 09:18:57 +0000419 "status %4.4x\n",
Florian Fainelli7d53b802010-04-07 21:39:27 +0000420 ioread16(ioaddr + MIER),
Florian Fainelli38318612010-05-31 09:18:57 +0000421 ioread16(ioaddr + MISR));
Florian Fainelli106adf32007-12-12 23:01:33 +0100422
Florian Fainelli106adf32007-12-12 23:01:33 +0100423 dev->stats.tx_errors++;
Florian Fainellifec3a232008-07-13 14:29:20 +0200424
425 /* Reset MAC and re-init all registers */
426 r6040_init_mac_regs(dev);
Florian Fainelli106adf32007-12-12 23:01:33 +0100427}
428
Sten Wang7a47dd72007-11-12 21:31:11 -0800429static struct net_device_stats *r6040_get_stats(struct net_device *dev)
430{
431 struct r6040_private *priv = netdev_priv(dev);
432 void __iomem *ioaddr = priv->base;
433 unsigned long flags;
434
435 spin_lock_irqsave(&priv->lock, flags);
Florian Fainellid248fd72007-12-12 22:34:55 +0100436 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
437 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
Sten Wang7a47dd72007-11-12 21:31:11 -0800438 spin_unlock_irqrestore(&priv->lock, flags);
439
Florian Fainellid248fd72007-12-12 22:34:55 +0100440 return &dev->stats;
Sten Wang7a47dd72007-11-12 21:31:11 -0800441}
442
443/* Stop RDC MAC and Free the allocated resource */
444static void r6040_down(struct net_device *dev)
445{
446 struct r6040_private *lp = netdev_priv(dev);
447 void __iomem *ioaddr = lp->base;
Sten Wang7a47dd72007-11-12 21:31:11 -0800448 u16 *adrp;
Sten Wang7a47dd72007-11-12 21:31:11 -0800449
450 /* Stop MAC */
451 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
Florian Fainelli90f750a2012-04-11 07:18:36 +0000452
453 /* Reset RDC MAC */
454 r6040_reset_mac(lp);
Sten Wang7a47dd72007-11-12 21:31:11 -0800455
456 /* Restore MAC Address to MIDx */
457 adrp = (u16 *) dev->dev_addr;
458 iowrite16(adrp[0], ioaddr + MID_0L);
459 iowrite16(adrp[1], ioaddr + MID_0M);
460 iowrite16(adrp[2], ioaddr + MID_0H);
Sten Wang7a47dd72007-11-12 21:31:11 -0800461}
462
Francois Romieu5ac5d612007-11-28 23:02:33 +0100463static int r6040_close(struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800464{
465 struct r6040_private *lp = netdev_priv(dev);
Florian Fainelli58854c62009-01-09 23:19:26 -0800466 struct pci_dev *pdev = lp->pdev;
Sten Wang7a47dd72007-11-12 21:31:11 -0800467
Manuel Besslerc762eaa2016-12-15 22:55:00 -0500468 phy_stop(dev->phydev);
Florian Fainelli129cf9a2008-07-13 14:32:45 +0200469 napi_disable(&lp->napi);
Sten Wang7a47dd72007-11-12 21:31:11 -0800470 netif_stop_queue(dev);
Florian Fainelli58854c62009-01-09 23:19:26 -0800471
Manuel Besslerc762eaa2016-12-15 22:55:00 -0500472 spin_lock_irq(&lp->lock);
473 r6040_down(dev);
Florian Fainelli58854c62009-01-09 23:19:26 -0800474
475 /* Free RX buffer */
476 r6040_free_rxbufs(dev);
477
478 /* Free TX buffer */
479 r6040_free_txbufs(dev);
480
Sten Wang7a47dd72007-11-12 21:31:11 -0800481 spin_unlock_irq(&lp->lock);
482
Manuel Besslerc762eaa2016-12-15 22:55:00 -0500483 free_irq(dev->irq, dev);
484
Florian Fainelli58854c62009-01-09 23:19:26 -0800485 /* Free Descriptor memory */
486 if (lp->rx_ring) {
Florian Fainelli2154c7042010-08-08 10:08:44 +0000487 pci_free_consistent(pdev,
488 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
Hannes Eder5b5103e2009-02-14 11:14:04 +0000489 lp->rx_ring = NULL;
Florian Fainelli58854c62009-01-09 23:19:26 -0800490 }
491
492 if (lp->tx_ring) {
Florian Fainelli2154c7042010-08-08 10:08:44 +0000493 pci_free_consistent(pdev,
494 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
Hannes Eder5b5103e2009-02-14 11:14:04 +0000495 lp->tx_ring = NULL;
Florian Fainelli58854c62009-01-09 23:19:26 -0800496 }
497
Sten Wang7a47dd72007-11-12 21:31:11 -0800498 return 0;
499}
500
Sten Wang7a47dd72007-11-12 21:31:11 -0800501static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
502{
Philippe Reynes542808f2016-06-25 21:09:01 +0200503 if (!dev->phydev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800504 return -EINVAL;
Florian Fainelli38318612010-05-31 09:18:57 +0000505
Philippe Reynes542808f2016-06-25 21:09:01 +0200506 return phy_mii_ioctl(dev->phydev, rq, cmd);
Sten Wang7a47dd72007-11-12 21:31:11 -0800507}
508
509static int r6040_rx(struct net_device *dev, int limit)
510{
511 struct r6040_private *priv = netdev_priv(dev);
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200512 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
513 struct sk_buff *skb_ptr, *new_skb;
514 int count = 0;
Sten Wang7a47dd72007-11-12 21:31:11 -0800515 u16 err;
516
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200517 /* Limit not reached and the descriptor belongs to the CPU */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200518 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200519 /* Read the descriptor status */
520 err = descptr->status;
521 /* Global error status set */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200522 if (err & DSC_RX_ERR) {
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200523 /* RX dribble */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200524 if (err & DSC_RX_ERR_DRI)
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200525 dev->stats.rx_frame_errors++;
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300526 /* Buffer length exceeded */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200527 if (err & DSC_RX_ERR_BUF)
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200528 dev->stats.rx_length_errors++;
529 /* Packet too long */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200530 if (err & DSC_RX_ERR_LONG)
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200531 dev->stats.rx_length_errors++;
532 /* Packet < 64 bytes */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200533 if (err & DSC_RX_ERR_RUNT)
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200534 dev->stats.rx_length_errors++;
535 /* CRC error */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200536 if (err & DSC_RX_ERR_CRC) {
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200537 spin_lock(&priv->lock);
538 dev->stats.rx_crc_errors++;
539 spin_unlock(&priv->lock);
Sten Wang7a47dd72007-11-12 21:31:11 -0800540 }
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200541 goto next_descr;
Sten Wang7a47dd72007-11-12 21:31:11 -0800542 }
Florian Fainelli2154c7042010-08-08 10:08:44 +0000543
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200544 /* Packet successfully received */
545 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
546 if (!new_skb) {
547 dev->stats.rx_dropped++;
548 goto next_descr;
549 }
550 skb_ptr = descptr->skb_ptr;
551 skb_ptr->dev = priv->dev;
Florian Fainelli2154c7042010-08-08 10:08:44 +0000552
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200553 /* Do not count the CRC */
554 skb_put(skb_ptr, descptr->len - 4);
555 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
556 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
557 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
Florian Fainelli2154c7042010-08-08 10:08:44 +0000558
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200559 /* Send to upper layer */
560 netif_receive_skb(skb_ptr);
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200561 dev->stats.rx_packets++;
562 dev->stats.rx_bytes += descptr->len - 4;
563
564 /* put new skb into descriptor */
565 descptr->skb_ptr = new_skb;
566 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
567 descptr->skb_ptr->data,
568 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
569
570next_descr:
571 /* put the descriptor back to the MAC */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200572 descptr->status = DSC_OWNER_MAC;
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200573 descptr = descptr->vndescp;
574 count++;
Sten Wang7a47dd72007-11-12 21:31:11 -0800575 }
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200576 priv->rx_remove_ptr = descptr;
Sten Wang7a47dd72007-11-12 21:31:11 -0800577
578 return count;
579}
580
581static void r6040_tx(struct net_device *dev)
582{
583 struct r6040_private *priv = netdev_priv(dev);
584 struct r6040_descriptor *descptr;
585 void __iomem *ioaddr = priv->base;
586 struct sk_buff *skb_ptr;
587 u16 err;
588
589 spin_lock(&priv->lock);
590 descptr = priv->tx_remove_ptr;
591 while (priv->tx_free_desc < TX_DCNT) {
592 /* Check for errors */
593 err = ioread16(ioaddr + MLSR);
594
Florian Fainelli8dd87a22012-04-11 07:18:40 +0000595 if (err & TX_FIFO_UNDR)
Florian Fainelli3440ecc2012-04-11 07:18:39 +0000596 dev->stats.tx_fifo_errors++;
Florian Fainelli8dd87a22012-04-11 07:18:40 +0000597 if (err & (TX_EXCEEDC | TX_LATEC))
Florian Fainellid248fd72007-12-12 22:34:55 +0100598 dev->stats.tx_carrier_errors++;
Sten Wang7a47dd72007-11-12 21:31:11 -0800599
Florian Fainelli32f565d2008-07-13 14:34:15 +0200600 if (descptr->status & DSC_OWNER_MAC)
Florian Fainelliec6d2d42007-12-12 23:13:15 +0100601 break; /* Not complete */
Sten Wang7a47dd72007-11-12 21:31:11 -0800602 skb_ptr = descptr->skb_ptr;
Florian Fainelli7def1712016-07-04 14:36:02 -0700603
604 /* Statistic Counter */
605 dev->stats.tx_packets++;
606 dev->stats.tx_bytes += skb_ptr->len;
607
Al Viroed773b4a2008-03-16 22:43:06 +0000608 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
Sten Wang7a47dd72007-11-12 21:31:11 -0800609 skb_ptr->len, PCI_DMA_TODEVICE);
610 /* Free buffer */
Florian Fainelli58e6b052016-07-04 14:36:04 -0700611 dev_kfree_skb(skb_ptr);
Sten Wang7a47dd72007-11-12 21:31:11 -0800612 descptr->skb_ptr = NULL;
613 /* To next descriptor */
614 descptr = descptr->vndescp;
615 priv->tx_free_desc++;
616 }
617 priv->tx_remove_ptr = descptr;
618
619 if (priv->tx_free_desc)
620 netif_wake_queue(dev);
621 spin_unlock(&priv->lock);
622}
623
624static int r6040_poll(struct napi_struct *napi, int budget)
625{
626 struct r6040_private *priv =
627 container_of(napi, struct r6040_private, napi);
628 struct net_device *dev = priv->dev;
629 void __iomem *ioaddr = priv->base;
630 int work_done;
631
Florian Fainelli58e6b052016-07-04 14:36:04 -0700632 r6040_tx(dev);
633
Sten Wang7a47dd72007-11-12 21:31:11 -0800634 work_done = r6040_rx(dev, budget);
635
636 if (work_done < budget) {
Florian Fainelli0305eff2016-07-04 14:36:07 -0700637 napi_complete_done(napi, work_done);
Florian Fainelli58e6b052016-07-04 14:36:04 -0700638 /* Enable RX/TX interrupt */
639 iowrite16(ioread16(ioaddr + MIER) | RX_INTS | TX_INTS,
640 ioaddr + MIER);
Sten Wang7a47dd72007-11-12 21:31:11 -0800641 }
642 return work_done;
643}
644
645/* The RDC interrupt handler. */
646static irqreturn_t r6040_interrupt(int irq, void *dev_id)
647{
648 struct net_device *dev = dev_id;
649 struct r6040_private *lp = netdev_priv(dev);
650 void __iomem *ioaddr = lp->base;
Joe Chou3e7c4692008-12-22 19:40:02 -0800651 u16 misr, status;
Sten Wang7a47dd72007-11-12 21:31:11 -0800652
Joe Chou3e7c4692008-12-22 19:40:02 -0800653 /* Save MIER */
654 misr = ioread16(ioaddr + MIER);
Sten Wang7a47dd72007-11-12 21:31:11 -0800655 /* Mask off RDC MAC interrupt */
656 iowrite16(MSK_INT, ioaddr + MIER);
657 /* Read MISR status and clear */
658 status = ioread16(ioaddr + MISR);
659
Florian Fainelli35976d42009-07-08 03:05:14 +0000660 if (status == 0x0000 || status == 0xffff) {
661 /* Restore RDC MAC interrupt */
662 iowrite16(misr, ioaddr + MIER);
Sten Wang7a47dd72007-11-12 21:31:11 -0800663 return IRQ_NONE;
Florian Fainelli35976d42009-07-08 03:05:14 +0000664 }
Sten Wang7a47dd72007-11-12 21:31:11 -0800665
666 /* RX interrupt request */
Florian Fainelli58e6b052016-07-04 14:36:04 -0700667 if (status & (RX_INTS | TX_INTS)) {
Florian Fainellie24ddf32008-07-13 14:35:32 +0200668 if (status & RX_NO_DESC) {
669 /* RX descriptor unavailable */
670 dev->stats.rx_dropped++;
671 dev->stats.rx_missed_errors++;
672 }
673 if (status & RX_FIFO_FULL)
674 dev->stats.rx_fifo_errors++;
675
Michael Thalmeier0d9b6e72011-07-15 01:28:26 +0000676 if (likely(napi_schedule_prep(&lp->napi))) {
677 /* Mask off RX interrupt */
Florian Fainelli58e6b052016-07-04 14:36:04 -0700678 misr &= ~(RX_INTS | TX_INTS);
Florian Fainelliffb5bce2016-07-04 14:36:06 -0700679 __napi_schedule_irqoff(&lp->napi);
Michael Thalmeier0d9b6e72011-07-15 01:28:26 +0000680 }
Sten Wang7a47dd72007-11-12 21:31:11 -0800681 }
682
Joe Chou3e7c4692008-12-22 19:40:02 -0800683 /* Restore RDC MAC interrupt */
684 iowrite16(misr, ioaddr + MIER);
685
Florian Fainelliec6d2d42007-12-12 23:13:15 +0100686 return IRQ_HANDLED;
Sten Wang7a47dd72007-11-12 21:31:11 -0800687}
688
689#ifdef CONFIG_NET_POLL_CONTROLLER
690static void r6040_poll_controller(struct net_device *dev)
691{
692 disable_irq(dev->irq);
Francois Romieu5ac5d612007-11-28 23:02:33 +0100693 r6040_interrupt(dev->irq, dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800694 enable_irq(dev->irq);
695}
696#endif
697
Sten Wang7a47dd72007-11-12 21:31:11 -0800698/* Init RDC MAC */
Florian Fainelli3d463412008-07-13 14:32:18 +0200699static int r6040_up(struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800700{
701 struct r6040_private *lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800702 void __iomem *ioaddr = lp->base;
Florian Fainelli3d463412008-07-13 14:32:18 +0200703 int ret;
Sten Wang7a47dd72007-11-12 21:31:11 -0800704
Florian Fainellib4f12552007-12-12 22:55:34 +0100705 /* Initialise and alloc RX/TX buffers */
Florian Fainelli3d463412008-07-13 14:32:18 +0200706 r6040_init_txbufs(dev);
707 ret = r6040_alloc_rxbufs(dev);
708 if (ret)
709 return ret;
Sten Wang7a47dd72007-11-12 21:31:11 -0800710
Sten Wang7a47dd72007-11-12 21:31:11 -0800711 /* improve performance (by RDC guys) */
Florian Fainelli2154c7042010-08-08 10:08:44 +0000712 r6040_phy_write(ioaddr, 30, 17,
713 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
714 r6040_phy_write(ioaddr, 30, 17,
715 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
Florian Fainellic6e69bb2008-07-13 13:39:32 +0200716 r6040_phy_write(ioaddr, 0, 19, 0x0000);
717 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
Sten Wang7a47dd72007-11-12 21:31:11 -0800718
Florian Fainellifec3a232008-07-13 14:29:20 +0200719 /* Initialize all MAC registers */
720 r6040_init_mac_regs(dev);
Florian Fainelli3d463412008-07-13 14:32:18 +0200721
Philippe Reynes542808f2016-06-25 21:09:01 +0200722 phy_start(dev->phydev);
Florian Fainelli06e92c32011-10-06 23:36:22 +0000723
Florian Fainelli3d463412008-07-13 14:32:18 +0200724 return 0;
Sten Wang7a47dd72007-11-12 21:31:11 -0800725}
726
Sten Wang7a47dd72007-11-12 21:31:11 -0800727
728/* Read/set MAC address routines */
729static void r6040_mac_address(struct net_device *dev)
730{
731 struct r6040_private *lp = netdev_priv(dev);
732 void __iomem *ioaddr = lp->base;
733 u16 *adrp;
734
Florian Fainelli48529682012-01-04 08:59:38 +0000735 /* Reset MAC */
Florian Fainelli90f750a2012-04-11 07:18:36 +0000736 r6040_reset_mac(lp);
Sten Wang7a47dd72007-11-12 21:31:11 -0800737
738 /* Restore MAC Address */
739 adrp = (u16 *) dev->dev_addr;
740 iowrite16(adrp[0], ioaddr + MID_0L);
741 iowrite16(adrp[1], ioaddr + MID_0M);
742 iowrite16(adrp[2], ioaddr + MID_0H);
743}
744
Francois Romieu5ac5d612007-11-28 23:02:33 +0100745static int r6040_open(struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800746{
Francois Romieu5ac5d612007-11-28 23:02:33 +0100747 struct r6040_private *lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800748 int ret;
749
750 /* Request IRQ and Register interrupt handler */
Julia Lawall91dcbf32009-11-18 08:23:00 +0000751 ret = request_irq(dev->irq, r6040_interrupt,
Sten Wang7a47dd72007-11-12 21:31:11 -0800752 IRQF_SHARED, dev->name, dev);
753 if (ret)
Denis Kirjanovced1de42010-08-24 23:57:55 +0000754 goto out;
Sten Wang7a47dd72007-11-12 21:31:11 -0800755
756 /* Set MAC address */
757 r6040_mac_address(dev);
758
759 /* Allocate Descriptor memory */
Francois Romieu6c323102007-11-28 22:31:00 +0100760 lp->rx_ring =
761 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
Denis Kirjanovced1de42010-08-24 23:57:55 +0000762 if (!lp->rx_ring) {
763 ret = -ENOMEM;
764 goto err_free_irq;
765 }
Sten Wang7a47dd72007-11-12 21:31:11 -0800766
Francois Romieu6c323102007-11-28 22:31:00 +0100767 lp->tx_ring =
768 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
769 if (!lp->tx_ring) {
Denis Kirjanovced1de42010-08-24 23:57:55 +0000770 ret = -ENOMEM;
771 goto err_free_rx_ring;
Francois Romieu6c323102007-11-28 22:31:00 +0100772 }
773
Florian Fainelli3d463412008-07-13 14:32:18 +0200774 ret = r6040_up(dev);
Denis Kirjanovced1de42010-08-24 23:57:55 +0000775 if (ret)
776 goto err_free_tx_ring;
Sten Wang7a47dd72007-11-12 21:31:11 -0800777
778 napi_enable(&lp->napi);
779 netif_start_queue(dev);
780
Sten Wang7a47dd72007-11-12 21:31:11 -0800781 return 0;
Denis Kirjanovced1de42010-08-24 23:57:55 +0000782
783err_free_tx_ring:
784 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
785 lp->tx_ring_dma);
786err_free_rx_ring:
787 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
788 lp->rx_ring_dma);
789err_free_irq:
790 free_irq(dev->irq, dev);
791out:
792 return ret;
Sten Wang7a47dd72007-11-12 21:31:11 -0800793}
794
Stephen Hemminger613573252009-08-31 19:50:58 +0000795static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
796 struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800797{
798 struct r6040_private *lp = netdev_priv(dev);
799 struct r6040_descriptor *descptr;
800 void __iomem *ioaddr = lp->base;
801 unsigned long flags;
Sten Wang7a47dd72007-11-12 21:31:11 -0800802
Florian Fainellia546e552016-07-04 14:36:03 -0700803 if (skb_put_padto(skb, ETH_ZLEN) < 0)
804 return NETDEV_TX_OK;
805
Sten Wang7a47dd72007-11-12 21:31:11 -0800806 /* Critical Section */
807 spin_lock_irqsave(&lp->lock, flags);
808
809 /* TX resource check */
810 if (!lp->tx_free_desc) {
811 spin_unlock_irqrestore(&lp->lock, flags);
Jeff Garzik092427b2007-11-23 21:49:27 -0500812 netif_stop_queue(dev);
Florian Fainelli7d53b802010-04-07 21:39:27 +0000813 netdev_err(dev, ": no tx descriptor\n");
Stephen Hemminger613573252009-08-31 19:50:58 +0000814 return NETDEV_TX_BUSY;
Sten Wang7a47dd72007-11-12 21:31:11 -0800815 }
816
Sten Wang7a47dd72007-11-12 21:31:11 -0800817 /* Set TX descriptor & Transmit it */
818 lp->tx_free_desc--;
819 descptr = lp->tx_insert_ptr;
Florian Fainellia546e552016-07-04 14:36:03 -0700820 descptr->len = skb->len;
Sten Wang7a47dd72007-11-12 21:31:11 -0800821 descptr->skb_ptr = skb;
822 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
823 skb->data, skb->len, PCI_DMA_TODEVICE));
Florian Fainelli32f565d2008-07-13 14:34:15 +0200824 descptr->status = DSC_OWNER_MAC;
Richard Cochran2aa8f4c2011-06-19 03:31:42 +0000825
826 skb_tx_timestamp(skb);
827
Sten Wang7a47dd72007-11-12 21:31:11 -0800828 /* Trigger the MAC to check the TX descriptor */
Florian Westphal6b16f9e2019-04-01 16:42:14 +0200829 if (!netdev_xmit_more() || netif_queue_stopped(dev))
Florian Fainelli9507ffc2016-07-04 14:36:05 -0700830 iowrite16(TM2TX, ioaddr + MTPR);
Sten Wang7a47dd72007-11-12 21:31:11 -0800831 lp->tx_insert_ptr = descptr->vndescp;
832
833 /* If no tx resource, stop */
834 if (!lp->tx_free_desc)
835 netif_stop_queue(dev);
836
Sten Wang7a47dd72007-11-12 21:31:11 -0800837 spin_unlock_irqrestore(&lp->lock, flags);
Stephen Hemminger613573252009-08-31 19:50:58 +0000838
839 return NETDEV_TX_OK;
Sten Wang7a47dd72007-11-12 21:31:11 -0800840}
841
Francois Romieu5ac5d612007-11-28 23:02:33 +0100842static void r6040_multicast_list(struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800843{
844 struct r6040_private *lp = netdev_priv(dev);
845 void __iomem *ioaddr = lp->base;
Sten Wang7a47dd72007-11-12 21:31:11 -0800846 unsigned long flags;
Jiri Pirko22bedad32010-04-01 21:22:57 +0000847 struct netdev_hw_addr *ha;
Sten Wang7a47dd72007-11-12 21:31:11 -0800848 int i;
Shawn Linc60c9c72011-03-07 00:09:40 +0000849 u16 *adrp;
850 u16 hash_table[4] = { 0 };
Sten Wang7a47dd72007-11-12 21:31:11 -0800851
Shawn Linc60c9c72011-03-07 00:09:40 +0000852 spin_lock_irqsave(&lp->lock, flags);
853
854 /* Keep our MAC Address */
Sten Wang7a47dd72007-11-12 21:31:11 -0800855 adrp = (u16 *)dev->dev_addr;
856 iowrite16(adrp[0], ioaddr + MID_0L);
857 iowrite16(adrp[1], ioaddr + MID_0M);
858 iowrite16(adrp[2], ioaddr + MID_0H);
859
Sten Wang7a47dd72007-11-12 21:31:11 -0800860 /* Clear AMCP & PROM bits */
Shawn Linc60c9c72011-03-07 00:09:40 +0000861 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
Sten Wang7a47dd72007-11-12 21:31:11 -0800862
Shawn Linc60c9c72011-03-07 00:09:40 +0000863 /* Promiscuous mode */
864 if (dev->flags & IFF_PROMISC)
865 lp->mcr0 |= MCR0_PROMISC;
Sten Wang7a47dd72007-11-12 21:31:11 -0800866
Shawn Linc60c9c72011-03-07 00:09:40 +0000867 /* Enable multicast hash table function to
868 * receive all multicast packets. */
869 else if (dev->flags & IFF_ALLMULTI) {
870 lp->mcr0 |= MCR0_HASH_EN;
871
872 for (i = 0; i < MCAST_MAX ; i++) {
873 iowrite16(0, ioaddr + MID_1L + 8 * i);
874 iowrite16(0, ioaddr + MID_1M + 8 * i);
875 iowrite16(0, ioaddr + MID_1H + 8 * i);
876 }
Sten Wang7a47dd72007-11-12 21:31:11 -0800877
878 for (i = 0; i < 4; i++)
Shawn Linc60c9c72011-03-07 00:09:40 +0000879 hash_table[i] = 0xffff;
880 }
881 /* Use internal multicast address registers if the number of
882 * multicast addresses is not greater than MCAST_MAX. */
883 else if (netdev_mc_count(dev) <= MCAST_MAX) {
884 i = 0;
Jiri Pirko22bedad32010-04-01 21:22:57 +0000885 netdev_for_each_mc_addr(ha, dev) {
Shawn Linc60c9c72011-03-07 00:09:40 +0000886 u16 *adrp = (u16 *) ha->addr;
887 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
888 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
889 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
890 i++;
Sten Wang7a47dd72007-11-12 21:31:11 -0800891 }
Shawn Linc60c9c72011-03-07 00:09:40 +0000892 while (i < MCAST_MAX) {
893 iowrite16(0, ioaddr + MID_1L + 8 * i);
894 iowrite16(0, ioaddr + MID_1M + 8 * i);
895 iowrite16(0, ioaddr + MID_1H + 8 * i);
896 i++;
897 }
898 }
899 /* Otherwise, Enable multicast hash table function. */
900 else {
901 u32 crc;
902
903 lp->mcr0 |= MCR0_HASH_EN;
904
905 for (i = 0; i < MCAST_MAX ; i++) {
906 iowrite16(0, ioaddr + MID_1L + 8 * i);
907 iowrite16(0, ioaddr + MID_1M + 8 * i);
908 iowrite16(0, ioaddr + MID_1H + 8 * i);
909 }
910
911 /* Build multicast hash table */
912 netdev_for_each_mc_addr(ha, dev) {
913 u8 *addrs = ha->addr;
914
915 crc = ether_crc(ETH_ALEN, addrs);
916 crc >>= 26;
917 hash_table[crc >> 4] |= 1 << (crc & 0xf);
918 }
919 }
920
921 iowrite16(lp->mcr0, ioaddr + MCR0);
922
923 /* Fill the MAC hash tables with their values */
Florian Fainellibbc13ab92011-11-16 06:00:08 +0000924 if (lp->mcr0 & MCR0_HASH_EN) {
Sten Wang7a47dd72007-11-12 21:31:11 -0800925 iowrite16(hash_table[0], ioaddr + MAR0);
926 iowrite16(hash_table[1], ioaddr + MAR1);
927 iowrite16(hash_table[2], ioaddr + MAR2);
928 iowrite16(hash_table[3], ioaddr + MAR3);
929 }
Shawn Linc60c9c72011-03-07 00:09:40 +0000930
931 spin_unlock_irqrestore(&lp->lock, flags);
Sten Wang7a47dd72007-11-12 21:31:11 -0800932}
933
934static void netdev_get_drvinfo(struct net_device *dev,
935 struct ethtool_drvinfo *info)
936{
937 struct r6040_private *rp = netdev_priv(dev);
938
Jiri Pirko7826d432013-01-06 00:44:26 +0000939 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
940 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
941 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
Sten Wang7a47dd72007-11-12 21:31:11 -0800942}
943
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -0800944static const struct ethtool_ops netdev_ethtool_ops = {
Sten Wang7a47dd72007-11-12 21:31:11 -0800945 .get_drvinfo = netdev_get_drvinfo,
Florian Fainelli38318612010-05-31 09:18:57 +0000946 .get_link = ethtool_op_get_link,
Richard Cochrand88e1022012-04-03 22:59:34 +0000947 .get_ts_info = ethtool_op_get_ts_info,
Philippe Reynescffce3612016-06-25 21:09:02 +0200948 .get_link_ksettings = phy_ethtool_get_link_ksettings,
949 .set_link_ksettings = phy_ethtool_set_link_ksettings,
Sten Wang7a47dd72007-11-12 21:31:11 -0800950};
951
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -0800952static const struct net_device_ops r6040_netdev_ops = {
953 .ndo_open = r6040_open,
954 .ndo_stop = r6040_close,
955 .ndo_start_xmit = r6040_start_xmit,
956 .ndo_get_stats = r6040_get_stats,
Jiri Pirkoafc4b132011-08-16 06:29:01 +0000957 .ndo_set_rx_mode = r6040_multicast_list,
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -0800958 .ndo_validate_addr = eth_validate_addr,
Florian Fainelli2154c7042010-08-08 10:08:44 +0000959 .ndo_set_mac_address = eth_mac_addr,
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -0800960 .ndo_do_ioctl = r6040_ioctl,
961 .ndo_tx_timeout = r6040_tx_timeout,
962#ifdef CONFIG_NET_POLL_CONTROLLER
963 .ndo_poll_controller = r6040_poll_controller,
964#endif
965};
966
Florian Fainelli38318612010-05-31 09:18:57 +0000967static void r6040_adjust_link(struct net_device *dev)
968{
969 struct r6040_private *lp = netdev_priv(dev);
Philippe Reynes542808f2016-06-25 21:09:01 +0200970 struct phy_device *phydev = dev->phydev;
Florian Fainelli38318612010-05-31 09:18:57 +0000971 int status_changed = 0;
972 void __iomem *ioaddr = lp->base;
973
974 BUG_ON(!phydev);
975
976 if (lp->old_link != phydev->link) {
977 status_changed = 1;
978 lp->old_link = phydev->link;
979 }
980
981 /* reflect duplex change */
982 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
Florian Fainelli4e16d6e2012-01-04 08:59:34 +0000983 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
Florian Fainelli38318612010-05-31 09:18:57 +0000984 iowrite16(lp->mcr0, ioaddr);
985
986 status_changed = 1;
987 lp->old_duplex = phydev->duplex;
988 }
989
Florian Fainelli3eb415d2016-07-04 14:36:01 -0700990 if (status_changed)
991 phy_print_status(phydev);
Florian Fainelli38318612010-05-31 09:18:57 +0000992}
993
994static int r6040_mii_probe(struct net_device *dev)
995{
996 struct r6040_private *lp = netdev_priv(dev);
997 struct phy_device *phydev = NULL;
998
999 phydev = phy_find_first(lp->mii_bus);
1000 if (!phydev) {
1001 dev_err(&lp->pdev->dev, "no PHY found\n");
1002 return -ENODEV;
1003 }
1004
Andrew Lunn84eff6d2016-01-06 20:11:10 +01001005 phydev = phy_connect(dev, phydev_name(phydev), &r6040_adjust_link,
Florian Fainellif9a8f832013-01-14 00:52:52 +00001006 PHY_INTERFACE_MODE_MII);
Florian Fainelli38318612010-05-31 09:18:57 +00001007
1008 if (IS_ERR(phydev)) {
1009 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1010 return PTR_ERR(phydev);
1011 }
1012
Andrew Lunn58056c12018-09-12 01:53:11 +02001013 phy_set_max_speed(phydev, SPEED_100);
Florian Fainelli38318612010-05-31 09:18:57 +00001014
Florian Fainelli38318612010-05-31 09:18:57 +00001015 lp->old_link = 0;
1016 lp->old_duplex = -1;
1017
Andrew Lunn22209432016-01-06 20:11:13 +01001018 phy_attached_info(phydev);
Florian Fainelli38318612010-05-31 09:18:57 +00001019
1020 return 0;
1021}
1022
Greg Kroah-Hartman1dd06ae2012-12-06 14:30:56 +00001023static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Sten Wang7a47dd72007-11-12 21:31:11 -08001024{
1025 struct net_device *dev;
1026 struct r6040_private *lp;
1027 void __iomem *ioaddr;
1028 int err, io_size = R6040_IO_SIZE;
1029 static int card_idx = -1;
1030 int bar = 0;
Sten Wang7a47dd72007-11-12 21:31:11 -08001031 u16 *adrp;
1032
Florian Fainelli2154c7042010-08-08 10:08:44 +00001033 pr_info("%s\n", version);
Sten Wang7a47dd72007-11-12 21:31:11 -08001034
1035 err = pci_enable_device(pdev);
1036 if (err)
Florian Fainellib0e45392008-07-21 12:32:29 +02001037 goto err_out;
Sten Wang7a47dd72007-11-12 21:31:11 -08001038
1039 /* this should always be supported */
Yang Hongyang284901a2009-04-06 19:01:15 -07001040 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Florian Fainellib0e45392008-07-21 12:32:29 +02001041 if (err) {
Colin Ian King22da7342016-09-16 10:43:38 +01001042 dev_err(&pdev->dev, "32-bit PCI DMA addresses not supported by the card\n");
Devendra Nagaacaf8272012-05-29 13:38:42 +00001043 goto err_out_disable_dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001044 }
Yang Hongyang284901a2009-04-06 19:01:15 -07001045 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Florian Fainellib0e45392008-07-21 12:32:29 +02001046 if (err) {
Colin Ian King22da7342016-09-16 10:43:38 +01001047 dev_err(&pdev->dev, "32-bit PCI DMA addresses not supported by the card\n");
Devendra Nagaacaf8272012-05-29 13:38:42 +00001048 goto err_out_disable_dev;
Jeff Garzik092427b2007-11-23 21:49:27 -05001049 }
Sten Wang7a47dd72007-11-12 21:31:11 -08001050
1051 /* IO Size check */
Michael Opdenacker6f5bec12009-06-24 21:05:09 +00001052 if (pci_resource_len(pdev, bar) < io_size) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001053 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
Florian Fainellib0e45392008-07-21 12:32:29 +02001054 err = -EIO;
Devendra Nagaacaf8272012-05-29 13:38:42 +00001055 goto err_out_disable_dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001056 }
1057
Sten Wang7a47dd72007-11-12 21:31:11 -08001058 pci_set_master(pdev);
1059
1060 dev = alloc_etherdev(sizeof(struct r6040_private));
1061 if (!dev) {
Florian Fainellib0e45392008-07-21 12:32:29 +02001062 err = -ENOMEM;
Devendra Nagaacaf8272012-05-29 13:38:42 +00001063 goto err_out_disable_dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001064 }
1065 SET_NETDEV_DEV(dev, &pdev->dev);
1066 lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -08001067
Florian Fainellib0e45392008-07-21 12:32:29 +02001068 err = pci_request_regions(pdev, DRV_NAME);
1069
1070 if (err) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001071 dev_err(&pdev->dev, "Failed to request PCI regions\n");
Florian Fainellib0e45392008-07-21 12:32:29 +02001072 goto err_out_free_dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001073 }
1074
1075 ioaddr = pci_iomap(pdev, bar, io_size);
1076 if (!ioaddr) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001077 dev_err(&pdev->dev, "ioremap failed for device\n");
Florian Fainellib0e45392008-07-21 12:32:29 +02001078 err = -EIO;
1079 goto err_out_free_res;
Sten Wang7a47dd72007-11-12 21:31:11 -08001080 }
Florian Fainelli31171ae2012-04-11 07:18:42 +00001081
Florian Fainelli84314bf2009-01-08 11:01:58 -08001082 /* If PHY status change register is still set to zero it means the
Florian Fainelli31171ae2012-04-11 07:18:42 +00001083 * bootloader didn't initialize it, so we set it to:
1084 * - enable phy status change
1085 * - enable all phy addresses
1086 * - set to lowest timer divider */
Florian Fainelli84314bf2009-01-08 11:01:58 -08001087 if (ioread16(ioaddr + PHY_CC) == 0)
Florian Fainelli31171ae2012-04-11 07:18:42 +00001088 iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1089 7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
Sten Wang7a47dd72007-11-12 21:31:11 -08001090
1091 /* Init system & device */
Sten Wang7a47dd72007-11-12 21:31:11 -08001092 lp->base = ioaddr;
1093 dev->irq = pdev->irq;
1094
1095 spin_lock_init(&lp->lock);
1096 pci_set_drvdata(pdev, dev);
1097
1098 /* Set MAC address */
1099 card_idx++;
1100
1101 adrp = (u16 *)dev->dev_addr;
1102 adrp[0] = ioread16(ioaddr + MID_0L);
1103 adrp[1] = ioread16(ioaddr + MID_0M);
1104 adrp[2] = ioread16(ioaddr + MID_0H);
1105
Florian Fainelli1d2b1a72009-01-08 11:02:30 -08001106 /* Some bootloader/BIOSes do not initialize
1107 * MAC address, warn about that */
Florian Fainelli9f113612009-01-08 15:04:45 +00001108 if (!(adrp[0] || adrp[1] || adrp[2])) {
Florian Fainelli2154c7042010-08-08 10:08:44 +00001109 netdev_warn(dev, "MAC address not initialized, "
1110 "generating random\n");
Danny Kukawkaf2cedb62012-02-15 06:45:39 +00001111 eth_hw_addr_random(dev);
Florian Fainelli9f113612009-01-08 15:04:45 +00001112 }
Florian Fainelli1d2b1a72009-01-08 11:02:30 -08001113
Sten Wang7a47dd72007-11-12 21:31:11 -08001114 /* Link new device into r6040_root_dev */
1115 lp->pdev = pdev;
Florian Fainelli129cf9a2008-07-13 14:32:45 +02001116 lp->dev = dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001117
1118 /* Init RDC private data */
Cesar Eduardo Barros77e1e432012-01-07 05:13:17 +00001119 lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
Sten Wang7a47dd72007-11-12 21:31:11 -08001120
1121 /* The RDC-specific entries in the device structure. */
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -08001122 dev->netdev_ops = &r6040_netdev_ops;
Sten Wang7a47dd72007-11-12 21:31:11 -08001123 dev->ethtool_ops = &netdev_ethtool_ops;
Sten Wang7a47dd72007-11-12 21:31:11 -08001124 dev->watchdog_timeo = TX_TIMEOUT;
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -08001125
Sten Wang7a47dd72007-11-12 21:31:11 -08001126 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
Sten Wang7a47dd72007-11-12 21:31:11 -08001127
Florian Fainelli38318612010-05-31 09:18:57 +00001128 lp->mii_bus = mdiobus_alloc();
1129 if (!lp->mii_bus) {
1130 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
Axel Lin9c86c0f2011-01-04 22:40:04 +00001131 err = -ENOMEM;
Mark Kellye03f6142009-08-20 01:26:20 +00001132 goto err_out_unmap;
1133 }
1134
Florian Fainelli38318612010-05-31 09:18:57 +00001135 lp->mii_bus->priv = dev;
1136 lp->mii_bus->read = r6040_mdiobus_read;
1137 lp->mii_bus->write = r6040_mdiobus_write;
Florian Fainelli38318612010-05-31 09:18:57 +00001138 lp->mii_bus->name = "r6040_eth_mii";
Florian Fainelli817380e2012-01-04 08:50:40 +00001139 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1140 dev_name(&pdev->dev), card_idx);
Florian Fainelli38318612010-05-31 09:18:57 +00001141
1142 err = mdiobus_register(lp->mii_bus);
1143 if (err) {
1144 dev_err(&pdev->dev, "failed to register MII bus\n");
Andrew Lunne7f4dc32016-01-06 20:11:15 +01001145 goto err_out_mdio;
Florian Fainelli38318612010-05-31 09:18:57 +00001146 }
1147
1148 err = r6040_mii_probe(dev);
1149 if (err) {
1150 dev_err(&pdev->dev, "failed to probe MII bus\n");
1151 goto err_out_mdio_unregister;
1152 }
1153
Sten Wang7a47dd72007-11-12 21:31:11 -08001154 /* Register net device. After this dev->name assign */
1155 err = register_netdev(dev);
1156 if (err) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001157 dev_err(&pdev->dev, "Failed to register net device\n");
Florian Fainelli38318612010-05-31 09:18:57 +00001158 goto err_out_mdio_unregister;
Sten Wang7a47dd72007-11-12 21:31:11 -08001159 }
1160 return 0;
1161
Florian Fainelli38318612010-05-31 09:18:57 +00001162err_out_mdio_unregister:
1163 mdiobus_unregister(lp->mii_bus);
Florian Fainelli38318612010-05-31 09:18:57 +00001164err_out_mdio:
1165 mdiobus_free(lp->mii_bus);
Florian Fainellib0e45392008-07-21 12:32:29 +02001166err_out_unmap:
Devendra Naga20571d82012-05-29 13:43:34 +00001167 netif_napi_del(&lp->napi);
Florian Fainellib0e45392008-07-21 12:32:29 +02001168 pci_iounmap(pdev, ioaddr);
1169err_out_free_res:
Sten Wang7a47dd72007-11-12 21:31:11 -08001170 pci_release_regions(pdev);
Florian Fainellib0e45392008-07-21 12:32:29 +02001171err_out_free_dev:
Sten Wang7a47dd72007-11-12 21:31:11 -08001172 free_netdev(dev);
Devendra Nagaacaf8272012-05-29 13:38:42 +00001173err_out_disable_dev:
1174 pci_disable_device(pdev);
Florian Fainellib0e45392008-07-21 12:32:29 +02001175err_out:
Sten Wang7a47dd72007-11-12 21:31:11 -08001176 return err;
1177}
1178
Bill Pembertonf1e24262012-12-03 09:23:30 -05001179static void r6040_remove_one(struct pci_dev *pdev)
Sten Wang7a47dd72007-11-12 21:31:11 -08001180{
1181 struct net_device *dev = pci_get_drvdata(pdev);
Florian Fainelli38318612010-05-31 09:18:57 +00001182 struct r6040_private *lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -08001183
1184 unregister_netdev(dev);
Florian Fainelli38318612010-05-31 09:18:57 +00001185 mdiobus_unregister(lp->mii_bus);
Florian Fainelli38318612010-05-31 09:18:57 +00001186 mdiobus_free(lp->mii_bus);
Devendra Naga20571d82012-05-29 13:43:34 +00001187 netif_napi_del(&lp->napi);
Devendra Naga20571d82012-05-29 13:43:34 +00001188 pci_iounmap(pdev, lp->base);
Sten Wang7a47dd72007-11-12 21:31:11 -08001189 pci_release_regions(pdev);
1190 free_netdev(dev);
1191 pci_disable_device(pdev);
Sten Wang7a47dd72007-11-12 21:31:11 -08001192}
1193
1194
Benoit Taine9baa3c32014-08-08 15:56:03 +02001195static const struct pci_device_id r6040_pci_tbl[] = {
Francois Romieu5ac5d612007-11-28 23:02:33 +01001196 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1197 { 0 }
Sten Wang7a47dd72007-11-12 21:31:11 -08001198};
1199MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1200
1201static struct pci_driver r6040_driver = {
Francois Romieu5ac5d612007-11-28 23:02:33 +01001202 .name = DRV_NAME,
Sten Wang7a47dd72007-11-12 21:31:11 -08001203 .id_table = r6040_pci_tbl,
1204 .probe = r6040_init_one,
Bill Pembertonf1e24262012-12-03 09:23:30 -05001205 .remove = r6040_remove_one,
Sten Wang7a47dd72007-11-12 21:31:11 -08001206};
1207
Devendra Naga36efc942012-07-08 05:57:57 +00001208module_pci_driver(r6040_driver);