blob: 4e983bc6cf93c3cb67fa25a1efbd17fc5b77855b [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Ard Biesheuvel706cffc2017-11-06 18:34:37 +00002/*
3 * Driver for Socionext External Interrupt Unit (EXIU)
4 *
5 * Copyright (c) 2017 Linaro, Ltd. <ard.biesheuvel@linaro.org>
6 *
7 * Based on irq-tegra.c:
8 * Copyright (C) 2011 Google, Inc.
9 * Copyright (C) 2010,2013, NVIDIA Corporation
Ard Biesheuvel706cffc2017-11-06 18:34:37 +000010 */
11
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/irqchip.h>
16#include <linux/irqdomain.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20
21#include <dt-bindings/interrupt-controller/arm-gic.h>
22
23#define NUM_IRQS 32
24
25#define EIMASK 0x00
26#define EISRCSEL 0x04
27#define EIREQSTA 0x08
28#define EIRAWREQSTA 0x0C
29#define EIREQCLR 0x10
30#define EILVL 0x14
31#define EIEDG 0x18
32#define EISIR 0x1C
33
34struct exiu_irq_data {
35 void __iomem *base;
36 u32 spi_base;
37};
38
39static void exiu_irq_eoi(struct irq_data *d)
40{
41 struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
42
43 writel(BIT(d->hwirq), data->base + EIREQCLR);
44 irq_chip_eoi_parent(d);
45}
46
47static void exiu_irq_mask(struct irq_data *d)
48{
49 struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
50 u32 val;
51
52 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq);
53 writel_relaxed(val, data->base + EIMASK);
54 irq_chip_mask_parent(d);
55}
56
57static void exiu_irq_unmask(struct irq_data *d)
58{
59 struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
60 u32 val;
61
62 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
63 writel_relaxed(val, data->base + EIMASK);
64 irq_chip_unmask_parent(d);
65}
66
67static void exiu_irq_enable(struct irq_data *d)
68{
69 struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
70 u32 val;
71
72 /* clear interrupts that were latched while disabled */
73 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
74
75 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
76 writel_relaxed(val, data->base + EIMASK);
77 irq_chip_enable_parent(d);
78}
79
80static int exiu_irq_set_type(struct irq_data *d, unsigned int type)
81{
82 struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
83 u32 val;
84
85 val = readl_relaxed(data->base + EILVL);
86 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
87 val |= BIT(d->hwirq);
88 else
89 val &= ~BIT(d->hwirq);
90 writel_relaxed(val, data->base + EILVL);
91
92 val = readl_relaxed(data->base + EIEDG);
93 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
94 val &= ~BIT(d->hwirq);
95 else
96 val |= BIT(d->hwirq);
97 writel_relaxed(val, data->base + EIEDG);
98
99 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
100
101 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
102}
103
104static struct irq_chip exiu_irq_chip = {
105 .name = "EXIU",
106 .irq_eoi = exiu_irq_eoi,
107 .irq_enable = exiu_irq_enable,
108 .irq_mask = exiu_irq_mask,
109 .irq_unmask = exiu_irq_unmask,
110 .irq_set_type = exiu_irq_set_type,
111 .irq_set_affinity = irq_chip_set_affinity_parent,
112 .flags = IRQCHIP_SET_TYPE_MASKED |
113 IRQCHIP_SKIP_SET_WAKE |
114 IRQCHIP_EOI_THREADED |
115 IRQCHIP_MASK_ON_SUSPEND,
116};
117
118static int exiu_domain_translate(struct irq_domain *domain,
119 struct irq_fwspec *fwspec,
120 unsigned long *hwirq,
121 unsigned int *type)
122{
123 struct exiu_irq_data *info = domain->host_data;
124
125 if (is_of_node(fwspec->fwnode)) {
126 if (fwspec->param_count != 3)
127 return -EINVAL;
128
129 if (fwspec->param[0] != GIC_SPI)
130 return -EINVAL; /* No PPI should point to this domain */
131
132 *hwirq = fwspec->param[1] - info->spi_base;
133 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
134 return 0;
135 }
136 return -EINVAL;
137}
138
139static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq,
140 unsigned int nr_irqs, void *data)
141{
142 struct irq_fwspec *fwspec = data;
143 struct irq_fwspec parent_fwspec;
144 struct exiu_irq_data *info = dom->host_data;
145 irq_hw_number_t hwirq;
146
147 if (fwspec->param_count != 3)
148 return -EINVAL; /* Not GIC compliant */
149 if (fwspec->param[0] != GIC_SPI)
150 return -EINVAL; /* No PPI should point to this domain */
151
152 WARN_ON(nr_irqs != 1);
153 hwirq = fwspec->param[1] - info->spi_base;
154 irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info);
155
156 parent_fwspec = *fwspec;
157 parent_fwspec.fwnode = dom->parent->fwnode;
158 return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec);
159}
160
161static const struct irq_domain_ops exiu_domain_ops = {
162 .translate = exiu_domain_translate,
163 .alloc = exiu_domain_alloc,
164 .free = irq_domain_free_irqs_common,
165};
166
167static int __init exiu_init(struct device_node *node,
168 struct device_node *parent)
169{
170 struct irq_domain *parent_domain, *domain;
171 struct exiu_irq_data *data;
172 int err;
173
174 if (!parent) {
175 pr_err("%pOF: no parent, giving up\n", node);
176 return -ENODEV;
177 }
178
179 parent_domain = irq_find_host(parent);
180 if (!parent_domain) {
181 pr_err("%pOF: unable to obtain parent domain\n", node);
182 return -ENXIO;
183 }
184
185 data = kzalloc(sizeof(*data), GFP_KERNEL);
186 if (!data)
187 return -ENOMEM;
188
189 if (of_property_read_u32(node, "socionext,spi-base", &data->spi_base)) {
190 pr_err("%pOF: failed to parse 'spi-base' property\n", node);
191 err = -ENODEV;
192 goto out_free;
193 }
194
195 data->base = of_iomap(node, 0);
Wei Yongjun0e547052017-11-14 06:57:28 +0000196 if (!data->base) {
197 err = -ENODEV;
Ard Biesheuvel706cffc2017-11-06 18:34:37 +0000198 goto out_free;
199 }
200
201 /* clear and mask all interrupts */
202 writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
203 writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
204
205 domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node,
206 &exiu_domain_ops, data);
207 if (!domain) {
208 pr_err("%pOF: failed to allocate domain\n", node);
209 err = -ENOMEM;
210 goto out_unmap;
211 }
212
213 pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS,
214 parent);
215
216 return 0;
217
218out_unmap:
219 iounmap(data->base);
220out_free:
221 kfree(data);
222 return err;
223}
224IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_init);