Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Samsung SoC MIPI DSI Master driver. |
| 4 | * |
| 5 | * Copyright (c) 2014 Samsung Electronics Co., Ltd |
| 6 | * |
| 7 | * Contacts: Tomasz Figa <t.figa@samsung.com> |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 8 | */ |
| 9 | |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 10 | #include <asm/unaligned.h> |
| 11 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 12 | #include <drm/drmP.h> |
Daniel Vetter | fcd70cd | 2019-01-17 22:03:34 +0100 | [diff] [blame] | 13 | #include <drm/drm_atomic_helper.h> |
Andrzej Hajda | deee328 | 2018-10-26 12:40:03 +0200 | [diff] [blame] | 14 | #include <drm/drm_fb_helper.h> |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 15 | #include <drm/drm_mipi_dsi.h> |
| 16 | #include <drm/drm_panel.h> |
Daniel Vetter | fcd70cd | 2019-01-17 22:03:34 +0100 | [diff] [blame] | 17 | #include <drm/drm_probe_helper.h> |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 18 | |
| 19 | #include <linux/clk.h> |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 20 | #include <linux/gpio/consumer.h> |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 21 | #include <linux/irq.h> |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 22 | #include <linux/of_device.h> |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 23 | #include <linux/of_gpio.h> |
Hyungwon Hwang | f5f3b9b | 2015-06-12 21:59:08 +0900 | [diff] [blame] | 24 | #include <linux/of_graph.h> |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 25 | #include <linux/phy/phy.h> |
| 26 | #include <linux/regulator/consumer.h> |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 27 | #include <linux/component.h> |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 28 | |
| 29 | #include <video/mipi_display.h> |
| 30 | #include <video/videomode.h> |
| 31 | |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 32 | #include "exynos_drm_crtc.h" |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 33 | #include "exynos_drm_drv.h" |
| 34 | |
| 35 | /* returns true iff both arguments logically differs */ |
| 36 | #define NEQV(a, b) (!(a) ^ !(b)) |
| 37 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 38 | /* DSIM_STATUS */ |
| 39 | #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) |
| 40 | #define DSIM_STOP_STATE_CLK (1 << 8) |
| 41 | #define DSIM_TX_READY_HS_CLK (1 << 10) |
| 42 | #define DSIM_PLL_STABLE (1 << 31) |
| 43 | |
| 44 | /* DSIM_SWRST */ |
| 45 | #define DSIM_FUNCRST (1 << 16) |
| 46 | #define DSIM_SWRST (1 << 0) |
| 47 | |
| 48 | /* DSIM_TIMEOUT */ |
| 49 | #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) |
| 50 | #define DSIM_BTA_TIMEOUT(x) ((x) << 16) |
| 51 | |
| 52 | /* DSIM_CLKCTRL */ |
| 53 | #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) |
| 54 | #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) |
| 55 | #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) |
| 56 | #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) |
| 57 | #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) |
| 58 | #define DSIM_BYTE_CLKEN (1 << 24) |
| 59 | #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) |
| 60 | #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) |
| 61 | #define DSIM_PLL_BYPASS (1 << 27) |
| 62 | #define DSIM_ESC_CLKEN (1 << 28) |
| 63 | #define DSIM_TX_REQUEST_HSCLK (1 << 31) |
| 64 | |
| 65 | /* DSIM_CONFIG */ |
| 66 | #define DSIM_LANE_EN_CLK (1 << 0) |
| 67 | #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) |
| 68 | #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) |
| 69 | #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) |
| 70 | #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) |
| 71 | #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) |
| 72 | #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) |
| 73 | #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) |
| 74 | #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) |
| 75 | #define DSIM_SUB_VC (((x) & 0x3) << 16) |
| 76 | #define DSIM_MAIN_VC (((x) & 0x3) << 18) |
| 77 | #define DSIM_HSA_MODE (1 << 20) |
| 78 | #define DSIM_HBP_MODE (1 << 21) |
| 79 | #define DSIM_HFP_MODE (1 << 22) |
| 80 | #define DSIM_HSE_MODE (1 << 23) |
| 81 | #define DSIM_AUTO_MODE (1 << 24) |
| 82 | #define DSIM_VIDEO_MODE (1 << 25) |
| 83 | #define DSIM_BURST_MODE (1 << 26) |
| 84 | #define DSIM_SYNC_INFORM (1 << 27) |
| 85 | #define DSIM_EOT_DISABLE (1 << 28) |
| 86 | #define DSIM_MFLUSH_VS (1 << 29) |
Krzysztof Kozlowski | 6bdc92e | 2017-03-11 20:04:16 +0200 | [diff] [blame] | 87 | /* This flag is valid only for exynos3250/3472/5260/5430 */ |
Inki Dae | 78d3a8c | 2014-08-13 17:03:12 +0900 | [diff] [blame] | 88 | #define DSIM_CLKLANE_STOP (1 << 30) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 89 | |
| 90 | /* DSIM_ESCMODE */ |
| 91 | #define DSIM_TX_TRIGGER_RST (1 << 4) |
| 92 | #define DSIM_TX_LPDT_LP (1 << 6) |
| 93 | #define DSIM_CMD_LPDT_LP (1 << 7) |
| 94 | #define DSIM_FORCE_BTA (1 << 16) |
| 95 | #define DSIM_FORCE_STOP_STATE (1 << 20) |
| 96 | #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) |
| 97 | #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) |
| 98 | |
| 99 | /* DSIM_MDRESOL */ |
| 100 | #define DSIM_MAIN_STAND_BY (1 << 31) |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 101 | #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) |
| 102 | #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 103 | |
| 104 | /* DSIM_MVPORCH */ |
| 105 | #define DSIM_CMD_ALLOW(x) ((x) << 28) |
| 106 | #define DSIM_STABLE_VFP(x) ((x) << 16) |
| 107 | #define DSIM_MAIN_VBP(x) ((x) << 0) |
| 108 | #define DSIM_CMD_ALLOW_MASK (0xf << 28) |
| 109 | #define DSIM_STABLE_VFP_MASK (0x7ff << 16) |
| 110 | #define DSIM_MAIN_VBP_MASK (0x7ff << 0) |
| 111 | |
| 112 | /* DSIM_MHPORCH */ |
| 113 | #define DSIM_MAIN_HFP(x) ((x) << 16) |
| 114 | #define DSIM_MAIN_HBP(x) ((x) << 0) |
| 115 | #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) |
| 116 | #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) |
| 117 | |
| 118 | /* DSIM_MSYNC */ |
| 119 | #define DSIM_MAIN_VSA(x) ((x) << 22) |
| 120 | #define DSIM_MAIN_HSA(x) ((x) << 0) |
| 121 | #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) |
| 122 | #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) |
| 123 | |
| 124 | /* DSIM_SDRESOL */ |
| 125 | #define DSIM_SUB_STANDY(x) ((x) << 31) |
| 126 | #define DSIM_SUB_VRESOL(x) ((x) << 16) |
| 127 | #define DSIM_SUB_HRESOL(x) ((x) << 0) |
| 128 | #define DSIM_SUB_STANDY_MASK ((0x1) << 31) |
| 129 | #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) |
| 130 | #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) |
| 131 | |
| 132 | /* DSIM_INTSRC */ |
| 133 | #define DSIM_INT_PLL_STABLE (1 << 31) |
| 134 | #define DSIM_INT_SW_RST_RELEASE (1 << 30) |
| 135 | #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 136 | #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 137 | #define DSIM_INT_BTA (1 << 25) |
| 138 | #define DSIM_INT_FRAME_DONE (1 << 24) |
| 139 | #define DSIM_INT_RX_TIMEOUT (1 << 21) |
| 140 | #define DSIM_INT_BTA_TIMEOUT (1 << 20) |
| 141 | #define DSIM_INT_RX_DONE (1 << 18) |
| 142 | #define DSIM_INT_RX_TE (1 << 17) |
| 143 | #define DSIM_INT_RX_ACK (1 << 16) |
| 144 | #define DSIM_INT_RX_ECC_ERR (1 << 15) |
| 145 | #define DSIM_INT_RX_CRC_ERR (1 << 14) |
| 146 | |
| 147 | /* DSIM_FIFOCTRL */ |
| 148 | #define DSIM_RX_DATA_FULL (1 << 25) |
| 149 | #define DSIM_RX_DATA_EMPTY (1 << 24) |
| 150 | #define DSIM_SFR_HEADER_FULL (1 << 23) |
| 151 | #define DSIM_SFR_HEADER_EMPTY (1 << 22) |
| 152 | #define DSIM_SFR_PAYLOAD_FULL (1 << 21) |
| 153 | #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) |
| 154 | #define DSIM_I80_HEADER_FULL (1 << 19) |
| 155 | #define DSIM_I80_HEADER_EMPTY (1 << 18) |
| 156 | #define DSIM_I80_PAYLOAD_FULL (1 << 17) |
| 157 | #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) |
| 158 | #define DSIM_SD_HEADER_FULL (1 << 15) |
| 159 | #define DSIM_SD_HEADER_EMPTY (1 << 14) |
| 160 | #define DSIM_SD_PAYLOAD_FULL (1 << 13) |
| 161 | #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) |
| 162 | #define DSIM_MD_HEADER_FULL (1 << 11) |
| 163 | #define DSIM_MD_HEADER_EMPTY (1 << 10) |
| 164 | #define DSIM_MD_PAYLOAD_FULL (1 << 9) |
| 165 | #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) |
| 166 | #define DSIM_RX_FIFO (1 << 4) |
| 167 | #define DSIM_SFR_FIFO (1 << 3) |
| 168 | #define DSIM_I80_FIFO (1 << 2) |
| 169 | #define DSIM_SD_FIFO (1 << 1) |
| 170 | #define DSIM_MD_FIFO (1 << 0) |
| 171 | |
| 172 | /* DSIM_PHYACCHR */ |
| 173 | #define DSIM_AFC_EN (1 << 14) |
| 174 | #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) |
| 175 | |
| 176 | /* DSIM_PLLCTRL */ |
| 177 | #define DSIM_FREQ_BAND(x) ((x) << 24) |
| 178 | #define DSIM_PLL_EN (1 << 23) |
| 179 | #define DSIM_PLL_P(x) ((x) << 13) |
| 180 | #define DSIM_PLL_M(x) ((x) << 4) |
| 181 | #define DSIM_PLL_S(x) ((x) << 1) |
| 182 | |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 183 | /* DSIM_PHYCTRL */ |
| 184 | #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 185 | #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) |
| 186 | #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 187 | |
| 188 | /* DSIM_PHYTIMING */ |
| 189 | #define DSIM_PHYTIMING_LPX(x) ((x) << 8) |
| 190 | #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) |
| 191 | |
| 192 | /* DSIM_PHYTIMING1 */ |
| 193 | #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) |
| 194 | #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) |
| 195 | #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) |
| 196 | #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) |
| 197 | |
| 198 | /* DSIM_PHYTIMING2 */ |
| 199 | #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) |
| 200 | #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) |
| 201 | #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) |
| 202 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 203 | #define DSI_MAX_BUS_WIDTH 4 |
| 204 | #define DSI_NUM_VIRTUAL_CHANNELS 4 |
| 205 | #define DSI_TX_FIFO_SIZE 2048 |
| 206 | #define DSI_RX_FIFO_SIZE 256 |
| 207 | #define DSI_XFER_TIMEOUT_MS 100 |
| 208 | #define DSI_RX_FIFO_EMPTY 0x30800002 |
| 209 | |
Hyungwon Hwang | 26269af | 2015-06-12 21:59:03 +0900 | [diff] [blame] | 210 | #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" |
| 211 | |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 212 | static char *clk_names[5] = { "bus_clk", "sclk_mipi", |
| 213 | "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", |
| 214 | "sclk_rgb_vclk_to_dsim0" }; |
Hyungwon Hwang | 0ff03fd | 2015-06-12 21:59:06 +0900 | [diff] [blame] | 215 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 216 | enum exynos_dsi_transfer_type { |
| 217 | EXYNOS_DSI_TX, |
| 218 | EXYNOS_DSI_RX, |
| 219 | }; |
| 220 | |
| 221 | struct exynos_dsi_transfer { |
| 222 | struct list_head list; |
| 223 | struct completion completed; |
| 224 | int result; |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 225 | struct mipi_dsi_packet packet; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 226 | u16 flags; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 227 | u16 tx_done; |
| 228 | |
| 229 | u8 *rx_payload; |
| 230 | u16 rx_len; |
| 231 | u16 rx_done; |
| 232 | }; |
| 233 | |
| 234 | #define DSIM_STATE_ENABLED BIT(0) |
| 235 | #define DSIM_STATE_INITIALIZED BIT(1) |
| 236 | #define DSIM_STATE_CMD_LPM BIT(2) |
Hyungwon Hwang | 0e480f6 | 2015-06-11 23:40:30 +0900 | [diff] [blame] | 237 | #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 238 | |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 239 | struct exynos_dsi_driver_data { |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 240 | const unsigned int *reg_ofs; |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 241 | unsigned int plltmr_reg; |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 242 | unsigned int has_freqband:1; |
Inki Dae | 78d3a8c | 2014-08-13 17:03:12 +0900 | [diff] [blame] | 243 | unsigned int has_clklane_stop:1; |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 244 | unsigned int num_clks; |
| 245 | unsigned int max_freq; |
| 246 | unsigned int wait_for_reset; |
| 247 | unsigned int num_bits_resol; |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 248 | const unsigned int *reg_values; |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 249 | }; |
| 250 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 251 | struct exynos_dsi { |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 252 | struct drm_encoder encoder; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 253 | struct mipi_dsi_host dsi_host; |
| 254 | struct drm_connector connector; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 255 | struct drm_panel *panel; |
Maciej Purski | 6afb772 | 2018-08-07 16:50:59 +0900 | [diff] [blame] | 256 | struct drm_bridge *out_bridge; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 257 | struct device *dev; |
| 258 | |
| 259 | void __iomem *reg_base; |
| 260 | struct phy *phy; |
Hyungwon Hwang | 0ff03fd | 2015-06-12 21:59:06 +0900 | [diff] [blame] | 261 | struct clk **clks; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 262 | struct regulator_bulk_data supplies[2]; |
| 263 | int irq; |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 264 | int te_gpio; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 265 | |
| 266 | u32 pll_clk_rate; |
| 267 | u32 burst_clk_rate; |
| 268 | u32 esc_clk_rate; |
| 269 | u32 lanes; |
| 270 | u32 mode_flags; |
| 271 | u32 format; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 272 | |
| 273 | int state; |
| 274 | struct drm_property *brightness; |
| 275 | struct completion completed; |
| 276 | |
| 277 | spinlock_t transfer_lock; /* protects transfer_list */ |
| 278 | struct list_head transfer_list; |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 279 | |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 280 | const struct exynos_dsi_driver_data *driver_data; |
Maciej Purski | 2782622 | 2018-07-25 17:46:36 +0200 | [diff] [blame] | 281 | struct device_node *in_bridge_node; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 282 | }; |
| 283 | |
| 284 | #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) |
| 285 | #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) |
| 286 | |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 287 | static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e) |
Andrzej Hajda | 5cd5db8 | 2014-10-07 14:01:11 +0200 | [diff] [blame] | 288 | { |
Gustavo Padovan | cf67cc9 | 2015-08-11 17:38:06 +0900 | [diff] [blame] | 289 | return container_of(e, struct exynos_dsi, encoder); |
Andrzej Hajda | 5cd5db8 | 2014-10-07 14:01:11 +0200 | [diff] [blame] | 290 | } |
| 291 | |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 292 | enum reg_idx { |
| 293 | DSIM_STATUS_REG, /* Status register */ |
| 294 | DSIM_SWRST_REG, /* Software reset register */ |
| 295 | DSIM_CLKCTRL_REG, /* Clock control register */ |
| 296 | DSIM_TIMEOUT_REG, /* Time out register */ |
| 297 | DSIM_CONFIG_REG, /* Configuration register */ |
| 298 | DSIM_ESCMODE_REG, /* Escape mode register */ |
| 299 | DSIM_MDRESOL_REG, |
| 300 | DSIM_MVPORCH_REG, /* Main display Vporch register */ |
| 301 | DSIM_MHPORCH_REG, /* Main display Hporch register */ |
| 302 | DSIM_MSYNC_REG, /* Main display sync area register */ |
| 303 | DSIM_INTSRC_REG, /* Interrupt source register */ |
| 304 | DSIM_INTMSK_REG, /* Interrupt mask register */ |
| 305 | DSIM_PKTHDR_REG, /* Packet Header FIFO register */ |
| 306 | DSIM_PAYLOAD_REG, /* Payload FIFO register */ |
| 307 | DSIM_RXFIFO_REG, /* Read FIFO register */ |
| 308 | DSIM_FIFOCTRL_REG, /* FIFO status and control register */ |
| 309 | DSIM_PLLCTRL_REG, /* PLL control register */ |
| 310 | DSIM_PHYCTRL_REG, |
| 311 | DSIM_PHYTIMING_REG, |
| 312 | DSIM_PHYTIMING1_REG, |
| 313 | DSIM_PHYTIMING2_REG, |
| 314 | NUM_REGS |
| 315 | }; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 316 | |
| 317 | static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, |
| 318 | u32 val) |
| 319 | { |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 320 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 321 | writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); |
| 322 | } |
| 323 | |
| 324 | static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) |
| 325 | { |
| 326 | return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); |
| 327 | } |
| 328 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 329 | static const unsigned int exynos_reg_ofs[] = { |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 330 | [DSIM_STATUS_REG] = 0x00, |
| 331 | [DSIM_SWRST_REG] = 0x04, |
| 332 | [DSIM_CLKCTRL_REG] = 0x08, |
| 333 | [DSIM_TIMEOUT_REG] = 0x0c, |
| 334 | [DSIM_CONFIG_REG] = 0x10, |
| 335 | [DSIM_ESCMODE_REG] = 0x14, |
| 336 | [DSIM_MDRESOL_REG] = 0x18, |
| 337 | [DSIM_MVPORCH_REG] = 0x1c, |
| 338 | [DSIM_MHPORCH_REG] = 0x20, |
| 339 | [DSIM_MSYNC_REG] = 0x24, |
| 340 | [DSIM_INTSRC_REG] = 0x2c, |
| 341 | [DSIM_INTMSK_REG] = 0x30, |
| 342 | [DSIM_PKTHDR_REG] = 0x34, |
| 343 | [DSIM_PAYLOAD_REG] = 0x38, |
| 344 | [DSIM_RXFIFO_REG] = 0x3c, |
| 345 | [DSIM_FIFOCTRL_REG] = 0x44, |
| 346 | [DSIM_PLLCTRL_REG] = 0x4c, |
| 347 | [DSIM_PHYCTRL_REG] = 0x5c, |
| 348 | [DSIM_PHYTIMING_REG] = 0x64, |
| 349 | [DSIM_PHYTIMING1_REG] = 0x68, |
| 350 | [DSIM_PHYTIMING2_REG] = 0x6c, |
| 351 | }; |
| 352 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 353 | static const unsigned int exynos5433_reg_ofs[] = { |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 354 | [DSIM_STATUS_REG] = 0x04, |
| 355 | [DSIM_SWRST_REG] = 0x0C, |
| 356 | [DSIM_CLKCTRL_REG] = 0x10, |
| 357 | [DSIM_TIMEOUT_REG] = 0x14, |
| 358 | [DSIM_CONFIG_REG] = 0x18, |
| 359 | [DSIM_ESCMODE_REG] = 0x1C, |
| 360 | [DSIM_MDRESOL_REG] = 0x20, |
| 361 | [DSIM_MVPORCH_REG] = 0x24, |
| 362 | [DSIM_MHPORCH_REG] = 0x28, |
| 363 | [DSIM_MSYNC_REG] = 0x2C, |
| 364 | [DSIM_INTSRC_REG] = 0x34, |
| 365 | [DSIM_INTMSK_REG] = 0x38, |
| 366 | [DSIM_PKTHDR_REG] = 0x3C, |
| 367 | [DSIM_PAYLOAD_REG] = 0x40, |
| 368 | [DSIM_RXFIFO_REG] = 0x44, |
| 369 | [DSIM_FIFOCTRL_REG] = 0x4C, |
| 370 | [DSIM_PLLCTRL_REG] = 0x94, |
| 371 | [DSIM_PHYCTRL_REG] = 0xA4, |
| 372 | [DSIM_PHYTIMING_REG] = 0xB4, |
| 373 | [DSIM_PHYTIMING1_REG] = 0xB8, |
| 374 | [DSIM_PHYTIMING2_REG] = 0xBC, |
| 375 | }; |
| 376 | |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 377 | enum reg_value_idx { |
| 378 | RESET_TYPE, |
| 379 | PLL_TIMER, |
| 380 | STOP_STATE_CNT, |
| 381 | PHYCTRL_ULPS_EXIT, |
| 382 | PHYCTRL_VREG_LP, |
| 383 | PHYCTRL_SLEW_UP, |
| 384 | PHYTIMING_LPX, |
| 385 | PHYTIMING_HS_EXIT, |
| 386 | PHYTIMING_CLK_PREPARE, |
| 387 | PHYTIMING_CLK_ZERO, |
| 388 | PHYTIMING_CLK_POST, |
| 389 | PHYTIMING_CLK_TRAIL, |
| 390 | PHYTIMING_HS_PREPARE, |
| 391 | PHYTIMING_HS_ZERO, |
| 392 | PHYTIMING_HS_TRAIL |
| 393 | }; |
| 394 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 395 | static const unsigned int reg_values[] = { |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 396 | [RESET_TYPE] = DSIM_SWRST, |
| 397 | [PLL_TIMER] = 500, |
| 398 | [STOP_STATE_CNT] = 0xf, |
| 399 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), |
| 400 | [PHYCTRL_VREG_LP] = 0, |
| 401 | [PHYCTRL_SLEW_UP] = 0, |
| 402 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), |
| 403 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), |
| 404 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), |
| 405 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), |
| 406 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), |
| 407 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), |
| 408 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), |
| 409 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), |
| 410 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), |
| 411 | }; |
| 412 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 413 | static const unsigned int exynos5422_reg_values[] = { |
Chanho Park | fdc2e10 | 2016-01-30 23:11:50 +0900 | [diff] [blame] | 414 | [RESET_TYPE] = DSIM_SWRST, |
| 415 | [PLL_TIMER] = 500, |
| 416 | [STOP_STATE_CNT] = 0xf, |
| 417 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), |
| 418 | [PHYCTRL_VREG_LP] = 0, |
| 419 | [PHYCTRL_SLEW_UP] = 0, |
| 420 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), |
| 421 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), |
| 422 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), |
| 423 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), |
| 424 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), |
| 425 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), |
| 426 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), |
| 427 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), |
| 428 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), |
| 429 | }; |
| 430 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 431 | static const unsigned int exynos5433_reg_values[] = { |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 432 | [RESET_TYPE] = DSIM_FUNCRST, |
| 433 | [PLL_TIMER] = 22200, |
| 434 | [STOP_STATE_CNT] = 0xa, |
| 435 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), |
| 436 | [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, |
| 437 | [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, |
| 438 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), |
| 439 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), |
| 440 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), |
| 441 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), |
| 442 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), |
| 443 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), |
| 444 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), |
| 445 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), |
| 446 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), |
| 447 | }; |
| 448 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 449 | static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 450 | .reg_ofs = exynos_reg_ofs, |
Inki Dae | 473462a | 2014-08-13 17:09:12 +0900 | [diff] [blame] | 451 | .plltmr_reg = 0x50, |
| 452 | .has_freqband = 1, |
| 453 | .has_clklane_stop = 1, |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 454 | .num_clks = 2, |
| 455 | .max_freq = 1000, |
| 456 | .wait_for_reset = 1, |
| 457 | .num_bits_resol = 11, |
| 458 | .reg_values = reg_values, |
Inki Dae | 473462a | 2014-08-13 17:09:12 +0900 | [diff] [blame] | 459 | }; |
| 460 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 461 | static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 462 | .reg_ofs = exynos_reg_ofs, |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 463 | .plltmr_reg = 0x50, |
| 464 | .has_freqband = 1, |
Inki Dae | 78d3a8c | 2014-08-13 17:03:12 +0900 | [diff] [blame] | 465 | .has_clklane_stop = 1, |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 466 | .num_clks = 2, |
| 467 | .max_freq = 1000, |
| 468 | .wait_for_reset = 1, |
| 469 | .num_bits_resol = 11, |
| 470 | .reg_values = reg_values, |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 471 | }; |
| 472 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 473 | static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 474 | .reg_ofs = exynos_reg_ofs, |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 475 | .plltmr_reg = 0x58, |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 476 | .num_clks = 2, |
| 477 | .max_freq = 1000, |
| 478 | .wait_for_reset = 1, |
| 479 | .num_bits_resol = 11, |
| 480 | .reg_values = reg_values, |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 481 | }; |
| 482 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 483 | static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 484 | .reg_ofs = exynos5433_reg_ofs, |
| 485 | .plltmr_reg = 0xa0, |
| 486 | .has_clklane_stop = 1, |
| 487 | .num_clks = 5, |
| 488 | .max_freq = 1500, |
| 489 | .wait_for_reset = 0, |
| 490 | .num_bits_resol = 12, |
| 491 | .reg_values = exynos5433_reg_values, |
| 492 | }; |
| 493 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 494 | static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { |
Chanho Park | fdc2e10 | 2016-01-30 23:11:50 +0900 | [diff] [blame] | 495 | .reg_ofs = exynos5433_reg_ofs, |
| 496 | .plltmr_reg = 0xa0, |
| 497 | .has_clklane_stop = 1, |
| 498 | .num_clks = 2, |
| 499 | .max_freq = 1500, |
| 500 | .wait_for_reset = 1, |
| 501 | .num_bits_resol = 12, |
| 502 | .reg_values = exynos5422_reg_values, |
| 503 | }; |
| 504 | |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 505 | static const struct of_device_id exynos_dsi_of_match[] = { |
Inki Dae | 473462a | 2014-08-13 17:09:12 +0900 | [diff] [blame] | 506 | { .compatible = "samsung,exynos3250-mipi-dsi", |
| 507 | .data = &exynos3_dsi_driver_data }, |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 508 | { .compatible = "samsung,exynos4210-mipi-dsi", |
| 509 | .data = &exynos4_dsi_driver_data }, |
| 510 | { .compatible = "samsung,exynos5410-mipi-dsi", |
| 511 | .data = &exynos5_dsi_driver_data }, |
Chanho Park | fdc2e10 | 2016-01-30 23:11:50 +0900 | [diff] [blame] | 512 | { .compatible = "samsung,exynos5422-mipi-dsi", |
| 513 | .data = &exynos5422_dsi_driver_data }, |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 514 | { .compatible = "samsung,exynos5433-mipi-dsi", |
| 515 | .data = &exynos5433_dsi_driver_data }, |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 516 | { } |
| 517 | }; |
| 518 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 519 | static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) |
| 520 | { |
| 521 | if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) |
| 522 | return; |
| 523 | |
| 524 | dev_err(dsi->dev, "timeout waiting for reset\n"); |
| 525 | } |
| 526 | |
| 527 | static void exynos_dsi_reset(struct exynos_dsi *dsi) |
| 528 | { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 529 | u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; |
Hyungwon Hwang | ba12ac2 | 2015-06-12 21:59:04 +0900 | [diff] [blame] | 530 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 531 | reinit_completion(&dsi->completed); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 532 | exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | #ifndef MHZ |
| 536 | #define MHZ (1000*1000) |
| 537 | #endif |
| 538 | |
| 539 | static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, |
| 540 | unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) |
| 541 | { |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 542 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 543 | unsigned long best_freq = 0; |
| 544 | u32 min_delta = 0xffffffff; |
| 545 | u8 p_min, p_max; |
| 546 | u8 _p, uninitialized_var(best_p); |
| 547 | u16 _m, uninitialized_var(best_m); |
| 548 | u8 _s, uninitialized_var(best_s); |
| 549 | |
| 550 | p_min = DIV_ROUND_UP(fin, (12 * MHZ)); |
| 551 | p_max = fin / (6 * MHZ); |
| 552 | |
| 553 | for (_p = p_min; _p <= p_max; ++_p) { |
| 554 | for (_s = 0; _s <= 5; ++_s) { |
| 555 | u64 tmp; |
| 556 | u32 delta; |
| 557 | |
| 558 | tmp = (u64)fout * (_p << _s); |
| 559 | do_div(tmp, fin); |
| 560 | _m = tmp; |
| 561 | if (_m < 41 || _m > 125) |
| 562 | continue; |
| 563 | |
| 564 | tmp = (u64)_m * fin; |
| 565 | do_div(tmp, _p); |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 566 | if (tmp < 500 * MHZ || |
| 567 | tmp > driver_data->max_freq * MHZ) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 568 | continue; |
| 569 | |
| 570 | tmp = (u64)_m * fin; |
| 571 | do_div(tmp, _p << _s); |
| 572 | |
| 573 | delta = abs(fout - tmp); |
| 574 | if (delta < min_delta) { |
| 575 | best_p = _p; |
| 576 | best_m = _m; |
| 577 | best_s = _s; |
| 578 | min_delta = delta; |
| 579 | best_freq = tmp; |
| 580 | } |
| 581 | } |
| 582 | } |
| 583 | |
| 584 | if (best_freq) { |
| 585 | *p = best_p; |
| 586 | *m = best_m; |
| 587 | *s = best_s; |
| 588 | } |
| 589 | |
| 590 | return best_freq; |
| 591 | } |
| 592 | |
| 593 | static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, |
| 594 | unsigned long freq) |
| 595 | { |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 596 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 597 | unsigned long fin, fout; |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 598 | int timeout; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 599 | u8 p, s; |
| 600 | u16 m; |
| 601 | u32 reg; |
| 602 | |
Hyungwon Hwang | 26269af | 2015-06-12 21:59:03 +0900 | [diff] [blame] | 603 | fin = dsi->pll_clk_rate; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 604 | fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); |
| 605 | if (!fout) { |
| 606 | dev_err(dsi->dev, |
| 607 | "failed to find PLL PMS for requested frequency\n"); |
YoungJun Cho | 8525b5e | 2014-08-14 11:22:36 +0900 | [diff] [blame] | 608 | return 0; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 609 | } |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 610 | dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 611 | |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 612 | writel(driver_data->reg_values[PLL_TIMER], |
| 613 | dsi->reg_base + driver_data->plltmr_reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 614 | |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 615 | reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 616 | |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 617 | if (driver_data->has_freqband) { |
| 618 | static const unsigned long freq_bands[] = { |
| 619 | 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, |
| 620 | 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, |
| 621 | 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, |
| 622 | 770 * MHZ, 870 * MHZ, 950 * MHZ, |
| 623 | }; |
| 624 | int band; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 625 | |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 626 | for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) |
| 627 | if (fout < freq_bands[band]) |
| 628 | break; |
| 629 | |
| 630 | dev_dbg(dsi->dev, "band %d\n", band); |
| 631 | |
| 632 | reg |= DSIM_FREQ_BAND(band); |
| 633 | } |
| 634 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 635 | exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 636 | |
| 637 | timeout = 1000; |
| 638 | do { |
| 639 | if (timeout-- == 0) { |
| 640 | dev_err(dsi->dev, "PLL failed to stabilize\n"); |
YoungJun Cho | 8525b5e | 2014-08-14 11:22:36 +0900 | [diff] [blame] | 641 | return 0; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 642 | } |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 643 | reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 644 | } while ((reg & DSIM_PLL_STABLE) == 0); |
| 645 | |
| 646 | return fout; |
| 647 | } |
| 648 | |
| 649 | static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) |
| 650 | { |
| 651 | unsigned long hs_clk, byte_clk, esc_clk; |
| 652 | unsigned long esc_div; |
| 653 | u32 reg; |
| 654 | |
| 655 | hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); |
| 656 | if (!hs_clk) { |
| 657 | dev_err(dsi->dev, "failed to configure DSI PLL\n"); |
| 658 | return -EFAULT; |
| 659 | } |
| 660 | |
| 661 | byte_clk = hs_clk / 8; |
| 662 | esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); |
| 663 | esc_clk = byte_clk / esc_div; |
| 664 | |
| 665 | if (esc_clk > 20 * MHZ) { |
| 666 | ++esc_div; |
| 667 | esc_clk = byte_clk / esc_div; |
| 668 | } |
| 669 | |
| 670 | dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", |
| 671 | hs_clk, byte_clk, esc_clk); |
| 672 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 673 | reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 674 | reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK |
| 675 | | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS |
| 676 | | DSIM_BYTE_CLK_SRC_MASK); |
| 677 | reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN |
| 678 | | DSIM_ESC_PRESCALER(esc_div) |
| 679 | | DSIM_LANE_ESC_CLK_EN_CLK |
| 680 | | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) |
| 681 | | DSIM_BYTE_CLK_SRC(0) |
| 682 | | DSIM_TX_REQUEST_HSCLK; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 683 | exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 684 | |
| 685 | return 0; |
| 686 | } |
| 687 | |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 688 | static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) |
| 689 | { |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 690 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
Andrzej Hajda | b115361 | 2016-02-11 12:55:44 +0100 | [diff] [blame] | 691 | const unsigned int *reg_values = driver_data->reg_values; |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 692 | u32 reg; |
| 693 | |
| 694 | if (driver_data->has_freqband) |
| 695 | return; |
| 696 | |
| 697 | /* B D-PHY: D-PHY Master & Slave Analog Block control */ |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 698 | reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | |
| 699 | reg_values[PHYCTRL_SLEW_UP]; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 700 | exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 701 | |
| 702 | /* |
| 703 | * T LPX: Transmitted length of any Low-Power state period |
| 704 | * T HS-EXIT: Time that the transmitter drives LP-11 following a HS |
| 705 | * burst |
| 706 | */ |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 707 | reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 708 | exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 709 | |
| 710 | /* |
| 711 | * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 |
| 712 | * Line state immediately before the HS-0 Line state starting the |
| 713 | * HS transmission |
| 714 | * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to |
| 715 | * transmitting the Clock. |
| 716 | * T CLK_POST: Time that the transmitter continues to send HS clock |
| 717 | * after the last associated Data Lane has transitioned to LP Mode |
| 718 | * Interval is defined as the period from the end of T HS-TRAIL to |
| 719 | * the beginning of T CLK-TRAIL |
| 720 | * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after |
| 721 | * the last payload clock bit of a HS transmission burst |
| 722 | */ |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 723 | reg = reg_values[PHYTIMING_CLK_PREPARE] | |
| 724 | reg_values[PHYTIMING_CLK_ZERO] | |
| 725 | reg_values[PHYTIMING_CLK_POST] | |
| 726 | reg_values[PHYTIMING_CLK_TRAIL]; |
| 727 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 728 | exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 729 | |
| 730 | /* |
| 731 | * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 |
| 732 | * Line state immediately before the HS-0 Line state starting the |
| 733 | * HS transmission |
| 734 | * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to |
| 735 | * transmitting the Sync sequence. |
| 736 | * T HS-TRAIL: Time that the transmitter drives the flipped differential |
| 737 | * state after last payload data bit of a HS transmission burst |
| 738 | */ |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 739 | reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | |
| 740 | reg_values[PHYTIMING_HS_TRAIL]; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 741 | exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 742 | } |
| 743 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 744 | static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) |
| 745 | { |
| 746 | u32 reg; |
| 747 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 748 | reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 749 | reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK |
| 750 | | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 751 | exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 752 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 753 | reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 754 | reg &= ~DSIM_PLL_EN; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 755 | exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 756 | } |
| 757 | |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 758 | static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) |
| 759 | { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 760 | u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 761 | reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | |
| 762 | DSIM_LANE_EN(lane)); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 763 | exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 764 | } |
| 765 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 766 | static int exynos_dsi_init_link(struct exynos_dsi *dsi) |
| 767 | { |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 768 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 769 | int timeout; |
| 770 | u32 reg; |
| 771 | u32 lanes_mask; |
| 772 | |
| 773 | /* Initialize FIFO pointers */ |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 774 | reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 775 | reg &= ~0x1f; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 776 | exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 777 | |
| 778 | usleep_range(9000, 11000); |
| 779 | |
| 780 | reg |= 0x1f; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 781 | exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 782 | usleep_range(9000, 11000); |
| 783 | |
| 784 | /* DSI configuration */ |
| 785 | reg = 0; |
| 786 | |
YoungJun Cho | 2f36e33 | 2014-07-17 18:01:16 +0900 | [diff] [blame] | 787 | /* |
| 788 | * The first bit of mode_flags specifies display configuration. |
| 789 | * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video |
| 790 | * mode, otherwise it will support command mode. |
| 791 | */ |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 792 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
| 793 | reg |= DSIM_VIDEO_MODE; |
| 794 | |
YoungJun Cho | 2f36e33 | 2014-07-17 18:01:16 +0900 | [diff] [blame] | 795 | /* |
| 796 | * The user manual describes that following bits are ignored in |
| 797 | * command mode. |
| 798 | */ |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 799 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) |
| 800 | reg |= DSIM_MFLUSH_VS; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 801 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
| 802 | reg |= DSIM_SYNC_INFORM; |
| 803 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) |
| 804 | reg |= DSIM_BURST_MODE; |
| 805 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) |
| 806 | reg |= DSIM_AUTO_MODE; |
| 807 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) |
| 808 | reg |= DSIM_HSE_MODE; |
| 809 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) |
| 810 | reg |= DSIM_HFP_MODE; |
| 811 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) |
| 812 | reg |= DSIM_HBP_MODE; |
| 813 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) |
| 814 | reg |= DSIM_HSA_MODE; |
| 815 | } |
| 816 | |
YoungJun Cho | 2f36e33 | 2014-07-17 18:01:16 +0900 | [diff] [blame] | 817 | if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) |
| 818 | reg |= DSIM_EOT_DISABLE; |
| 819 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 820 | switch (dsi->format) { |
| 821 | case MIPI_DSI_FMT_RGB888: |
| 822 | reg |= DSIM_MAIN_PIX_FORMAT_RGB888; |
| 823 | break; |
| 824 | case MIPI_DSI_FMT_RGB666: |
| 825 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666; |
| 826 | break; |
| 827 | case MIPI_DSI_FMT_RGB666_PACKED: |
| 828 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; |
| 829 | break; |
| 830 | case MIPI_DSI_FMT_RGB565: |
| 831 | reg |= DSIM_MAIN_PIX_FORMAT_RGB565; |
| 832 | break; |
| 833 | default: |
| 834 | dev_err(dsi->dev, "invalid pixel format\n"); |
| 835 | return -EINVAL; |
| 836 | } |
| 837 | |
Inki Dae | 78d3a8c | 2014-08-13 17:03:12 +0900 | [diff] [blame] | 838 | /* |
| 839 | * Use non-continuous clock mode if the periparal wants and |
| 840 | * host controller supports |
| 841 | * |
| 842 | * In non-continous clock mode, host controller will turn off |
| 843 | * the HS clock between high-speed transmissions to reduce |
| 844 | * power consumption. |
| 845 | */ |
| 846 | if (driver_data->has_clklane_stop && |
| 847 | dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { |
| 848 | reg |= DSIM_CLKLANE_STOP; |
Inki Dae | 78d3a8c | 2014-08-13 17:03:12 +0900 | [diff] [blame] | 849 | } |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 850 | exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 851 | |
| 852 | lanes_mask = BIT(dsi->lanes) - 1; |
| 853 | exynos_dsi_enable_lane(dsi, lanes_mask); |
Inki Dae | 78d3a8c | 2014-08-13 17:03:12 +0900 | [diff] [blame] | 854 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 855 | /* Check clock and data lane state are stop state */ |
| 856 | timeout = 100; |
| 857 | do { |
| 858 | if (timeout-- == 0) { |
| 859 | dev_err(dsi->dev, "waiting for bus lanes timed out\n"); |
| 860 | return -EFAULT; |
| 861 | } |
| 862 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 863 | reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 864 | if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) |
| 865 | != DSIM_STOP_STATE_DAT(lanes_mask)) |
| 866 | continue; |
| 867 | } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); |
| 868 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 869 | reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 870 | reg &= ~DSIM_STOP_STATE_CNT_MASK; |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 871 | reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 872 | exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 873 | |
| 874 | reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 875 | exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 876 | |
| 877 | return 0; |
| 878 | } |
| 879 | |
| 880 | static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) |
| 881 | { |
Andrzej Hajda | e892999 | 2018-05-07 11:29:28 +0200 | [diff] [blame] | 882 | struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode; |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 883 | unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 884 | u32 reg; |
| 885 | |
| 886 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
| 887 | reg = DSIM_CMD_ALLOW(0xf) |
Andrzej Hajda | e892999 | 2018-05-07 11:29:28 +0200 | [diff] [blame] | 888 | | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) |
| 889 | | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 890 | exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 891 | |
Andrzej Hajda | e892999 | 2018-05-07 11:29:28 +0200 | [diff] [blame] | 892 | reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) |
| 893 | | DSIM_MAIN_HBP(m->htotal - m->hsync_end); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 894 | exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 895 | |
Andrzej Hajda | e892999 | 2018-05-07 11:29:28 +0200 | [diff] [blame] | 896 | reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) |
| 897 | | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 898 | exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 899 | } |
Andrzej Hajda | e892999 | 2018-05-07 11:29:28 +0200 | [diff] [blame] | 900 | reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | |
| 901 | DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 902 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 903 | exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 904 | |
Andrzej Hajda | e892999 | 2018-05-07 11:29:28 +0200 | [diff] [blame] | 905 | dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 906 | } |
| 907 | |
| 908 | static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) |
| 909 | { |
| 910 | u32 reg; |
| 911 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 912 | reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 913 | if (enable) |
| 914 | reg |= DSIM_MAIN_STAND_BY; |
| 915 | else |
| 916 | reg &= ~DSIM_MAIN_STAND_BY; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 917 | exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 918 | } |
| 919 | |
| 920 | static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) |
| 921 | { |
| 922 | int timeout = 2000; |
| 923 | |
| 924 | do { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 925 | u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 926 | |
| 927 | if (!(reg & DSIM_SFR_HEADER_FULL)) |
| 928 | return 0; |
| 929 | |
| 930 | if (!cond_resched()) |
| 931 | usleep_range(950, 1050); |
| 932 | } while (--timeout); |
| 933 | |
| 934 | return -ETIMEDOUT; |
| 935 | } |
| 936 | |
| 937 | static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) |
| 938 | { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 939 | u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 940 | |
| 941 | if (lpm) |
| 942 | v |= DSIM_CMD_LPDT_LP; |
| 943 | else |
| 944 | v &= ~DSIM_CMD_LPDT_LP; |
| 945 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 946 | exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 947 | } |
| 948 | |
| 949 | static void exynos_dsi_force_bta(struct exynos_dsi *dsi) |
| 950 | { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 951 | u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 952 | v |= DSIM_FORCE_BTA; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 953 | exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 954 | } |
| 955 | |
| 956 | static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, |
| 957 | struct exynos_dsi_transfer *xfer) |
| 958 | { |
| 959 | struct device *dev = dsi->dev; |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 960 | struct mipi_dsi_packet *pkt = &xfer->packet; |
| 961 | const u8 *payload = pkt->payload + xfer->tx_done; |
| 962 | u16 length = pkt->payload_length - xfer->tx_done; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 963 | bool first = !xfer->tx_done; |
| 964 | u32 reg; |
| 965 | |
Krzysztof Kozlowski | 9cdf0ed | 2017-03-14 20:38:04 +0200 | [diff] [blame] | 966 | dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 967 | xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 968 | |
| 969 | if (length > DSI_TX_FIFO_SIZE) |
| 970 | length = DSI_TX_FIFO_SIZE; |
| 971 | |
| 972 | xfer->tx_done += length; |
| 973 | |
| 974 | /* Send payload */ |
| 975 | while (length >= 4) { |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 976 | reg = get_unaligned_le32(payload); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 977 | exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 978 | payload += 4; |
| 979 | length -= 4; |
| 980 | } |
| 981 | |
| 982 | reg = 0; |
| 983 | switch (length) { |
| 984 | case 3: |
| 985 | reg |= payload[2] << 16; |
| 986 | /* Fall through */ |
| 987 | case 2: |
| 988 | reg |= payload[1] << 8; |
| 989 | /* Fall through */ |
| 990 | case 1: |
| 991 | reg |= payload[0]; |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 992 | exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 993 | break; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 994 | } |
| 995 | |
| 996 | /* Send packet header */ |
| 997 | if (!first) |
| 998 | return; |
| 999 | |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 1000 | reg = get_unaligned_le32(pkt->header); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1001 | if (exynos_dsi_wait_for_hdr_fifo(dsi)) { |
| 1002 | dev_err(dev, "waiting for header FIFO timed out\n"); |
| 1003 | return; |
| 1004 | } |
| 1005 | |
| 1006 | if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, |
| 1007 | dsi->state & DSIM_STATE_CMD_LPM)) { |
| 1008 | exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); |
| 1009 | dsi->state ^= DSIM_STATE_CMD_LPM; |
| 1010 | } |
| 1011 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 1012 | exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1013 | |
| 1014 | if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) |
| 1015 | exynos_dsi_force_bta(dsi); |
| 1016 | } |
| 1017 | |
| 1018 | static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, |
| 1019 | struct exynos_dsi_transfer *xfer) |
| 1020 | { |
| 1021 | u8 *payload = xfer->rx_payload + xfer->rx_done; |
| 1022 | bool first = !xfer->rx_done; |
| 1023 | struct device *dev = dsi->dev; |
| 1024 | u16 length; |
| 1025 | u32 reg; |
| 1026 | |
| 1027 | if (first) { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 1028 | reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1029 | |
| 1030 | switch (reg & 0x3f) { |
| 1031 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: |
| 1032 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: |
| 1033 | if (xfer->rx_len >= 2) { |
| 1034 | payload[1] = reg >> 16; |
| 1035 | ++xfer->rx_done; |
| 1036 | } |
| 1037 | /* Fall through */ |
| 1038 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: |
| 1039 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: |
| 1040 | payload[0] = reg >> 8; |
| 1041 | ++xfer->rx_done; |
| 1042 | xfer->rx_len = xfer->rx_done; |
| 1043 | xfer->result = 0; |
| 1044 | goto clear_fifo; |
| 1045 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: |
| 1046 | dev_err(dev, "DSI Error Report: 0x%04x\n", |
| 1047 | (reg >> 8) & 0xffff); |
| 1048 | xfer->result = 0; |
| 1049 | goto clear_fifo; |
| 1050 | } |
| 1051 | |
| 1052 | length = (reg >> 8) & 0xffff; |
| 1053 | if (length > xfer->rx_len) { |
| 1054 | dev_err(dev, |
| 1055 | "response too long (%u > %u bytes), stripping\n", |
| 1056 | xfer->rx_len, length); |
| 1057 | length = xfer->rx_len; |
| 1058 | } else if (length < xfer->rx_len) |
| 1059 | xfer->rx_len = length; |
| 1060 | } |
| 1061 | |
| 1062 | length = xfer->rx_len - xfer->rx_done; |
| 1063 | xfer->rx_done += length; |
| 1064 | |
| 1065 | /* Receive payload */ |
| 1066 | while (length >= 4) { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 1067 | reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1068 | payload[0] = (reg >> 0) & 0xff; |
| 1069 | payload[1] = (reg >> 8) & 0xff; |
| 1070 | payload[2] = (reg >> 16) & 0xff; |
| 1071 | payload[3] = (reg >> 24) & 0xff; |
| 1072 | payload += 4; |
| 1073 | length -= 4; |
| 1074 | } |
| 1075 | |
| 1076 | if (length) { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 1077 | reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1078 | switch (length) { |
| 1079 | case 3: |
| 1080 | payload[2] = (reg >> 16) & 0xff; |
| 1081 | /* Fall through */ |
| 1082 | case 2: |
| 1083 | payload[1] = (reg >> 8) & 0xff; |
| 1084 | /* Fall through */ |
| 1085 | case 1: |
| 1086 | payload[0] = reg & 0xff; |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | if (xfer->rx_done == xfer->rx_len) |
| 1091 | xfer->result = 0; |
| 1092 | |
| 1093 | clear_fifo: |
| 1094 | length = DSI_RX_FIFO_SIZE / 4; |
| 1095 | do { |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 1096 | reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1097 | if (reg == DSI_RX_FIFO_EMPTY) |
| 1098 | break; |
| 1099 | } while (--length); |
| 1100 | } |
| 1101 | |
| 1102 | static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) |
| 1103 | { |
| 1104 | unsigned long flags; |
| 1105 | struct exynos_dsi_transfer *xfer; |
| 1106 | bool start = false; |
| 1107 | |
| 1108 | again: |
| 1109 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
| 1110 | |
| 1111 | if (list_empty(&dsi->transfer_list)) { |
| 1112 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1113 | return; |
| 1114 | } |
| 1115 | |
| 1116 | xfer = list_first_entry(&dsi->transfer_list, |
| 1117 | struct exynos_dsi_transfer, list); |
| 1118 | |
| 1119 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1120 | |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 1121 | if (xfer->packet.payload_length && |
| 1122 | xfer->tx_done == xfer->packet.payload_length) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1123 | /* waiting for RX */ |
| 1124 | return; |
| 1125 | |
| 1126 | exynos_dsi_send_to_fifo(dsi, xfer); |
| 1127 | |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 1128 | if (xfer->packet.payload_length || xfer->rx_len) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1129 | return; |
| 1130 | |
| 1131 | xfer->result = 0; |
| 1132 | complete(&xfer->completed); |
| 1133 | |
| 1134 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
| 1135 | |
| 1136 | list_del_init(&xfer->list); |
| 1137 | start = !list_empty(&dsi->transfer_list); |
| 1138 | |
| 1139 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1140 | |
| 1141 | if (start) |
| 1142 | goto again; |
| 1143 | } |
| 1144 | |
| 1145 | static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) |
| 1146 | { |
| 1147 | struct exynos_dsi_transfer *xfer; |
| 1148 | unsigned long flags; |
| 1149 | bool start = true; |
| 1150 | |
| 1151 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
| 1152 | |
| 1153 | if (list_empty(&dsi->transfer_list)) { |
| 1154 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1155 | return false; |
| 1156 | } |
| 1157 | |
| 1158 | xfer = list_first_entry(&dsi->transfer_list, |
| 1159 | struct exynos_dsi_transfer, list); |
| 1160 | |
| 1161 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1162 | |
| 1163 | dev_dbg(dsi->dev, |
Krzysztof Kozlowski | 9cdf0ed | 2017-03-14 20:38:04 +0200 | [diff] [blame] | 1164 | "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 1165 | xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, |
| 1166 | xfer->rx_done); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1167 | |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 1168 | if (xfer->tx_done != xfer->packet.payload_length) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1169 | return true; |
| 1170 | |
| 1171 | if (xfer->rx_done != xfer->rx_len) |
| 1172 | exynos_dsi_read_from_fifo(dsi, xfer); |
| 1173 | |
| 1174 | if (xfer->rx_done != xfer->rx_len) |
| 1175 | return true; |
| 1176 | |
| 1177 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
| 1178 | |
| 1179 | list_del_init(&xfer->list); |
| 1180 | start = !list_empty(&dsi->transfer_list); |
| 1181 | |
| 1182 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1183 | |
| 1184 | if (!xfer->rx_len) |
| 1185 | xfer->result = 0; |
| 1186 | complete(&xfer->completed); |
| 1187 | |
| 1188 | return start; |
| 1189 | } |
| 1190 | |
| 1191 | static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, |
| 1192 | struct exynos_dsi_transfer *xfer) |
| 1193 | { |
| 1194 | unsigned long flags; |
| 1195 | bool start; |
| 1196 | |
| 1197 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
| 1198 | |
| 1199 | if (!list_empty(&dsi->transfer_list) && |
| 1200 | xfer == list_first_entry(&dsi->transfer_list, |
| 1201 | struct exynos_dsi_transfer, list)) { |
| 1202 | list_del_init(&xfer->list); |
| 1203 | start = !list_empty(&dsi->transfer_list); |
| 1204 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1205 | if (start) |
| 1206 | exynos_dsi_transfer_start(dsi); |
| 1207 | return; |
| 1208 | } |
| 1209 | |
| 1210 | list_del_init(&xfer->list); |
| 1211 | |
| 1212 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1213 | } |
| 1214 | |
| 1215 | static int exynos_dsi_transfer(struct exynos_dsi *dsi, |
| 1216 | struct exynos_dsi_transfer *xfer) |
| 1217 | { |
| 1218 | unsigned long flags; |
| 1219 | bool stopped; |
| 1220 | |
| 1221 | xfer->tx_done = 0; |
| 1222 | xfer->rx_done = 0; |
| 1223 | xfer->result = -ETIMEDOUT; |
| 1224 | init_completion(&xfer->completed); |
| 1225 | |
| 1226 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
| 1227 | |
| 1228 | stopped = list_empty(&dsi->transfer_list); |
| 1229 | list_add_tail(&xfer->list, &dsi->transfer_list); |
| 1230 | |
| 1231 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); |
| 1232 | |
| 1233 | if (stopped) |
| 1234 | exynos_dsi_transfer_start(dsi); |
| 1235 | |
| 1236 | wait_for_completion_timeout(&xfer->completed, |
| 1237 | msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); |
| 1238 | if (xfer->result == -ETIMEDOUT) { |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 1239 | struct mipi_dsi_packet *pkt = &xfer->packet; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1240 | exynos_dsi_remove_transfer(dsi, xfer); |
Andrzej Hajda | 6c81e96 | 2016-02-17 14:33:08 +0100 | [diff] [blame] | 1241 | dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, |
| 1242 | (int)pkt->payload_length, pkt->payload); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1243 | return -ETIMEDOUT; |
| 1244 | } |
| 1245 | |
| 1246 | /* Also covers hardware timeout condition */ |
| 1247 | return xfer->result; |
| 1248 | } |
| 1249 | |
| 1250 | static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) |
| 1251 | { |
| 1252 | struct exynos_dsi *dsi = dev_id; |
| 1253 | u32 status; |
| 1254 | |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 1255 | status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1256 | if (!status) { |
| 1257 | static unsigned long int j; |
| 1258 | if (printk_timed_ratelimit(&j, 500)) |
| 1259 | dev_warn(dsi->dev, "spurious interrupt\n"); |
| 1260 | return IRQ_HANDLED; |
| 1261 | } |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 1262 | exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1263 | |
| 1264 | if (status & DSIM_INT_SW_RST_RELEASE) { |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 1265 | u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
Andrzej Hajda | ecf81ed | 2018-05-08 11:36:58 +0200 | [diff] [blame] | 1266 | DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR | |
| 1267 | DSIM_INT_SW_RST_RELEASE); |
Andrzej Hajda | bb32e40 | 2016-02-11 12:55:43 +0100 | [diff] [blame] | 1268 | exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1269 | complete(&dsi->completed); |
| 1270 | return IRQ_HANDLED; |
| 1271 | } |
| 1272 | |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 1273 | if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
Andrzej Hajda | ecf81ed | 2018-05-08 11:36:58 +0200 | [diff] [blame] | 1274 | DSIM_INT_PLL_STABLE))) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1275 | return IRQ_HANDLED; |
| 1276 | |
| 1277 | if (exynos_dsi_transfer_finish(dsi)) |
| 1278 | exynos_dsi_transfer_start(dsi); |
| 1279 | |
| 1280 | return IRQ_HANDLED; |
| 1281 | } |
| 1282 | |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1283 | static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) |
| 1284 | { |
| 1285 | struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1286 | struct drm_encoder *encoder = &dsi->encoder; |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1287 | |
Hyungwon Hwang | 0e480f6 | 2015-06-11 23:40:30 +0900 | [diff] [blame] | 1288 | if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1289 | exynos_drm_crtc_te_handler(encoder->crtc); |
| 1290 | |
| 1291 | return IRQ_HANDLED; |
| 1292 | } |
| 1293 | |
| 1294 | static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) |
| 1295 | { |
| 1296 | enable_irq(dsi->irq); |
| 1297 | |
| 1298 | if (gpio_is_valid(dsi->te_gpio)) |
| 1299 | enable_irq(gpio_to_irq(dsi->te_gpio)); |
| 1300 | } |
| 1301 | |
| 1302 | static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) |
| 1303 | { |
| 1304 | if (gpio_is_valid(dsi->te_gpio)) |
| 1305 | disable_irq(gpio_to_irq(dsi->te_gpio)); |
| 1306 | |
| 1307 | disable_irq(dsi->irq); |
| 1308 | } |
| 1309 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1310 | static int exynos_dsi_init(struct exynos_dsi *dsi) |
| 1311 | { |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 1312 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 1313 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1314 | exynos_dsi_reset(dsi); |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1315 | exynos_dsi_enable_irq(dsi); |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 1316 | |
| 1317 | if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) |
| 1318 | exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); |
| 1319 | |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 1320 | exynos_dsi_enable_clock(dsi); |
Hyungwon Hwang | d668e8b | 2015-06-12 21:59:05 +0900 | [diff] [blame] | 1321 | if (driver_data->wait_for_reset) |
| 1322 | exynos_dsi_wait_for_reset(dsi); |
YoungJun Cho | 9a32041 | 2014-07-17 18:01:23 +0900 | [diff] [blame] | 1323 | exynos_dsi_set_phy_ctrl(dsi); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1324 | exynos_dsi_init_link(dsi); |
| 1325 | |
| 1326 | return 0; |
| 1327 | } |
| 1328 | |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1329 | static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, |
| 1330 | struct device *panel) |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1331 | { |
| 1332 | int ret; |
YoungJun Cho | 0cef83a5 | 2014-11-17 22:00:16 +0900 | [diff] [blame] | 1333 | int te_gpio_irq; |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1334 | |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1335 | dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0); |
Andrzej Hajda | 22e098d | 2017-03-15 12:20:42 +0100 | [diff] [blame] | 1336 | if (dsi->te_gpio == -ENOENT) |
| 1337 | return 0; |
| 1338 | |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1339 | if (!gpio_is_valid(dsi->te_gpio)) { |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1340 | ret = dsi->te_gpio; |
Andrzej Hajda | 22e098d | 2017-03-15 12:20:42 +0100 | [diff] [blame] | 1341 | dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret); |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1342 | goto out; |
| 1343 | } |
| 1344 | |
Hyungwon Hwang | 51d1dec | 2015-06-12 21:59:09 +0900 | [diff] [blame] | 1345 | ret = gpio_request(dsi->te_gpio, "te_gpio"); |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1346 | if (ret) { |
| 1347 | dev_err(dsi->dev, "gpio request failed with %d\n", ret); |
| 1348 | goto out; |
| 1349 | } |
| 1350 | |
YoungJun Cho | 0cef83a5 | 2014-11-17 22:00:16 +0900 | [diff] [blame] | 1351 | te_gpio_irq = gpio_to_irq(dsi->te_gpio); |
YoungJun Cho | 0cef83a5 | 2014-11-17 22:00:16 +0900 | [diff] [blame] | 1352 | irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); |
Hyungwon Hwang | 51d1dec | 2015-06-12 21:59:09 +0900 | [diff] [blame] | 1353 | |
YoungJun Cho | 0cef83a5 | 2014-11-17 22:00:16 +0900 | [diff] [blame] | 1354 | ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1355 | IRQF_TRIGGER_RISING, "TE", dsi); |
| 1356 | if (ret) { |
| 1357 | dev_err(dsi->dev, "request interrupt failed with %d\n", ret); |
| 1358 | gpio_free(dsi->te_gpio); |
| 1359 | goto out; |
| 1360 | } |
| 1361 | |
| 1362 | out: |
| 1363 | return ret; |
| 1364 | } |
| 1365 | |
| 1366 | static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) |
| 1367 | { |
| 1368 | if (gpio_is_valid(dsi->te_gpio)) { |
| 1369 | free_irq(gpio_to_irq(dsi->te_gpio), dsi); |
| 1370 | gpio_free(dsi->te_gpio); |
| 1371 | dsi->te_gpio = -ENOENT; |
| 1372 | } |
| 1373 | } |
| 1374 | |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1375 | static void exynos_dsi_enable(struct drm_encoder *encoder) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1376 | { |
Gustavo Padovan | cf67cc9 | 2015-08-11 17:38:06 +0900 | [diff] [blame] | 1377 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1378 | int ret; |
| 1379 | |
| 1380 | if (dsi->state & DSIM_STATE_ENABLED) |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1381 | return; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1382 | |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1383 | pm_runtime_get_sync(dsi->dev); |
Hyungwon Hwang | 0e480f6 | 2015-06-11 23:40:30 +0900 | [diff] [blame] | 1384 | dsi->state |= DSIM_STATE_ENABLED; |
| 1385 | |
Maciej Purski | 8a08f67 | 2018-07-25 17:46:38 +0200 | [diff] [blame] | 1386 | if (dsi->panel) { |
| 1387 | ret = drm_panel_prepare(dsi->panel); |
| 1388 | if (ret < 0) |
| 1389 | goto err_put_sync; |
| 1390 | } else { |
| 1391 | drm_bridge_pre_enable(dsi->out_bridge); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1392 | } |
| 1393 | |
| 1394 | exynos_dsi_set_display_mode(dsi); |
| 1395 | exynos_dsi_set_display_enable(dsi, true); |
| 1396 | |
Maciej Purski | 8a08f67 | 2018-07-25 17:46:38 +0200 | [diff] [blame] | 1397 | if (dsi->panel) { |
| 1398 | ret = drm_panel_enable(dsi->panel); |
| 1399 | if (ret < 0) |
| 1400 | goto err_display_disable; |
| 1401 | } else { |
| 1402 | drm_bridge_enable(dsi->out_bridge); |
Ajay Kumar | cdfb869 | 2014-07-31 23:12:06 +0530 | [diff] [blame] | 1403 | } |
| 1404 | |
Hyungwon Hwang | 0e480f6 | 2015-06-11 23:40:30 +0900 | [diff] [blame] | 1405 | dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; |
Maciej Purski | 8a08f67 | 2018-07-25 17:46:38 +0200 | [diff] [blame] | 1406 | return; |
| 1407 | |
| 1408 | err_display_disable: |
| 1409 | exynos_dsi_set_display_enable(dsi, false); |
| 1410 | drm_panel_unprepare(dsi->panel); |
| 1411 | |
| 1412 | err_put_sync: |
| 1413 | dsi->state &= ~DSIM_STATE_ENABLED; |
| 1414 | pm_runtime_put(dsi->dev); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1415 | } |
| 1416 | |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1417 | static void exynos_dsi_disable(struct drm_encoder *encoder) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1418 | { |
Gustavo Padovan | cf67cc9 | 2015-08-11 17:38:06 +0900 | [diff] [blame] | 1419 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1420 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1421 | if (!(dsi->state & DSIM_STATE_ENABLED)) |
| 1422 | return; |
| 1423 | |
Hyungwon Hwang | 0e480f6 | 2015-06-11 23:40:30 +0900 | [diff] [blame] | 1424 | dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; |
| 1425 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1426 | drm_panel_disable(dsi->panel); |
Maciej Purski | 8a08f67 | 2018-07-25 17:46:38 +0200 | [diff] [blame] | 1427 | drm_bridge_disable(dsi->out_bridge); |
Ajay Kumar | cdfb869 | 2014-07-31 23:12:06 +0530 | [diff] [blame] | 1428 | exynos_dsi_set_display_enable(dsi, false); |
| 1429 | drm_panel_unprepare(dsi->panel); |
Maciej Purski | 8a08f67 | 2018-07-25 17:46:38 +0200 | [diff] [blame] | 1430 | drm_bridge_post_disable(dsi->out_bridge); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1431 | dsi->state &= ~DSIM_STATE_ENABLED; |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1432 | pm_runtime_put_sync(dsi->dev); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1433 | } |
| 1434 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1435 | static enum drm_connector_status |
| 1436 | exynos_dsi_detect(struct drm_connector *connector, bool force) |
| 1437 | { |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1438 | return connector->status; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1439 | } |
| 1440 | |
| 1441 | static void exynos_dsi_connector_destroy(struct drm_connector *connector) |
| 1442 | { |
Andrzej Hajda | 0ae4601 | 2014-09-09 15:16:10 +0200 | [diff] [blame] | 1443 | drm_connector_unregister(connector); |
| 1444 | drm_connector_cleanup(connector); |
| 1445 | connector->dev = NULL; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1446 | } |
| 1447 | |
Ville Syrjälä | 800ba2b | 2015-12-15 12:21:06 +0100 | [diff] [blame] | 1448 | static const struct drm_connector_funcs exynos_dsi_connector_funcs = { |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1449 | .detect = exynos_dsi_detect, |
| 1450 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 1451 | .destroy = exynos_dsi_connector_destroy, |
Gustavo Padovan | 4ea9526 | 2015-06-01 12:04:44 -0300 | [diff] [blame] | 1452 | .reset = drm_atomic_helper_connector_reset, |
| 1453 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
| 1454 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1455 | }; |
| 1456 | |
| 1457 | static int exynos_dsi_get_modes(struct drm_connector *connector) |
| 1458 | { |
| 1459 | struct exynos_dsi *dsi = connector_to_dsi(connector); |
| 1460 | |
| 1461 | if (dsi->panel) |
| 1462 | return dsi->panel->funcs->get_modes(dsi->panel); |
| 1463 | |
| 1464 | return 0; |
| 1465 | } |
| 1466 | |
Ville Syrjälä | 800ba2b | 2015-12-15 12:21:06 +0100 | [diff] [blame] | 1467 | static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1468 | .get_modes = exynos_dsi_get_modes, |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1469 | }; |
| 1470 | |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1471 | static int exynos_dsi_create_connector(struct drm_encoder *encoder) |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1472 | { |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1473 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1474 | struct drm_connector *connector = &dsi->connector; |
Andrzej Hajda | deee328 | 2018-10-26 12:40:03 +0200 | [diff] [blame] | 1475 | struct drm_device *drm = encoder->dev; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1476 | int ret; |
| 1477 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1478 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 1479 | |
Andrzej Hajda | deee328 | 2018-10-26 12:40:03 +0200 | [diff] [blame] | 1480 | ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs, |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1481 | DRM_MODE_CONNECTOR_DSI); |
| 1482 | if (ret) { |
Inki Dae | 6f83d20 | 2019-04-15 14:24:36 +0900 | [diff] [blame] | 1483 | DRM_DEV_ERROR(dsi->dev, |
| 1484 | "Failed to initialize connector with drm\n"); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1485 | return ret; |
| 1486 | } |
| 1487 | |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1488 | connector->status = connector_status_disconnected; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1489 | drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); |
Daniel Vetter | cde4c44 | 2018-07-09 10:40:07 +0200 | [diff] [blame] | 1490 | drm_connector_attach_encoder(connector, encoder); |
Andrzej Hajda | deee328 | 2018-10-26 12:40:03 +0200 | [diff] [blame] | 1491 | if (!drm->registered) |
| 1492 | return 0; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1493 | |
Andrzej Hajda | deee328 | 2018-10-26 12:40:03 +0200 | [diff] [blame] | 1494 | connector->funcs->reset(connector); |
| 1495 | drm_fb_helper_add_one_connector(drm->fb_helper, connector); |
| 1496 | drm_connector_register(connector); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1497 | return 0; |
| 1498 | } |
| 1499 | |
Ville Syrjälä | 800ba2b | 2015-12-15 12:21:06 +0100 | [diff] [blame] | 1500 | static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = { |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1501 | .enable = exynos_dsi_enable, |
| 1502 | .disable = exynos_dsi_disable, |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1503 | }; |
| 1504 | |
Ville Syrjälä | 800ba2b | 2015-12-15 12:21:06 +0100 | [diff] [blame] | 1505 | static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = { |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1506 | .destroy = drm_encoder_cleanup, |
| 1507 | }; |
| 1508 | |
Sjoerd Simons | bd024b8 | 2014-07-30 11:29:41 +0900 | [diff] [blame] | 1509 | MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1510 | |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1511 | static int exynos_dsi_host_attach(struct mipi_dsi_host *host, |
| 1512 | struct mipi_dsi_device *device) |
| 1513 | { |
| 1514 | struct exynos_dsi *dsi = host_to_dsi(host); |
Maciej Purski | 6afb772 | 2018-08-07 16:50:59 +0900 | [diff] [blame] | 1515 | struct drm_encoder *encoder = &dsi->encoder; |
| 1516 | struct drm_device *drm = encoder->dev; |
| 1517 | struct drm_bridge *out_bridge; |
| 1518 | |
| 1519 | out_bridge = of_drm_find_bridge(device->dev.of_node); |
| 1520 | if (out_bridge) { |
| 1521 | drm_bridge_attach(encoder, out_bridge, NULL); |
| 1522 | dsi->out_bridge = out_bridge; |
| 1523 | encoder->bridge = NULL; |
| 1524 | } else { |
| 1525 | int ret = exynos_dsi_create_connector(encoder); |
| 1526 | |
| 1527 | if (ret) { |
Inki Dae | 6f83d20 | 2019-04-15 14:24:36 +0900 | [diff] [blame] | 1528 | DRM_DEV_ERROR(dsi->dev, |
| 1529 | "failed to create connector ret = %d\n", |
| 1530 | ret); |
Maciej Purski | 6afb772 | 2018-08-07 16:50:59 +0900 | [diff] [blame] | 1531 | drm_encoder_cleanup(encoder); |
| 1532 | return ret; |
| 1533 | } |
| 1534 | |
| 1535 | dsi->panel = of_drm_find_panel(device->dev.of_node); |
Dan Carpenter | 8727b23 | 2018-10-13 13:21:40 +0300 | [diff] [blame] | 1536 | if (IS_ERR(dsi->panel)) { |
| 1537 | dsi->panel = NULL; |
| 1538 | } else { |
Maciej Purski | 6afb772 | 2018-08-07 16:50:59 +0900 | [diff] [blame] | 1539 | drm_panel_attach(dsi->panel, &dsi->connector); |
| 1540 | dsi->connector.status = connector_status_connected; |
| 1541 | } |
| 1542 | } |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1543 | |
| 1544 | /* |
| 1545 | * This is a temporary solution and should be made by more generic way. |
| 1546 | * |
| 1547 | * If attached panel device is for command mode one, dsi should register |
| 1548 | * TE interrupt handler. |
| 1549 | */ |
| 1550 | if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { |
| 1551 | int ret = exynos_dsi_register_te_irq(dsi, &device->dev); |
| 1552 | if (ret) |
| 1553 | return ret; |
| 1554 | } |
| 1555 | |
| 1556 | mutex_lock(&drm->mode_config.mutex); |
| 1557 | |
| 1558 | dsi->lanes = device->lanes; |
| 1559 | dsi->format = device->format; |
| 1560 | dsi->mode_flags = device->mode_flags; |
Andrzej Hajda | c038f53 | 2017-08-24 15:33:53 +0200 | [diff] [blame] | 1561 | exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = |
| 1562 | !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1563 | |
| 1564 | mutex_unlock(&drm->mode_config.mutex); |
| 1565 | |
| 1566 | if (drm->mode_config.poll_enabled) |
| 1567 | drm_kms_helper_hotplug_event(drm); |
| 1568 | |
| 1569 | return 0; |
| 1570 | } |
| 1571 | |
| 1572 | static int exynos_dsi_host_detach(struct mipi_dsi_host *host, |
| 1573 | struct mipi_dsi_device *device) |
| 1574 | { |
| 1575 | struct exynos_dsi *dsi = host_to_dsi(host); |
Maciej Purski | 6afb772 | 2018-08-07 16:50:59 +0900 | [diff] [blame] | 1576 | struct drm_device *drm = dsi->encoder.dev; |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1577 | |
| 1578 | if (dsi->panel) { |
Maciej Purski | 6afb772 | 2018-08-07 16:50:59 +0900 | [diff] [blame] | 1579 | mutex_lock(&drm->mode_config.mutex); |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1580 | exynos_dsi_disable(&dsi->encoder); |
| 1581 | drm_panel_detach(dsi->panel); |
| 1582 | dsi->panel = NULL; |
| 1583 | dsi->connector.status = connector_status_disconnected; |
Maciej Purski | 6afb772 | 2018-08-07 16:50:59 +0900 | [diff] [blame] | 1584 | mutex_unlock(&drm->mode_config.mutex); |
| 1585 | } else { |
| 1586 | if (dsi->out_bridge->funcs->detach) |
| 1587 | dsi->out_bridge->funcs->detach(dsi->out_bridge); |
| 1588 | dsi->out_bridge = NULL; |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1589 | } |
| 1590 | |
Andrzej Hajda | 295e795 | 2017-08-24 15:33:52 +0200 | [diff] [blame] | 1591 | if (drm->mode_config.poll_enabled) |
| 1592 | drm_kms_helper_hotplug_event(drm); |
| 1593 | |
| 1594 | exynos_dsi_unregister_te_irq(dsi); |
| 1595 | |
| 1596 | return 0; |
| 1597 | } |
| 1598 | |
| 1599 | static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, |
| 1600 | const struct mipi_dsi_msg *msg) |
| 1601 | { |
| 1602 | struct exynos_dsi *dsi = host_to_dsi(host); |
| 1603 | struct exynos_dsi_transfer xfer; |
| 1604 | int ret; |
| 1605 | |
| 1606 | if (!(dsi->state & DSIM_STATE_ENABLED)) |
| 1607 | return -EINVAL; |
| 1608 | |
| 1609 | if (!(dsi->state & DSIM_STATE_INITIALIZED)) { |
| 1610 | ret = exynos_dsi_init(dsi); |
| 1611 | if (ret) |
| 1612 | return ret; |
| 1613 | dsi->state |= DSIM_STATE_INITIALIZED; |
| 1614 | } |
| 1615 | |
| 1616 | ret = mipi_dsi_create_packet(&xfer.packet, msg); |
| 1617 | if (ret < 0) |
| 1618 | return ret; |
| 1619 | |
| 1620 | xfer.rx_len = msg->rx_len; |
| 1621 | xfer.rx_payload = msg->rx_buf; |
| 1622 | xfer.flags = msg->flags; |
| 1623 | |
| 1624 | ret = exynos_dsi_transfer(dsi, &xfer); |
| 1625 | return (ret < 0) ? ret : xfer.rx_done; |
| 1626 | } |
| 1627 | |
| 1628 | static const struct mipi_dsi_host_ops exynos_dsi_ops = { |
| 1629 | .attach = exynos_dsi_host_attach, |
| 1630 | .detach = exynos_dsi_host_detach, |
| 1631 | .transfer = exynos_dsi_host_transfer, |
| 1632 | }; |
| 1633 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1634 | static int exynos_dsi_of_read_u32(const struct device_node *np, |
| 1635 | const char *propname, u32 *out_value) |
| 1636 | { |
| 1637 | int ret = of_property_read_u32(np, propname, out_value); |
| 1638 | |
| 1639 | if (ret < 0) |
Rob Herring | 4bf9914 | 2017-07-18 16:43:04 -0500 | [diff] [blame] | 1640 | pr_err("%pOF: failed to get '%s' property\n", np, propname); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1641 | |
| 1642 | return ret; |
| 1643 | } |
| 1644 | |
| 1645 | enum { |
| 1646 | DSI_PORT_IN, |
| 1647 | DSI_PORT_OUT |
| 1648 | }; |
| 1649 | |
| 1650 | static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) |
| 1651 | { |
| 1652 | struct device *dev = dsi->dev; |
| 1653 | struct device_node *node = dev->of_node; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1654 | int ret; |
| 1655 | |
| 1656 | ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", |
| 1657 | &dsi->pll_clk_rate); |
| 1658 | if (ret < 0) |
| 1659 | return ret; |
| 1660 | |
Hoegeun Kwon | f2921d8 | 2017-04-13 15:05:26 +0900 | [diff] [blame] | 1661 | ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1662 | &dsi->burst_clk_rate); |
| 1663 | if (ret < 0) |
Hoegeun Kwon | f2921d8 | 2017-04-13 15:05:26 +0900 | [diff] [blame] | 1664 | return ret; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1665 | |
Hoegeun Kwon | f2921d8 | 2017-04-13 15:05:26 +0900 | [diff] [blame] | 1666 | ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1667 | &dsi->esc_clk_rate); |
Hyungwon Hwang | f5f3b9b | 2015-06-12 21:59:08 +0900 | [diff] [blame] | 1668 | if (ret < 0) |
Hoegeun Kwon | f2921d8 | 2017-04-13 15:05:26 +0900 | [diff] [blame] | 1669 | return ret; |
Hyungwon Hwang | f5f3b9b | 2015-06-12 21:59:08 +0900 | [diff] [blame] | 1670 | |
Maciej Purski | 2782622 | 2018-07-25 17:46:36 +0200 | [diff] [blame] | 1671 | dsi->in_bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0); |
Hyungwon Hwang | f5f3b9b | 2015-06-12 21:59:08 +0900 | [diff] [blame] | 1672 | |
Hoegeun Kwon | f2921d8 | 2017-04-13 15:05:26 +0900 | [diff] [blame] | 1673 | return 0; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1674 | } |
| 1675 | |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1676 | static int exynos_dsi_bind(struct device *dev, struct device *master, |
| 1677 | void *data) |
| 1678 | { |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1679 | struct drm_encoder *encoder = dev_get_drvdata(dev); |
| 1680 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1681 | struct drm_device *drm_dev = data; |
Maciej Purski | 2782622 | 2018-07-25 17:46:36 +0200 | [diff] [blame] | 1682 | struct drm_bridge *in_bridge; |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1683 | int ret; |
| 1684 | |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1685 | drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, |
Ville Syrjälä | 13a3d91 | 2015-12-09 16:20:18 +0200 | [diff] [blame] | 1686 | DRM_MODE_ENCODER_TMDS, NULL); |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1687 | |
| 1688 | drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); |
| 1689 | |
Andrzej Hajda | 1ca582f | 2017-08-24 15:33:51 +0200 | [diff] [blame] | 1690 | ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); |
| 1691 | if (ret < 0) |
| 1692 | return ret; |
| 1693 | |
Maciej Purski | 2782622 | 2018-07-25 17:46:36 +0200 | [diff] [blame] | 1694 | if (dsi->in_bridge_node) { |
| 1695 | in_bridge = of_drm_find_bridge(dsi->in_bridge_node); |
| 1696 | if (in_bridge) |
| 1697 | drm_bridge_attach(encoder, in_bridge, NULL); |
Inki Dae | c994892 | 2017-06-14 17:09:00 +0900 | [diff] [blame] | 1698 | } |
Hyungwon Hwang | f5f3b9b | 2015-06-12 21:59:08 +0900 | [diff] [blame] | 1699 | |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1700 | return mipi_dsi_host_register(&dsi->dsi_host); |
| 1701 | } |
| 1702 | |
| 1703 | static void exynos_dsi_unbind(struct device *dev, struct device *master, |
| 1704 | void *data) |
| 1705 | { |
Gustavo Padovan | 2b8376c | 2015-08-15 12:14:08 -0300 | [diff] [blame] | 1706 | struct drm_encoder *encoder = dev_get_drvdata(dev); |
Gustavo Padovan | cf67cc9 | 2015-08-11 17:38:06 +0900 | [diff] [blame] | 1707 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1708 | |
Gustavo Padovan | cf67cc9 | 2015-08-11 17:38:06 +0900 | [diff] [blame] | 1709 | exynos_dsi_disable(encoder); |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1710 | |
Andrzej Hajda | 0ae4601 | 2014-09-09 15:16:10 +0200 | [diff] [blame] | 1711 | mipi_dsi_host_unregister(&dsi->dsi_host); |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1712 | } |
| 1713 | |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1714 | static const struct component_ops exynos_dsi_component_ops = { |
| 1715 | .bind = exynos_dsi_bind, |
| 1716 | .unbind = exynos_dsi_unbind, |
| 1717 | }; |
| 1718 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1719 | static int exynos_dsi_probe(struct platform_device *pdev) |
| 1720 | { |
Andrzej Hajda | 2900c69 | 2014-10-07 14:01:08 +0200 | [diff] [blame] | 1721 | struct device *dev = &pdev->dev; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1722 | struct resource *res; |
| 1723 | struct exynos_dsi *dsi; |
Hyungwon Hwang | 0ff03fd | 2015-06-12 21:59:06 +0900 | [diff] [blame] | 1724 | int ret, i; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1725 | |
Andrzej Hajda | 2900c69 | 2014-10-07 14:01:08 +0200 | [diff] [blame] | 1726 | dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); |
| 1727 | if (!dsi) |
| 1728 | return -ENOMEM; |
| 1729 | |
YoungJun Cho | e17ddec | 2014-07-22 19:49:44 +0900 | [diff] [blame] | 1730 | /* To be checked as invalid one */ |
| 1731 | dsi->te_gpio = -ENOENT; |
| 1732 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1733 | init_completion(&dsi->completed); |
| 1734 | spin_lock_init(&dsi->transfer_lock); |
| 1735 | INIT_LIST_HEAD(&dsi->transfer_list); |
| 1736 | |
| 1737 | dsi->dsi_host.ops = &exynos_dsi_ops; |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1738 | dsi->dsi_host.dev = dev; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1739 | |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1740 | dsi->dev = dev; |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 1741 | dsi->driver_data = of_device_get_match_data(dev); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1742 | |
| 1743 | ret = exynos_dsi_parse_dt(dsi); |
| 1744 | if (ret) |
Andrzej Hajda | 8665040 | 2015-06-11 23:23:37 +0900 | [diff] [blame] | 1745 | return ret; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1746 | |
| 1747 | dsi->supplies[0].supply = "vddcore"; |
| 1748 | dsi->supplies[1].supply = "vddio"; |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1749 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1750 | dsi->supplies); |
| 1751 | if (ret) { |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1752 | dev_info(dev, "failed to get regulators: %d\n", ret); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1753 | return -EPROBE_DEFER; |
| 1754 | } |
| 1755 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 1756 | dsi->clks = devm_kcalloc(dev, |
| 1757 | dsi->driver_data->num_clks, sizeof(*dsi->clks), |
Hyungwon Hwang | 0ff03fd | 2015-06-12 21:59:06 +0900 | [diff] [blame] | 1758 | GFP_KERNEL); |
Hyungwon Hwang | e6f988a | 2015-06-12 21:59:07 +0900 | [diff] [blame] | 1759 | if (!dsi->clks) |
| 1760 | return -ENOMEM; |
| 1761 | |
Hyungwon Hwang | 0ff03fd | 2015-06-12 21:59:06 +0900 | [diff] [blame] | 1762 | for (i = 0; i < dsi->driver_data->num_clks; i++) { |
| 1763 | dsi->clks[i] = devm_clk_get(dev, clk_names[i]); |
| 1764 | if (IS_ERR(dsi->clks[i])) { |
| 1765 | if (strcmp(clk_names[i], "sclk_mipi") == 0) { |
| 1766 | strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); |
| 1767 | i--; |
| 1768 | continue; |
| 1769 | } |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1770 | |
Hyungwon Hwang | 0ff03fd | 2015-06-12 21:59:06 +0900 | [diff] [blame] | 1771 | dev_info(dev, "failed to get the clock: %s\n", |
| 1772 | clk_names[i]); |
| 1773 | return PTR_ERR(dsi->clks[i]); |
| 1774 | } |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1775 | } |
| 1776 | |
| 1777 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1778 | dsi->reg_base = devm_ioremap_resource(dev, res); |
Jingoo Han | 293d3f6 | 2014-04-17 19:08:40 +0900 | [diff] [blame] | 1779 | if (IS_ERR(dsi->reg_base)) { |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1780 | dev_err(dev, "failed to remap io region\n"); |
Andrzej Hajda | 8665040 | 2015-06-11 23:23:37 +0900 | [diff] [blame] | 1781 | return PTR_ERR(dsi->reg_base); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1782 | } |
| 1783 | |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1784 | dsi->phy = devm_phy_get(dev, "dsim"); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1785 | if (IS_ERR(dsi->phy)) { |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1786 | dev_info(dev, "failed to get dsim phy\n"); |
Andrzej Hajda | 8665040 | 2015-06-11 23:23:37 +0900 | [diff] [blame] | 1787 | return PTR_ERR(dsi->phy); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1788 | } |
| 1789 | |
| 1790 | dsi->irq = platform_get_irq(pdev, 0); |
| 1791 | if (dsi->irq < 0) { |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1792 | dev_err(dev, "failed to request dsi irq resource\n"); |
Andrzej Hajda | 8665040 | 2015-06-11 23:23:37 +0900 | [diff] [blame] | 1793 | return dsi->irq; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1794 | } |
| 1795 | |
| 1796 | irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1797 | ret = devm_request_threaded_irq(dev, dsi->irq, NULL, |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1798 | exynos_dsi_irq, IRQF_ONESHOT, |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1799 | dev_name(dev), dsi); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1800 | if (ret) { |
Andrzej Hajda | e2d2a1e | 2014-10-07 14:01:09 +0200 | [diff] [blame] | 1801 | dev_err(dev, "failed to request dsi irq\n"); |
Andrzej Hajda | 8665040 | 2015-06-11 23:23:37 +0900 | [diff] [blame] | 1802 | return ret; |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1803 | } |
| 1804 | |
Gustavo Padovan | cf67cc9 | 2015-08-11 17:38:06 +0900 | [diff] [blame] | 1805 | platform_set_drvdata(pdev, &dsi->encoder); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1806 | |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1807 | pm_runtime_enable(dev); |
| 1808 | |
Andrzej Hajda | 8665040 | 2015-06-11 23:23:37 +0900 | [diff] [blame] | 1809 | return component_add(dev, &exynos_dsi_component_ops); |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1810 | } |
| 1811 | |
| 1812 | static int exynos_dsi_remove(struct platform_device *pdev) |
| 1813 | { |
Hoegeun Kwon | 70505c2 | 2017-05-26 10:02:01 +0900 | [diff] [blame] | 1814 | struct exynos_dsi *dsi = platform_get_drvdata(pdev); |
| 1815 | |
Maciej Purski | 2782622 | 2018-07-25 17:46:36 +0200 | [diff] [blame] | 1816 | of_node_put(dsi->in_bridge_node); |
Hoegeun Kwon | 70505c2 | 2017-05-26 10:02:01 +0900 | [diff] [blame] | 1817 | |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1818 | pm_runtime_disable(&pdev->dev); |
| 1819 | |
Inki Dae | df5225b | 2014-05-29 18:28:02 +0900 | [diff] [blame] | 1820 | component_del(&pdev->dev, &exynos_dsi_component_ops); |
Inki Dae | df5225b | 2014-05-29 18:28:02 +0900 | [diff] [blame] | 1821 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1822 | return 0; |
| 1823 | } |
| 1824 | |
Arnd Bergmann | 010848a | 2016-01-20 11:33:37 +0100 | [diff] [blame] | 1825 | static int __maybe_unused exynos_dsi_suspend(struct device *dev) |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1826 | { |
| 1827 | struct drm_encoder *encoder = dev_get_drvdata(dev); |
| 1828 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 1829 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1830 | int ret, i; |
| 1831 | |
| 1832 | usleep_range(10000, 20000); |
| 1833 | |
| 1834 | if (dsi->state & DSIM_STATE_INITIALIZED) { |
| 1835 | dsi->state &= ~DSIM_STATE_INITIALIZED; |
| 1836 | |
| 1837 | exynos_dsi_disable_clock(dsi); |
| 1838 | |
| 1839 | exynos_dsi_disable_irq(dsi); |
| 1840 | } |
| 1841 | |
| 1842 | dsi->state &= ~DSIM_STATE_CMD_LPM; |
| 1843 | |
| 1844 | phy_power_off(dsi->phy); |
| 1845 | |
| 1846 | for (i = driver_data->num_clks - 1; i > -1; i--) |
| 1847 | clk_disable_unprepare(dsi->clks[i]); |
| 1848 | |
| 1849 | ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); |
| 1850 | if (ret < 0) |
| 1851 | dev_err(dsi->dev, "cannot disable regulators %d\n", ret); |
| 1852 | |
| 1853 | return 0; |
| 1854 | } |
| 1855 | |
Arnd Bergmann | 010848a | 2016-01-20 11:33:37 +0100 | [diff] [blame] | 1856 | static int __maybe_unused exynos_dsi_resume(struct device *dev) |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1857 | { |
| 1858 | struct drm_encoder *encoder = dev_get_drvdata(dev); |
| 1859 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
Marek Szyprowski | 2154ac9 | 2016-04-19 09:37:10 +0200 | [diff] [blame] | 1860 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1861 | int ret, i; |
| 1862 | |
| 1863 | ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); |
| 1864 | if (ret < 0) { |
| 1865 | dev_err(dsi->dev, "cannot enable regulators %d\n", ret); |
| 1866 | return ret; |
| 1867 | } |
| 1868 | |
| 1869 | for (i = 0; i < driver_data->num_clks; i++) { |
| 1870 | ret = clk_prepare_enable(dsi->clks[i]); |
| 1871 | if (ret < 0) |
| 1872 | goto err_clk; |
| 1873 | } |
| 1874 | |
| 1875 | ret = phy_power_on(dsi->phy); |
| 1876 | if (ret < 0) { |
| 1877 | dev_err(dsi->dev, "cannot enable phy %d\n", ret); |
| 1878 | goto err_clk; |
| 1879 | } |
| 1880 | |
| 1881 | return 0; |
| 1882 | |
| 1883 | err_clk: |
| 1884 | while (--i > -1) |
| 1885 | clk_disable_unprepare(dsi->clks[i]); |
| 1886 | regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); |
| 1887 | |
| 1888 | return ret; |
| 1889 | } |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1890 | |
| 1891 | static const struct dev_pm_ops exynos_dsi_pm_ops = { |
| 1892 | SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) |
Marek Szyprowski | 7e91574 | 2018-06-11 14:25:00 +0200 | [diff] [blame] | 1893 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
| 1894 | pm_runtime_force_resume) |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1895 | }; |
| 1896 | |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1897 | struct platform_driver dsi_driver = { |
| 1898 | .probe = exynos_dsi_probe, |
| 1899 | .remove = exynos_dsi_remove, |
| 1900 | .driver = { |
| 1901 | .name = "exynos-dsi", |
| 1902 | .owner = THIS_MODULE, |
Inki Dae | ba6e477 | 2015-11-16 20:29:24 +0900 | [diff] [blame] | 1903 | .pm = &exynos_dsi_pm_ops, |
Andrzej Hajda | 7eb8f06 | 2014-04-04 01:19:56 +0900 | [diff] [blame] | 1904 | .of_match_table = exynos_dsi_of_match, |
| 1905 | }, |
| 1906 | }; |
| 1907 | |
| 1908 | MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); |
| 1909 | MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); |
| 1910 | MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); |
| 1911 | MODULE_LICENSE("GPL v2"); |