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Thomas Gleixner9c92ab62019-05-29 07:17:56 -07001// SPDX-License-Identifier: GPL-2.0-only
John Linnb85a3ef2011-06-20 11:47:27 -06002/*
Michal Simek9e09dc52013-03-27 12:05:28 +01003 * This file contains driver for the Cadence Triple Timer Counter Rev 06
John Linnb85a3ef2011-06-20 11:47:27 -06004 *
Michal Simeke9329002013-03-20 10:15:28 +01005 * Copyright (C) 2011-2013 Xilinx
John Linnb85a3ef2011-06-20 11:47:27 -06006 *
7 * based on arch/mips/kernel/time.c timer driver
John Linnb85a3ef2011-06-20 11:47:27 -06008 */
9
Michal Simeke9329002013-03-20 10:15:28 +010010#include <linux/clk.h>
John Linnb85a3ef2011-06-20 11:47:27 -060011#include <linux/interrupt.h>
John Linnb85a3ef2011-06-20 11:47:27 -060012#include <linux/clockchips.h>
Stephen Rothwell459fa242017-06-11 15:22:10 +100013#include <linux/clocksource.h>
Josh Cartwright91dc9852012-10-31 13:56:14 -060014#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/slab.h>
Soren Brinkmann3d77b302013-07-08 09:51:38 -070017#include <linux/sched_clock.h>
John Linnb85a3ef2011-06-20 11:47:27 -060018
John Linnb85a3ef2011-06-20 11:47:27 -060019/*
Michal Simek4e2bec02014-09-29 01:50:05 +020020 * This driver configures the 2 16/32-bit count-up timers as follows:
Michal Simeke9329002013-03-20 10:15:28 +010021 *
22 * T1: Timer 1, clocksource for generic timekeeping
23 * T2: Timer 2, clockevent source for hrtimers
24 * T3: Timer 3, <unused>
25 *
26 * The input frequency to the timer module for emulation is 2.5MHz which is
27 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
28 * the timers are clocked at 78.125KHz (12.8 us resolution).
29
30 * The input frequency to the timer module in silicon is configurable and
31 * obtained from device tree. The pre-scaler of 32 is used.
32 */
33
34/*
John Linnb85a3ef2011-06-20 11:47:27 -060035 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
36 * and use same offsets for Timer 2
37 */
Michal Simek9e09dc52013-03-27 12:05:28 +010038#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
39#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
40#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
41#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
42#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
43#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
John Linnb85a3ef2011-06-20 11:47:27 -060044
Michal Simek9e09dc52013-03-27 12:05:28 +010045#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
John Linnb85a3ef2011-06-20 11:47:27 -060046
Soren Brinkmann30e1e282013-05-13 10:46:38 -070047#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
Soren Brinkmannb3e90722014-02-19 15:14:42 -080048#define TTC_CLK_CNTRL_PSV_MASK 0x1e
49#define TTC_CLK_CNTRL_PSV_SHIFT 1
Soren Brinkmann30e1e282013-05-13 10:46:38 -070050
Soren Brinkmann03377e52012-12-19 10:18:41 -080051/*
52 * Setup the timers to use pre-scaling, using a fixed value for now that will
Josh Cartwright91dc9852012-10-31 13:56:14 -060053 * work across most input frequency, but it may need to be more dynamic
54 */
55#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
56#define PRESCALE 2048 /* The exponent must match this */
57#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
58#define CLK_CNTRL_PRESCALE_EN 1
Michal Simeke9329002013-03-20 10:15:28 +010059#define CNT_CNTRL_RESET (1 << 4)
John Linnb85a3ef2011-06-20 11:47:27 -060060
Soren Brinkmannb3e90722014-02-19 15:14:42 -080061#define MAX_F_ERR 50
62
John Linnb85a3ef2011-06-20 11:47:27 -060063/**
Michal Simek9e09dc52013-03-27 12:05:28 +010064 * struct ttc_timer - This definition defines local timer structure
John Linnb85a3ef2011-06-20 11:47:27 -060065 *
66 * @base_addr: Base address of timer
Soren Brinkmannc1dcc922013-11-26 17:04:50 -080067 * @freq: Timer input clock frequency
Michal Simeke9329002013-03-20 10:15:28 +010068 * @clk: Associated clock source
69 * @clk_rate_change_nb Notifier block for clock rate changes
70 */
Michal Simek9e09dc52013-03-27 12:05:28 +010071struct ttc_timer {
Michal Simeke9329002013-03-20 10:15:28 +010072 void __iomem *base_addr;
Soren Brinkmannc1dcc922013-11-26 17:04:50 -080073 unsigned long freq;
Michal Simeke9329002013-03-20 10:15:28 +010074 struct clk *clk;
75 struct notifier_block clk_rate_change_nb;
John Linnb85a3ef2011-06-20 11:47:27 -060076};
77
Michal Simek9e09dc52013-03-27 12:05:28 +010078#define to_ttc_timer(x) \
79 container_of(x, struct ttc_timer, clk_rate_change_nb)
Michal Simeke9329002013-03-20 10:15:28 +010080
Michal Simek9e09dc52013-03-27 12:05:28 +010081struct ttc_timer_clocksource {
Soren Brinkmannb3e90722014-02-19 15:14:42 -080082 u32 scale_clk_ctrl_reg_old;
83 u32 scale_clk_ctrl_reg_new;
Michal Simek9e09dc52013-03-27 12:05:28 +010084 struct ttc_timer ttc;
Josh Cartwright91dc9852012-10-31 13:56:14 -060085 struct clocksource cs;
86};
87
Michal Simek9e09dc52013-03-27 12:05:28 +010088#define to_ttc_timer_clksrc(x) \
89 container_of(x, struct ttc_timer_clocksource, cs)
Josh Cartwright91dc9852012-10-31 13:56:14 -060090
Michal Simek9e09dc52013-03-27 12:05:28 +010091struct ttc_timer_clockevent {
92 struct ttc_timer ttc;
Josh Cartwright91dc9852012-10-31 13:56:14 -060093 struct clock_event_device ce;
Josh Cartwright91dc9852012-10-31 13:56:14 -060094};
95
Michal Simek9e09dc52013-03-27 12:05:28 +010096#define to_ttc_timer_clkevent(x) \
97 container_of(x, struct ttc_timer_clockevent, ce)
John Linnb85a3ef2011-06-20 11:47:27 -060098
Soren Brinkmann3d77b302013-07-08 09:51:38 -070099static void __iomem *ttc_sched_clock_val_reg;
100
John Linnb85a3ef2011-06-20 11:47:27 -0600101/**
Michal Simek9e09dc52013-03-27 12:05:28 +0100102 * ttc_set_interval - Set the timer interval value
John Linnb85a3ef2011-06-20 11:47:27 -0600103 *
104 * @timer: Pointer to the timer instance
105 * @cycles: Timer interval ticks
106 **/
Michal Simek9e09dc52013-03-27 12:05:28 +0100107static void ttc_set_interval(struct ttc_timer *timer,
John Linnb85a3ef2011-06-20 11:47:27 -0600108 unsigned long cycles)
109{
110 u32 ctrl_reg;
111
112 /* Disable the counter, set the counter value and re-enable counter */
Michal Simek87ab4362014-04-11 15:39:29 +0200113 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
Michal Simek9e09dc52013-03-27 12:05:28 +0100114 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
Michal Simek87ab4362014-04-11 15:39:29 +0200115 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
John Linnb85a3ef2011-06-20 11:47:27 -0600116
Michal Simek87ab4362014-04-11 15:39:29 +0200117 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
John Linnb85a3ef2011-06-20 11:47:27 -0600118
Soren Brinkmann03377e52012-12-19 10:18:41 -0800119 /*
120 * Reset the counter (0x10) so that it starts from 0, one-shot
121 * mode makes this needed for timing to be right.
122 */
Josh Cartwright91dc9852012-10-31 13:56:14 -0600123 ctrl_reg |= CNT_CNTRL_RESET;
Michal Simek9e09dc52013-03-27 12:05:28 +0100124 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
Michal Simek87ab4362014-04-11 15:39:29 +0200125 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
John Linnb85a3ef2011-06-20 11:47:27 -0600126}
127
128/**
Michal Simek9e09dc52013-03-27 12:05:28 +0100129 * ttc_clock_event_interrupt - Clock event timer interrupt handler
John Linnb85a3ef2011-06-20 11:47:27 -0600130 *
131 * @irq: IRQ number of the Timer
Michal Simek9e09dc52013-03-27 12:05:28 +0100132 * @dev_id: void pointer to the ttc_timer instance
John Linnb85a3ef2011-06-20 11:47:27 -0600133 *
134 * returns: Always IRQ_HANDLED - success
135 **/
Michal Simek9e09dc52013-03-27 12:05:28 +0100136static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
John Linnb85a3ef2011-06-20 11:47:27 -0600137{
Michal Simek9e09dc52013-03-27 12:05:28 +0100138 struct ttc_timer_clockevent *ttce = dev_id;
139 struct ttc_timer *timer = &ttce->ttc;
John Linnb85a3ef2011-06-20 11:47:27 -0600140
141 /* Acknowledge the interrupt and call event handler */
Michal Simek87ab4362014-04-11 15:39:29 +0200142 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
John Linnb85a3ef2011-06-20 11:47:27 -0600143
Michal Simek9e09dc52013-03-27 12:05:28 +0100144 ttce->ce.event_handler(&ttce->ce);
John Linnb85a3ef2011-06-20 11:47:27 -0600145
146 return IRQ_HANDLED;
147}
148
John Linnb85a3ef2011-06-20 11:47:27 -0600149/**
Michal Simek9e09dc52013-03-27 12:05:28 +0100150 * __ttc_clocksource_read - Reads the timer counter register
John Linnb85a3ef2011-06-20 11:47:27 -0600151 *
152 * returns: Current timer counter register value
153 **/
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +0100154static u64 __ttc_clocksource_read(struct clocksource *cs)
John Linnb85a3ef2011-06-20 11:47:27 -0600155{
Michal Simek9e09dc52013-03-27 12:05:28 +0100156 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
John Linnb85a3ef2011-06-20 11:47:27 -0600157
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +0100158 return (u64)readl_relaxed(timer->base_addr +
Michal Simek9e09dc52013-03-27 12:05:28 +0100159 TTC_COUNT_VAL_OFFSET);
John Linnb85a3ef2011-06-20 11:47:27 -0600160}
161
Stephen Boyddfded002013-11-20 00:47:32 +0100162static u64 notrace ttc_sched_clock_read(void)
Soren Brinkmann3d77b302013-07-08 09:51:38 -0700163{
Michal Simek87ab4362014-04-11 15:39:29 +0200164 return readl_relaxed(ttc_sched_clock_val_reg);
Soren Brinkmann3d77b302013-07-08 09:51:38 -0700165}
166
John Linnb85a3ef2011-06-20 11:47:27 -0600167/**
Michal Simek9e09dc52013-03-27 12:05:28 +0100168 * ttc_set_next_event - Sets the time interval for next event
John Linnb85a3ef2011-06-20 11:47:27 -0600169 *
170 * @cycles: Timer interval ticks
171 * @evt: Address of clock event instance
172 *
173 * returns: Always 0 - success
174 **/
Michal Simek9e09dc52013-03-27 12:05:28 +0100175static int ttc_set_next_event(unsigned long cycles,
John Linnb85a3ef2011-06-20 11:47:27 -0600176 struct clock_event_device *evt)
177{
Michal Simek9e09dc52013-03-27 12:05:28 +0100178 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
179 struct ttc_timer *timer = &ttce->ttc;
John Linnb85a3ef2011-06-20 11:47:27 -0600180
Michal Simek9e09dc52013-03-27 12:05:28 +0100181 ttc_set_interval(timer, cycles);
John Linnb85a3ef2011-06-20 11:47:27 -0600182 return 0;
183}
184
185/**
Viresh Kumar5c0a4bb2015-06-18 16:24:16 +0530186 * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
John Linnb85a3ef2011-06-20 11:47:27 -0600187 *
John Linnb85a3ef2011-06-20 11:47:27 -0600188 * @evt: Address of clock event instance
189 **/
Viresh Kumar5c0a4bb2015-06-18 16:24:16 +0530190static int ttc_shutdown(struct clock_event_device *evt)
John Linnb85a3ef2011-06-20 11:47:27 -0600191{
Michal Simek9e09dc52013-03-27 12:05:28 +0100192 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
193 struct ttc_timer *timer = &ttce->ttc;
John Linnb85a3ef2011-06-20 11:47:27 -0600194 u32 ctrl_reg;
195
Viresh Kumar5c0a4bb2015-06-18 16:24:16 +0530196 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
197 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
198 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
199 return 0;
200}
201
202static int ttc_set_periodic(struct clock_event_device *evt)
203{
204 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
205 struct ttc_timer *timer = &ttce->ttc;
206
207 ttc_set_interval(timer,
208 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
209 return 0;
210}
211
212static int ttc_resume(struct clock_event_device *evt)
213{
214 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
215 struct ttc_timer *timer = &ttce->ttc;
216 u32 ctrl_reg;
217
218 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
219 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
220 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
221 return 0;
John Linnb85a3ef2011-06-20 11:47:27 -0600222}
223
Michal Simek9e09dc52013-03-27 12:05:28 +0100224static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
Michal Simeke9329002013-03-20 10:15:28 +0100225 unsigned long event, void *data)
226{
227 struct clk_notifier_data *ndata = data;
Michal Simek9e09dc52013-03-27 12:05:28 +0100228 struct ttc_timer *ttc = to_ttc_timer(nb);
229 struct ttc_timer_clocksource *ttccs = container_of(ttc,
230 struct ttc_timer_clocksource, ttc);
Michal Simeke9329002013-03-20 10:15:28 +0100231
232 switch (event) {
Michal Simeke9329002013-03-20 10:15:28 +0100233 case PRE_RATE_CHANGE:
Soren Brinkmannb3e90722014-02-19 15:14:42 -0800234 {
235 u32 psv;
236 unsigned long factor, rate_low, rate_high;
237
238 if (ndata->new_rate > ndata->old_rate) {
239 factor = DIV_ROUND_CLOSEST(ndata->new_rate,
240 ndata->old_rate);
241 rate_low = ndata->old_rate;
242 rate_high = ndata->new_rate;
243 } else {
244 factor = DIV_ROUND_CLOSEST(ndata->old_rate,
245 ndata->new_rate);
246 rate_low = ndata->new_rate;
247 rate_high = ndata->old_rate;
248 }
249
250 if (!is_power_of_2(factor))
251 return NOTIFY_BAD;
252
253 if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
254 return NOTIFY_BAD;
255
256 factor = __ilog2_u32(factor);
257
258 /*
259 * store timer clock ctrl register so we can restore it in case
260 * of an abort.
261 */
262 ttccs->scale_clk_ctrl_reg_old =
Michal Simek87ab4362014-04-11 15:39:29 +0200263 readl_relaxed(ttccs->ttc.base_addr +
264 TTC_CLK_CNTRL_OFFSET);
Soren Brinkmannb3e90722014-02-19 15:14:42 -0800265
266 psv = (ttccs->scale_clk_ctrl_reg_old &
267 TTC_CLK_CNTRL_PSV_MASK) >>
268 TTC_CLK_CNTRL_PSV_SHIFT;
269 if (ndata->new_rate < ndata->old_rate)
270 psv -= factor;
271 else
272 psv += factor;
273
274 /* prescaler within legal range? */
275 if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
276 return NOTIFY_BAD;
277
278 ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
279 ~TTC_CLK_CNTRL_PSV_MASK;
280 ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
281
282
283 /* scale down: adjust divider in post-change notification */
284 if (ndata->new_rate < ndata->old_rate)
285 return NOTIFY_DONE;
286
287 /* scale up: adjust divider now - before frequency change */
Michal Simek87ab4362014-04-11 15:39:29 +0200288 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
289 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
Soren Brinkmannb3e90722014-02-19 15:14:42 -0800290 break;
291 }
292 case POST_RATE_CHANGE:
293 /* scale up: pre-change notification did the adjustment */
294 if (ndata->new_rate > ndata->old_rate)
295 return NOTIFY_OK;
296
297 /* scale down: adjust divider now - after frequency change */
Michal Simek87ab4362014-04-11 15:39:29 +0200298 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
299 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
Soren Brinkmannb3e90722014-02-19 15:14:42 -0800300 break;
301
Michal Simeke9329002013-03-20 10:15:28 +0100302 case ABORT_RATE_CHANGE:
Soren Brinkmannb3e90722014-02-19 15:14:42 -0800303 /* we have to undo the adjustment in case we scale up */
304 if (ndata->new_rate < ndata->old_rate)
305 return NOTIFY_OK;
306
307 /* restore original register value */
Michal Simek87ab4362014-04-11 15:39:29 +0200308 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
309 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
Soren Brinkmannb3e90722014-02-19 15:14:42 -0800310 /* fall through */
Michal Simeke9329002013-03-20 10:15:28 +0100311 default:
312 return NOTIFY_DONE;
313 }
Soren Brinkmannb3e90722014-02-19 15:14:42 -0800314
315 return NOTIFY_DONE;
Michal Simeke9329002013-03-20 10:15:28 +0100316}
317
Daniel Lezcano70504f32016-05-31 19:52:09 +0200318static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
Michal Simek4e2bec02014-09-29 01:50:05 +0200319 u32 timer_width)
Josh Cartwright91dc9852012-10-31 13:56:14 -0600320{
Michal Simek9e09dc52013-03-27 12:05:28 +0100321 struct ttc_timer_clocksource *ttccs;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600322 int err;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600323
324 ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200325 if (!ttccs)
326 return -ENOMEM;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600327
Michal Simek9e09dc52013-03-27 12:05:28 +0100328 ttccs->ttc.clk = clk;
Michal Simeke9329002013-03-20 10:15:28 +0100329
Michal Simek9e09dc52013-03-27 12:05:28 +0100330 err = clk_prepare_enable(ttccs->ttc.clk);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200331 if (err) {
Michal Simekc5263bb2013-03-20 10:24:59 +0100332 kfree(ttccs);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200333 return err;
Michal Simekc5263bb2013-03-20 10:24:59 +0100334 }
Josh Cartwright91dc9852012-10-31 13:56:14 -0600335
Soren Brinkmannc1dcc922013-11-26 17:04:50 -0800336 ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
337
Michal Simek9e09dc52013-03-27 12:05:28 +0100338 ttccs->ttc.clk_rate_change_nb.notifier_call =
339 ttc_rate_change_clocksource_cb;
340 ttccs->ttc.clk_rate_change_nb.next = NULL;
Daniel Lezcano70504f32016-05-31 19:52:09 +0200341
342 err = clk_notifier_register(ttccs->ttc.clk,
343 &ttccs->ttc.clk_rate_change_nb);
344 if (err)
Michal Simeke9329002013-03-20 10:15:28 +0100345 pr_warn("Unable to register clock notifier.\n");
Josh Cartwright91dc9852012-10-31 13:56:14 -0600346
Michal Simek9e09dc52013-03-27 12:05:28 +0100347 ttccs->ttc.base_addr = base;
348 ttccs->cs.name = "ttc_clocksource";
Josh Cartwright91dc9852012-10-31 13:56:14 -0600349 ttccs->cs.rating = 200;
Michal Simek9e09dc52013-03-27 12:05:28 +0100350 ttccs->cs.read = __ttc_clocksource_read;
Michal Simek4e2bec02014-09-29 01:50:05 +0200351 ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
Josh Cartwright91dc9852012-10-31 13:56:14 -0600352 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
353
Michal Simeke9329002013-03-20 10:15:28 +0100354 /*
355 * Setup the clock source counter to be an incrementing counter
356 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
357 * it by 32 also. Let it start running now.
358 */
Michal Simek87ab4362014-04-11 15:39:29 +0200359 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
360 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
Michal Simek9e09dc52013-03-27 12:05:28 +0100361 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
Michal Simek87ab4362014-04-11 15:39:29 +0200362 writel_relaxed(CNT_CNTRL_RESET,
Michal Simek9e09dc52013-03-27 12:05:28 +0100363 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
Josh Cartwright91dc9852012-10-31 13:56:14 -0600364
Soren Brinkmannc1dcc922013-11-26 17:04:50 -0800365 err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200366 if (err) {
Michal Simekc5263bb2013-03-20 10:24:59 +0100367 kfree(ttccs);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200368 return err;
Michal Simekc5263bb2013-03-20 10:24:59 +0100369 }
Soren Brinkmann3d77b302013-07-08 09:51:38 -0700370
371 ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
Michal Simek4e2bec02014-09-29 01:50:05 +0200372 sched_clock_register(ttc_sched_clock_read, timer_width,
373 ttccs->ttc.freq / PRESCALE);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200374
375 return 0;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600376}
377
Michal Simek9e09dc52013-03-27 12:05:28 +0100378static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
Michal Simeke9329002013-03-20 10:15:28 +0100379 unsigned long event, void *data)
380{
381 struct clk_notifier_data *ndata = data;
Michal Simek9e09dc52013-03-27 12:05:28 +0100382 struct ttc_timer *ttc = to_ttc_timer(nb);
383 struct ttc_timer_clockevent *ttcce = container_of(ttc,
384 struct ttc_timer_clockevent, ttc);
Michal Simeke9329002013-03-20 10:15:28 +0100385
386 switch (event) {
387 case POST_RATE_CHANGE:
Soren Brinkmannc1dcc922013-11-26 17:04:50 -0800388 /* update cached frequency */
389 ttc->freq = ndata->new_rate;
390
Soren Brinkmann5f0ba3b2014-02-19 15:14:41 -0800391 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
392
Michal Simeke9329002013-03-20 10:15:28 +0100393 /* fall through */
Michal Simeke9329002013-03-20 10:15:28 +0100394 case PRE_RATE_CHANGE:
395 case ABORT_RATE_CHANGE:
396 default:
397 return NOTIFY_DONE;
398 }
399}
400
Daniel Lezcano70504f32016-05-31 19:52:09 +0200401static int __init ttc_setup_clockevent(struct clk *clk,
402 void __iomem *base, u32 irq)
Josh Cartwright91dc9852012-10-31 13:56:14 -0600403{
Michal Simek9e09dc52013-03-27 12:05:28 +0100404 struct ttc_timer_clockevent *ttcce;
Michal Simeke9329002013-03-20 10:15:28 +0100405 int err;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600406
407 ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200408 if (!ttcce)
409 return -ENOMEM;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600410
Michal Simek9e09dc52013-03-27 12:05:28 +0100411 ttcce->ttc.clk = clk;
Michal Simeke9329002013-03-20 10:15:28 +0100412
Michal Simek9e09dc52013-03-27 12:05:28 +0100413 err = clk_prepare_enable(ttcce->ttc.clk);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200414 if (err) {
Michal Simekc5263bb2013-03-20 10:24:59 +0100415 kfree(ttcce);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200416 return err;
Michal Simekc5263bb2013-03-20 10:24:59 +0100417 }
Josh Cartwright91dc9852012-10-31 13:56:14 -0600418
Michal Simek9e09dc52013-03-27 12:05:28 +0100419 ttcce->ttc.clk_rate_change_nb.notifier_call =
420 ttc_rate_change_clockevent_cb;
421 ttcce->ttc.clk_rate_change_nb.next = NULL;
Daniel Lezcano70504f32016-05-31 19:52:09 +0200422
423 err = clk_notifier_register(ttcce->ttc.clk,
424 &ttcce->ttc.clk_rate_change_nb);
425 if (err) {
Michal Simeke9329002013-03-20 10:15:28 +0100426 pr_warn("Unable to register clock notifier.\n");
Daniel Lezcano70504f32016-05-31 19:52:09 +0200427 return err;
428 }
429
Soren Brinkmannc1dcc922013-11-26 17:04:50 -0800430 ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
Josh Cartwright91dc9852012-10-31 13:56:14 -0600431
Michal Simek9e09dc52013-03-27 12:05:28 +0100432 ttcce->ttc.base_addr = base;
433 ttcce->ce.name = "ttc_clockevent";
Josh Cartwright91dc9852012-10-31 13:56:14 -0600434 ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
Michal Simek9e09dc52013-03-27 12:05:28 +0100435 ttcce->ce.set_next_event = ttc_set_next_event;
Viresh Kumar5c0a4bb2015-06-18 16:24:16 +0530436 ttcce->ce.set_state_shutdown = ttc_shutdown;
437 ttcce->ce.set_state_periodic = ttc_set_periodic;
438 ttcce->ce.set_state_oneshot = ttc_shutdown;
439 ttcce->ce.tick_resume = ttc_resume;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600440 ttcce->ce.rating = 200;
441 ttcce->ce.irq = irq;
Soren Brinkmann87e4ee72012-12-19 10:18:42 -0800442 ttcce->ce.cpumask = cpu_possible_mask;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600443
Michal Simeke9329002013-03-20 10:15:28 +0100444 /*
445 * Setup the clock event timer to be an interval timer which
446 * is prescaled by 32 using the interval interrupt. Leave it
447 * disabled for now.
448 */
Michal Simek87ab4362014-04-11 15:39:29 +0200449 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
450 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
Michal Simek9e09dc52013-03-27 12:05:28 +0100451 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
Michal Simek87ab4362014-04-11 15:39:29 +0200452 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
Josh Cartwright91dc9852012-10-31 13:56:14 -0600453
Michal Simek9e09dc52013-03-27 12:05:28 +0100454 err = request_irq(irq, ttc_clock_event_interrupt,
Michael Opdenacker38c30a82013-12-09 10:12:10 +0100455 IRQF_TIMER, ttcce->ce.name, ttcce);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200456 if (err) {
Michal Simekc5263bb2013-03-20 10:24:59 +0100457 kfree(ttcce);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200458 return err;
Michal Simekc5263bb2013-03-20 10:24:59 +0100459 }
Josh Cartwright91dc9852012-10-31 13:56:14 -0600460
461 clockevents_config_and_register(&ttcce->ce,
Soren Brinkmannc1dcc922013-11-26 17:04:50 -0800462 ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200463
464 return 0;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600465}
466
John Linnb85a3ef2011-06-20 11:47:27 -0600467/**
Michal Simek9e09dc52013-03-27 12:05:28 +0100468 * ttc_timer_init - Initialize the timer
John Linnb85a3ef2011-06-20 11:47:27 -0600469 *
470 * Initializes the timer hardware and register the clock source and clock event
471 * timers with Linux kernal timer framework
Michal Simeke9329002013-03-20 10:15:28 +0100472 */
Daniel Lezcano70504f32016-05-31 19:52:09 +0200473static int __init ttc_timer_init(struct device_node *timer)
Michal Simeke9329002013-03-20 10:15:28 +0100474{
475 unsigned int irq;
476 void __iomem *timer_baseaddr;
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700477 struct clk *clk_cs, *clk_ce;
Michal Simekc5263bb2013-03-20 10:24:59 +0100478 static int initialized;
Daniel Lezcano70504f32016-05-31 19:52:09 +0200479 int clksel, ret;
Michal Simek4e2bec02014-09-29 01:50:05 +0200480 u32 timer_width = 16;
Michal Simekc5263bb2013-03-20 10:24:59 +0100481
482 if (initialized)
Daniel Lezcano70504f32016-05-31 19:52:09 +0200483 return 0;
Michal Simekc5263bb2013-03-20 10:24:59 +0100484
485 initialized = 1;
Michal Simeke9329002013-03-20 10:15:28 +0100486
487 /*
488 * Get the 1st Triple Timer Counter (TTC) block from the device tree
489 * and use it. Note that the event timer uses the interrupt and it's the
490 * 2nd TTC hence the irq_of_parse_and_map(,1)
491 */
492 timer_baseaddr = of_iomap(timer, 0);
493 if (!timer_baseaddr) {
494 pr_err("ERROR: invalid timer base address\n");
Daniel Lezcano70504f32016-05-31 19:52:09 +0200495 return -ENXIO;
Michal Simeke9329002013-03-20 10:15:28 +0100496 }
497
498 irq = irq_of_parse_and_map(timer, 1);
499 if (irq <= 0) {
500 pr_err("ERROR: invalid interrupt number\n");
Daniel Lezcano70504f32016-05-31 19:52:09 +0200501 return -EINVAL;
Michal Simeke9329002013-03-20 10:15:28 +0100502 }
503
Michal Simek4e2bec02014-09-29 01:50:05 +0200504 of_property_read_u32(timer, "timer-width", &timer_width);
505
Michal Simek87ab4362014-04-11 15:39:29 +0200506 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700507 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
508 clk_cs = of_clk_get(timer, clksel);
509 if (IS_ERR(clk_cs)) {
Michal Simeke9329002013-03-20 10:15:28 +0100510 pr_err("ERROR: timer input clock not found\n");
Daniel Lezcano70504f32016-05-31 19:52:09 +0200511 return PTR_ERR(clk_cs);
Michal Simeke9329002013-03-20 10:15:28 +0100512 }
513
Michal Simek87ab4362014-04-11 15:39:29 +0200514 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700515 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
516 clk_ce = of_clk_get(timer, clksel);
517 if (IS_ERR(clk_ce)) {
518 pr_err("ERROR: timer input clock not found\n");
Christophe Jaillet34c720a2016-07-06 07:35:23 +0200519 return PTR_ERR(clk_ce);
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700520 }
521
Daniel Lezcano70504f32016-05-31 19:52:09 +0200522 ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
523 if (ret)
524 return ret;
525
526 ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
527 if (ret)
528 return ret;
Michal Simeke9329002013-03-20 10:15:28 +0100529
Rob Herring2a4849d2018-08-27 20:52:14 -0500530 pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
Daniel Lezcano70504f32016-05-31 19:52:09 +0200531
532 return 0;
Michal Simeke9329002013-03-20 10:15:28 +0100533}
534
Daniel Lezcano17273392017-05-26 16:56:11 +0200535TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);