Thomas Gleixner | 9c92ab6 | 2019-05-29 07:17:56 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 2 | /* |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 3 | * This file contains driver for the Cadence Triple Timer Counter Rev 06 |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 4 | * |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 5 | * Copyright (C) 2011-2013 Xilinx |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 6 | * |
| 7 | * based on arch/mips/kernel/time.c timer driver |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 8 | */ |
| 9 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 10 | #include <linux/clk.h> |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 11 | #include <linux/interrupt.h> |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 12 | #include <linux/clockchips.h> |
Stephen Rothwell | 459fa24 | 2017-06-11 15:22:10 +1000 | [diff] [blame] | 13 | #include <linux/clocksource.h> |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 14 | #include <linux/of_address.h> |
| 15 | #include <linux/of_irq.h> |
| 16 | #include <linux/slab.h> |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 17 | #include <linux/sched_clock.h> |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 18 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 19 | /* |
Michal Simek | 4e2bec0 | 2014-09-29 01:50:05 +0200 | [diff] [blame] | 20 | * This driver configures the 2 16/32-bit count-up timers as follows: |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 21 | * |
| 22 | * T1: Timer 1, clocksource for generic timekeeping |
| 23 | * T2: Timer 2, clockevent source for hrtimers |
| 24 | * T3: Timer 3, <unused> |
| 25 | * |
| 26 | * The input frequency to the timer module for emulation is 2.5MHz which is |
| 27 | * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, |
| 28 | * the timers are clocked at 78.125KHz (12.8 us resolution). |
| 29 | |
| 30 | * The input frequency to the timer module in silicon is configurable and |
| 31 | * obtained from device tree. The pre-scaler of 32 is used. |
| 32 | */ |
| 33 | |
| 34 | /* |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 35 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 |
| 36 | * and use same offsets for Timer 2 |
| 37 | */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 38 | #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ |
| 39 | #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ |
| 40 | #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ |
| 41 | #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ |
| 42 | #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ |
| 43 | #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 44 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 45 | #define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 46 | |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 47 | #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 48 | #define TTC_CLK_CNTRL_PSV_MASK 0x1e |
| 49 | #define TTC_CLK_CNTRL_PSV_SHIFT 1 |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 50 | |
Soren Brinkmann | 03377e5 | 2012-12-19 10:18:41 -0800 | [diff] [blame] | 51 | /* |
| 52 | * Setup the timers to use pre-scaling, using a fixed value for now that will |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 53 | * work across most input frequency, but it may need to be more dynamic |
| 54 | */ |
| 55 | #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ |
| 56 | #define PRESCALE 2048 /* The exponent must match this */ |
| 57 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) |
| 58 | #define CLK_CNTRL_PRESCALE_EN 1 |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 59 | #define CNT_CNTRL_RESET (1 << 4) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 60 | |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 61 | #define MAX_F_ERR 50 |
| 62 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 63 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 64 | * struct ttc_timer - This definition defines local timer structure |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 65 | * |
| 66 | * @base_addr: Base address of timer |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 67 | * @freq: Timer input clock frequency |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 68 | * @clk: Associated clock source |
| 69 | * @clk_rate_change_nb Notifier block for clock rate changes |
| 70 | */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 71 | struct ttc_timer { |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 72 | void __iomem *base_addr; |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 73 | unsigned long freq; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 74 | struct clk *clk; |
| 75 | struct notifier_block clk_rate_change_nb; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 76 | }; |
| 77 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 78 | #define to_ttc_timer(x) \ |
| 79 | container_of(x, struct ttc_timer, clk_rate_change_nb) |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 80 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 81 | struct ttc_timer_clocksource { |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 82 | u32 scale_clk_ctrl_reg_old; |
| 83 | u32 scale_clk_ctrl_reg_new; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 84 | struct ttc_timer ttc; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 85 | struct clocksource cs; |
| 86 | }; |
| 87 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 88 | #define to_ttc_timer_clksrc(x) \ |
| 89 | container_of(x, struct ttc_timer_clocksource, cs) |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 90 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 91 | struct ttc_timer_clockevent { |
| 92 | struct ttc_timer ttc; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 93 | struct clock_event_device ce; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 94 | }; |
| 95 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 96 | #define to_ttc_timer_clkevent(x) \ |
| 97 | container_of(x, struct ttc_timer_clockevent, ce) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 98 | |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 99 | static void __iomem *ttc_sched_clock_val_reg; |
| 100 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 101 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 102 | * ttc_set_interval - Set the timer interval value |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 103 | * |
| 104 | * @timer: Pointer to the timer instance |
| 105 | * @cycles: Timer interval ticks |
| 106 | **/ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 107 | static void ttc_set_interval(struct ttc_timer *timer, |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 108 | unsigned long cycles) |
| 109 | { |
| 110 | u32 ctrl_reg; |
| 111 | |
| 112 | /* Disable the counter, set the counter value and re-enable counter */ |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 113 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 114 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 115 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 116 | |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 117 | writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 118 | |
Soren Brinkmann | 03377e5 | 2012-12-19 10:18:41 -0800 | [diff] [blame] | 119 | /* |
| 120 | * Reset the counter (0x10) so that it starts from 0, one-shot |
| 121 | * mode makes this needed for timing to be right. |
| 122 | */ |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 123 | ctrl_reg |= CNT_CNTRL_RESET; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 124 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 125 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 129 | * ttc_clock_event_interrupt - Clock event timer interrupt handler |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 130 | * |
| 131 | * @irq: IRQ number of the Timer |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 132 | * @dev_id: void pointer to the ttc_timer instance |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 133 | * |
| 134 | * returns: Always IRQ_HANDLED - success |
| 135 | **/ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 136 | static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 137 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 138 | struct ttc_timer_clockevent *ttce = dev_id; |
| 139 | struct ttc_timer *timer = &ttce->ttc; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 140 | |
| 141 | /* Acknowledge the interrupt and call event handler */ |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 142 | readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 143 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 144 | ttce->ce.event_handler(&ttce->ce); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 145 | |
| 146 | return IRQ_HANDLED; |
| 147 | } |
| 148 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 149 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 150 | * __ttc_clocksource_read - Reads the timer counter register |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 151 | * |
| 152 | * returns: Current timer counter register value |
| 153 | **/ |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 154 | static u64 __ttc_clocksource_read(struct clocksource *cs) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 155 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 156 | struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 157 | |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 158 | return (u64)readl_relaxed(timer->base_addr + |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 159 | TTC_COUNT_VAL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 160 | } |
| 161 | |
Stephen Boyd | dfded00 | 2013-11-20 00:47:32 +0100 | [diff] [blame] | 162 | static u64 notrace ttc_sched_clock_read(void) |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 163 | { |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 164 | return readl_relaxed(ttc_sched_clock_val_reg); |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 165 | } |
| 166 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 167 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 168 | * ttc_set_next_event - Sets the time interval for next event |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 169 | * |
| 170 | * @cycles: Timer interval ticks |
| 171 | * @evt: Address of clock event instance |
| 172 | * |
| 173 | * returns: Always 0 - success |
| 174 | **/ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 175 | static int ttc_set_next_event(unsigned long cycles, |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 176 | struct clock_event_device *evt) |
| 177 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 178 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
| 179 | struct ttc_timer *timer = &ttce->ttc; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 180 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 181 | ttc_set_interval(timer, cycles); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 182 | return 0; |
| 183 | } |
| 184 | |
| 185 | /** |
Viresh Kumar | 5c0a4bb | 2015-06-18 16:24:16 +0530 | [diff] [blame] | 186 | * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 187 | * |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 188 | * @evt: Address of clock event instance |
| 189 | **/ |
Viresh Kumar | 5c0a4bb | 2015-06-18 16:24:16 +0530 | [diff] [blame] | 190 | static int ttc_shutdown(struct clock_event_device *evt) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 191 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 192 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
| 193 | struct ttc_timer *timer = &ttce->ttc; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 194 | u32 ctrl_reg; |
| 195 | |
Viresh Kumar | 5c0a4bb | 2015-06-18 16:24:16 +0530 | [diff] [blame] | 196 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
| 197 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; |
| 198 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static int ttc_set_periodic(struct clock_event_device *evt) |
| 203 | { |
| 204 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
| 205 | struct ttc_timer *timer = &ttce->ttc; |
| 206 | |
| 207 | ttc_set_interval(timer, |
| 208 | DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ)); |
| 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | static int ttc_resume(struct clock_event_device *evt) |
| 213 | { |
| 214 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
| 215 | struct ttc_timer *timer = &ttce->ttc; |
| 216 | u32 ctrl_reg; |
| 217 | |
| 218 | ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
| 219 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
| 220 | writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
| 221 | return 0; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 222 | } |
| 223 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 224 | static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 225 | unsigned long event, void *data) |
| 226 | { |
| 227 | struct clk_notifier_data *ndata = data; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 228 | struct ttc_timer *ttc = to_ttc_timer(nb); |
| 229 | struct ttc_timer_clocksource *ttccs = container_of(ttc, |
| 230 | struct ttc_timer_clocksource, ttc); |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 231 | |
| 232 | switch (event) { |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 233 | case PRE_RATE_CHANGE: |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 234 | { |
| 235 | u32 psv; |
| 236 | unsigned long factor, rate_low, rate_high; |
| 237 | |
| 238 | if (ndata->new_rate > ndata->old_rate) { |
| 239 | factor = DIV_ROUND_CLOSEST(ndata->new_rate, |
| 240 | ndata->old_rate); |
| 241 | rate_low = ndata->old_rate; |
| 242 | rate_high = ndata->new_rate; |
| 243 | } else { |
| 244 | factor = DIV_ROUND_CLOSEST(ndata->old_rate, |
| 245 | ndata->new_rate); |
| 246 | rate_low = ndata->new_rate; |
| 247 | rate_high = ndata->old_rate; |
| 248 | } |
| 249 | |
| 250 | if (!is_power_of_2(factor)) |
| 251 | return NOTIFY_BAD; |
| 252 | |
| 253 | if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR) |
| 254 | return NOTIFY_BAD; |
| 255 | |
| 256 | factor = __ilog2_u32(factor); |
| 257 | |
| 258 | /* |
| 259 | * store timer clock ctrl register so we can restore it in case |
| 260 | * of an abort. |
| 261 | */ |
| 262 | ttccs->scale_clk_ctrl_reg_old = |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 263 | readl_relaxed(ttccs->ttc.base_addr + |
| 264 | TTC_CLK_CNTRL_OFFSET); |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 265 | |
| 266 | psv = (ttccs->scale_clk_ctrl_reg_old & |
| 267 | TTC_CLK_CNTRL_PSV_MASK) >> |
| 268 | TTC_CLK_CNTRL_PSV_SHIFT; |
| 269 | if (ndata->new_rate < ndata->old_rate) |
| 270 | psv -= factor; |
| 271 | else |
| 272 | psv += factor; |
| 273 | |
| 274 | /* prescaler within legal range? */ |
| 275 | if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT)) |
| 276 | return NOTIFY_BAD; |
| 277 | |
| 278 | ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old & |
| 279 | ~TTC_CLK_CNTRL_PSV_MASK; |
| 280 | ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT; |
| 281 | |
| 282 | |
| 283 | /* scale down: adjust divider in post-change notification */ |
| 284 | if (ndata->new_rate < ndata->old_rate) |
| 285 | return NOTIFY_DONE; |
| 286 | |
| 287 | /* scale up: adjust divider now - before frequency change */ |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 288 | writel_relaxed(ttccs->scale_clk_ctrl_reg_new, |
| 289 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 290 | break; |
| 291 | } |
| 292 | case POST_RATE_CHANGE: |
| 293 | /* scale up: pre-change notification did the adjustment */ |
| 294 | if (ndata->new_rate > ndata->old_rate) |
| 295 | return NOTIFY_OK; |
| 296 | |
| 297 | /* scale down: adjust divider now - after frequency change */ |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 298 | writel_relaxed(ttccs->scale_clk_ctrl_reg_new, |
| 299 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 300 | break; |
| 301 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 302 | case ABORT_RATE_CHANGE: |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 303 | /* we have to undo the adjustment in case we scale up */ |
| 304 | if (ndata->new_rate < ndata->old_rate) |
| 305 | return NOTIFY_OK; |
| 306 | |
| 307 | /* restore original register value */ |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 308 | writel_relaxed(ttccs->scale_clk_ctrl_reg_old, |
| 309 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 310 | /* fall through */ |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 311 | default: |
| 312 | return NOTIFY_DONE; |
| 313 | } |
Soren Brinkmann | b3e9072 | 2014-02-19 15:14:42 -0800 | [diff] [blame] | 314 | |
| 315 | return NOTIFY_DONE; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 316 | } |
| 317 | |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 318 | static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base, |
Michal Simek | 4e2bec0 | 2014-09-29 01:50:05 +0200 | [diff] [blame] | 319 | u32 timer_width) |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 320 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 321 | struct ttc_timer_clocksource *ttccs; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 322 | int err; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 323 | |
| 324 | ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 325 | if (!ttccs) |
| 326 | return -ENOMEM; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 327 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 328 | ttccs->ttc.clk = clk; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 329 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 330 | err = clk_prepare_enable(ttccs->ttc.clk); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 331 | if (err) { |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 332 | kfree(ttccs); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 333 | return err; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 334 | } |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 335 | |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 336 | ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk); |
| 337 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 338 | ttccs->ttc.clk_rate_change_nb.notifier_call = |
| 339 | ttc_rate_change_clocksource_cb; |
| 340 | ttccs->ttc.clk_rate_change_nb.next = NULL; |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 341 | |
| 342 | err = clk_notifier_register(ttccs->ttc.clk, |
| 343 | &ttccs->ttc.clk_rate_change_nb); |
| 344 | if (err) |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 345 | pr_warn("Unable to register clock notifier.\n"); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 346 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 347 | ttccs->ttc.base_addr = base; |
| 348 | ttccs->cs.name = "ttc_clocksource"; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 349 | ttccs->cs.rating = 200; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 350 | ttccs->cs.read = __ttc_clocksource_read; |
Michal Simek | 4e2bec0 | 2014-09-29 01:50:05 +0200 | [diff] [blame] | 351 | ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 352 | ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
| 353 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 354 | /* |
| 355 | * Setup the clock source counter to be an incrementing counter |
| 356 | * with no interrupt and it rolls over at 0xFFFF. Pre-scale |
| 357 | * it by 32 also. Let it start running now. |
| 358 | */ |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 359 | writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); |
| 360 | writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 361 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 362 | writel_relaxed(CNT_CNTRL_RESET, |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 363 | ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 364 | |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 365 | err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 366 | if (err) { |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 367 | kfree(ttccs); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 368 | return err; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 369 | } |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 370 | |
| 371 | ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; |
Michal Simek | 4e2bec0 | 2014-09-29 01:50:05 +0200 | [diff] [blame] | 372 | sched_clock_register(ttc_sched_clock_read, timer_width, |
| 373 | ttccs->ttc.freq / PRESCALE); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 374 | |
| 375 | return 0; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 376 | } |
| 377 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 378 | static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 379 | unsigned long event, void *data) |
| 380 | { |
| 381 | struct clk_notifier_data *ndata = data; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 382 | struct ttc_timer *ttc = to_ttc_timer(nb); |
| 383 | struct ttc_timer_clockevent *ttcce = container_of(ttc, |
| 384 | struct ttc_timer_clockevent, ttc); |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 385 | |
| 386 | switch (event) { |
| 387 | case POST_RATE_CHANGE: |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 388 | /* update cached frequency */ |
| 389 | ttc->freq = ndata->new_rate; |
| 390 | |
Soren Brinkmann | 5f0ba3b | 2014-02-19 15:14:41 -0800 | [diff] [blame] | 391 | clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE); |
| 392 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 393 | /* fall through */ |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 394 | case PRE_RATE_CHANGE: |
| 395 | case ABORT_RATE_CHANGE: |
| 396 | default: |
| 397 | return NOTIFY_DONE; |
| 398 | } |
| 399 | } |
| 400 | |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 401 | static int __init ttc_setup_clockevent(struct clk *clk, |
| 402 | void __iomem *base, u32 irq) |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 403 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 404 | struct ttc_timer_clockevent *ttcce; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 405 | int err; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 406 | |
| 407 | ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 408 | if (!ttcce) |
| 409 | return -ENOMEM; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 410 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 411 | ttcce->ttc.clk = clk; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 412 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 413 | err = clk_prepare_enable(ttcce->ttc.clk); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 414 | if (err) { |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 415 | kfree(ttcce); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 416 | return err; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 417 | } |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 418 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 419 | ttcce->ttc.clk_rate_change_nb.notifier_call = |
| 420 | ttc_rate_change_clockevent_cb; |
| 421 | ttcce->ttc.clk_rate_change_nb.next = NULL; |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 422 | |
| 423 | err = clk_notifier_register(ttcce->ttc.clk, |
| 424 | &ttcce->ttc.clk_rate_change_nb); |
| 425 | if (err) { |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 426 | pr_warn("Unable to register clock notifier.\n"); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 427 | return err; |
| 428 | } |
| 429 | |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 430 | ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 431 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 432 | ttcce->ttc.base_addr = base; |
| 433 | ttcce->ce.name = "ttc_clockevent"; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 434 | ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 435 | ttcce->ce.set_next_event = ttc_set_next_event; |
Viresh Kumar | 5c0a4bb | 2015-06-18 16:24:16 +0530 | [diff] [blame] | 436 | ttcce->ce.set_state_shutdown = ttc_shutdown; |
| 437 | ttcce->ce.set_state_periodic = ttc_set_periodic; |
| 438 | ttcce->ce.set_state_oneshot = ttc_shutdown; |
| 439 | ttcce->ce.tick_resume = ttc_resume; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 440 | ttcce->ce.rating = 200; |
| 441 | ttcce->ce.irq = irq; |
Soren Brinkmann | 87e4ee7 | 2012-12-19 10:18:42 -0800 | [diff] [blame] | 442 | ttcce->ce.cpumask = cpu_possible_mask; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 443 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 444 | /* |
| 445 | * Setup the clock event timer to be an interval timer which |
| 446 | * is prescaled by 32 using the interval interrupt. Leave it |
| 447 | * disabled for now. |
| 448 | */ |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 449 | writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
| 450 | writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 451 | ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 452 | writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 453 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 454 | err = request_irq(irq, ttc_clock_event_interrupt, |
Michael Opdenacker | 38c30a8 | 2013-12-09 10:12:10 +0100 | [diff] [blame] | 455 | IRQF_TIMER, ttcce->ce.name, ttcce); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 456 | if (err) { |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 457 | kfree(ttcce); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 458 | return err; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 459 | } |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 460 | |
| 461 | clockevents_config_and_register(&ttcce->ce, |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 462 | ttcce->ttc.freq / PRESCALE, 1, 0xfffe); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 463 | |
| 464 | return 0; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 465 | } |
| 466 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 467 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 468 | * ttc_timer_init - Initialize the timer |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 469 | * |
| 470 | * Initializes the timer hardware and register the clock source and clock event |
| 471 | * timers with Linux kernal timer framework |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 472 | */ |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 473 | static int __init ttc_timer_init(struct device_node *timer) |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 474 | { |
| 475 | unsigned int irq; |
| 476 | void __iomem *timer_baseaddr; |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 477 | struct clk *clk_cs, *clk_ce; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 478 | static int initialized; |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 479 | int clksel, ret; |
Michal Simek | 4e2bec0 | 2014-09-29 01:50:05 +0200 | [diff] [blame] | 480 | u32 timer_width = 16; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 481 | |
| 482 | if (initialized) |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 483 | return 0; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 484 | |
| 485 | initialized = 1; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 486 | |
| 487 | /* |
| 488 | * Get the 1st Triple Timer Counter (TTC) block from the device tree |
| 489 | * and use it. Note that the event timer uses the interrupt and it's the |
| 490 | * 2nd TTC hence the irq_of_parse_and_map(,1) |
| 491 | */ |
| 492 | timer_baseaddr = of_iomap(timer, 0); |
| 493 | if (!timer_baseaddr) { |
| 494 | pr_err("ERROR: invalid timer base address\n"); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 495 | return -ENXIO; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 496 | } |
| 497 | |
| 498 | irq = irq_of_parse_and_map(timer, 1); |
| 499 | if (irq <= 0) { |
| 500 | pr_err("ERROR: invalid interrupt number\n"); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 501 | return -EINVAL; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 502 | } |
| 503 | |
Michal Simek | 4e2bec0 | 2014-09-29 01:50:05 +0200 | [diff] [blame] | 504 | of_property_read_u32(timer, "timer-width", &timer_width); |
| 505 | |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 506 | clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 507 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); |
| 508 | clk_cs = of_clk_get(timer, clksel); |
| 509 | if (IS_ERR(clk_cs)) { |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 510 | pr_err("ERROR: timer input clock not found\n"); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 511 | return PTR_ERR(clk_cs); |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 512 | } |
| 513 | |
Michal Simek | 87ab436 | 2014-04-11 15:39:29 +0200 | [diff] [blame] | 514 | clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 515 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); |
| 516 | clk_ce = of_clk_get(timer, clksel); |
| 517 | if (IS_ERR(clk_ce)) { |
| 518 | pr_err("ERROR: timer input clock not found\n"); |
Christophe Jaillet | 34c720a | 2016-07-06 07:35:23 +0200 | [diff] [blame] | 519 | return PTR_ERR(clk_ce); |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 520 | } |
| 521 | |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 522 | ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width); |
| 523 | if (ret) |
| 524 | return ret; |
| 525 | |
| 526 | ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); |
| 527 | if (ret) |
| 528 | return ret; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 529 | |
Rob Herring | 2a4849d | 2018-08-27 20:52:14 -0500 | [diff] [blame] | 530 | pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq); |
Daniel Lezcano | 70504f3 | 2016-05-31 19:52:09 +0200 | [diff] [blame] | 531 | |
| 532 | return 0; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 533 | } |
| 534 | |
Daniel Lezcano | 1727339 | 2017-05-26 16:56:11 +0200 | [diff] [blame] | 535 | TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |