Thomas Gleixner | fcaf203 | 2019-05-27 08:55:08 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Martin Kaiser | 1d54494 | 2017-07-23 19:49:06 +0200 | [diff] [blame] | 2 | /* |
| 3 | * RNG driver for Freescale RNGC |
| 4 | * |
| 5 | * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. |
| 6 | * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx> |
Martin Kaiser | 1d54494 | 2017-07-23 19:49:06 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <linux/module.h> |
Randy Dunlap | ac31672 | 2018-06-19 22:47:28 -0700 | [diff] [blame] | 10 | #include <linux/mod_devicetable.h> |
Martin Kaiser | 1d54494 | 2017-07-23 19:49:06 +0200 | [diff] [blame] | 11 | #include <linux/init.h> |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/clk.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/hw_random.h> |
| 18 | #include <linux/completion.h> |
| 19 | #include <linux/io.h> |
| 20 | |
| 21 | #define RNGC_COMMAND 0x0004 |
| 22 | #define RNGC_CONTROL 0x0008 |
| 23 | #define RNGC_STATUS 0x000C |
| 24 | #define RNGC_ERROR 0x0010 |
| 25 | #define RNGC_FIFO 0x0014 |
| 26 | |
| 27 | #define RNGC_CMD_CLR_ERR 0x00000020 |
| 28 | #define RNGC_CMD_CLR_INT 0x00000010 |
| 29 | #define RNGC_CMD_SEED 0x00000002 |
| 30 | #define RNGC_CMD_SELF_TEST 0x00000001 |
| 31 | |
| 32 | #define RNGC_CTRL_MASK_ERROR 0x00000040 |
| 33 | #define RNGC_CTRL_MASK_DONE 0x00000020 |
| 34 | |
| 35 | #define RNGC_STATUS_ERROR 0x00010000 |
| 36 | #define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00 |
| 37 | #define RNGC_STATUS_FIFO_LEVEL_SHIFT 8 |
| 38 | #define RNGC_STATUS_SEED_DONE 0x00000020 |
| 39 | #define RNGC_STATUS_ST_DONE 0x00000010 |
| 40 | |
| 41 | #define RNGC_ERROR_STATUS_STAT_ERR 0x00000008 |
| 42 | |
| 43 | #define RNGC_TIMEOUT 3000 /* 3 sec */ |
| 44 | |
| 45 | |
| 46 | static bool self_test = true; |
| 47 | module_param(self_test, bool, 0); |
| 48 | |
| 49 | struct imx_rngc { |
| 50 | struct device *dev; |
| 51 | struct clk *clk; |
| 52 | void __iomem *base; |
| 53 | struct hwrng rng; |
| 54 | struct completion rng_op_done; |
| 55 | /* |
| 56 | * err_reg is written only by the irq handler and read only |
| 57 | * when interrupts are masked, we need no spinlock |
| 58 | */ |
| 59 | u32 err_reg; |
| 60 | }; |
| 61 | |
| 62 | |
| 63 | static inline void imx_rngc_irq_mask_clear(struct imx_rngc *rngc) |
| 64 | { |
| 65 | u32 ctrl, cmd; |
| 66 | |
| 67 | /* mask interrupts */ |
| 68 | ctrl = readl(rngc->base + RNGC_CONTROL); |
| 69 | ctrl |= RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR; |
| 70 | writel(ctrl, rngc->base + RNGC_CONTROL); |
| 71 | |
| 72 | /* |
| 73 | * CLR_INT clears the interrupt only if there's no error |
| 74 | * CLR_ERR clear the interrupt and the error register if there |
| 75 | * is an error |
| 76 | */ |
| 77 | cmd = readl(rngc->base + RNGC_COMMAND); |
| 78 | cmd |= RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR; |
| 79 | writel(cmd, rngc->base + RNGC_COMMAND); |
| 80 | } |
| 81 | |
| 82 | static inline void imx_rngc_irq_unmask(struct imx_rngc *rngc) |
| 83 | { |
| 84 | u32 ctrl; |
| 85 | |
| 86 | ctrl = readl(rngc->base + RNGC_CONTROL); |
| 87 | ctrl &= ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR); |
| 88 | writel(ctrl, rngc->base + RNGC_CONTROL); |
| 89 | } |
| 90 | |
| 91 | static int imx_rngc_self_test(struct imx_rngc *rngc) |
| 92 | { |
| 93 | u32 cmd; |
| 94 | int ret; |
| 95 | |
| 96 | imx_rngc_irq_unmask(rngc); |
| 97 | |
| 98 | /* run self test */ |
| 99 | cmd = readl(rngc->base + RNGC_COMMAND); |
| 100 | writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND); |
| 101 | |
| 102 | ret = wait_for_completion_timeout(&rngc->rng_op_done, RNGC_TIMEOUT); |
| 103 | if (!ret) { |
| 104 | imx_rngc_irq_mask_clear(rngc); |
| 105 | return -ETIMEDOUT; |
| 106 | } |
| 107 | |
| 108 | if (rngc->err_reg != 0) |
| 109 | return -EIO; |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | static int imx_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait) |
| 115 | { |
| 116 | struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng); |
| 117 | unsigned int status; |
| 118 | unsigned int level; |
| 119 | int retval = 0; |
| 120 | |
| 121 | while (max >= sizeof(u32)) { |
| 122 | status = readl(rngc->base + RNGC_STATUS); |
| 123 | |
| 124 | /* is there some error while reading this random number? */ |
| 125 | if (status & RNGC_STATUS_ERROR) |
| 126 | break; |
| 127 | |
| 128 | /* how many random numbers are in FIFO? [0-16] */ |
| 129 | level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >> |
| 130 | RNGC_STATUS_FIFO_LEVEL_SHIFT; |
| 131 | |
| 132 | if (level) { |
| 133 | /* retrieve a random number from FIFO */ |
| 134 | *(u32 *)data = readl(rngc->base + RNGC_FIFO); |
| 135 | |
| 136 | retval += sizeof(u32); |
| 137 | data += sizeof(u32); |
| 138 | max -= sizeof(u32); |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | return retval ? retval : -EIO; |
| 143 | } |
| 144 | |
| 145 | static irqreturn_t imx_rngc_irq(int irq, void *priv) |
| 146 | { |
| 147 | struct imx_rngc *rngc = (struct imx_rngc *)priv; |
| 148 | u32 status; |
| 149 | |
| 150 | /* |
| 151 | * clearing the interrupt will also clear the error register |
| 152 | * read error and status before clearing |
| 153 | */ |
| 154 | status = readl(rngc->base + RNGC_STATUS); |
| 155 | rngc->err_reg = readl(rngc->base + RNGC_ERROR); |
| 156 | |
| 157 | imx_rngc_irq_mask_clear(rngc); |
| 158 | |
| 159 | if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE)) |
| 160 | complete(&rngc->rng_op_done); |
| 161 | |
| 162 | return IRQ_HANDLED; |
| 163 | } |
| 164 | |
| 165 | static int imx_rngc_init(struct hwrng *rng) |
| 166 | { |
| 167 | struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng); |
| 168 | u32 cmd; |
| 169 | int ret; |
| 170 | |
| 171 | /* clear error */ |
| 172 | cmd = readl(rngc->base + RNGC_COMMAND); |
| 173 | writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND); |
| 174 | |
| 175 | /* create seed, repeat while there is some statistical error */ |
| 176 | do { |
| 177 | imx_rngc_irq_unmask(rngc); |
| 178 | |
| 179 | /* seed creation */ |
| 180 | cmd = readl(rngc->base + RNGC_COMMAND); |
| 181 | writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND); |
| 182 | |
| 183 | ret = wait_for_completion_timeout(&rngc->rng_op_done, |
| 184 | RNGC_TIMEOUT); |
| 185 | |
| 186 | if (!ret) { |
| 187 | imx_rngc_irq_mask_clear(rngc); |
| 188 | return -ETIMEDOUT; |
| 189 | } |
| 190 | |
| 191 | } while (rngc->err_reg == RNGC_ERROR_STATUS_STAT_ERR); |
| 192 | |
| 193 | return rngc->err_reg ? -EIO : 0; |
| 194 | } |
| 195 | |
| 196 | static int imx_rngc_probe(struct platform_device *pdev) |
| 197 | { |
| 198 | struct imx_rngc *rngc; |
| 199 | struct resource *res; |
| 200 | int ret; |
| 201 | int irq; |
| 202 | |
| 203 | rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL); |
| 204 | if (!rngc) |
| 205 | return -ENOMEM; |
| 206 | |
| 207 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 208 | rngc->base = devm_ioremap_resource(&pdev->dev, res); |
| 209 | if (IS_ERR(rngc->base)) |
| 210 | return PTR_ERR(rngc->base); |
| 211 | |
| 212 | rngc->clk = devm_clk_get(&pdev->dev, NULL); |
| 213 | if (IS_ERR(rngc->clk)) { |
| 214 | dev_err(&pdev->dev, "Can not get rng_clk\n"); |
| 215 | return PTR_ERR(rngc->clk); |
| 216 | } |
| 217 | |
| 218 | irq = platform_get_irq(pdev, 0); |
| 219 | if (irq <= 0) { |
| 220 | dev_err(&pdev->dev, "Couldn't get irq %d\n", irq); |
| 221 | return irq; |
| 222 | } |
| 223 | |
| 224 | ret = clk_prepare_enable(rngc->clk); |
| 225 | if (ret) |
| 226 | return ret; |
| 227 | |
| 228 | ret = devm_request_irq(&pdev->dev, |
| 229 | irq, imx_rngc_irq, 0, pdev->name, (void *)rngc); |
| 230 | if (ret) { |
| 231 | dev_err(rngc->dev, "Can't get interrupt working.\n"); |
| 232 | goto err; |
| 233 | } |
| 234 | |
| 235 | init_completion(&rngc->rng_op_done); |
| 236 | |
| 237 | rngc->rng.name = pdev->name; |
| 238 | rngc->rng.init = imx_rngc_init; |
| 239 | rngc->rng.read = imx_rngc_read; |
| 240 | |
| 241 | rngc->dev = &pdev->dev; |
| 242 | platform_set_drvdata(pdev, rngc); |
| 243 | |
| 244 | imx_rngc_irq_mask_clear(rngc); |
| 245 | |
| 246 | if (self_test) { |
| 247 | ret = imx_rngc_self_test(rngc); |
| 248 | if (ret) { |
| 249 | dev_err(rngc->dev, "FSL RNGC self test failed.\n"); |
| 250 | goto err; |
| 251 | } |
| 252 | } |
| 253 | |
| 254 | ret = hwrng_register(&rngc->rng); |
| 255 | if (ret) { |
| 256 | dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", ret); |
| 257 | goto err; |
| 258 | } |
| 259 | |
| 260 | dev_info(&pdev->dev, "Freescale RNGC registered.\n"); |
| 261 | return 0; |
| 262 | |
| 263 | err: |
| 264 | clk_disable_unprepare(rngc->clk); |
| 265 | |
| 266 | return ret; |
| 267 | } |
| 268 | |
| 269 | static int __exit imx_rngc_remove(struct platform_device *pdev) |
| 270 | { |
| 271 | struct imx_rngc *rngc = platform_get_drvdata(pdev); |
| 272 | |
| 273 | hwrng_unregister(&rngc->rng); |
| 274 | |
| 275 | clk_disable_unprepare(rngc->clk); |
| 276 | |
| 277 | return 0; |
| 278 | } |
| 279 | |
Martin Kaiser | cd0bb67 | 2018-01-11 22:06:39 +0100 | [diff] [blame] | 280 | static int __maybe_unused imx_rngc_suspend(struct device *dev) |
Martin Kaiser | 1d54494 | 2017-07-23 19:49:06 +0200 | [diff] [blame] | 281 | { |
| 282 | struct imx_rngc *rngc = dev_get_drvdata(dev); |
| 283 | |
| 284 | clk_disable_unprepare(rngc->clk); |
| 285 | |
| 286 | return 0; |
| 287 | } |
| 288 | |
Martin Kaiser | cd0bb67 | 2018-01-11 22:06:39 +0100 | [diff] [blame] | 289 | static int __maybe_unused imx_rngc_resume(struct device *dev) |
Martin Kaiser | 1d54494 | 2017-07-23 19:49:06 +0200 | [diff] [blame] | 290 | { |
| 291 | struct imx_rngc *rngc = dev_get_drvdata(dev); |
| 292 | |
| 293 | clk_prepare_enable(rngc->clk); |
| 294 | |
| 295 | return 0; |
| 296 | } |
| 297 | |
weiyongjun \(A\) | 40b776a | 2018-01-23 02:08:56 +0000 | [diff] [blame] | 298 | static SIMPLE_DEV_PM_OPS(imx_rngc_pm_ops, imx_rngc_suspend, imx_rngc_resume); |
Martin Kaiser | 1d54494 | 2017-07-23 19:49:06 +0200 | [diff] [blame] | 299 | |
| 300 | static const struct of_device_id imx_rngc_dt_ids[] = { |
| 301 | { .compatible = "fsl,imx25-rngb", .data = NULL, }, |
| 302 | { /* sentinel */ } |
| 303 | }; |
| 304 | MODULE_DEVICE_TABLE(of, imx_rngc_dt_ids); |
| 305 | |
| 306 | static struct platform_driver imx_rngc_driver = { |
| 307 | .driver = { |
| 308 | .name = "imx_rngc", |
Martin Kaiser | 1d54494 | 2017-07-23 19:49:06 +0200 | [diff] [blame] | 309 | .pm = &imx_rngc_pm_ops, |
Martin Kaiser | 1d54494 | 2017-07-23 19:49:06 +0200 | [diff] [blame] | 310 | .of_match_table = imx_rngc_dt_ids, |
| 311 | }, |
| 312 | .remove = __exit_p(imx_rngc_remove), |
| 313 | }; |
| 314 | |
| 315 | module_platform_driver_probe(imx_rngc_driver, imx_rngc_probe); |
| 316 | |
| 317 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); |
| 318 | MODULE_DESCRIPTION("H/W RNGC driver for i.MX"); |
| 319 | MODULE_LICENSE("GPL"); |