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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
David Gibsonf7f6f4f2005-10-19 14:53:32 +10003 * arch/powerpc/kernel/pmc.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * Copyright (C) 2004 David Gibson, IBM Corporation.
David Gibsonf7f6f4f2005-10-19 14:53:32 +10006 * Includes code formerly from arch/ppc/kernel/perfmon.c:
7 * Author: Andy Fleming
8 * Copyright (c) 2004 Freescale Semiconductor, Inc
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 */
10
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/errno.h>
Paul Gortmaker50af5ea2012-01-20 18:35:53 -050012#include <linux/bug.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/spinlock.h>
Paul Gortmaker4b16f8e2011-07-22 18:24:23 -040014#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
16#include <asm/processor.h>
Olof Johansson6529c132007-01-28 21:25:57 -060017#include <asm/cputable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <asm/pmc.h>
19
Anton Blanchard177e9ea2007-05-20 03:13:43 +100020#ifndef MMCR0_PMAO
21#define MMCR0_PMAO 0
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060022#endif
23
24static void dummy_perf(struct pt_regs *regs)
25{
Andy Fleming39aef682008-02-04 18:27:55 -060026#if defined(CONFIG_FSL_EMB_PERFMON)
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060027 mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
Christophe Leroyd7cceda2018-11-17 10:24:56 +000028#elif defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
Olof Johansson6529c132007-01-28 21:25:57 -060029 if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
Anton Blanchard177e9ea2007-05-20 03:13:43 +100030 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMAO));
David Gibsonf7f6f4f2005-10-19 14:53:32 +100031#else
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060032 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE);
David Gibsonf7f6f4f2005-10-19 14:53:32 +100033#endif
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060034}
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Thomas Gleixner071c06c2010-02-18 02:22:27 +000037static DEFINE_RAW_SPINLOCK(pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070038static void *pmc_owner_caller; /* mostly for debugging */
39perf_irq_t perf_irq = dummy_perf;
40
41int reserve_pmc_hardware(perf_irq_t new_perf_irq)
42{
43 int err = 0;
44
Thomas Gleixner071c06c2010-02-18 02:22:27 +000045 raw_spin_lock(&pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
47 if (pmc_owner_caller) {
48 printk(KERN_WARNING "reserve_pmc_hardware: "
49 "PMC hardware busy (reserved by caller %p)\n",
50 pmc_owner_caller);
51 err = -EBUSY;
52 goto out;
53 }
54
55 pmc_owner_caller = __builtin_return_address(0);
Andy Flemingdd6c89f2006-10-27 15:06:32 -050056 perf_irq = new_perf_irq ? new_perf_irq : dummy_perf;
Linus Torvalds1da177e2005-04-16 15:20:36 -070057
58 out:
Thomas Gleixner071c06c2010-02-18 02:22:27 +000059 raw_spin_unlock(&pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070060 return err;
61}
62EXPORT_SYMBOL_GPL(reserve_pmc_hardware);
63
64void release_pmc_hardware(void)
65{
Thomas Gleixner071c06c2010-02-18 02:22:27 +000066 raw_spin_lock(&pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
68 WARN_ON(! pmc_owner_caller);
69
70 pmc_owner_caller = NULL;
71 perf_irq = dummy_perf;
72
Thomas Gleixner071c06c2010-02-18 02:22:27 +000073 raw_spin_unlock(&pmc_owner_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070074}
75EXPORT_SYMBOL_GPL(release_pmc_hardware);
Michael Ellerman180a3362005-08-09 11:13:36 +100076
David Gibsonf7f6f4f2005-10-19 14:53:32 +100077#ifdef CONFIG_PPC64
Michael Ellerman180a3362005-08-09 11:13:36 +100078void power4_enable_pmcs(void)
79{
80 unsigned long hid0;
81
Paul Mackerrasb5bbeb22005-10-10 14:01:07 +100082 hid0 = mfspr(SPRN_HID0);
Michael Ellerman180a3362005-08-09 11:13:36 +100083 hid0 |= 1UL << (63 - 20);
84
85 /* POWER4 requires the following sequence */
86 asm volatile(
87 "sync\n"
88 "mtspr %1, %0\n"
89 "mfspr %0, %1\n"
90 "mfspr %0, %1\n"
91 "mfspr %0, %1\n"
92 "mfspr %0, %1\n"
93 "mfspr %0, %1\n"
94 "mfspr %0, %1\n"
Paul Mackerrasb5bbeb22005-10-10 14:01:07 +100095 "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0):
Michael Ellerman180a3362005-08-09 11:13:36 +100096 "memory");
97}
David Gibsonf7f6f4f2005-10-19 14:53:32 +100098#endif /* CONFIG_PPC64 */