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Thomas Gleixner1a59d1b82019-05-27 08:55:05 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +05302/*
3 * Machine check exception handling CPU-side for power7 and power8
4 *
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +05305 * Copyright 2013 IBM Corporation
6 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
7 */
8
9#undef DEBUG
10#define pr_fmt(fmt) "mce_power: " fmt
11
12#include <linux/types.h>
13#include <linux/ptrace.h>
14#include <asm/mmu.h>
15#include <asm/mce.h>
Mahesh Salgaonkar55672ec2013-12-16 10:46:24 +053016#include <asm/machdep.h>
Balbir Singhba41e1e2017-09-29 14:26:53 +100017#include <asm/pgtable.h>
18#include <asm/pte-walk.h>
19#include <asm/sstep.h>
20#include <asm/exception-64s.h>
21
22/*
23 * Convert an address related to an mm to a PFN. NOTE: we are in real
24 * mode, we could potentially race with page table updates.
25 */
Ganesh Goudar7f177f92019-04-15 15:35:44 +053026unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr)
Balbir Singhba41e1e2017-09-29 14:26:53 +100027{
28 pte_t *ptep;
29 unsigned long flags;
30 struct mm_struct *mm;
31
32 if (user_mode(regs))
33 mm = current->mm;
34 else
35 mm = &init_mm;
36
37 local_irq_save(flags);
38 if (mm == current->mm)
39 ptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);
40 else
41 ptep = find_init_mm_pte(addr, NULL);
42 local_irq_restore(flags);
43 if (!ptep || pte_special(*ptep))
44 return ULONG_MAX;
45 return pte_pfn(*ptep);
46}
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +053047
48/* flush SLBs and reload */
Michael Ellerman4e003742017-10-19 15:08:43 +110049#ifdef CONFIG_PPC_BOOK3S_64
Mahesh Salgaonkara43c1592018-09-11 19:57:00 +053050void flush_and_reload_slb(void)
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +053051{
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +053052 /* Invalidate all SLBs */
Nicholas Piggine7e81842018-08-10 16:42:48 +100053 slb_flush_all_realmode();
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +053054
55#ifdef CONFIG_KVM_BOOK3S_HANDLER
56 /*
57 * If machine check is hit when in guest or in transition, we will
58 * only flush the SLBs and continue.
59 */
60 if (get_paca()->kvm_hstate.in_guest)
61 return;
62#endif
Nicholas Piggine7e81842018-08-10 16:42:48 +100063 if (early_radix_enabled())
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +053064 return;
65
Nicholas Piggine7e81842018-08-10 16:42:48 +100066 /*
67 * This probably shouldn't happen, but it may be possible it's
68 * called in early boot before SLB shadows are allocated.
69 */
70 if (!get_slb_shadow())
71 return;
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +053072
Nicholas Piggine7e81842018-08-10 16:42:48 +100073 slb_restore_bolted_realmode();
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +053074}
Aneesh Kumar K.Vcaca2852016-04-29 23:26:07 +100075#endif
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +053076
Nicholas Piggin7b9f71f92017-02-28 12:00:48 +100077static void flush_erat(void)
78{
Nicholas Pigginbc276ec2018-08-27 13:03:01 +100079#ifdef CONFIG_PPC_BOOK3S_64
80 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) {
81 flush_and_reload_slb();
82 return;
83 }
84#endif
85 /* PPC_INVALIDATE_ERAT can only be used on ISA v3 and newer */
Nicholas Piggin7b9f71f92017-02-28 12:00:48 +100086 asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
87}
88
89#define MCE_FLUSH_SLB 1
90#define MCE_FLUSH_TLB 2
91#define MCE_FLUSH_ERAT 3
92
93static int mce_flush(int what)
94{
Michael Ellerman4e003742017-10-19 15:08:43 +110095#ifdef CONFIG_PPC_BOOK3S_64
Nicholas Piggin7b9f71f92017-02-28 12:00:48 +100096 if (what == MCE_FLUSH_SLB) {
97 flush_and_reload_slb();
98 return 1;
99 }
100#endif
101 if (what == MCE_FLUSH_ERAT) {
102 flush_erat();
103 return 1;
104 }
105 if (what == MCE_FLUSH_TLB) {
Nicholas Piggind4748272017-12-24 01:15:50 +1000106 tlbiel_all();
107 return 1;
Nicholas Piggin7b9f71f92017-02-28 12:00:48 +1000108 }
109
110 return 0;
111}
112
Nicholas Piggin755309b2017-03-14 22:36:47 +1000113#define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
Nicholas Piggin58c8d172017-03-14 22:36:45 +1000114
Nicholas Piggin631bc462017-03-14 22:36:46 +1000115struct mce_ierror_table {
116 unsigned long srr1_mask;
117 unsigned long srr1_value;
118 bool nip_valid; /* nip is a valid indicator of faulting address */
119 unsigned int error_type;
120 unsigned int error_subtype;
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530121 unsigned int error_class;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000122 unsigned int initiator;
123 unsigned int severity;
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530124 bool sync_error;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000125};
126
127static const struct mce_ierror_table mce_p7_ierror_table[] = {
128{ 0x00000000001c0000, 0x0000000000040000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530129 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530130 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000131{ 0x00000000001c0000, 0x0000000000080000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530132 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530133 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000134{ 0x00000000001c0000, 0x00000000000c0000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530135 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530136 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000137{ 0x00000000001c0000, 0x0000000000100000, true,
138 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530139 MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530140 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000141{ 0x00000000001c0000, 0x0000000000140000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530142 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530143 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000144{ 0x00000000001c0000, 0x0000000000180000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530145 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530146 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000147{ 0x00000000001c0000, 0x00000000001c0000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530148 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530149 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
150{ 0, 0, 0, 0, 0, 0, 0 } };
Nicholas Piggin631bc462017-03-14 22:36:46 +1000151
152static const struct mce_ierror_table mce_p8_ierror_table[] = {
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000153{ 0x00000000081c0000, 0x0000000000040000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530154 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530155 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000156{ 0x00000000081c0000, 0x0000000000080000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530157 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530158 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000159{ 0x00000000081c0000, 0x00000000000c0000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530160 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530161 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000162{ 0x00000000081c0000, 0x0000000000100000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530163 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530164 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000165{ 0x00000000081c0000, 0x0000000000140000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530166 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530167 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000168{ 0x00000000081c0000, 0x0000000000180000, true,
Nicholas Piggin631bc462017-03-14 22:36:46 +1000169 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530170 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530171 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000172{ 0x00000000081c0000, 0x00000000001c0000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530173 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530174 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000175{ 0x00000000081c0000, 0x0000000008000000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530176 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530177 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000178{ 0x00000000081c0000, 0x0000000008040000, true,
179 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530180 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530181 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
182{ 0, 0, 0, 0, 0, 0, 0 } };
Nicholas Piggin631bc462017-03-14 22:36:46 +1000183
184static const struct mce_ierror_table mce_p9_ierror_table[] = {
185{ 0x00000000081c0000, 0x0000000000040000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530186 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530187 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000188{ 0x00000000081c0000, 0x0000000000080000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530189 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530190 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000191{ 0x00000000081c0000, 0x00000000000c0000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530192 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530193 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000194{ 0x00000000081c0000, 0x0000000000100000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530195 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530196 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000197{ 0x00000000081c0000, 0x0000000000140000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530198 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530199 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000200{ 0x00000000081c0000, 0x0000000000180000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530201 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530202 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin90df4bf2017-05-29 16:26:44 +1000203{ 0x00000000081c0000, 0x00000000001c0000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530204 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, MCE_ECLASS_SOFTWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530205 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000206{ 0x00000000081c0000, 0x0000000008000000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530207 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530208 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000209{ 0x00000000081c0000, 0x0000000008040000, true,
210 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530211 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530212 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000213{ 0x00000000081c0000, 0x00000000080c0000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530214 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, MCE_ECLASS_SOFTWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530215 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000216{ 0x00000000081c0000, 0x0000000008100000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530217 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_SOFTWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530218 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000219{ 0x00000000081c0000, 0x0000000008140000, false,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530220 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530221 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
Nicholas Piggin631bc462017-03-14 22:36:46 +1000222{ 0x00000000081c0000, 0x0000000008180000, false,
223 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530224 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530225{ 0x00000000081c0000, 0x00000000081c0000, true, MCE_ECLASS_HARDWARE,
Nicholas Piggin631bc462017-03-14 22:36:46 +1000226 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530227 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
228{ 0, 0, 0, 0, 0, 0, 0 } };
Nicholas Piggin631bc462017-03-14 22:36:46 +1000229
230struct mce_derror_table {
231 unsigned long dsisr_value;
232 bool dar_valid; /* dar is a valid indicator of faulting address */
233 unsigned int error_type;
234 unsigned int error_subtype;
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530235 unsigned int error_class;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000236 unsigned int initiator;
237 unsigned int severity;
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530238 bool sync_error;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000239};
240
241static const struct mce_derror_table mce_p7_derror_table[] = {
242{ 0x00008000, false,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530243 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530244 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000245{ 0x00004000, true,
246 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530247 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530248 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000249{ 0x00000800, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530250 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530251 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000252{ 0x00000400, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530253 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530254 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Michael Ellerman54dbcfc2018-06-13 23:24:14 +1000255{ 0x00000080, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530256 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530257 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000258{ 0x00000100, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530259 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530260 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000261{ 0x00000040, true,
262 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530263 MCE_ECLASS_HARD_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530264 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
265{ 0, false, 0, 0, 0, 0, 0 } };
Nicholas Piggin631bc462017-03-14 22:36:46 +1000266
267static const struct mce_derror_table mce_p8_derror_table[] = {
268{ 0x00008000, false,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530269 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530270 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000271{ 0x00004000, true,
272 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530273 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530274 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000275{ 0x00002000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530276 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530277 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Pigginc7e790c2017-03-14 22:36:48 +1000278{ 0x00001000, true,
279 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530280 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530281 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000282{ 0x00000800, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530283 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530284 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000285{ 0x00000400, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530286 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530287 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000288{ 0x00000200, true,
289 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530290 MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530291 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Michael Ellerman54dbcfc2018-06-13 23:24:14 +1000292{ 0x00000080, true,
293 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530294 MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530295 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000296{ 0x00000100, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530297 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530298 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
299{ 0, false, 0, 0, 0, 0, 0 } };
Nicholas Piggin631bc462017-03-14 22:36:46 +1000300
301static const struct mce_derror_table mce_p9_derror_table[] = {
302{ 0x00008000, false,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530303 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530304 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000305{ 0x00004000, true,
306 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530307 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530308 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000309{ 0x00002000, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530310 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530311 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000312{ 0x00001000, true,
313 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530314 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530315 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000316{ 0x00000800, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530317 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530318 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000319{ 0x00000400, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530320 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530321 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000322{ 0x00000200, false,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530323 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, MCE_ECLASS_SOFTWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530324 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Michael Ellerman54dbcfc2018-06-13 23:24:14 +1000325{ 0x00000080, true,
326 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530327 MCE_ECLASS_SOFT_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530328 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000329{ 0x00000100, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530330 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530331 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000332{ 0x00000040, true,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530333 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530334 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000335{ 0x00000020, false,
336 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530337 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530338 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000339{ 0x00000010, false,
340 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530341 MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530342 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
Nicholas Piggin631bc462017-03-14 22:36:46 +1000343{ 0x00000008, false,
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530344 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, MCE_ECLASS_HARDWARE,
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530345 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
346{ 0, false, 0, 0, 0, 0, 0 } };
Nicholas Piggin631bc462017-03-14 22:36:46 +1000347
Balbir Singhba41e1e2017-09-29 14:26:53 +1000348static int mce_find_instr_ea_and_pfn(struct pt_regs *regs, uint64_t *addr,
349 uint64_t *phys_addr)
350{
351 /*
352 * Carefully look at the NIP to determine
353 * the instruction to analyse. Reading the NIP
354 * in real-mode is tricky and can lead to recursive
355 * faults
356 */
357 int instr;
358 unsigned long pfn, instr_addr;
359 struct instruction_op op;
360 struct pt_regs tmp = *regs;
361
362 pfn = addr_to_pfn(regs, regs->nip);
363 if (pfn != ULONG_MAX) {
364 instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
365 instr = *(unsigned int *)(instr_addr);
366 if (!analyse_instr(&op, &tmp, instr)) {
367 pfn = addr_to_pfn(regs, op.ea);
368 *addr = op.ea;
369 *phys_addr = (pfn << PAGE_SHIFT);
370 return 0;
371 }
372 /*
373 * analyse_instr() might fail if the instruction
374 * is not a load/store, although this is unexpected
375 * for load/store errors or if we got the NIP
376 * wrong
377 */
378 }
379 *addr = 0;
380 return -1;
381}
382
Nicholas Piggin755309b2017-03-14 22:36:47 +1000383static int mce_handle_ierror(struct pt_regs *regs,
Nicholas Piggin631bc462017-03-14 22:36:46 +1000384 const struct mce_ierror_table table[],
Balbir Singh01eaac22017-09-29 14:26:54 +1000385 struct mce_error_info *mce_err, uint64_t *addr,
386 uint64_t *phys_addr)
Nicholas Piggin631bc462017-03-14 22:36:46 +1000387{
388 uint64_t srr1 = regs->msr;
Nicholas Piggin755309b2017-03-14 22:36:47 +1000389 int handled = 0;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000390 int i;
391
392 *addr = 0;
393
394 for (i = 0; table[i].srr1_mask; i++) {
395 if ((srr1 & table[i].srr1_mask) != table[i].srr1_value)
396 continue;
397
Nicholas Piggin755309b2017-03-14 22:36:47 +1000398 /* attempt to correct the error */
399 switch (table[i].error_type) {
400 case MCE_ERROR_TYPE_SLB:
401 handled = mce_flush(MCE_FLUSH_SLB);
402 break;
403 case MCE_ERROR_TYPE_ERAT:
404 handled = mce_flush(MCE_FLUSH_ERAT);
405 break;
406 case MCE_ERROR_TYPE_TLB:
407 handled = mce_flush(MCE_FLUSH_TLB);
408 break;
409 }
410
411 /* now fill in mce_error_info */
Nicholas Piggin631bc462017-03-14 22:36:46 +1000412 mce_err->error_type = table[i].error_type;
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530413 mce_err->error_class = table[i].error_class;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000414 switch (table[i].error_type) {
415 case MCE_ERROR_TYPE_UE:
416 mce_err->u.ue_error_type = table[i].error_subtype;
417 break;
418 case MCE_ERROR_TYPE_SLB:
419 mce_err->u.slb_error_type = table[i].error_subtype;
420 break;
421 case MCE_ERROR_TYPE_ERAT:
422 mce_err->u.erat_error_type = table[i].error_subtype;
423 break;
424 case MCE_ERROR_TYPE_TLB:
425 mce_err->u.tlb_error_type = table[i].error_subtype;
426 break;
427 case MCE_ERROR_TYPE_USER:
428 mce_err->u.user_error_type = table[i].error_subtype;
429 break;
430 case MCE_ERROR_TYPE_RA:
431 mce_err->u.ra_error_type = table[i].error_subtype;
432 break;
433 case MCE_ERROR_TYPE_LINK:
434 mce_err->u.link_error_type = table[i].error_subtype;
435 break;
436 }
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530437 mce_err->sync_error = table[i].sync_error;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000438 mce_err->severity = table[i].severity;
439 mce_err->initiator = table[i].initiator;
Balbir Singh01eaac22017-09-29 14:26:54 +1000440 if (table[i].nip_valid) {
Nicholas Piggin631bc462017-03-14 22:36:46 +1000441 *addr = regs->nip;
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530442 if (mce_err->sync_error &&
Balbir Singh01eaac22017-09-29 14:26:54 +1000443 table[i].error_type == MCE_ERROR_TYPE_UE) {
444 unsigned long pfn;
445
446 if (get_paca()->in_mce < MAX_MCE_DEPTH) {
447 pfn = addr_to_pfn(regs, regs->nip);
448 if (pfn != ULONG_MAX) {
449 *phys_addr =
450 (pfn << PAGE_SHIFT);
Balbir Singh01eaac22017-09-29 14:26:54 +1000451 }
452 }
453 }
454 }
Nicholas Piggin755309b2017-03-14 22:36:47 +1000455 return handled;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000456 }
457
458 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530459 mce_err->error_class = MCE_ECLASS_UNKNOWN;
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530460 mce_err->severity = MCE_SEV_SEVERE;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000461 mce_err->initiator = MCE_INITIATOR_CPU;
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530462 mce_err->sync_error = true;
Nicholas Piggin755309b2017-03-14 22:36:47 +1000463
464 return 0;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000465}
466
Nicholas Piggin755309b2017-03-14 22:36:47 +1000467static int mce_handle_derror(struct pt_regs *regs,
Nicholas Piggin631bc462017-03-14 22:36:46 +1000468 const struct mce_derror_table table[],
Balbir Singhba41e1e2017-09-29 14:26:53 +1000469 struct mce_error_info *mce_err, uint64_t *addr,
470 uint64_t *phys_addr)
Nicholas Piggin631bc462017-03-14 22:36:46 +1000471{
472 uint64_t dsisr = regs->dsisr;
Nicholas Piggin755309b2017-03-14 22:36:47 +1000473 int handled = 0;
474 int found = 0;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000475 int i;
476
477 *addr = 0;
478
479 for (i = 0; table[i].dsisr_value; i++) {
480 if (!(dsisr & table[i].dsisr_value))
481 continue;
482
Nicholas Piggin755309b2017-03-14 22:36:47 +1000483 /* attempt to correct the error */
484 switch (table[i].error_type) {
485 case MCE_ERROR_TYPE_SLB:
486 if (mce_flush(MCE_FLUSH_SLB))
487 handled = 1;
488 break;
489 case MCE_ERROR_TYPE_ERAT:
490 if (mce_flush(MCE_FLUSH_ERAT))
491 handled = 1;
492 break;
493 case MCE_ERROR_TYPE_TLB:
494 if (mce_flush(MCE_FLUSH_TLB))
495 handled = 1;
496 break;
497 }
498
499 /*
500 * Attempt to handle multiple conditions, but only return
501 * one. Ensure uncorrectable errors are first in the table
502 * to match.
503 */
504 if (found)
505 continue;
506
507 /* now fill in mce_error_info */
Nicholas Piggin631bc462017-03-14 22:36:46 +1000508 mce_err->error_type = table[i].error_type;
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530509 mce_err->error_class = table[i].error_class;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000510 switch (table[i].error_type) {
511 case MCE_ERROR_TYPE_UE:
512 mce_err->u.ue_error_type = table[i].error_subtype;
513 break;
514 case MCE_ERROR_TYPE_SLB:
515 mce_err->u.slb_error_type = table[i].error_subtype;
516 break;
517 case MCE_ERROR_TYPE_ERAT:
518 mce_err->u.erat_error_type = table[i].error_subtype;
519 break;
520 case MCE_ERROR_TYPE_TLB:
521 mce_err->u.tlb_error_type = table[i].error_subtype;
522 break;
523 case MCE_ERROR_TYPE_USER:
524 mce_err->u.user_error_type = table[i].error_subtype;
525 break;
526 case MCE_ERROR_TYPE_RA:
527 mce_err->u.ra_error_type = table[i].error_subtype;
528 break;
529 case MCE_ERROR_TYPE_LINK:
530 mce_err->u.link_error_type = table[i].error_subtype;
531 break;
532 }
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530533 mce_err->sync_error = table[i].sync_error;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000534 mce_err->severity = table[i].severity;
535 mce_err->initiator = table[i].initiator;
536 if (table[i].dar_valid)
537 *addr = regs->dar;
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530538 else if (mce_err->sync_error &&
Balbir Singhba41e1e2017-09-29 14:26:53 +1000539 table[i].error_type == MCE_ERROR_TYPE_UE) {
540 /*
541 * We do a maximum of 4 nested MCE calls, see
542 * kernel/exception-64s.h
543 */
544 if (get_paca()->in_mce < MAX_MCE_DEPTH)
Mahesh Salgaonkar75ecfb42018-04-23 10:29:27 +0530545 mce_find_instr_ea_and_pfn(regs, addr, phys_addr);
Balbir Singhba41e1e2017-09-29 14:26:53 +1000546 }
Nicholas Piggin755309b2017-03-14 22:36:47 +1000547 found = 1;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000548 }
549
Nicholas Piggin755309b2017-03-14 22:36:47 +1000550 if (found)
551 return handled;
552
Nicholas Piggin631bc462017-03-14 22:36:46 +1000553 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
Mahesh Salgaonkar50dbabe2019-04-29 23:46:02 +0530554 mce_err->error_class = MCE_ECLASS_UNKNOWN;
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530555 mce_err->severity = MCE_SEV_SEVERE;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000556 mce_err->initiator = MCE_INITIATOR_CPU;
Mahesh Salgaonkarcda66182019-04-29 23:45:55 +0530557 mce_err->sync_error = true;
Nicholas Piggin755309b2017-03-14 22:36:47 +1000558
559 return 0;
Nicholas Piggin631bc462017-03-14 22:36:46 +1000560}
561
562static long mce_handle_ue_error(struct pt_regs *regs)
563{
564 long handled = 0;
565
566 /*
567 * On specific SCOM read via MMIO we may get a machine check
568 * exception with SRR0 pointing inside opal. If that is the
569 * case OPAL may have recovery address to re-read SCOM data in
570 * different way and hence we can recover from this MC.
571 */
572
573 if (ppc_md.mce_check_early_recovery) {
574 if (ppc_md.mce_check_early_recovery(regs))
575 handled = 1;
576 }
577 return handled;
578}
579
Nicholas Piggin755309b2017-03-14 22:36:47 +1000580static long mce_handle_error(struct pt_regs *regs,
581 const struct mce_derror_table dtable[],
582 const struct mce_ierror_table itable[])
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +0530583{
Nicholas Piggin755309b2017-03-14 22:36:47 +1000584 struct mce_error_info mce_err = { 0 };
Mahesh Salgaonkar75ecfb42018-04-23 10:29:27 +0530585 uint64_t addr, phys_addr = ULONG_MAX;
Nicholas Piggin755309b2017-03-14 22:36:47 +1000586 uint64_t srr1 = regs->msr;
587 long handled;
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +0530588
Nicholas Piggin755309b2017-03-14 22:36:47 +1000589 if (SRR1_MC_LOADSTORE(srr1))
Balbir Singhba41e1e2017-09-29 14:26:53 +1000590 handled = mce_handle_derror(regs, dtable, &mce_err, &addr,
591 &phys_addr);
Nicholas Piggin755309b2017-03-14 22:36:47 +1000592 else
Balbir Singh01eaac22017-09-29 14:26:54 +1000593 handled = mce_handle_ierror(regs, itable, &mce_err, &addr,
594 &phys_addr);
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +0530595
Nicholas Piggin755309b2017-03-14 22:36:47 +1000596 if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE)
597 handled = mce_handle_ue_error(regs);
598
Balbir Singhba41e1e2017-09-29 14:26:53 +1000599 save_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr);
Nicholas Piggin755309b2017-03-14 22:36:47 +1000600
601 return handled;
Mahesh Salgaonkare22a2272013-10-30 20:05:11 +0530602}
603
604long __machine_check_early_realmode_p7(struct pt_regs *regs)
605{
Nicholas Piggin631bc462017-03-14 22:36:46 +1000606 /* P7 DD1 leaves top bits of DSISR undefined */
607 regs->dsisr &= 0x0000ffff;
608
Nicholas Piggin755309b2017-03-14 22:36:47 +1000609 return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table);
Mahesh Salgaonkarae744f32013-10-30 20:05:26 +0530610}
611
612long __machine_check_early_realmode_p8(struct pt_regs *regs)
613{
Nicholas Piggin755309b2017-03-14 22:36:47 +1000614 return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table);
Nicholas Piggin7b9f71f92017-02-28 12:00:48 +1000615}
616
Nicholas Piggin7b9f71f92017-02-28 12:00:48 +1000617long __machine_check_early_realmode_p9(struct pt_regs *regs)
618{
Michael Neulingd8bd9f32017-09-22 13:32:21 +1000619 /*
620 * On POWER9 DD2.1 and below, it's possible to get a machine check
Michael Neulingbca73f52017-09-28 22:37:35 -0500621 * caused by a paste instruction where only DSISR bit 25 is set. This
Michael Neulingd8bd9f32017-09-22 13:32:21 +1000622 * will result in the MCE handler seeing an unknown event and the kernel
623 * crashing. An MCE that occurs like this is spurious, so we don't need
624 * to do anything in terms of servicing it. If there is something that
625 * needs to be serviced, the CPU will raise the MCE again with the
626 * correct DSISR so that it can be serviced properly. So detect this
627 * case and mark it as handled.
628 */
Michael Neulingbca73f52017-09-28 22:37:35 -0500629 if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)
Michael Neulingd8bd9f32017-09-22 13:32:21 +1000630 return 1;
631
Nicholas Piggin755309b2017-03-14 22:36:47 +1000632 return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);
Nicholas Piggin7b9f71f92017-02-28 12:00:48 +1000633}