Blame - arch/powerpc/kernel/cpu_setup_power.S - linux-5.10

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Thomas Gleixner	2874c5f	2019-05-27 08:55:01 +0200	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	2	/*
				3	* This file contains low level CPU setup functions.
				4	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	5	*/
				6
				7	#include <asm/processor.h>
				8	#include <asm/page.h>
				9	#include <asm/cputable.h>
				10	#include <asm/ppc_asm.h>
				11	#include <asm/asm-offsets.h>
				12	#include <asm/cache.h>
Aneesh Kumar K.V	f64e808	2016-03-01 12:59:20 +0530	[diff] [blame]	13	#include <asm/book3s/64/mmu-hash.h>
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	14
				15	/* Entry: r3 = crap, r4 = ptr to cputable entry
				16	*
				17	* Note that we can be called twice for pseudo-PVRs
				18	*/
				19	_GLOBAL(__setup_cpu_power7)
				20	mflr r11
				21	bl __init_hvmode_206
				22	mtlr r11
				23	beqlr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	24	li r0,0
				25	mtspr SPRN_LPID,r0
Michael Neuling	faf37c4	2018-05-18 11:37:42 +1000	[diff] [blame]	26	mtspr SPRN_PCR,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	27	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	08a1e65	2017-04-05 17:54:55 +1000	[diff] [blame]	28	li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
Nicholas Piggin	700b7ead	2017-04-19 05:12:17 +1000	[diff] [blame]	29	bl __init_LPCR_ISA206
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	30	mtlr r11
				31	blr
				32
				33	_GLOBAL(__restore_cpu_power7)
				34	mflr r11
				35	mfmsr r3
				36	rldicl. r0,r3,4,63
				37	beqlr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	38	li r0,0
				39	mtspr SPRN_LPID,r0
Michael Neuling	faf37c4	2018-05-18 11:37:42 +1000	[diff] [blame]	40	mtspr SPRN_PCR,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	41	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	08a1e65	2017-04-05 17:54:55 +1000	[diff] [blame]	42	li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
Nicholas Piggin	700b7ead	2017-04-19 05:12:17 +1000	[diff] [blame]	43	bl __init_LPCR_ISA206
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	44	mtlr r11
				45	blr
				46
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	47	_GLOBAL(__setup_cpu_power8)
				48	mflr r11
Michael Neuling	57d2316	2013-03-04 19:45:50 +0000	[diff] [blame]	49	bl __init_FSCR
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	50	bl __init_PMU
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	51	bl __init_PMU_ISA207
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	52	bl __init_hvmode_206
				53	mtlr r11
				54	beqlr
				55	li r0,0
				56	mtspr SPRN_LPID,r0
Michael Neuling	faf37c4	2018-05-18 11:37:42 +1000	[diff] [blame]	57	mtspr SPRN_PCR,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	58	mfspr r3,SPRN_LPCR
Michael Neuling	d4e58e5	2014-06-11 15:59:28 +1000	[diff] [blame]	59	ori r3, r3, LPCR_PECEDH
Benjamin Herrenschmidt	08a1e65	2017-04-05 17:54:55 +1000	[diff] [blame]	60	li r4,0 /* LPES = 0 */
Nicholas Piggin	700b7ead	2017-04-19 05:12:17 +1000	[diff] [blame]	61	bl __init_LPCR_ISA206
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	62	bl __init_HFSCR
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	63	bl __init_PMU_HV
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	64	bl __init_PMU_HV_ISA207
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	65	mtlr r11
				66	blr
				67
				68	_GLOBAL(__restore_cpu_power8)
				69	mflr r11
Michael Neuling	57d2316	2013-03-04 19:45:50 +0000	[diff] [blame]	70	bl __init_FSCR
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	71	bl __init_PMU
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	72	bl __init_PMU_ISA207
				73	mfmsr r3
				74	rldicl. r0,r3,4,63
				75	mtlr r11
				76	beqlr
				77	li r0,0
				78	mtspr SPRN_LPID,r0
Michael Neuling	faf37c4	2018-05-18 11:37:42 +1000	[diff] [blame]	79	mtspr SPRN_PCR,r0
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	80	mfspr r3,SPRN_LPCR
				81	ori r3, r3, LPCR_PECEDH
Benjamin Herrenschmidt	08a1e65	2017-04-05 17:54:55 +1000	[diff] [blame]	82	li r4,0 /* LPES = 0 */
Nicholas Piggin	700b7ead	2017-04-19 05:12:17 +1000	[diff] [blame]	83	bl __init_LPCR_ISA206
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	84	bl __init_HFSCR
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	85	bl __init_PMU_HV
				86	bl __init_PMU_HV_ISA207
				87	mtlr r11
				88	blr
				89
				90	_GLOBAL(__setup_cpu_power9)
				91	mflr r11
				92	bl __init_FSCR
				93	bl __init_PMU
				94	bl __init_hvmode_206
				95	mtlr r11
				96	beqlr
				97	li r0,0
Gautham R. Shenoy	378f96d	2016-11-22 23:36:40 +0530	[diff] [blame]	98	mtspr SPRN_PSSCR,r0
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	99	mtspr SPRN_LPID,r0
Nicholas Piggin	371b8044	2017-12-06 18:21:14 +1000	[diff] [blame]	100	mtspr SPRN_PID,r0
Michael Neuling	faf37c4	2018-05-18 11:37:42 +1000	[diff] [blame]	101	mtspr SPRN_PCR,r0
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	102	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	08a1e65	2017-04-05 17:54:55 +1000	[diff] [blame]	103	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE \| LPCR_HEIC)
Benjamin Herrenschmidt	7a43906	2016-11-21 18:08:05 +1100	[diff] [blame]	104	or r3, r3, r4
Aneesh Kumar K.V	fda2d27	2017-02-22 10:42:02 +0530	[diff] [blame]	105	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
				106	andc r3, r3, r4
Nicholas Piggin	8d1b48e	2017-04-19 05:12:16 +1000	[diff] [blame]	107	li r4,0 /* LPES = 0 */
Nicholas Piggin	700b7ead	2017-04-19 05:12:17 +1000	[diff] [blame]	108	bl __init_LPCR_ISA300
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	109	bl __init_HFSCR
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	110	bl __init_PMU_HV
				111	mtlr r11
				112	blr
				113
				114	_GLOBAL(__restore_cpu_power9)
				115	mflr r11
				116	bl __init_FSCR
				117	bl __init_PMU
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	118	mfmsr r3
				119	rldicl. r0,r3,4,63
Michael Neuling	8c2a381	2013-04-24 21:00:37 +0000	[diff] [blame]	120	mtlr r11
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	121	beqlr
				122	li r0,0
Gautham R. Shenoy	378f96d	2016-11-22 23:36:40 +0530	[diff] [blame]	123	mtspr SPRN_PSSCR,r0
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	124	mtspr SPRN_LPID,r0
Nicholas Piggin	371b8044	2017-12-06 18:21:14 +1000	[diff] [blame]	125	mtspr SPRN_PID,r0
Michael Neuling	faf37c4	2018-05-18 11:37:42 +1000	[diff] [blame]	126	mtspr SPRN_PCR,r0
Michael Neuling	f7c32c2	2012-11-05 14:40:18 +1100	[diff] [blame]	127	mfspr r3,SPRN_LPCR
Benjamin Herrenschmidt	08a1e65	2017-04-05 17:54:55 +1000	[diff] [blame]	128	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE \| LPCR_HEIC)
Benjamin Herrenschmidt	7a43906	2016-11-21 18:08:05 +1100	[diff] [blame]	129	or r3, r3, r4
Aneesh Kumar K.V	fda2d27	2017-02-22 10:42:02 +0530	[diff] [blame]	130	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
				131	andc r3, r3, r4
Nicholas Piggin	8d1b48e	2017-04-19 05:12:16 +1000	[diff] [blame]	132	li r4,0 /* LPES = 0 */
Nicholas Piggin	700b7ead	2017-04-19 05:12:17 +1000	[diff] [blame]	133	bl __init_LPCR_ISA300
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	134	bl __init_HFSCR
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	135	bl __init_PMU_HV
Michael Neuling	aec937b	2012-10-30 19:34:14 +0000	[diff] [blame]	136	mtlr r11
				137	blr
				138
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	139	__init_hvmode_206:
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	140	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	141	mfmsr r3
				142	rldicl. r0,r3,4,63
				143	bnelr
				144	ld r5,CPU_SPEC_FEATURES(r4)
Paul Mackerras	e7b17d5	2018-10-08 16:30:47 +1100	[diff] [blame]	145	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE \| CPU_FTR_P9_TM_HV_ASSIST)
				146	andc r5,r5,r6
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	147	std r5,CPU_SPEC_FEATURES(r4)
				148	blr
				149
Nicholas Piggin	700b7ead	2017-04-19 05:12:17 +1000	[diff] [blame]	150	__init_LPCR_ISA206:
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	151	/* Setup a sane LPCR:
Benjamin Herrenschmidt	08a1e65	2017-04-05 17:54:55 +1000	[diff] [blame]	152	* Called with initial LPCR in R3 and desired LPES 2-bit value in R4
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	153	*
Benjamin Herrenschmidt	a5d4f3a	2011-04-05 14:20:31 +1000	[diff] [blame]	154	* LPES = 0b01 (HSRR0/1 used for 0x500)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	155	* PECE = 0b111
Benjamin Herrenschmidt	895796a	2011-01-24 13:25:55 +1100	[diff] [blame]	156	* DPFD = 4
Paul Mackerras	923c53c	2011-06-29 00:20:24 +0000	[diff] [blame]	157	* HDICE = 0
				158	* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
				159	* VRMASD = 0b10000 (L=1, LP=00)
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	160	*
				161	* Other bits untouched for now
				162	*/
Nicholas Piggin	700b7ead	2017-04-19 05:12:17 +1000	[diff] [blame]	163	li r5,0x10
				164	rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
				165
				166	/* POWER9 has no VRMASD */
				167	__init_LPCR_ISA300:
Benjamin Herrenschmidt	08a1e65	2017-04-05 17:54:55 +1000	[diff] [blame]	168	rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	169	ori r3,r3,(LPCR_PECE0\|LPCR_PECE1\|LPCR_PECE2)
Benjamin Herrenschmidt	895796a	2011-01-24 13:25:55 +1100	[diff] [blame]	170	li r5,4
Paul Mackerras	923c53c	2011-06-29 00:20:24 +0000	[diff] [blame]	171	rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
				172	clrrdi r3,r3,1 /* clear HDICE */
				173	li r5,4
				174	rldimi r3,r5, LPCR_VC_SH, 0
Benjamin Herrenschmidt	24cc67d	2011-01-20 18:50:55 +1100	[diff] [blame]	175	mtspr SPRN_LPCR,r3
				176	isync
				177	blr
Benjamin Herrenschmidt	b144871	2011-03-01 15:46:09 +1100	[diff] [blame]	178
Ian Munsie	2468dcf	2013-02-07 15:46:58 +0000	[diff] [blame]	179	__init_FSCR:
				180	mfspr r3,SPRN_FSCR
Michael Neuling	1ddf499	2013-04-30 20:17:03 +0000	[diff] [blame]	181	ori r3,r3,FSCR_TAR\|FSCR_DSCR\|FSCR_EBB
Ian Munsie	2468dcf	2013-02-07 15:46:58 +0000	[diff] [blame]	182	mtspr SPRN_FSCR,r3
				183	blr
				184
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	185	__init_HFSCR:
				186	mfspr r3,SPRN_HFSCR
Anshuman Khandual	53b56ca	2013-04-25 20:54:55 +0000	[diff] [blame]	187	ori r3,r3,HFSCR_TAR\|HFSCR_TM\|HFSCR_BHRB\|HFSCR_PM\|\
Michael Neuling	02ed21a	2016-11-23 10:44:09 +1100	[diff] [blame]	188	HFSCR_DSCR\|HFSCR_VECVSX\|HFSCR_FP\|HFSCR_EBB\|HFSCR_MSGP
Michael Neuling	2a3563b	2013-03-05 17:35:24 +0000	[diff] [blame]	189	mtspr SPRN_HFSCR,r3
				190	blr
				191
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	192	__init_PMU_HV:
				193	li r5,0
				194	mtspr SPRN_MMCRC,r5
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	195	blr
				196
				197	__init_PMU_HV_ISA207:
				198	li r5,0
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	199	mtspr SPRN_MMCRH,r5
				200	blr
				201
				202	__init_PMU:
				203	li r5,0
Michael Ellerman	240686c	2013-04-25 19:28:22 +0000	[diff] [blame]	204	mtspr SPRN_MMCRA,r5
				205	mtspr SPRN_MMCR0,r5
				206	mtspr SPRN_MMCR1,r5
				207	mtspr SPRN_MMCR2,r5
				208	blr
Madhavan Srinivasan	393eb79	2016-06-26 23:07:06 +0530	[diff] [blame]	209
				210	__init_PMU_ISA207:
				211	li r5,0
				212	mtspr SPRN_MMCRS,r5
				213	blr