Thomas Gleixner | f4344b1 | 2019-05-23 11:14:49 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 2 | #ifndef __ASM_POWERPC_IMC_PMU_H |
| 3 | #define __ASM_POWERPC_IMC_PMU_H |
| 4 | |
| 5 | /* |
| 6 | * IMC Nest Performance Monitor counter support. |
| 7 | * |
| 8 | * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation. |
| 9 | * (C) 2017 Anju T Sudhakar, IBM Corporation. |
| 10 | * (C) 2017 Hemant K Shaw, IBM Corporation. |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <linux/perf_event.h> |
| 14 | #include <linux/slab.h> |
| 15 | #include <linux/of.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <asm/opal.h> |
| 18 | |
| 19 | /* |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 20 | * Compatibility macros for IMC devices |
| 21 | */ |
| 22 | #define IMC_DTB_COMPAT "ibm,opal-in-memory-counters" |
| 23 | #define IMC_DTB_UNIT_COMPAT "ibm,imc-counters" |
| 24 | |
| 25 | |
| 26 | /* |
| 27 | * LDBAR: Counter address and Enable/Disable macro. |
| 28 | * perf/imc-pmu.c has the LDBAR layout information. |
| 29 | */ |
| 30 | #define THREAD_IMC_LDBAR_MASK 0x0003ffffffffe000ULL |
| 31 | #define THREAD_IMC_ENABLE 0x8000000000000000ULL |
Anju T Sudhakar | d1720ad | 2019-04-16 15:18:27 +0530 | [diff] [blame] | 32 | #define TRACE_IMC_ENABLE 0x4000000000000000ULL |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 33 | |
| 34 | /* |
Anju T Sudhakar | 684d984 | 2017-12-13 11:39:54 +0530 | [diff] [blame] | 35 | * For debugfs interface for imc-mode and imc-command |
| 36 | */ |
| 37 | #define IMC_CNTL_BLK_OFFSET 0x3FC00 |
| 38 | #define IMC_CNTL_BLK_CMD_OFFSET 8 |
| 39 | #define IMC_CNTL_BLK_MODE_OFFSET 32 |
| 40 | |
| 41 | /* |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 42 | * Structure to hold memory address information for imc units. |
| 43 | */ |
| 44 | struct imc_mem_info { |
| 45 | u64 *vbase; |
| 46 | u32 id; |
| 47 | }; |
| 48 | |
| 49 | /* |
| 50 | * Place holder for nest pmu events and values. |
| 51 | */ |
| 52 | struct imc_events { |
| 53 | u32 value; |
| 54 | char *name; |
| 55 | char *unit; |
| 56 | char *scale; |
| 57 | }; |
| 58 | |
Anju T Sudhakar | d1720ad | 2019-04-16 15:18:27 +0530 | [diff] [blame] | 59 | /* |
| 60 | * Trace IMC hardware updates a 64bytes record on |
| 61 | * Core Performance Monitoring Counter (CPMC) |
| 62 | * overflow. Here is the layout for the trace imc record |
| 63 | * |
| 64 | * DW 0 : Timebase |
| 65 | * DW 1 : Program Counter |
| 66 | * DW 2 : PIDR information |
| 67 | * DW 3 : CPMC1 |
| 68 | * DW 4 : CPMC2 |
| 69 | * DW 5 : CPMC3 |
| 70 | * Dw 6 : CPMC4 |
| 71 | * DW 7 : Timebase |
| 72 | * ..... |
| 73 | * |
| 74 | * The following is the data structure to hold trace imc data. |
| 75 | */ |
| 76 | struct trace_imc_data { |
| 77 | u64 tb1; |
| 78 | u64 ip; |
| 79 | u64 val; |
| 80 | u64 cpmc1; |
| 81 | u64 cpmc2; |
| 82 | u64 cpmc3; |
| 83 | u64 cpmc4; |
| 84 | u64 tb2; |
| 85 | }; |
| 86 | |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 87 | /* Event attribute array index */ |
| 88 | #define IMC_FORMAT_ATTR 0 |
| 89 | #define IMC_EVENT_ATTR 1 |
| 90 | #define IMC_CPUMASK_ATTR 2 |
| 91 | #define IMC_NULL_ATTR 3 |
| 92 | |
| 93 | /* PMU Format attribute macros */ |
| 94 | #define IMC_EVENT_OFFSET_MASK 0xffffffffULL |
| 95 | |
| 96 | /* |
Anju T Sudhakar | d1720ad | 2019-04-16 15:18:27 +0530 | [diff] [blame] | 97 | * Macro to mask bits 0:21 of first double word(which is the timebase) to |
| 98 | * compare with 8th double word (timebase) of trace imc record data. |
| 99 | */ |
| 100 | #define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL |
| 101 | |
| 102 | |
| 103 | /* |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 104 | * Device tree parser code detects IMC pmu support and |
| 105 | * registers new IMC pmus. This structure will hold the |
| 106 | * pmu functions, events, counter memory information |
| 107 | * and attrs for each imc pmu and will be referenced at |
| 108 | * the time of pmu registration. |
| 109 | */ |
| 110 | struct imc_pmu { |
| 111 | struct pmu pmu; |
| 112 | struct imc_mem_info *mem_info; |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 113 | struct imc_events *events; |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 114 | /* |
| 115 | * Attribute groups for the PMU. Slot 0 used for |
| 116 | * format attribute, slot 1 used for cpusmask attribute, |
| 117 | * slot 2 used for event attribute. Slot 3 keep as |
| 118 | * NULL. |
| 119 | */ |
| 120 | const struct attribute_group *attr_groups[4]; |
| 121 | u32 counter_mem_size; |
| 122 | int domain; |
| 123 | /* |
| 124 | * flag to notify whether the memory is mmaped |
| 125 | * or allocated by kernel. |
| 126 | */ |
| 127 | bool imc_counter_mmaped; |
| 128 | }; |
| 129 | |
| 130 | /* |
| 131 | * Structure to hold id, lock and reference count for the imc events which |
| 132 | * are inited. |
| 133 | */ |
| 134 | struct imc_pmu_ref { |
| 135 | struct mutex lock; |
| 136 | unsigned int id; |
| 137 | int refc; |
| 138 | }; |
| 139 | |
| 140 | /* |
| 141 | * In-Memory Collection Counters type. |
| 142 | * Data comes from Device tree. |
| 143 | * Three device type are supported. |
| 144 | */ |
| 145 | |
| 146 | enum { |
| 147 | IMC_TYPE_THREAD = 0x1, |
Anju T Sudhakar | d1720ad | 2019-04-16 15:18:27 +0530 | [diff] [blame] | 148 | IMC_TYPE_TRACE = 0x2, |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 149 | IMC_TYPE_CORE = 0x4, |
| 150 | IMC_TYPE_CHIP = 0x10, |
| 151 | }; |
| 152 | |
| 153 | /* |
| 154 | * Domains for IMC PMUs |
| 155 | */ |
| 156 | #define IMC_DOMAIN_NEST 1 |
| 157 | #define IMC_DOMAIN_CORE 2 |
| 158 | #define IMC_DOMAIN_THREAD 3 |
Anju T Sudhakar | d1720ad | 2019-04-16 15:18:27 +0530 | [diff] [blame] | 159 | /* For trace-imc the domain is still thread but it operates in trace-mode */ |
| 160 | #define IMC_DOMAIN_TRACE 4 |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 161 | |
| 162 | extern int init_imc_pmu(struct device_node *parent, |
| 163 | struct imc_pmu *pmu_ptr, int pmu_id); |
| 164 | extern void thread_imc_disable(void); |
Madhavan Srinivasan | 73ce9aec | 2017-11-22 10:45:39 +0530 | [diff] [blame] | 165 | extern int get_max_nest_dev(void); |
Anju T Sudhakar | 25af86b | 2018-05-22 14:42:37 +0530 | [diff] [blame] | 166 | extern void unregister_thread_imc(void); |
Madhavan Srinivasan | 8f95faa | 2017-07-19 03:06:33 +0530 | [diff] [blame] | 167 | #endif /* __ASM_POWERPC_IMC_PMU_H */ |