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nv-tegra.nvidia.com / linux-5.10 / d2912cb15bdda8ba4a5dd73396ad62641af2f520 / . / arch / powerpc / include / asm / hugetlb.h
blob: 20a101046cffc32a9e03117e0987ba4d39caee68 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Gerald Schaefer6d779072008-04-28 02:13:27 -0700[diff] [blame]2#ifndef _ASM_POWERPC_HUGETLB_H
3#define _ASM_POWERPC_HUGETLB_H
4
Becky Bruce41151e72011-06-28 09:54:48 +0000[diff] [blame]5#ifdef CONFIG_HUGETLB_PAGE
Gerald Schaefer6d779072008-04-28 02:13:27 -0700[diff] [blame]6#include <asm/page.h>
7
Aneesh Kumar K.Vcf9427b2013-04-28 09:37:29 +0000[diff] [blame]8#ifdef CONFIG_PPC_BOOK3S_64
Aneesh Kumar K.Vbee8b3b2016-11-28 11:46:58 +0530[diff] [blame]9#include <asm/book3s/64/hugetlb.h>
Christophe Leroy8197af22019-04-26 05:59:44 +0000[diff] [blame]10#elif defined(CONFIG_PPC_FSL_BOOK3E)
11#include <asm/nohash/hugetlb-book3e.h>
12#elif defined(CONFIG_PPC_8xx)
13#include <asm/nohash/32/hugetlb-8xx.h>
Aneesh Kumar K.Vcf9427b2013-04-28 09:37:29 +0000[diff] [blame]14#endif /* CONFIG_PPC_BOOK3S_64 */
15
Christophe Leroy45d0ba52019-04-26 05:59:47 +0000[diff] [blame]16extern bool hugetlb_disabled;
17
Christophe Leroyc5710cd22019-04-26 05:59:48 +0000[diff] [blame]18void hugetlbpage_init_default(void);
19
David Gibson0895ecd2009-10-26 19:24:31 +0000[diff] [blame]20void flush_dcache_icache_hugepage(struct page *page);
21
Nicholas Piggin014a32b2018-03-07 11:37:17 +1000[diff] [blame]22int slice_is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
Gerald Schaefer6d779072008-04-28 02:13:27 -0700[diff] [blame]23 unsigned long len);
Nicholas Piggin014a32b2018-03-07 11:37:17 +1000[diff] [blame]24
Becky Bruce41151e72011-06-28 09:54:48 +0000[diff] [blame]25static inline int is_hugepage_only_range(struct mm_struct *mm,
26 unsigned long addr,
27 unsigned long len)
28{
Nicholas Piggin014a32b2018-03-07 11:37:17 +1000[diff] [blame]29 if (IS_ENABLED(CONFIG_PPC_MM_SLICES) && !radix_enabled())
30 return slice_is_hugepage_only_range(mm, addr, len);
Becky Bruce41151e72011-06-28 09:54:48 +0000[diff] [blame]31 return 0;
32}
Becky Bruce41151e72011-06-28 09:54:48 +0000[diff] [blame]33
Becky Bruced93e4d72011-11-28 14:43:33 +0000[diff] [blame]34void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
35 pte_t pte);
Gerald Schaefer6d779072008-04-28 02:13:27 -0700[diff] [blame]36
Alexandre Ghiti1e5f50f2018-10-26 15:08:03 -0700[diff] [blame]37#define __HAVE_ARCH_HUGETLB_FREE_PGD_RANGE
Jan Beulich42b77722008-07-23 21:27:10 -0700[diff] [blame]38void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
Gerald Schaefer6d779072008-04-28 02:13:27 -0700[diff] [blame]39 unsigned long end, unsigned long floor,
40 unsigned long ceiling);
41
Alexandre Ghitia4d83852018-10-26 15:08:12 -0700[diff] [blame]42#define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR
David Gibson0895ecd2009-10-26 19:24:31 +0000[diff] [blame]43static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
44 unsigned long addr, pte_t *ptep)
45{
Becky Bruce41151e72011-06-28 09:54:48 +0000[diff] [blame]46#ifdef CONFIG_PPC64
Aneesh Kumar K.V88247e82014-02-12 09:13:36 +0530[diff] [blame]47 return __pte(pte_update(mm, addr, ptep, ~0UL, 0, 1));
Becky Bruce41151e72011-06-28 09:54:48 +0000[diff] [blame]48#else
49 return __pte(pte_update(ptep, ~0UL, 0));
50#endif
David Gibson0895ecd2009-10-26 19:24:31 +0000[diff] [blame]51}
52
Alexandre Ghitife632222018-10-26 15:08:17 -0700[diff] [blame]53#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
Gerald Schaefer8fe627e2008-04-28 02:13:28 -0700[diff] [blame]54static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
55 unsigned long addr, pte_t *ptep)
56{
Christophe Leroy584dbc72018-10-18 05:22:06 +0000[diff] [blame]57 huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
Aneesh Kumar K.V13dce032016-07-13 15:06:38 +0530[diff] [blame]58 flush_hugetlb_page(vma, addr);
Gerald Schaefer8fe627e2008-04-28 02:13:28 -0700[diff] [blame]59}
60
Alexandre Ghitifacf6d52018-10-26 15:08:39 -0700[diff] [blame]61#define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS
Breno Leitaobce85a12018-10-31 11:24:11 -0300[diff] [blame]62int huge_ptep_set_access_flags(struct vm_area_struct *vma,
63 unsigned long addr, pte_t *ptep,
64 pte_t pte, int dirty);
Gerald Schaefer7f2e9522008-04-28 02:13:29 -0700[diff] [blame]65
Will Deacon5d3a5512012-10-08 16:29:32 -0700[diff] [blame]66static inline void arch_clear_hugepage_flags(struct page *page)
67{
68}
69
Alexandre Ghiti1e5f50f2018-10-26 15:08:03 -0700[diff] [blame]70#include <asm-generic/hugetlb.h>
71
Becky Bruce41151e72011-06-28 09:54:48 +0000[diff] [blame]72#else /* ! CONFIG_HUGETLB_PAGE */
Becky Bruce41151e72011-06-28 09:54:48 +0000[diff] [blame]73static inline void flush_hugetlb_page(struct vm_area_struct *vma,
74 unsigned long vmaddr)
75{
76}
Becky Brucea6146882011-10-10 10:50:43 +0000[diff] [blame]77
Aneesh Kumar K.V29409992013-06-20 14:30:16 +0530[diff] [blame]78#define hugepd_shift(x) 0
Aneesh Kumar K.Vb30e7592014-11-05 21:57:41 +0530[diff] [blame]79static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr,
Aneesh Kumar K.V29409992013-06-20 14:30:16 +0530[diff] [blame]80 unsigned pdshift)
81{
Mathieu Malaterred8731522018-04-13 20:41:43 +0200[diff] [blame]82 return NULL;
Aneesh Kumar K.V29409992013-06-20 14:30:16 +0530[diff] [blame]83}
84#endif /* CONFIG_HUGETLB_PAGE */
Becky Brucea6146882011-10-10 10:50:43 +0000[diff] [blame]85
Gerald Schaefer6d779072008-04-28 02:13:27 -0700[diff] [blame]86#endif /* _ASM_POWERPC_HUGETLB_H */