Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aurelien Jacquiot | 784bdcd | 2011-10-04 11:11:35 -0400 | [diff] [blame] | 2 | /* |
| 3 | * Port on Texas Instruments TMS320C6x architecture |
| 4 | * |
| 5 | * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated |
| 6 | * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) |
Aurelien Jacquiot | 784bdcd | 2011-10-04 11:11:35 -0400 | [diff] [blame] | 7 | */ |
| 8 | #ifndef _ASM_C6X_CACHEFLUSH_H |
| 9 | #define _ASM_C6X_CACHEFLUSH_H |
| 10 | |
| 11 | #include <linux/spinlock.h> |
| 12 | |
| 13 | #include <asm/setup.h> |
| 14 | #include <asm/cache.h> |
| 15 | #include <asm/mman.h> |
| 16 | #include <asm/page.h> |
| 17 | #include <asm/string.h> |
| 18 | |
| 19 | /* |
| 20 | * virtually-indexed cache management (our cache is physically indexed) |
| 21 | */ |
| 22 | #define flush_cache_all() do {} while (0) |
| 23 | #define flush_cache_mm(mm) do {} while (0) |
| 24 | #define flush_cache_dup_mm(mm) do {} while (0) |
| 25 | #define flush_cache_range(mm, start, end) do {} while (0) |
| 26 | #define flush_cache_page(vma, vmaddr, pfn) do {} while (0) |
| 27 | #define flush_cache_vmap(start, end) do {} while (0) |
| 28 | #define flush_cache_vunmap(start, end) do {} while (0) |
| 29 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 |
| 30 | #define flush_dcache_page(page) do {} while (0) |
| 31 | #define flush_dcache_mmap_lock(mapping) do {} while (0) |
| 32 | #define flush_dcache_mmap_unlock(mapping) do {} while (0) |
| 33 | |
| 34 | /* |
| 35 | * physically-indexed cache management |
| 36 | */ |
| 37 | #define flush_icache_range(s, e) \ |
| 38 | do { \ |
| 39 | L1D_cache_block_writeback((s), (e)); \ |
| 40 | L1P_cache_block_invalidate((s), (e)); \ |
| 41 | } while (0) |
| 42 | |
| 43 | #define flush_icache_page(vma, page) \ |
| 44 | do { \ |
| 45 | if ((vma)->vm_flags & PROT_EXEC) \ |
| 46 | L1D_cache_block_writeback_invalidate(page_address(page), \ |
| 47 | (unsigned long) page_address(page) + PAGE_SIZE)); \ |
| 48 | L1P_cache_block_invalidate(page_address(page), \ |
| 49 | (unsigned long) page_address(page) + PAGE_SIZE)); \ |
| 50 | } while (0) |
| 51 | |
| 52 | |
| 53 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 54 | do { \ |
| 55 | memcpy(dst, src, len); \ |
| 56 | flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ |
| 57 | } while (0) |
| 58 | |
| 59 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
| 60 | memcpy(dst, src, len) |
| 61 | |
| 62 | #endif /* _ASM_C6X_CACHEFLUSH_H */ |