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nv-tegra.nvidia.com / linux-5.10 / d2912cb15bdda8ba4a5dd73396ad62641af2f520 / . / arch / arm / mach-omap2 / omap-secure.h
blob: 20046e8f8ecbe4478b8f575dd6c6b45d0482ea72 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
Santosh Shilimkarba9456a2011-06-06 17:56:49 +0530[diff] [blame]2/*
3 * omap-secure.h: OMAP Secure infrastructure header.
4 *
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
Pali Rohár4748a722013-09-18 21:43:56 +0200[diff] [blame]7 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
8 * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
Santosh Shilimkarba9456a2011-06-06 17:56:49 +0530[diff] [blame]9 */
10#ifndef OMAP_ARCH_OMAP_SECURE_H
11#define OMAP_ARCH_OMAP_SECURE_H
12
13/* Monitor error code */
14#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
15#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
16
17/* HAL API error codes */
18#define API_HAL_RET_VALUE_OK 0x00
19#define API_HAL_RET_VALUE_FAIL 0x01
20
21/* Secure HAL API flags */
22#define FLAG_START_CRITICAL 0x4
23#define FLAG_IRQFIQ_MASK 0x3
24#define FLAG_IRQ_ENABLE 0x2
25#define FLAG_FIQ_ENABLE 0x1
26#define NO_FLAG 0x0
27
Santosh Shilimkar259ee572011-06-06 20:28:23 +0530[diff] [blame]28/* Maximum Secure memory storage size */
29#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
Santosh Shilimkarba9456a2011-06-06 17:56:49 +0530[diff] [blame]30
Tony Lindgrend09220a2017-11-27 08:57:26 -0800[diff] [blame]31#define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
32
Santosh Shilimkarba9456a2011-06-06 17:56:49 +0530[diff] [blame]33/* Secure low power HAL API index */
34#define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a
35#define OMAP4_HAL_SAVEHW_INDEX 0x1b
36#define OMAP4_HAL_SAVEALL_INDEX 0x1c
37#define OMAP4_HAL_SAVEGIC_INDEX 0x1d
38
Santosh Shilimkarb2b97622010-06-16 22:19:48 +0530[diff] [blame]39/* Secure Monitor mode APIs */
40#define OMAP4_MON_SCU_PWR_INDEX 0x108
Santosh Shilimkar5e94c6e32011-01-09 02:59:09 +0530[diff] [blame]41#define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100
42#define OMAP4_MON_L2X0_CTRL_INDEX 0x102
43#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
44#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
Santosh Shilimkarb2b97622010-06-16 22:19:48 +0530[diff] [blame]45
R Sricharan5523e402013-10-10 13:13:48 +0530[diff] [blame]46#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
Santosh Shilimkar4664d4d2013-02-08 17:07:31 +0530[diff] [blame]47#define OMAP5_MON_AMBA_IF_INDEX 0x108
Nishanth Menonc0053bd2015-08-06 10:54:24 -0500[diff] [blame]48#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
R Sricharan5523e402013-10-10 13:13:48 +0530[diff] [blame]49
Santosh Shilimkarb2b97622010-06-16 22:19:48 +0530[diff] [blame]50/* Secure PPA(Primary Protected Application) APIs */
Santosh Shilimkar5e94c6e32011-01-09 02:59:09 +0530[diff] [blame]51#define OMAP4_PPA_L2_POR_INDEX 0x23
Santosh Shilimkarb2b97622010-06-16 22:19:48 +0530[diff] [blame]52#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
53
Pali Rohár4748a722013-09-18 21:43:56 +0200[diff] [blame]54/* Secure RX-51 PPA (Primary Protected Application) APIs */
55#define RX51_PPA_HWRNG 29
56#define RX51_PPA_L2_INVAL 40
57#define RX51_PPA_WRITE_ACR 42
58
Santosh Shilimkarb2b97622010-06-16 22:19:48 +0530[diff] [blame]59#ifndef __ASSEMBLER__
60
Santosh Shilimkarba9456a2011-06-06 17:56:49 +0530[diff] [blame]61extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
62 u32 arg1, u32 arg2, u32 arg3, u32 arg4);
63extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
Pali Rohára33f1782013-09-08 09:43:29 +0200[diff] [blame]64extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
Santosh Shilimkar259ee572011-06-06 20:28:23 +0530[diff] [blame]65extern phys_addr_t omap_secure_ram_mempool_base(void);
Lokesh Vutlaf7a9b8a2012-10-02 00:17:06 +0530[diff] [blame]66extern int omap_secure_ram_reserve_memblock(void);
Tony Lindgrend09220a2017-11-27 08:57:26 -0800[diff] [blame]67extern u32 save_secure_ram_context(u32 args_pa);
68extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size);
Santosh Shilimkarba9456a2011-06-06 17:56:49 +0530[diff] [blame]69
Pali Rohár4748a722013-09-18 21:43:56 +0200[diff] [blame]70extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
71 u32 arg1, u32 arg2, u32 arg3, u32 arg4);
72extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
Pali Rohárd2065e22013-09-20 15:25:07 +0200[diff] [blame]73extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
Pali Rohár4748a722013-09-18 21:43:56 +0200[diff] [blame]74
Tony Lindgren39cec622013-11-18 13:56:48 -0800[diff] [blame]75#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
R Sricharan5523e402013-10-10 13:13:48 +0530[diff] [blame]76void set_cntfreq(void);
Tony Lindgren39cec622013-11-18 13:56:48 -0800[diff] [blame]77#else
78static inline void set_cntfreq(void)
79{
80}
81#endif
82
Santosh Shilimkarb2b97622010-06-16 22:19:48 +0530[diff] [blame]83#endif /* __ASSEMBLER__ */
Santosh Shilimkarba9456a2011-06-06 17:56:49 +0530[diff] [blame]84#endif /* OMAP_ARCH_OMAP_SECURE_H */