blob: 4122a61aae70368d2c1c13f3258926b3739578bc [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Rod Whitby7e36e2f2008-04-01 10:53:23 +01002/*
3 * arch/arch/mach-ixp4xx/fsg-pci.c
4 *
5 * FSG board-level PCI initialization
6 *
7 * Author: Rod Whitby <rod@whitby.id.au>
8 * Maintainer: http://www.nslu2-linux.org/
9 *
10 * based on ixdp425-pci.c:
11 * Copyright (C) 2002 Intel Corporation.
12 * Copyright (C) 2003-2004 MontaVista Software, Inc.
Rod Whitby7e36e2f2008-04-01 10:53:23 +010013 */
14
15#include <linux/pci.h>
16#include <linux/init.h>
17#include <linux/irq.h>
Rod Whitby7e36e2f2008-04-01 10:53:23 +010018#include <asm/mach/pci.h>
19#include <asm/mach-types.h>
20
Linus Walleijdc8ef8cd2018-12-29 15:47:52 +010021#include "irqs.h"
22
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010023#define MAX_DEV 3
24#define IRQ_LINES 3
Krzysztof Hałasa914e7bc2009-11-16 22:53:53 +010025
26/* PCI controller GPIO to IRQ pin mappings */
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010027#define INTA 6
28#define INTB 7
29#define INTC 5
Krzysztof Hałasa914e7bc2009-11-16 22:53:53 +010030
Rod Whitby7e36e2f2008-04-01 10:53:23 +010031void __init fsg_pci_preinit(void)
32{
Thomas Gleixner6845664a2011-03-24 13:25:22 +010033 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
34 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
35 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
Rod Whitby7e36e2f2008-04-01 10:53:23 +010036 ixp4xx_pci_preinit();
37}
38
Ralf Baechled5341942011-06-10 15:30:21 +010039static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
Rod Whitby7e36e2f2008-04-01 10:53:23 +010040{
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010041 static int pci_irq_table[IRQ_LINES] = {
42 IXP4XX_GPIO_IRQ(INTC),
43 IXP4XX_GPIO_IRQ(INTB),
44 IXP4XX_GPIO_IRQ(INTA),
Rod Whitby7e36e2f2008-04-01 10:53:23 +010045 };
46
47 int irq = -1;
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010048 slot -= 11;
Rod Whitby7e36e2f2008-04-01 10:53:23 +010049
Krzysztof Hałasa8d3fdf32009-11-17 18:48:23 +010050 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
51 irq = pci_irq_table[slot - 1];
Rod Whitby7e36e2f2008-04-01 10:53:23 +010052 printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
53 __func__, slot, pin, irq);
54
55 return irq;
56}
57
58struct hw_pci fsg_pci __initdata = {
59 .nr_controllers = 1,
Russell Kingc23bfc32012-03-10 12:49:16 +000060 .ops = &ixp4xx_ops,
Rod Whitby7e36e2f2008-04-01 10:53:23 +010061 .preinit = fsg_pci_preinit,
Rod Whitby7e36e2f2008-04-01 10:53:23 +010062 .setup = ixp4xx_setup,
Rod Whitby7e36e2f2008-04-01 10:53:23 +010063 .map_irq = fsg_map_irq,
64};
65
66int __init fsg_pci_init(void)
67{
68 if (machine_is_fsg())
69 pci_common_init(&fsg_pci);
70 return 0;
71}
72
73subsys_initcall(fsg_pci_init);