blob: 2aa26928221dec8ca6ca5e1baa83fa058598b8ae [file] [log] [blame]
Thomas Gleixnerfcaf2032019-05-27 08:55:08 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Shawn Guo69c31b72011-09-06 14:59:40 +08002/*
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
Shawn Guo69c31b72011-09-06 14:59:40 +08005 */
6
7#include <linux/init.h>
Jingchang Lu4e3fea42014-10-31 17:01:13 +08008#include <linux/of_address.h>
9#include <linux/of.h>
Shawn Guo69c31b72011-09-06 14:59:40 +080010#include <linux/smp.h>
Jingchang Lu4e3fea42014-10-31 17:01:13 +080011
Shawn Guo087bb282013-04-16 22:11:19 +080012#include <asm/cacheflush.h>
Shawn Guo69c31b72011-09-06 14:59:40 +080013#include <asm/page.h>
14#include <asm/smp_scu.h>
Shawn Guo69c31b72011-09-06 14:59:40 +080015#include <asm/mach/map.h>
Shawn Guo69c31b72011-09-06 14:59:40 +080016
Shawn Guoe3372472012-09-13 21:01:00 +080017#include "common.h"
Shawn Guo50f2de62012-09-14 14:14:45 +080018#include "hardware.h"
Shawn Guoe3372472012-09-13 21:01:00 +080019
Shawn Guo087bb282013-04-16 22:11:19 +080020u32 g_diag_reg;
Shawn Guo69c31b72011-09-06 14:59:40 +080021static void __iomem *scu_base;
22
23static struct map_desc scu_io_desc __initdata = {
24 /* .virtual and .pfn are run-time assigned */
25 .length = SZ_4K,
26 .type = MT_DEVICE,
27};
28
29void __init imx_scu_map_io(void)
30{
31 unsigned long base;
32
33 /* Get SCU base */
34 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
35
36 scu_io_desc.virtual = IMX_IO_P2V(base);
37 scu_io_desc.pfn = __phys_to_pfn(base);
38 iotable_init(&scu_io_desc, 1);
39
40 scu_base = IMX_IO_ADDRESS(base);
41}
42
Paul Gortmaker8bd26e32013-06-17 15:43:14 -040043static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
Shawn Guo69c31b72011-09-06 14:59:40 +080044{
45 imx_set_cpu_jump(cpu, v7_secondary_startup);
46 imx_enable_cpu(cpu, true);
47 return 0;
48}
49
50/*
51 * Initialise the CPU possible map early - this describes the CPUs
52 * which may be present or become present in the system.
53 */
Marc Zyngiere4f2d972011-09-08 13:15:22 +010054static void __init imx_smp_init_cpus(void)
Shawn Guo69c31b72011-09-06 14:59:40 +080055{
56 int i, ncores;
57
58 ncores = scu_get_core_count(scu_base);
59
Shawn Guodc13ba22013-04-02 16:37:21 +080060 for (i = ncores; i < NR_CPUS; i++)
61 set_cpu_possible(i, false);
Shawn Guo69c31b72011-09-06 14:59:40 +080062}
63
64void imx_smp_prepare(void)
65{
66 scu_enable(scu_base);
67}
68
Marc Zyngiere4f2d972011-09-08 13:15:22 +010069static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
Shawn Guo69c31b72011-09-06 14:59:40 +080070{
71 imx_smp_prepare();
Shawn Guo087bb282013-04-16 22:11:19 +080072
73 /*
74 * The diagnostic register holds the errata bits. Mostly bootloader
75 * does not bring up secondary cores, so that when errata bits are set
76 * in bootloader, they are set only for boot cpu. But on a SMP
77 * configuration, it should be equally done on every single core.
78 * Read the register from boot cpu here, and will replicate it into
79 * secondary cores when booting them.
80 */
81 asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
Nicolas Pitref45913f2013-12-05 14:26:16 -050082 sync_cache_w(&g_diag_reg);
Shawn Guo69c31b72011-09-06 14:59:40 +080083}
Marc Zyngiere4f2d972011-09-08 13:15:22 +010084
Masahiro Yamada75305272015-11-15 10:39:53 +090085const struct smp_operations imx_smp_ops __initconst = {
Marc Zyngiere4f2d972011-09-08 13:15:22 +010086 .smp_init_cpus = imx_smp_init_cpus,
87 .smp_prepare_cpus = imx_smp_prepare_cpus,
Marc Zyngiere4f2d972011-09-08 13:15:22 +010088 .smp_boot_secondary = imx_boot_secondary,
89#ifdef CONFIG_HOTPLUG_CPU
90 .cpu_die = imx_cpu_die,
Shawn Guo83757662013-01-14 14:08:50 +080091 .cpu_kill = imx_cpu_kill,
Marc Zyngiere4f2d972011-09-08 13:15:22 +010092#endif
93};
Jingchang Lu4e3fea42014-10-31 17:01:13 +080094
95#define DCFG_CCSR_SCRATCHRW1 0x200
96
97static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
98{
99 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
100
101 return 0;
102}
103
104static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
105{
106 struct device_node *np;
107 void __iomem *dcfg_base;
108 unsigned long paddr;
109
110 np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
111 dcfg_base = of_iomap(np, 0);
112 BUG_ON(!dcfg_base);
113
Florian Fainelli64fc2a92017-01-15 03:59:29 +0100114 paddr = __pa_symbol(secondary_startup);
Jingchang Lu4e3fea42014-10-31 17:01:13 +0800115 writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
116
117 iounmap(dcfg_base);
118}
119
Masahiro Yamada75305272015-11-15 10:39:53 +0900120const struct smp_operations ls1021a_smp_ops __initconst = {
Jingchang Lu4e3fea42014-10-31 17:01:13 +0800121 .smp_prepare_cpus = ls1021a_smp_prepare_cpus,
122 .smp_boot_secondary = ls1021a_boot_secondary,
123};