Blame - arch/arm/lib/delay-loop.S - linux-5.10

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Thomas Gleixner	d2912cb	2019-06-04 10:11:33 +0200	[diff] [blame^]	1	/* SPDX-License-Identifier: GPL-2.0-only */
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2	/*
				3	* linux/arch/arm/lib/delay.S
				4	*
				5	* Copyright (C) 1995, 1996 Russell King
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
				7	#include <linux/linkage.h>
				8	#include <asm/assembler.h>
Will Deacon	d0a533b	2012-07-06 15:47:17 +0100	[diff] [blame]	9	#include <asm/delay.h>
Nicolas Pitre	215e362	2015-02-25 22:50:39 +0100	[diff] [blame]	10
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	11	.text
				12
Nicolas Pitre	8adbb37	2005-11-11 21:51:49 +0000	[diff] [blame]	13	.LC0: .word loops_per_jiffy
Will Deacon	d0a533b	2012-07-06 15:47:17 +0100	[diff] [blame]	14	.LC1: .word UDELAY_MULT
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	15
				16	/*
Nicolas Pitre	207b115	2016-10-07 05:38:35 +0100	[diff] [blame]	17	* loops = r0 * HZ * loops_per_jiffy / 1000000
				18	*
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	19	* r0 <= 2000
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	20	* HZ <= 1000
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	21	*/
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	22
Will Deacon	d0a533b	2012-07-06 15:47:17 +0100	[diff] [blame]	23	ENTRY(__loop_udelay)
Peter Teichmann	6d4518d	2006-03-20 17:10:09 +0000	[diff] [blame]	24	ldr r2, .LC1
Nicolas Pitre	207b115	2016-10-07 05:38:35 +0100	[diff] [blame]	25	mul r0, r2, r0 @ r0 = delay_us * UDELAY_MULT
				26	ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0xfffffaf0
Nicolas Pitre	8adbb37	2005-11-11 21:51:49 +0000	[diff] [blame]	27	ldr r2, .LC0
Nicolas Pitre	215e362	2015-02-25 22:50:39 +0100	[diff] [blame]	28	ldr r2, [r2]
Nicolas Pitre	207b115	2016-10-07 05:38:35 +0100	[diff] [blame]	29	umull r1, r0, r2, r0 @ r0-r1 = r0 * loops_per_jiffy
				30	adds r1, r1, #0xffffffff @ rounding up ...
				31	adcs r0, r0, r0 @ and right shift by 31
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	32	reteq lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	33
Fabio Estevam	11d4bb1	2013-11-30 15:24:42 +0100	[diff] [blame]	34	.align 3
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	35
				36	@ Delay routine
Will Deacon	d0a533b	2012-07-06 15:47:17 +0100	[diff] [blame]	37	ENTRY(__loop_delay)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	38	subs r0, r0, #1
				39	#if 0
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	40	retls lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	41	subs r0, r0, #1
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	42	retls lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	43	subs r0, r0, #1
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	44	retls lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	45	subs r0, r0, #1
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	46	retls lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	47	subs r0, r0, #1
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	48	retls lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	49	subs r0, r0, #1
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	50	retls lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	51	subs r0, r0, #1
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	52	retls lr
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	53	subs r0, r0, #1
				54	#endif
Will Deacon	d0a533b	2012-07-06 15:47:17 +0100	[diff] [blame]	55	bhi __loop_delay
Russell King	6ebbf2c	2014-06-30 16:29:12 +0100	[diff] [blame]	56	ret lr
Will Deacon	d0a533b	2012-07-06 15:47:17 +0100	[diff] [blame]	57	ENDPROC(__loop_udelay)
				58	ENDPROC(__loop_const_udelay)
				59	ENDPROC(__loop_delay)