Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | /* |
| 3 | * linux/arch/arm/lib/csumpartialcopyuser.S |
| 4 | * |
| 5 | * Copyright (C) 1995-1998 Russell King |
| 6 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * 27/03/03 Ian Molton Clean up CONFIG_CPU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | */ |
| 9 | #include <linux/linkage.h> |
| 10 | #include <asm/assembler.h> |
| 11 | #include <asm/errno.h> |
Sam Ravnborg | e6ae744 | 2005-09-09 21:08:59 +0200 | [diff] [blame] | 12 | #include <asm/asm-offsets.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | |
| 14 | .text |
| 15 | |
Russell King | a5e090a | 2015-08-19 20:40:41 +0100 | [diff] [blame] | 16 | #ifdef CONFIG_CPU_SW_DOMAIN_PAN |
| 17 | .macro save_regs |
| 18 | mrc p15, 0, ip, c3, c0, 0 |
| 19 | stmfd sp!, {r1, r2, r4 - r8, ip, lr} |
| 20 | uaccess_enable ip |
| 21 | .endm |
| 22 | |
| 23 | .macro load_regs |
| 24 | ldmfd sp!, {r1, r2, r4 - r8, ip, lr} |
| 25 | mcr p15, 0, ip, c3, c0, 0 |
| 26 | ret lr |
| 27 | .endm |
| 28 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | .macro save_regs |
Catalin Marinas | 22acc4e | 2008-08-29 18:31:27 +0100 | [diff] [blame] | 30 | stmfd sp!, {r1, r2, r4 - r8, lr} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | .endm |
| 32 | |
Catalin Marinas | 90303b1 | 2006-01-12 16:53:51 +0000 | [diff] [blame] | 33 | .macro load_regs |
Catalin Marinas | 22acc4e | 2008-08-29 18:31:27 +0100 | [diff] [blame] | 34 | ldmfd sp!, {r1, r2, r4 - r8, pc} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | .endm |
Russell King | a5e090a | 2015-08-19 20:40:41 +0100 | [diff] [blame] | 36 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
| 38 | .macro load1b, reg1 |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 39 | ldrusr \reg1, r0, 1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | .endm |
| 41 | |
| 42 | .macro load2b, reg1, reg2 |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 43 | ldrusr \reg1, r0, 1 |
| 44 | ldrusr \reg2, r0, 1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | .endm |
| 46 | |
| 47 | .macro load1l, reg1 |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 48 | ldrusr \reg1, r0, 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | .endm |
| 50 | |
| 51 | .macro load2l, reg1, reg2 |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 52 | ldrusr \reg1, r0, 4 |
| 53 | ldrusr \reg2, r0, 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | .endm |
| 55 | |
| 56 | .macro load4l, reg1, reg2, reg3, reg4 |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 57 | ldrusr \reg1, r0, 4 |
| 58 | ldrusr \reg2, r0, 4 |
| 59 | ldrusr \reg3, r0, 4 |
| 60 | ldrusr \reg4, r0, 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | .endm |
| 62 | |
| 63 | /* |
| 64 | * unsigned int |
| 65 | * csum_partial_copy_from_user(const char *src, char *dst, int len, int sum, int *err_ptr) |
| 66 | * r0 = src, r1 = dst, r2 = len, r3 = sum, [sp] = *err_ptr |
| 67 | * Returns : r0 = checksum, [[sp, #0], #0] = 0 or -EFAULT |
| 68 | */ |
| 69 | |
| 70 | #define FN_ENTRY ENTRY(csum_partial_copy_from_user) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 71 | #define FN_EXIT ENDPROC(csum_partial_copy_from_user) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | |
| 73 | #include "csumpartialcopygeneric.S" |
| 74 | |
| 75 | /* |
| 76 | * FIXME: minor buglet here |
| 77 | * We don't return the checksum for the data present in the buffer. To do |
| 78 | * so properly, we would have to add in whatever registers were loaded before |
| 79 | * the fault, which, with the current asm above is not predictable. |
| 80 | */ |
Ard Biesheuvel | c4a84ae | 2015-03-24 10:41:09 +0100 | [diff] [blame] | 81 | .pushsection .text.fixup,"ax" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | .align 4 |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 83 | 9001: mov r4, #-EFAULT |
Chunyan Zhang | 36b0cb8 | 2017-12-01 03:51:04 +0100 | [diff] [blame] | 84 | #ifdef CONFIG_CPU_SW_DOMAIN_PAN |
| 85 | ldr r5, [sp, #9*4] @ *err_ptr |
| 86 | #else |
Russell King | 4609a17 | 2010-07-26 12:18:16 +0100 | [diff] [blame] | 87 | ldr r5, [sp, #8*4] @ *err_ptr |
Chunyan Zhang | 36b0cb8 | 2017-12-01 03:51:04 +0100 | [diff] [blame] | 88 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | str r4, [r5] |
| 90 | ldmia sp, {r1, r2} @ retrieve dst, len |
| 91 | add r2, r2, r1 |
| 92 | mov r0, #0 @ zero the buffer |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 93 | 9002: teq r2, r1 |
Stefan Agner | e44fc38 | 2019-02-18 00:57:38 +0100 | [diff] [blame] | 94 | strbne r0, [r1], #1 |
Catalin Marinas | 8b59278 | 2009-07-24 12:32:57 +0100 | [diff] [blame] | 95 | bne 9002b |
Catalin Marinas | 90303b1 | 2006-01-12 16:53:51 +0000 | [diff] [blame] | 96 | load_regs |
Russell King | 4260415 | 2010-04-19 10:15:03 +0100 | [diff] [blame] | 97 | .popsection |