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Thomas Gleixner45051532019-05-29 16:57:47 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Catalin Marinas382266a2007-02-05 14:48:19 +01002/*
Russell King4baa9922008-08-02 10:55:55 +01003 * arch/arm/include/asm/hardware/cache-l2x0.h
Catalin Marinas382266a2007-02-05 14:48:19 +01004 *
5 * Copyright (C) 2007 ARM Limited
Catalin Marinas382266a2007-02-05 14:48:19 +01006 */
7
8#ifndef __ASM_ARM_HARDWARE_L2X0_H
9#define __ASM_ARM_HARDWARE_L2X0_H
10
Olof Johanssone7c86c72011-11-09 22:10:00 +010011#include <linux/errno.h>
12
Catalin Marinas382266a2007-02-05 14:48:19 +010013#define L2X0_CACHE_ID 0x000
14#define L2X0_CACHE_TYPE 0x004
15#define L2X0_CTRL 0x100
16#define L2X0_AUX_CTRL 0x104
Russell King1a5a9542014-03-16 20:52:25 +000017#define L310_TAG_LATENCY_CTRL 0x108
18#define L310_DATA_LATENCY_CTRL 0x10C
Catalin Marinas382266a2007-02-05 14:48:19 +010019#define L2X0_EVENT_CNT_CTRL 0x200
20#define L2X0_EVENT_CNT1_CFG 0x204
21#define L2X0_EVENT_CNT0_CFG 0x208
22#define L2X0_EVENT_CNT1_VAL 0x20C
23#define L2X0_EVENT_CNT0_VAL 0x210
24#define L2X0_INTR_MASK 0x214
25#define L2X0_MASKED_INTR_STAT 0x218
26#define L2X0_RAW_INTR_STAT 0x21C
27#define L2X0_INTR_CLEAR 0x220
28#define L2X0_CACHE_SYNC 0x730
Srinidhi Kasagar885028e2011-02-17 07:03:51 +010029#define L2X0_DUMMY_REG 0x740
Catalin Marinas382266a2007-02-05 14:48:19 +010030#define L2X0_INV_LINE_PA 0x770
31#define L2X0_INV_WAY 0x77C
32#define L2X0_CLEAN_LINE_PA 0x7B0
33#define L2X0_CLEAN_LINE_IDX 0x7B8
34#define L2X0_CLEAN_WAY 0x7BC
35#define L2X0_CLEAN_INV_LINE_PA 0x7F0
36#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
37#define L2X0_CLEAN_INV_WAY 0x7FC
Linus Walleijbac7e6e2011-09-06 07:45:46 +010038/*
39 * The lockdown registers repeat 8 times for L310, the L210 has only one
40 * D and one I lockdown register at 0x0900 and 0x0904.
41 */
42#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
43#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
44#define L2X0_LOCKDOWN_STRIDE 0x08
Russell King1a5a9542014-03-16 20:52:25 +000045#define L310_ADDR_FILTER_START 0xC00
46#define L310_ADDR_FILTER_END 0xC04
Catalin Marinas382266a2007-02-05 14:48:19 +010047#define L2X0_TEST_OPERATION 0xF00
48#define L2X0_LINE_DATA 0xF10
49#define L2X0_LINE_TAG 0xF30
50#define L2X0_DEBUG_CTRL 0xF40
Russell King1a5a9542014-03-16 20:52:25 +000051#define L310_PREFETCH_CTRL 0xF60
52#define L310_POWER_CTRL 0xF80
53#define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
54#define L310_STNDBY_MODE_EN (1 << 0)
Catalin Marinas382266a2007-02-05 14:48:19 +010055
Santosh Shilimkar7db27e82010-07-11 14:13:26 +053056/* Registers shifts and masks */
57#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
58#define L2X0_CACHE_ID_PART_L210 (1 << 6)
Russell King14b882c2014-03-15 16:47:49 +000059#define L2X0_CACHE_ID_PART_L220 (2 << 6)
Santosh Shilimkar7db27e82010-07-11 14:13:26 +053060#define L2X0_CACHE_ID_PART_L310 (3 << 6)
Barry Song91c2ebb2011-09-30 14:43:12 +010061#define L2X0_CACHE_ID_RTL_MASK 0x3f
Russell King14b882c2014-03-15 16:47:49 +000062#define L210_CACHE_ID_RTL_R0P2_02 0x00
63#define L210_CACHE_ID_RTL_R0P1 0x01
64#define L210_CACHE_ID_RTL_R0P2_01 0x02
65#define L210_CACHE_ID_RTL_R0P3 0x03
66#define L210_CACHE_ID_RTL_R0P4 0x0b
67#define L210_CACHE_ID_RTL_R0P5 0x0f
68#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
69#define L310_CACHE_ID_RTL_R0P0 0x00
70#define L310_CACHE_ID_RTL_R1P0 0x02
71#define L310_CACHE_ID_RTL_R2P0 0x04
72#define L310_CACHE_ID_RTL_R3P0 0x05
73#define L310_CACHE_ID_RTL_R3P1 0x06
74#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
75#define L310_CACHE_ID_RTL_R3P2 0x08
76#define L310_CACHE_ID_RTL_R3P3 0x09
Santosh Shilimkar0aaa6f82010-11-19 23:01:02 +053077
Mark Rutlandb828f962016-09-02 10:35:18 +010078#define L2X0_EVENT_CNT_CTRL_ENABLE BIT(0)
79
80#define L2X0_EVENT_CNT_CFG_SRC_SHIFT 2
81#define L2X0_EVENT_CNT_CFG_SRC_MASK 0xf
82#define L2X0_EVENT_CNT_CFG_SRC_DISABLED 0
83#define L2X0_EVENT_CNT_CFG_INT_DISABLED 0
84#define L2X0_EVENT_CNT_CFG_INT_INCR 1
85#define L2X0_EVENT_CNT_CFG_INT_OVERFLOW 2
86
Russell King1a5a9542014-03-16 20:52:25 +000087/* L2C auxiliary control register - bits common to L2C-210/220/310 */
88#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
89#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
90#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
91#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
92#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
93#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
94/* L2C-210/220 common bits */
Rob Herring8c369262011-08-03 18:12:05 +010095#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
Russell King1a5a9542014-03-16 20:52:25 +000096#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
Rob Herring8c369262011-08-03 18:12:05 +010097#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
Russell King1a5a9542014-03-16 20:52:25 +000098#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
Rob Herring8c369262011-08-03 18:12:05 +010099#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
Russell King1a5a9542014-03-16 20:52:25 +0000100#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
Rob Herring8c369262011-08-03 18:12:05 +0100101#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
Russell King1a5a9542014-03-16 20:52:25 +0000102#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
103#define L2X0_AUX_CTRL_ASSOC_SHIFT 13
104#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
105/* L2C-210 specific bits */
106#define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
107#define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
108#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
109/* L2C-220 specific bits */
110#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
111#define L220_AUX_CTRL_FWA_SHIFT 23
112#define L220_AUX_CTRL_FWA_MASK (3 << 23)
113#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
114#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
115/* L2C-310 specific bits */
116#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
117#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
118#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
119#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
120#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
121#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
122#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
123#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
124#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
125#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
126#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
Santosh Shilimkar7db27e82010-07-11 14:13:26 +0530127
Russell King1a5a9542014-03-16 20:52:25 +0000128#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
129#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
130#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
Rob Herring8c369262011-08-03 18:12:05 +0100131
Russell King1a5a9542014-03-16 20:52:25 +0000132#define L310_ADDR_FILTER_EN 1
Rob Herring8c369262011-08-03 18:12:05 +0100133
Russell King8ef418c2014-03-18 21:40:01 +0000134#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f
135#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23)
136#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24)
137#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27)
138#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28)
139#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29)
140#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30)
141
Gregory CLEMENTb8db6b82012-11-06 01:58:07 +0100142#define L2X0_CTRL_EN 1
143
144#define L2X0_WAY_SIZE_SHIFT 3
145
Catalin Marinas382266a2007-02-05 14:48:19 +0100146#ifndef __ASSEMBLY__
Russell King3e175ca2011-09-18 11:27:30 +0100147extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
Rob Herringfae2b892011-08-25 08:14:52 -0500148#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
Russell King3e175ca2011-09-18 11:27:30 +0100149extern int l2x0_of_init(u32 aux_val, u32 aux_mask);
Rob Herringfae2b892011-08-25 08:14:52 -0500150#else
Russell King3e175ca2011-09-18 11:27:30 +0100151static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
Rob Herringfae2b892011-08-25 08:14:52 -0500152{
153 return -ENODEV;
154}
155#endif
Barry Song91c2ebb2011-09-30 14:43:12 +0100156
Mark Rutlandb828f962016-09-02 10:35:18 +0100157#ifdef CONFIG_CACHE_L2X0_PMU
158void l2x0_pmu_register(void __iomem *base, u32 part);
159void l2x0_pmu_suspend(void);
160void l2x0_pmu_resume(void);
161#else
162static inline void l2x0_pmu_register(void __iomem *base, u32 part) {}
163static inline void l2x0_pmu_suspend(void) {}
164static inline void l2x0_pmu_resume(void) {}
165#endif
166
Barry Song91c2ebb2011-09-30 14:43:12 +0100167struct l2x0_regs {
168 unsigned long phy_base;
169 unsigned long aux_ctrl;
170 /*
171 * Whether the following registers need to be saved/restored
172 * depends on platform
173 */
174 unsigned long tag_latency;
175 unsigned long data_latency;
176 unsigned long filter_start;
177 unsigned long filter_end;
178 unsigned long prefetch_ctrl;
179 unsigned long pwr_ctrl;
Gregory CLEMENTc3545232012-10-01 10:59:29 +0100180 unsigned long ctrl;
Sebastian Hesselbarthe68f31f2013-12-13 16:42:19 +0100181 unsigned long aux2_ctrl;
Barry Song91c2ebb2011-09-30 14:43:12 +0100182};
183
184extern struct l2x0_regs l2x0_saved_regs;
185
Rob Herringfae2b892011-08-25 08:14:52 -0500186#endif /* __ASSEMBLY__ */
Catalin Marinas382266a2007-02-05 14:48:19 +0100187
188#endif