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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Russell King753790e2011-02-06 15:32:24 +00002/*
3 * arch/arm/include/asm/glue-cache.h
4 *
5 * Copyright (C) 1999-2002 Russell King
Russell King753790e2011-02-06 15:32:24 +00006 */
7#ifndef ASM_GLUE_CACHE_H
8#define ASM_GLUE_CACHE_H
9
10#include <asm/glue.h>
11
12/*
13 * Cache Model
14 * ===========
15 */
16#undef _CACHE
17#undef MULTI_CACHE
18
Russell King753790e2011-02-06 15:32:24 +000019#if defined(CONFIG_CPU_CACHE_V4)
20# ifdef _CACHE
21# define MULTI_CACHE 1
22# else
23# define _CACHE v4
24# endif
25#endif
26
27#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
28 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
29 defined(CONFIG_CPU_ARM1026)
30# define MULTI_CACHE 1
31#endif
32
33#if defined(CONFIG_CPU_FA526)
34# ifdef _CACHE
35# define MULTI_CACHE 1
36# else
37# define _CACHE fa
38# endif
39#endif
40
41#if defined(CONFIG_CPU_ARM926T)
42# ifdef _CACHE
43# define MULTI_CACHE 1
44# else
45# define _CACHE arm926
46# endif
47#endif
48
49#if defined(CONFIG_CPU_ARM940T)
50# ifdef _CACHE
51# define MULTI_CACHE 1
52# else
53# define _CACHE arm940
54# endif
55#endif
56
57#if defined(CONFIG_CPU_ARM946E)
58# ifdef _CACHE
59# define MULTI_CACHE 1
60# else
61# define _CACHE arm946
62# endif
63#endif
64
65#if defined(CONFIG_CPU_CACHE_V4WB)
66# ifdef _CACHE
67# define MULTI_CACHE 1
68# else
69# define _CACHE v4wb
70# endif
71#endif
72
73#if defined(CONFIG_CPU_XSCALE)
74# ifdef _CACHE
75# define MULTI_CACHE 1
76# else
77# define _CACHE xscale
78# endif
79#endif
80
81#if defined(CONFIG_CPU_XSC3)
82# ifdef _CACHE
83# define MULTI_CACHE 1
84# else
85# define _CACHE xsc3
86# endif
87#endif
88
89#if defined(CONFIG_CPU_MOHAWK)
90# ifdef _CACHE
91# define MULTI_CACHE 1
92# else
93# define _CACHE mohawk
94# endif
95#endif
96
97#if defined(CONFIG_CPU_FEROCEON)
98# define MULTI_CACHE 1
99#endif
100
Russell Kingbd1274d2011-03-16 23:35:26 +0000101#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
Russell Kinga67e1ce2012-09-02 09:17:09 +0100102# ifdef _CACHE
Russell King753790e2011-02-06 15:32:24 +0000103# define MULTI_CACHE 1
Russell Kinga67e1ce2012-09-02 09:17:09 +0100104# else
105# define _CACHE v6
106# endif
Russell King753790e2011-02-06 15:32:24 +0000107#endif
108
109#if defined(CONFIG_CPU_V7)
Russell Kinga67e1ce2012-09-02 09:17:09 +0100110# ifdef _CACHE
Russell King753790e2011-02-06 15:32:24 +0000111# define MULTI_CACHE 1
Russell Kinga67e1ce2012-09-02 09:17:09 +0100112# else
113# define _CACHE v7
114# endif
Russell King753790e2011-02-06 15:32:24 +0000115#endif
116
Florian Fainellif6f9be12017-12-01 01:10:09 +0100117#if defined(CONFIG_CACHE_B15_RAC)
118# define MULTI_CACHE 1
119#endif
120
Catalin Marinas55bdd692010-05-21 18:06:41 +0100121#if defined(CONFIG_CPU_V7M)
Catalin Marinas55bdd692010-05-21 18:06:41 +0100122# define MULTI_CACHE 1
Catalin Marinas55bdd692010-05-21 18:06:41 +0100123#endif
124
Russell King753790e2011-02-06 15:32:24 +0000125#if !defined(_CACHE) && !defined(MULTI_CACHE)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300126#error Unknown cache maintenance model
Russell King753790e2011-02-06 15:32:24 +0000127#endif
128
Catalin Marinas55bdd692010-05-21 18:06:41 +0100129#ifndef __ASSEMBLER__
Behan Webster76ae0382013-09-03 22:27:26 -0400130static inline void nop_flush_icache_all(void) { }
131static inline void nop_flush_kern_cache_all(void) { }
132static inline void nop_flush_kern_cache_louis(void) { }
133static inline void nop_flush_user_cache_all(void) { }
134static inline void nop_flush_user_cache_range(unsigned long a,
Catalin Marinas55bdd692010-05-21 18:06:41 +0100135 unsigned long b, unsigned int c) { }
136
Behan Webster76ae0382013-09-03 22:27:26 -0400137static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
138static inline int nop_coherent_user_range(unsigned long a,
Catalin Marinas55bdd692010-05-21 18:06:41 +0100139 unsigned long b) { return 0; }
Behan Webster76ae0382013-09-03 22:27:26 -0400140static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
Catalin Marinas55bdd692010-05-21 18:06:41 +0100141
Behan Webster76ae0382013-09-03 22:27:26 -0400142static inline void nop_dma_flush_range(const void *a, const void *b) { }
Catalin Marinas55bdd692010-05-21 18:06:41 +0100143
Behan Webster76ae0382013-09-03 22:27:26 -0400144static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
145static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
Catalin Marinas55bdd692010-05-21 18:06:41 +0100146#endif
147
Russell King753790e2011-02-06 15:32:24 +0000148#ifndef MULTI_CACHE
149#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
150#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
Lorenzo Pieralisi031bd872012-09-06 18:35:13 +0530151#define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis)
Russell King753790e2011-02-06 15:32:24 +0000152#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
153#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
154#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
155#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
156#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
157
Russell King753790e2011-02-06 15:32:24 +0000158#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
159#endif
160
161#endif