blob: 784d98989e3a9a7ec596ed366b04becdd23ee3c5 [file] [log] [blame]
Rob Clarkfacb4f42013-11-30 12:45:48 -05001#ifndef MDP5_XML
2#define MDP5_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
Rob Clark2d756322018-08-06 14:57:14 -040011- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
12- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
14- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
15- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
16- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
17- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
18- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
19- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
20- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
21- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
Rob Clarkfacb4f42013-11-30 12:45:48 -050022
Rob Clark2d756322018-08-06 14:57:14 -040023Copyright (C) 2013-2018 by the following authors:
Rob Clarkfacb4f42013-11-30 12:45:48 -050024- Rob Clark <robdclark@gmail.com> (robclark)
Rob Clarka2272e42016-02-20 13:37:58 -050025- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Rob Clarkfacb4f42013-11-30 12:45:48 -050026
27Permission is hereby granted, free of charge, to any person obtaining
28a copy of this software and associated documentation files (the
29"Software"), to deal in the Software without restriction, including
30without limitation the rights to use, copy, modify, merge, publish,
31distribute, sublicense, and/or sell copies of the Software, and to
32permit persons to whom the Software is furnished to do so, subject to
33the following conditions:
34
35The above copyright notice and this permission notice (including the
36next paragraph) shall be included in all copies or substantial
37portions of the Software.
38
39THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46*/
47
48
Stephane Viaua13ceba2015-03-13 15:49:31 -040049enum mdp5_intf_type {
50 INTF_DISABLED = 0,
Rob Clarkfacb4f42013-11-30 12:45:48 -050051 INTF_DSI = 1,
52 INTF_HDMI = 3,
53 INTF_LCDC = 5,
54 INTF_eDP = 9,
Stephane Viaua13ceba2015-03-13 15:49:31 -040055 INTF_VIRTUAL = 100,
56 INTF_WB = 101,
Rob Clarkfacb4f42013-11-30 12:45:48 -050057};
58
59enum mdp5_intfnum {
60 NO_INTF = 0,
61 INTF0 = 1,
62 INTF1 = 2,
63 INTF2 = 3,
64 INTF3 = 4,
65};
66
67enum mdp5_pipe {
Archit Tanejaf71516b2017-01-16 11:34:19 +053068 SSPP_NONE = 0,
69 SSPP_VIG0 = 1,
70 SSPP_VIG1 = 2,
71 SSPP_VIG2 = 3,
72 SSPP_RGB0 = 4,
73 SSPP_RGB1 = 5,
74 SSPP_RGB2 = 6,
75 SSPP_DMA0 = 7,
76 SSPP_DMA1 = 8,
77 SSPP_VIG3 = 9,
78 SSPP_RGB3 = 10,
79 SSPP_CURSOR0 = 11,
80 SSPP_CURSOR1 = 12,
Rob Clarkfacb4f42013-11-30 12:45:48 -050081};
82
83enum mdp5_ctl_mode {
84 MODE_NONE = 0,
Stephane Viaua13ceba2015-03-13 15:49:31 -040085 MODE_WB_0_BLOCK = 1,
86 MODE_WB_1_BLOCK = 2,
87 MODE_WB_0_LINE = 3,
88 MODE_WB_1_LINE = 4,
89 MODE_WB_2_LINE = 5,
Rob Clarkfacb4f42013-11-30 12:45:48 -050090};
91
92enum mdp5_pack_3d {
93 PACK_3D_FRAME_INT = 0,
94 PACK_3D_H_ROW_INT = 1,
95 PACK_3D_V_ROW_INT = 2,
96 PACK_3D_COL_INT = 3,
97};
98
Rob Clarkfacb4f42013-11-30 12:45:48 -050099enum mdp5_scale_filter {
100 SCALE_FILTER_NEAREST = 0,
101 SCALE_FILTER_BIL = 1,
102 SCALE_FILTER_PCMN = 2,
103 SCALE_FILTER_CA = 3,
104};
105
106enum mdp5_pipe_bwc {
107 BWC_LOSSLESS = 0,
108 BWC_Q_HIGH = 1,
109 BWC_Q_MED = 2,
110};
111
Rob Clark8a264742014-12-08 11:30:02 -0500112enum mdp5_cursor_format {
113 CURSOR_FMT_ARGB8888 = 0,
114 CURSOR_FMT_ARGB1555 = 2,
115 CURSOR_FMT_ARGB4444 = 4,
116};
117
118enum mdp5_cursor_alpha {
119 CURSOR_ALPHA_CONST = 0,
120 CURSOR_ALPHA_PER_PIXEL = 2,
121};
122
Rob Clarkfacb4f42013-11-30 12:45:48 -0500123enum mdp5_igc_type {
124 IGC_VIG = 0,
125 IGC_RGB = 1,
126 IGC_DMA = 2,
127 IGC_DSPP = 3,
128};
129
Rob Clark8a264742014-12-08 11:30:02 -0500130enum mdp5_data_format {
131 DATA_FORMAT_RGB = 0,
132 DATA_FORMAT_YUV = 1,
133};
134
Rob Clarkaf6cb4c2015-05-20 10:50:30 -0400135enum mdp5_block_size {
136 BLOCK_SIZE_64 = 0,
137 BLOCK_SIZE_128 = 1,
138};
139
140enum mdp5_rotate_mode {
141 ROTATE_0 = 0,
142 ROTATE_90 = 1,
143};
144
145enum mdp5_chroma_downsample_method {
146 DS_MTHD_NO_PIXEL_DROP = 0,
147 DS_MTHD_PIXEL_DROP = 1,
148};
149
Stephane Viaua13ceba2015-03-13 15:49:31 -0400150#define MDP5_IRQ_WB_0_DONE 0x00000001
151#define MDP5_IRQ_WB_1_DONE 0x00000002
152#define MDP5_IRQ_WB_2_DONE 0x00000010
153#define MDP5_IRQ_PING_PONG_0_DONE 0x00000100
154#define MDP5_IRQ_PING_PONG_1_DONE 0x00000200
155#define MDP5_IRQ_PING_PONG_2_DONE 0x00000400
156#define MDP5_IRQ_PING_PONG_3_DONE 0x00000800
157#define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000
158#define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000
159#define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000
160#define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000
161#define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000
162#define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000
163#define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000
164#define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000
165#define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000
166#define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000
167#define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000
168#define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000
Rob Clarkfacb4f42013-11-30 12:45:48 -0500169#define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
170#define MDP5_IRQ_INTF0_VSYNC 0x02000000
171#define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
172#define MDP5_IRQ_INTF1_VSYNC 0x08000000
173#define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
174#define MDP5_IRQ_INTF2_VSYNC 0x20000000
175#define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
176#define MDP5_IRQ_INTF3_VSYNC 0x80000000
Stephane Viauba474a02015-03-09 09:11:03 -0400177#define REG_MDSS_HW_VERSION 0x00000000
178#define MDSS_HW_VERSION_STEP__MASK 0x0000ffff
179#define MDSS_HW_VERSION_STEP__SHIFT 0
180static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500181{
Stephane Viauba474a02015-03-09 09:11:03 -0400182 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500183}
Stephane Viauba474a02015-03-09 09:11:03 -0400184#define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000
185#define MDSS_HW_VERSION_MINOR__SHIFT 16
186static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500187{
Stephane Viauba474a02015-03-09 09:11:03 -0400188 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
189}
190#define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000
191#define MDSS_HW_VERSION_MAJOR__SHIFT 28
192static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
193{
194 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500195}
196
Stephane Viauba474a02015-03-09 09:11:03 -0400197#define REG_MDSS_HW_INTR_STATUS 0x00000010
198#define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001
199#define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010
200#define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020
201#define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
202#define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
203
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530204#define REG_MDP5_HW_VERSION 0x00000000
205#define MDP5_HW_VERSION_STEP__MASK 0x0000ffff
206#define MDP5_HW_VERSION_STEP__SHIFT 0
207static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500208{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530209 return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500210}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530211#define MDP5_HW_VERSION_MINOR__MASK 0x0fff0000
212#define MDP5_HW_VERSION_MINOR__SHIFT 16
213static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500214{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530215 return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500216}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530217#define MDP5_HW_VERSION_MAJOR__MASK 0xf0000000
218#define MDP5_HW_VERSION_MAJOR__SHIFT 28
219static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500220{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530221 return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500222}
223
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530224#define REG_MDP5_DISP_INTF_SEL 0x00000004
225#define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
226#define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
227static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500228{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530229 return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500230}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530231#define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
232#define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
233static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500234{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530235 return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500236}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530237#define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
238#define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
239static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500240{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530241 return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
Stephane Viauba474a02015-03-09 09:11:03 -0400242}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530243#define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
244#define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
245static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
Stephane Viauba474a02015-03-09 09:11:03 -0400246{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530247 return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500248}
249
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530250#define REG_MDP5_INTR_EN 0x00000010
Rob Clarkfacb4f42013-11-30 12:45:48 -0500251
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530252#define REG_MDP5_INTR_STATUS 0x00000014
Stephane Viauba474a02015-03-09 09:11:03 -0400253
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530254#define REG_MDP5_INTR_CLEAR 0x00000018
Stephane Viauba474a02015-03-09 09:11:03 -0400255
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530256#define REG_MDP5_HIST_INTR_EN 0x0000001c
Stephane Viauba474a02015-03-09 09:11:03 -0400257
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530258#define REG_MDP5_HIST_INTR_STATUS 0x00000020
Stephane Viauba474a02015-03-09 09:11:03 -0400259
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530260#define REG_MDP5_HIST_INTR_CLEAR 0x00000024
Stephane Viauba474a02015-03-09 09:11:03 -0400261
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530262#define REG_MDP5_SPARE_0 0x00000028
263#define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
Stephane Viauba474a02015-03-09 09:11:03 -0400264
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530265static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
Stephane Viauba474a02015-03-09 09:11:03 -0400266
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530267static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
268#define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
269#define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
270static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500271{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530272 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500273}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530274#define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
275#define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
276static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500277{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530278 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500279}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530280#define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
281#define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
282static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500283{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530284 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
Stephane Viauba474a02015-03-09 09:11:03 -0400285}
286
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530287static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
Stephane Viauba474a02015-03-09 09:11:03 -0400288
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530289static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
290#define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
291#define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
292static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
Stephane Viauba474a02015-03-09 09:11:03 -0400293{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530294 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
Stephane Viauba474a02015-03-09 09:11:03 -0400295}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530296#define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
297#define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
298static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
Stephane Viauba474a02015-03-09 09:11:03 -0400299{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530300 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
Stephane Viauba474a02015-03-09 09:11:03 -0400301}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530302#define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
303#define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
304static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
Stephane Viauba474a02015-03-09 09:11:03 -0400305{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530306 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500307}
308
309static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
310{
311 switch (idx) {
Stephane Viauba474a02015-03-09 09:11:03 -0400312 case IGC_VIG: return 0x00000200;
313 case IGC_RGB: return 0x00000210;
314 case IGC_DMA: return 0x00000220;
315 case IGC_DSPP: return 0x00000300;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500316 default: return INVALID_IDX(idx);
317 }
318}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530319static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500320
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530321static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500322
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530323static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
324#define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
325#define MDP5_IGC_LUT_REG_VAL__SHIFT 0
326static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500327{
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530328 return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500329}
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530330#define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
331#define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
332#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
333#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
Rob Clarkfacb4f42013-11-30 12:45:48 -0500334
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530335#define REG_MDP5_SPLIT_DPL_EN 0x000002f4
Hai Li81c71ad2015-03-05 15:20:48 -0500336
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530337#define REG_MDP5_SPLIT_DPL_UPPER 0x000002f8
338#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
339#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
340#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
341#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
Hai Li81c71ad2015-03-05 15:20:48 -0500342
Archit Taneja7b59c7e2016-05-10 11:05:58 +0530343#define REG_MDP5_SPLIT_DPL_LOWER 0x000003f0
344#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
345#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
346#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
347#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
Hai Li81c71ad2015-03-05 15:20:48 -0500348
Stephane Viau3d47fd42014-07-07 10:34:01 -0400349static inline uint32_t __offset_CTL(uint32_t idx)
350{
351 switch (idx) {
352 case 0: return (mdp5_cfg->ctl.base[0]);
353 case 1: return (mdp5_cfg->ctl.base[1]);
354 case 2: return (mdp5_cfg->ctl.base[2]);
355 case 3: return (mdp5_cfg->ctl.base[3]);
356 case 4: return (mdp5_cfg->ctl.base[4]);
357 default: return INVALID_IDX(idx);
358 }
359}
360static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500361
Stephane Viau3d47fd42014-07-07 10:34:01 -0400362static inline uint32_t __offset_LAYER(uint32_t idx)
363{
364 switch (idx) {
365 case 0: return 0x00000000;
366 case 1: return 0x00000004;
367 case 2: return 0x00000008;
368 case 3: return 0x0000000c;
369 case 4: return 0x00000010;
370 case 5: return 0x00000024;
371 default: return INVALID_IDX(idx);
372 }
373}
374static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500375
Stephane Viau3d47fd42014-07-07 10:34:01 -0400376static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500377#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
378#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
Rob Clark2d3584e2015-07-27 19:37:12 -0400379static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500380{
381 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
382}
383#define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
384#define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
Rob Clark2d3584e2015-07-27 19:37:12 -0400385static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500386{
387 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
388}
389#define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
390#define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
Rob Clark2d3584e2015-07-27 19:37:12 -0400391static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500392{
393 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
394}
395#define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
396#define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
Rob Clark2d3584e2015-07-27 19:37:12 -0400397static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500398{
399 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
400}
401#define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
402#define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
Rob Clark2d3584e2015-07-27 19:37:12 -0400403static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500404{
405 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
406}
407#define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
408#define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
Rob Clark2d3584e2015-07-27 19:37:12 -0400409static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500410{
411 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
412}
413#define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
414#define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
Rob Clark2d3584e2015-07-27 19:37:12 -0400415static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500416{
417 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
418}
419#define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
420#define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
Rob Clark2d3584e2015-07-27 19:37:12 -0400421static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500422{
423 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
424}
425#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
426#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
Stephane Viau3d47fd42014-07-07 10:34:01 -0400427#define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
428#define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
Rob Clark2d3584e2015-07-27 19:37:12 -0400429static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
Stephane Viau3d47fd42014-07-07 10:34:01 -0400430{
431 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
432}
433#define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
434#define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
Rob Clark2d3584e2015-07-27 19:37:12 -0400435static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
Stephane Viau3d47fd42014-07-07 10:34:01 -0400436{
437 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
438}
Rob Clarkfacb4f42013-11-30 12:45:48 -0500439
Stephane Viau3d47fd42014-07-07 10:34:01 -0400440static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500441#define MDP5_CTL_OP_MODE__MASK 0x0000000f
442#define MDP5_CTL_OP_MODE__SHIFT 0
443static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
444{
445 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
446}
447#define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
448#define MDP5_CTL_OP_INTF_NUM__SHIFT 4
449static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
450{
451 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
452}
453#define MDP5_CTL_OP_CMD_MODE 0x00020000
454#define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
455#define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
456#define MDP5_CTL_OP_PACK_3D__SHIFT 20
457static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
458{
459 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
460}
461
Stephane Viau3d47fd42014-07-07 10:34:01 -0400462static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500463#define MDP5_CTL_FLUSH_VIG0 0x00000001
464#define MDP5_CTL_FLUSH_VIG1 0x00000002
465#define MDP5_CTL_FLUSH_VIG2 0x00000004
466#define MDP5_CTL_FLUSH_RGB0 0x00000008
467#define MDP5_CTL_FLUSH_RGB1 0x00000010
468#define MDP5_CTL_FLUSH_RGB2 0x00000020
469#define MDP5_CTL_FLUSH_LM0 0x00000040
470#define MDP5_CTL_FLUSH_LM1 0x00000080
471#define MDP5_CTL_FLUSH_LM2 0x00000100
Stephane Viau3d47fd42014-07-07 10:34:01 -0400472#define MDP5_CTL_FLUSH_LM3 0x00000200
473#define MDP5_CTL_FLUSH_LM4 0x00000400
Rob Clarkfacb4f42013-11-30 12:45:48 -0500474#define MDP5_CTL_FLUSH_DMA0 0x00000800
475#define MDP5_CTL_FLUSH_DMA1 0x00001000
476#define MDP5_CTL_FLUSH_DSPP0 0x00002000
477#define MDP5_CTL_FLUSH_DSPP1 0x00004000
478#define MDP5_CTL_FLUSH_DSPP2 0x00008000
Stephane Viau87ed66c2015-03-24 09:30:01 -0400479#define MDP5_CTL_FLUSH_WB 0x00010000
Rob Clarkfacb4f42013-11-30 12:45:48 -0500480#define MDP5_CTL_FLUSH_CTL 0x00020000
Stephane Viau3d47fd42014-07-07 10:34:01 -0400481#define MDP5_CTL_FLUSH_VIG3 0x00040000
482#define MDP5_CTL_FLUSH_RGB3 0x00080000
483#define MDP5_CTL_FLUSH_LM5 0x00100000
484#define MDP5_CTL_FLUSH_DSPP3 0x00200000
Stephane Viau87ed66c2015-03-24 09:30:01 -0400485#define MDP5_CTL_FLUSH_CURSOR_0 0x00400000
486#define MDP5_CTL_FLUSH_CURSOR_1 0x00800000
487#define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000
488#define MDP5_CTL_FLUSH_TIMING_3 0x10000000
489#define MDP5_CTL_FLUSH_TIMING_2 0x20000000
490#define MDP5_CTL_FLUSH_TIMING_1 0x40000000
491#define MDP5_CTL_FLUSH_TIMING_0 0x80000000
Rob Clarkfacb4f42013-11-30 12:45:48 -0500492
Stephane Viau3d47fd42014-07-07 10:34:01 -0400493static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500494
Stephane Viau3d47fd42014-07-07 10:34:01 -0400495static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500496
Rob Clark2d3584e2015-07-27 19:37:12 -0400497static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
498{
499 switch (idx) {
500 case 0: return 0x00000040;
501 case 1: return 0x00000044;
502 case 2: return 0x00000048;
503 case 3: return 0x0000004c;
504 case 4: return 0x00000050;
505 case 5: return 0x00000054;
506 default: return INVALID_IDX(idx);
507 }
508}
509static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
510
511static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
512#define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001
513#define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004
514#define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010
515#define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040
516#define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100
517#define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400
518#define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000
519#define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000
520#define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000
521#define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000
522#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000
523#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20
524static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
525{
526 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
527}
528#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000
529#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26
530static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
531{
532 return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
533}
534
Stephane Viau3d47fd42014-07-07 10:34:01 -0400535static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
536{
537 switch (idx) {
Archit Tanejaf71516b2017-01-16 11:34:19 +0530538 case SSPP_NONE: return (INVALID_IDX(idx));
Stephane Viau3d47fd42014-07-07 10:34:01 -0400539 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
540 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
541 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
542 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
543 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
544 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
545 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
546 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
547 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
548 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
Archit Tanejaf71516b2017-01-16 11:34:19 +0530549 case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]);
550 case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]);
Stephane Viau3d47fd42014-07-07 10:34:01 -0400551 default: return INVALID_IDX(idx);
552 }
553}
554static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500555
Rob Clark8a264742014-12-08 11:30:02 -0500556static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
557#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
558#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
559static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
560{
561 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
562}
563#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
564#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
565static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
566{
567 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
568}
569#define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
570
Stephane Viau3d47fd42014-07-07 10:34:01 -0400571static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500572
Stephane Viau3d47fd42014-07-07 10:34:01 -0400573static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500574
Stephane Viau3d47fd42014-07-07 10:34:01 -0400575static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500576
Rob Clark8a264742014-12-08 11:30:02 -0500577static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
578#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
579#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
580static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
581{
582 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
583}
584#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
585#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
586static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
587{
588 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
589}
590
591static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
592#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
593#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
594static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
595{
596 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
597}
598#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
599#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
600static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
601{
602 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
603}
604
605static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
606#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
607#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
608static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
609{
610 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
611}
612#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
613#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
614static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
615{
616 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
617}
618
619static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
620#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
621#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
622static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
623{
624 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
625}
626#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
627#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
628static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
629{
630 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
631}
632
633static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
634#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
635#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
636static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
637{
638 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
639}
640
641static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
642
643static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
644#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
645#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
646static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
647{
648 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
649}
650#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
651#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
652static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
653{
654 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
655}
656
657static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
658
659static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
660#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
661#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
662static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
663{
664 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
665}
666#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
667#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
668static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
669{
670 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
671}
672
673static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
674
675static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
676#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
677#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
678static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
679{
680 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
681}
682
683static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
684
685static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
686#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
687#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
688static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
689{
690 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
691}
692
Stephane Viau3d47fd42014-07-07 10:34:01 -0400693static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500694#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
695#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
696static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
697{
698 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
699}
700#define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
701#define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
702static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
703{
704 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
705}
706
Stephane Viau3d47fd42014-07-07 10:34:01 -0400707static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500708#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
709#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
710static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
711{
712 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
713}
714#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
715#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
716static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
717{
718 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
719}
720
Stephane Viau3d47fd42014-07-07 10:34:01 -0400721static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500722#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
723#define MDP5_PIPE_SRC_XY_Y__SHIFT 16
724static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
725{
726 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
727}
728#define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
729#define MDP5_PIPE_SRC_XY_X__SHIFT 0
730static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
731{
732 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
733}
734
Stephane Viau3d47fd42014-07-07 10:34:01 -0400735static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500736#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
737#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
738static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
739{
740 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
741}
742#define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
743#define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
744static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
745{
746 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
747}
748
Stephane Viau3d47fd42014-07-07 10:34:01 -0400749static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500750#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
751#define MDP5_PIPE_OUT_XY_Y__SHIFT 16
752static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
753{
754 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
755}
756#define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
757#define MDP5_PIPE_OUT_XY_X__SHIFT 0
758static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
759{
760 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
761}
762
Stephane Viau3d47fd42014-07-07 10:34:01 -0400763static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500764
Stephane Viau3d47fd42014-07-07 10:34:01 -0400765static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500766
Stephane Viau3d47fd42014-07-07 10:34:01 -0400767static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500768
Stephane Viau3d47fd42014-07-07 10:34:01 -0400769static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500770
Stephane Viau3d47fd42014-07-07 10:34:01 -0400771static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500772#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
773#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
774static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
775{
776 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
777}
778#define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
779#define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
780static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
781{
782 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
783}
784
Stephane Viau3d47fd42014-07-07 10:34:01 -0400785static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500786#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
787#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
788static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
789{
790 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
791}
792#define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
793#define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
794static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
795{
796 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
797}
798
Stephane Viau3d47fd42014-07-07 10:34:01 -0400799static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500800
Stephane Viau3d47fd42014-07-07 10:34:01 -0400801static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500802#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
803#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
804static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
805{
806 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
807}
808#define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
809#define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
810static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
811{
812 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
813}
814#define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
815#define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
816static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
817{
818 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
819}
820#define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
821#define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
822static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
823{
824 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
825}
826#define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
827#define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
828#define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
829static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
830{
831 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
832}
833#define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
834#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
835#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
836static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
837{
838 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
839}
840#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
841#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
Rob Clark2d3584e2015-07-27 19:37:12 -0400842#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000
843#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
844static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500845{
Rob Clark2d3584e2015-07-27 19:37:12 -0400846 return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -0500847}
848#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
849#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
Rob Clark8a264742014-12-08 11:30:02 -0500850static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
Rob Clarkfacb4f42013-11-30 12:45:48 -0500851{
852 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
853}
854
Stephane Viau3d47fd42014-07-07 10:34:01 -0400855static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500856#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
857#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
858static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
859{
860 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
861}
862#define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
863#define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
864static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
865{
866 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
867}
868#define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
869#define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
870static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
871{
872 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
873}
874#define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
875#define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
876static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
877{
878 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
879}
880
Stephane Viau3d47fd42014-07-07 10:34:01 -0400881static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500882#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
883#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
884#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
885static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
886{
887 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
888}
889#define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
890#define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
891#define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
892#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
893#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
894#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
895#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
Rob Clark8217e972015-10-22 12:36:57 -0400896#define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000
Rob Clarkfacb4f42013-11-30 12:45:48 -0500897
Stephane Viau3d47fd42014-07-07 10:34:01 -0400898static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500899
Stephane Viau3d47fd42014-07-07 10:34:01 -0400900static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500901
Stephane Viau3d47fd42014-07-07 10:34:01 -0400902static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500903
Stephane Viau3d47fd42014-07-07 10:34:01 -0400904static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500905
Stephane Viau3d47fd42014-07-07 10:34:01 -0400906static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500907
Stephane Viau3d47fd42014-07-07 10:34:01 -0400908static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500909
Stephane Viau3d47fd42014-07-07 10:34:01 -0400910static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500911
Stephane Viau3d47fd42014-07-07 10:34:01 -0400912static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500913
Stephane Viau3d47fd42014-07-07 10:34:01 -0400914static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500915
Stephane Viau3d47fd42014-07-07 10:34:01 -0400916static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500917
Stephane Viau3d47fd42014-07-07 10:34:01 -0400918static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500919
Stephane Viau3d47fd42014-07-07 10:34:01 -0400920static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -0500921#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
922#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
923static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
924{
925 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
926}
927#define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
928#define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
929static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
930{
931 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
932}
933
Rob Clark8217e972015-10-22 12:36:57 -0400934static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
935{
936 switch (idx) {
937 case COMP_0: return 0x00000100;
938 case COMP_1_2: return 0x00000110;
939 case COMP_3: return 0x00000120;
940 default: return INVALID_IDX(idx);
941 }
942}
943static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
944
945static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
946#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff
947#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0
948static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
949{
950 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
951}
952#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00
953#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8
954static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
955{
956 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
957}
958#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000
959#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16
960static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
961{
962 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
963}
964#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000
965#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24
966static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
967{
968 return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
969}
970
971static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
972#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff
973#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
974static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
975{
976 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
977}
978#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00
979#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
980static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
981{
982 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
983}
984#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000
985#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16
986static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
987{
988 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
989}
990#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000
991#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24
992static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
993{
994 return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
995}
996
997static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
998#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff
999#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0
1000static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
1001{
1002 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
1003}
1004#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000
1005#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16
1006static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
1007{
1008 return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
1009}
1010
Stephane Viau3d47fd42014-07-07 10:34:01 -04001011static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001012#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
1013#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
Rob Clark2d3584e2015-07-27 19:37:12 -04001014#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300
1015#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
1016static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
Rob Clarkfacb4f42013-11-30 12:45:48 -05001017{
Rob Clark2d3584e2015-07-27 19:37:12 -04001018 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -05001019}
Rob Clark2d3584e2015-07-27 19:37:12 -04001020#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00
1021#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
1022static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
Rob Clarkfacb4f42013-11-30 12:45:48 -05001023{
Rob Clark2d3584e2015-07-27 19:37:12 -04001024 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -05001025}
Rob Clark2d3584e2015-07-27 19:37:12 -04001026#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
1027#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12
1028static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
Rob Clarkfacb4f42013-11-30 12:45:48 -05001029{
Rob Clark2d3584e2015-07-27 19:37:12 -04001030 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -05001031}
Rob Clark2d3584e2015-07-27 19:37:12 -04001032#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
1033#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14
1034static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
Rob Clarkfacb4f42013-11-30 12:45:48 -05001035{
Rob Clark2d3584e2015-07-27 19:37:12 -04001036 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -05001037}
Rob Clark2d3584e2015-07-27 19:37:12 -04001038#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000
1039#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16
1040static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
Rob Clarkfacb4f42013-11-30 12:45:48 -05001041{
Rob Clark2d3584e2015-07-27 19:37:12 -04001042 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -05001043}
Rob Clark2d3584e2015-07-27 19:37:12 -04001044#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000
1045#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18
1046static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
Rob Clarkfacb4f42013-11-30 12:45:48 -05001047{
Rob Clark2d3584e2015-07-27 19:37:12 -04001048 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
Rob Clarkfacb4f42013-11-30 12:45:48 -05001049}
1050
Stephane Viau3d47fd42014-07-07 10:34:01 -04001051static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001052
Stephane Viau3d47fd42014-07-07 10:34:01 -04001053static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001054
Rob Clark8a264742014-12-08 11:30:02 -05001055static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
1056
1057static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
1058
Stephane Viau3d47fd42014-07-07 10:34:01 -04001059static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001060
Stephane Viau3d47fd42014-07-07 10:34:01 -04001061static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001062
Stephane Viau3d47fd42014-07-07 10:34:01 -04001063static inline uint32_t __offset_LM(uint32_t idx)
1064{
1065 switch (idx) {
1066 case 0: return (mdp5_cfg->lm.base[0]);
1067 case 1: return (mdp5_cfg->lm.base[1]);
1068 case 2: return (mdp5_cfg->lm.base[2]);
1069 case 3: return (mdp5_cfg->lm.base[3]);
1070 case 4: return (mdp5_cfg->lm.base[4]);
Stephane Viau8a4247d2015-02-20 16:30:55 -05001071 case 5: return (mdp5_cfg->lm.base[5]);
Stephane Viau3d47fd42014-07-07 10:34:01 -04001072 default: return INVALID_IDX(idx);
1073 }
1074}
1075static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001076
Stephane Viau3d47fd42014-07-07 10:34:01 -04001077static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001078#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
1079#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
1080#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
1081#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
Archit Tanejaf71516b2017-01-16 11:34:19 +05301082#define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA 0x00000020
1083#define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA 0x00000040
1084#define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA 0x00000080
1085#define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT 0x80000000
Rob Clarkfacb4f42013-11-30 12:45:48 -05001086
Stephane Viau3d47fd42014-07-07 10:34:01 -04001087static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001088#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
1089#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
1090static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
1091{
1092 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
1093}
1094#define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
1095#define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
1096static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
1097{
1098 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
1099}
1100
Stephane Viau3d47fd42014-07-07 10:34:01 -04001101static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001102
Stephane Viau3d47fd42014-07-07 10:34:01 -04001103static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001104
Rob Clark2d3584e2015-07-27 19:37:12 -04001105static inline uint32_t __offset_BLEND(uint32_t idx)
1106{
1107 switch (idx) {
1108 case 0: return 0x00000020;
1109 case 1: return 0x00000050;
1110 case 2: return 0x00000080;
1111 case 3: return 0x000000b0;
1112 case 4: return 0x00000230;
1113 case 5: return 0x00000260;
1114 case 6: return 0x00000290;
1115 default: return INVALID_IDX(idx);
1116 }
1117}
1118static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001119
Rob Clark2d3584e2015-07-27 19:37:12 -04001120static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001121#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
1122#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
1123static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
1124{
1125 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
1126}
1127#define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
1128#define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
1129#define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
1130#define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
1131#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
1132#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
1133static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
1134{
1135 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
1136}
1137#define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
1138#define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
1139#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
1140#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
1141
Rob Clark2d3584e2015-07-27 19:37:12 -04001142static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001143
Rob Clark2d3584e2015-07-27 19:37:12 -04001144static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001145
Rob Clark2d3584e2015-07-27 19:37:12 -04001146static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001147
Rob Clark2d3584e2015-07-27 19:37:12 -04001148static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001149
Rob Clark2d3584e2015-07-27 19:37:12 -04001150static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001151
Rob Clark2d3584e2015-07-27 19:37:12 -04001152static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001153
Rob Clark2d3584e2015-07-27 19:37:12 -04001154static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001155
Rob Clark2d3584e2015-07-27 19:37:12 -04001156static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001157
Rob Clark2d3584e2015-07-27 19:37:12 -04001158static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001159
Rob Clark2d3584e2015-07-27 19:37:12 -04001160static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001161
Stephane Viau3d47fd42014-07-07 10:34:01 -04001162static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
Rob Clark8a264742014-12-08 11:30:02 -05001163#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
1164#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
1165static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1166{
1167 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1168}
1169#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
1170#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
1171static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1172{
1173 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1174}
Rob Clarkfacb4f42013-11-30 12:45:48 -05001175
Stephane Viau3d47fd42014-07-07 10:34:01 -04001176static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
Rob Clark8a264742014-12-08 11:30:02 -05001177#define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
1178#define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
1179static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1180{
1181 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1182}
1183#define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1184#define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
1185static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1186{
1187 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1188}
Rob Clarkfacb4f42013-11-30 12:45:48 -05001189
Stephane Viau3d47fd42014-07-07 10:34:01 -04001190static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
Rob Clark8a264742014-12-08 11:30:02 -05001191#define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1192#define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
1193static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1194{
1195 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1196}
1197#define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1198#define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
1199static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1200{
1201 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1202}
Rob Clarkfacb4f42013-11-30 12:45:48 -05001203
Stephane Viau3d47fd42014-07-07 10:34:01 -04001204static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
Rob Clark8a264742014-12-08 11:30:02 -05001205#define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1206#define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
1207static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1208{
1209 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1210}
Rob Clarkfacb4f42013-11-30 12:45:48 -05001211
Stephane Viau3d47fd42014-07-07 10:34:01 -04001212static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
Rob Clark8a264742014-12-08 11:30:02 -05001213#define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1214#define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
1215static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1216{
1217 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1218}
Rob Clarkfacb4f42013-11-30 12:45:48 -05001219
Stephane Viau3d47fd42014-07-07 10:34:01 -04001220static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001221
Stephane Viau3d47fd42014-07-07 10:34:01 -04001222static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
Rob Clark8a264742014-12-08 11:30:02 -05001223#define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1224#define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
1225static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1226{
1227 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1228}
1229#define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1230#define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
1231static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1232{
1233 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1234}
Rob Clarkfacb4f42013-11-30 12:45:48 -05001235
Stephane Viau3d47fd42014-07-07 10:34:01 -04001236static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
Rob Clark8a264742014-12-08 11:30:02 -05001237#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1238#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1239#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
1240static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1241{
1242 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1243}
1244#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
Rob Clarkfacb4f42013-11-30 12:45:48 -05001245
Stephane Viau3d47fd42014-07-07 10:34:01 -04001246static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001247
Stephane Viau3d47fd42014-07-07 10:34:01 -04001248static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001249
Stephane Viau3d47fd42014-07-07 10:34:01 -04001250static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001251
Stephane Viau3d47fd42014-07-07 10:34:01 -04001252static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001253
Stephane Viau3d47fd42014-07-07 10:34:01 -04001254static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001255
Stephane Viau3d47fd42014-07-07 10:34:01 -04001256static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001257
Stephane Viau3d47fd42014-07-07 10:34:01 -04001258static inline uint32_t __offset_DSPP(uint32_t idx)
1259{
1260 switch (idx) {
1261 case 0: return (mdp5_cfg->dspp.base[0]);
1262 case 1: return (mdp5_cfg->dspp.base[1]);
1263 case 2: return (mdp5_cfg->dspp.base[2]);
1264 case 3: return (mdp5_cfg->dspp.base[3]);
1265 default: return INVALID_IDX(idx);
1266 }
1267}
1268static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001269
Stephane Viau3d47fd42014-07-07 10:34:01 -04001270static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001271#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1272#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1273#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
1274static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1275{
1276 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1277}
1278#define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1279#define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1280#define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1281#define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1282#define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1283#define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1284#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1285#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1286
Stephane Viau3d47fd42014-07-07 10:34:01 -04001287static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001288
Stephane Viau3d47fd42014-07-07 10:34:01 -04001289static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001290
Stephane Viau3d47fd42014-07-07 10:34:01 -04001291static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001292
Stephane Viau3d47fd42014-07-07 10:34:01 -04001293static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001294
Stephane Viau3d47fd42014-07-07 10:34:01 -04001295static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001296
Stephane Viau3d47fd42014-07-07 10:34:01 -04001297static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001298
Stephane Viau3d47fd42014-07-07 10:34:01 -04001299static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001300
Stephane Viau3d47fd42014-07-07 10:34:01 -04001301static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001302
Hai Li81c71ad2015-03-05 15:20:48 -05001303static inline uint32_t __offset_PP(uint32_t idx)
1304{
1305 switch (idx) {
1306 case 0: return (mdp5_cfg->pp.base[0]);
1307 case 1: return (mdp5_cfg->pp.base[1]);
1308 case 2: return (mdp5_cfg->pp.base[2]);
1309 case 3: return (mdp5_cfg->pp.base[3]);
1310 default: return INVALID_IDX(idx);
1311 }
1312}
1313static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1314
1315static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1316
1317static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1318#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff
1319#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0
1320static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1321{
1322 return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1323}
1324#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000
1325#define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000
1326
1327static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1328
1329static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1330#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff
1331#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0
1332static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1333{
1334 return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1335}
1336#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000
1337#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16
1338static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1339{
1340 return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1341}
1342
1343static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1344
1345static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1346#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff
1347#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0
1348static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1349{
1350 return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1351}
1352#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000
1353#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16
1354static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1355{
1356 return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1357}
1358
1359static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1360#define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff
1361#define MDP5_PP_SYNC_THRESH_START__SHIFT 0
1362static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1363{
1364 return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1365}
1366#define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000
1367#define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16
1368static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1369{
1370 return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1371}
1372
1373static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1374
1375static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1376
1377static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1378
1379static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1380
1381static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1382
1383static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1384
1385static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1386
1387static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1388
1389static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1390
Rob Clarkaf6cb4c2015-05-20 10:50:30 -04001391static inline uint32_t __offset_WB(uint32_t idx)
1392{
1393 switch (idx) {
Rob Clark2d3584e2015-07-27 19:37:12 -04001394#if 0 /* TEMPORARY until patch that adds wb.base[] is merged */
1395 case 0: return (mdp5_cfg->wb.base[0]);
1396 case 1: return (mdp5_cfg->wb.base[1]);
1397 case 2: return (mdp5_cfg->wb.base[2]);
1398 case 3: return (mdp5_cfg->wb.base[3]);
1399 case 4: return (mdp5_cfg->wb.base[4]);
1400#endif
Rob Clarkaf6cb4c2015-05-20 10:50:30 -04001401 default: return INVALID_IDX(idx);
1402 }
1403}
1404static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1405
1406static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1407#define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003
1408#define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0
1409static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
1410{
1411 return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
1412}
1413#define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c
1414#define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2
1415static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
1416{
1417 return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
1418}
1419#define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030
1420#define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4
1421static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
1422{
1423 return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
1424}
1425#define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0
1426#define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6
1427static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
1428{
1429 return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
1430}
1431#define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100
1432#define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600
1433#define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9
1434static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
1435{
1436 return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
1437}
1438#define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000
1439#define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12
1440static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
1441{
1442 return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
1443}
1444#define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000
1445#define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000
1446#define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000
1447#define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000
1448#define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19
1449static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
1450{
1451 return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
1452}
1453#define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000
1454#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000
1455#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23
1456static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
1457{
1458 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
1459}
1460#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000
1461#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26
1462static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
1463{
1464 return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
1465}
1466#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000
1467#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30
1468static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
1469{
1470 return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
1471}
1472
1473static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
1474#define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001
1475#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006
1476#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1
1477static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
1478{
1479 return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
1480}
1481#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010
1482#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4
1483static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
1484{
1485 return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
1486}
1487#define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020
1488#define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5
1489static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
1490{
1491 return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
1492}
1493#define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040
1494#define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100
1495#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200
1496#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9
1497static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
1498{
1499 return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
1500}
1501#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400
1502#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10
1503static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
1504{
1505 return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
1506}
1507#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800
1508#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000
1509#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
1510static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
1511{
1512 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
1513}
1514#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000
1515#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
1516static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
1517{
1518 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
1519}
1520#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000
1521#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
1522static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
1523{
1524 return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
1525}
1526
1527static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
1528#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003
1529#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0
1530static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
1531{
1532 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
1533}
1534#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300
1535#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8
1536static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
1537{
1538 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
1539}
1540#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000
1541#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16
1542static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
1543{
1544 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
1545}
1546#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000
1547#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24
1548static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
1549{
1550 return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
1551}
1552
1553static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
1554
1555static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
1556
1557static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
1558
1559static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
1560
1561static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
1562#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff
1563#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0
1564static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
1565{
1566 return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
1567}
1568#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000
1569#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16
1570static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
1571{
1572 return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
1573}
1574
1575static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
1576#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff
1577#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0
1578static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
1579{
1580 return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
1581}
1582#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000
1583#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16
1584static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
1585{
1586 return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
1587}
1588
1589static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
1590
1591static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
1592
1593static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
1594
1595static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
1596
1597static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
1598
1599static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
1600
1601static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
1602
1603static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
1604
1605static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
1606
1607static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
1608
1609static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
1610
1611static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
1612#define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff
1613#define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0
1614static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
1615{
1616 return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
1617}
1618#define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000
1619#define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16
1620static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
1621{
1622 return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
1623}
1624
1625static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
1626
1627static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
1628#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
1629#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0
1630static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
1631{
1632 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
1633}
1634#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
1635#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16
1636static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
1637{
1638 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
1639}
1640
1641static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
1642#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
1643#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0
1644static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
1645{
1646 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
1647}
1648#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
1649#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16
1650static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
1651{
1652 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
1653}
1654
1655static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
1656#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
1657#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0
1658static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
1659{
1660 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
1661}
1662#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
1663#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16
1664static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
1665{
1666 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
1667}
1668
1669static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
1670#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
1671#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0
1672static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
1673{
1674 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
1675}
1676#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
1677#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16
1678static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
1679{
1680 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
1681}
1682
1683static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
1684#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
1685#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0
1686static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
1687{
1688 return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
1689}
1690
1691static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1692
1693static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1694#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff
1695#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0
1696static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
1697{
1698 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
1699}
1700#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00
1701#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8
1702static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
1703{
1704 return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
1705}
1706
1707static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1708
1709static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1710#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff
1711#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0
1712static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
1713{
1714 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
1715}
1716#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00
1717#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8
1718static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
1719{
1720 return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
1721}
1722
1723static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1724
1725static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1726#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff
1727#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0
1728static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
1729{
1730 return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
1731}
1732
1733static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1734
1735static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1736#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff
1737#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0
1738static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
1739{
1740 return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
1741}
1742
Stephane Viau3d47fd42014-07-07 10:34:01 -04001743static inline uint32_t __offset_INTF(uint32_t idx)
1744{
1745 switch (idx) {
1746 case 0: return (mdp5_cfg->intf.base[0]);
1747 case 1: return (mdp5_cfg->intf.base[1]);
1748 case 2: return (mdp5_cfg->intf.base[2]);
1749 case 3: return (mdp5_cfg->intf.base[3]);
1750 case 4: return (mdp5_cfg->intf.base[4]);
1751 default: return INVALID_IDX(idx);
1752 }
1753}
1754static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001755
Stephane Viau3d47fd42014-07-07 10:34:01 -04001756static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001757
Stephane Viau3d47fd42014-07-07 10:34:01 -04001758static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001759
Stephane Viau3d47fd42014-07-07 10:34:01 -04001760static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001761#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1762#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
1763static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1764{
1765 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1766}
1767#define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1768#define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
1769static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1770{
1771 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1772}
1773
Stephane Viau3d47fd42014-07-07 10:34:01 -04001774static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001775
Stephane Viau3d47fd42014-07-07 10:34:01 -04001776static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001777
Stephane Viau3d47fd42014-07-07 10:34:01 -04001778static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001779
Stephane Viau3d47fd42014-07-07 10:34:01 -04001780static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001781
Stephane Viau3d47fd42014-07-07 10:34:01 -04001782static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001783
Stephane Viau3d47fd42014-07-07 10:34:01 -04001784static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001785
Stephane Viau3d47fd42014-07-07 10:34:01 -04001786static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001787
Stephane Viau3d47fd42014-07-07 10:34:01 -04001788static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001789
Stephane Viau3d47fd42014-07-07 10:34:01 -04001790static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001791#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1792#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
1793static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1794{
1795 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1796}
1797#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1798
Stephane Viau3d47fd42014-07-07 10:34:01 -04001799static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001800#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1801#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
1802static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1803{
1804 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1805}
1806
Stephane Viau3d47fd42014-07-07 10:34:01 -04001807static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001808
Stephane Viau3d47fd42014-07-07 10:34:01 -04001809static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001810
Stephane Viau3d47fd42014-07-07 10:34:01 -04001811static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001812#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1813#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
1814static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1815{
1816 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1817}
1818#define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1819#define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
1820static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1821{
1822 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1823}
1824
Stephane Viau3d47fd42014-07-07 10:34:01 -04001825static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001826#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1827#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
1828static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1829{
1830 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1831}
1832#define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1833#define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
1834static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1835{
1836 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1837}
1838#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1839
Stephane Viau3d47fd42014-07-07 10:34:01 -04001840static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001841
Stephane Viau3d47fd42014-07-07 10:34:01 -04001842static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001843
Stephane Viau3d47fd42014-07-07 10:34:01 -04001844static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001845
Stephane Viau3d47fd42014-07-07 10:34:01 -04001846static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001847#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1848#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1849#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1850
Stephane Viau3d47fd42014-07-07 10:34:01 -04001851static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001852
Stephane Viau3d47fd42014-07-07 10:34:01 -04001853static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001854
Stephane Viau3d47fd42014-07-07 10:34:01 -04001855static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001856
Stephane Viau3d47fd42014-07-07 10:34:01 -04001857static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001858
Stephane Viau3d47fd42014-07-07 10:34:01 -04001859static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001860
Stephane Viau3d47fd42014-07-07 10:34:01 -04001861static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001862
Stephane Viau3d47fd42014-07-07 10:34:01 -04001863static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001864
Stephane Viau3d47fd42014-07-07 10:34:01 -04001865static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001866
Stephane Viau3d47fd42014-07-07 10:34:01 -04001867static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001868
Stephane Viau3d47fd42014-07-07 10:34:01 -04001869static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001870
Stephane Viau3d47fd42014-07-07 10:34:01 -04001871static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001872
Stephane Viau3d47fd42014-07-07 10:34:01 -04001873static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001874
Stephane Viau3d47fd42014-07-07 10:34:01 -04001875static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001876
Stephane Viau3d47fd42014-07-07 10:34:01 -04001877static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001878
Stephane Viau3d47fd42014-07-07 10:34:01 -04001879static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001880
Stephane Viau3d47fd42014-07-07 10:34:01 -04001881static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001882
Stephane Viau3d47fd42014-07-07 10:34:01 -04001883static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001884
Stephane Viau3d47fd42014-07-07 10:34:01 -04001885static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001886
Stephane Viau3d47fd42014-07-07 10:34:01 -04001887static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001888
Stephane Viau3d47fd42014-07-07 10:34:01 -04001889static inline uint32_t __offset_AD(uint32_t idx)
1890{
1891 switch (idx) {
1892 case 0: return (mdp5_cfg->ad.base[0]);
1893 case 1: return (mdp5_cfg->ad.base[1]);
1894 default: return INVALID_IDX(idx);
1895 }
1896}
1897static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001898
Stephane Viau3d47fd42014-07-07 10:34:01 -04001899static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001900
Stephane Viau3d47fd42014-07-07 10:34:01 -04001901static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001902
Stephane Viau3d47fd42014-07-07 10:34:01 -04001903static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001904
Stephane Viau3d47fd42014-07-07 10:34:01 -04001905static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001906
Stephane Viau3d47fd42014-07-07 10:34:01 -04001907static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001908
Stephane Viau3d47fd42014-07-07 10:34:01 -04001909static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001910
Stephane Viau3d47fd42014-07-07 10:34:01 -04001911static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001912
Stephane Viau3d47fd42014-07-07 10:34:01 -04001913static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001914
Stephane Viau3d47fd42014-07-07 10:34:01 -04001915static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001916
Stephane Viau3d47fd42014-07-07 10:34:01 -04001917static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001918
Stephane Viau3d47fd42014-07-07 10:34:01 -04001919static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001920
Stephane Viau3d47fd42014-07-07 10:34:01 -04001921static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001922
Stephane Viau3d47fd42014-07-07 10:34:01 -04001923static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001924
Stephane Viau3d47fd42014-07-07 10:34:01 -04001925static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001926
Stephane Viau3d47fd42014-07-07 10:34:01 -04001927static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001928
Stephane Viau3d47fd42014-07-07 10:34:01 -04001929static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001930
Stephane Viau3d47fd42014-07-07 10:34:01 -04001931static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001932
Stephane Viau3d47fd42014-07-07 10:34:01 -04001933static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001934
Stephane Viau3d47fd42014-07-07 10:34:01 -04001935static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001936
Stephane Viau3d47fd42014-07-07 10:34:01 -04001937static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001938
Stephane Viau3d47fd42014-07-07 10:34:01 -04001939static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001940
Stephane Viau3d47fd42014-07-07 10:34:01 -04001941static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001942
Stephane Viau3d47fd42014-07-07 10:34:01 -04001943static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001944
Stephane Viau3d47fd42014-07-07 10:34:01 -04001945static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001946
Stephane Viau3d47fd42014-07-07 10:34:01 -04001947static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001948
Stephane Viau3d47fd42014-07-07 10:34:01 -04001949static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001950
Stephane Viau3d47fd42014-07-07 10:34:01 -04001951static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001952
Stephane Viau3d47fd42014-07-07 10:34:01 -04001953static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001954
Stephane Viau3d47fd42014-07-07 10:34:01 -04001955static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001956
Stephane Viau3d47fd42014-07-07 10:34:01 -04001957static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001958
Stephane Viau3d47fd42014-07-07 10:34:01 -04001959static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001960
Stephane Viau3d47fd42014-07-07 10:34:01 -04001961static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001962
Stephane Viau3d47fd42014-07-07 10:34:01 -04001963static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001964
Stephane Viau3d47fd42014-07-07 10:34:01 -04001965static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
Rob Clarkfacb4f42013-11-30 12:45:48 -05001966
1967
1968#endif /* MDP5_XML */